NetNews Usenet Archive 1992 #27/NN_1992_27.iso/spool/comp/arch/10864

Internet Message Format | 1992-11-18 | 3.7 KB

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From: [e-mail] (Rod Skinner)
Newsgroups: comp.arch
Subject: Re: IBM Clock-tripled 486
Message-ID: <[e-mail]>
Date: 18 Nov 92 16:18:19 GMT
References: <[e-mail]> <[e-mail]>
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Organization: Intel Corporation, Santa Clara, CA USA
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In article <[e-mail]> [e-mail] (Josh Osborne) writes:
>In article <[e-mail]> [e-mail] writes:
>>So, I understand that IBM announced a clock-tripled (33MHz/99MHz) version
>>of the 486 (a DX3?) at Comdex.  Can anyone in the know at IBM (or Intel)
>>comment further on this?  IBM supposedly designed this chip under their
>>existing licensing agreement with Intel.

IBM has a license from Intel to produce derivatives from the 80386 not
the 80486.  The IBM 486 SLC2 was introducted in June.  It is a clock
doubled version of the IBM 386 SLC part.  It has a 16k on-chip cache
and no on-chip math coprocessor but supports the standard Intel387 math
coprocessor chip.  IBM introduced the "tripler" part at Comdex and will
operate at 33 MHz externally and 100 MHz internally.

>
>The only 486 CPU that I know of that IBM announced is a 486SXL, which is
>a clock dubled 486 in a 386SX pinout (for the portable market).  Even
>with it's extra large cache it seems a tad bit silly to me (the clock).
>
>>                                          If I understand that agreement
>>properly, IBM has 6 months to exclusively do their thing with it before
>>Intel can provide their own version to the masses.  Is that correct?

The license agreement allows Intel to build the parts for IBM...not the
masses.  The agreement allows IBM to build a portion of the parts for
IBM internal needs.


>
>I don't know, but if it is it would give IBM a price advantage even after
>the first 6months...  (on their PCs)

Probably a perceived "feature" advantage.

>
>>Also, what kind of incremental/marginal gain is there to clock tripling?
>>Does this chip have extra cache to compensate for the additional I/O burden?
With the DX2-66 parts, we have generally seen that we get 10% to 30% higher
performance than the a DX-50 on DOS applications.  On UNIX applications,
we see a SPECint89 and SPECint92 about 15% higher on the DX2-66.  I
would expect that at some point the ability of the bus to feed the chip
will limit the improvements.

>
>I would assume they have at least as much cache as their 486SXL, but I
>don't know.  Even if it has NO extra cache the tripled clock would help
>a great deal on floating point ops.  How much more on-chip cache would

Since this part is a 386 derivative, its floating point is off-chip and
since the bus is not faster, I would expect that only the "integer"
portion of floating point benchmarks will improve in performance.  You
will see improvement but none from the floating point.

>it need to signifagntly effect the integer speed (assuming most of the
>int instructions are the one cycle kind...)?  And if IBM can make
>a 486 run at 99Mhz what could they have done with a SPARC/MIPS/generic
>RISC CPU?
>--
>           [e-mail]              "Security for Unix is like
>      Josh_Osborne@Real_World,The          Multitasking for MS-DOS"
>      "The dyslexic porgramer"                  - Kevin Lockwood
>We all agree on the necessity of compromise.  We just can't agree on
>when it's necessary to compromise.       - Larry Wall


Rod Skinner                I speak for myself only.
Intel Corp
2200 Mission College Blvd RN4-21          PH [phone]
Santa Clara, CA 95052                     FAX [phone]