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- From: snyder@ricks.enet.dec.com (Wilson P. Snyder II)
- Subject: Re: DEC Alpha AXP System INTEGER Performance
- In-Reply-To: eoahmad@ntuix.ntu.ac.sg's message of Mon, 16 Nov 1992 05:58:33 GMT
- Message-ID: <SNYDER.92Nov16160318@LARGO.enet.dec.com>
- Lines: 22
- Sender: news@ryn.mro4.dec.com (USENET News System)
- Organization: Digital Equipment Corp., Hudson, MA.
- References: <1698@niktow.canisius.edu> <1992Nov16.055833.14566@ntuix.ntu.ac.sg>
- Date: 16 Nov 92 20:03:18 GMT
-
- In article <1992Nov16.055833.14566@ntuix.ntu.ac.sg> eoahmad@ntuix.ntu.ac.sg (Othman Ahmad) writes:
-
- >Greg Pavlov (pavlov@niktow.canisius.edu) wrote:
- >The bus clock for alpha is much lower. If I remember correctly it is only
- >half that or even worse(33Mhz?).
- > With 64 bits, the amount of data and instruction that can be cached
- >is much smaller so the internal cache is not as effective as many people
- >thought, especially in this newsgroup.
-
- Er, not really. The bus clock (called the system clock) is a integer
- multiple of the cpu clock period. IF you have a 6ns CPU, the less
- aggressive path is to choose say 30ns (*5) to give a 33 Mhz bus. Of course
- the faster machines such as Laser do much better. (I don't know the
- number.)
-
- Also, the cache access is NOT based upon the system clock. You program the
- cache read and write timing seperately as a number of cpu cycles, which is
- normally able to be faster then the system clock time. One system I know
- of with a 30 ns bus has a 24 ns cache read loop (for 6 ns CPU),
- others can do better.
-
- -Wilson Snyder
-