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- From: eoahmad@ntuix.ntu.ac.sg (Othman Ahmad)
- Subject: Re: Registerless processor
- Message-ID: <1992Nov17.042935.1962@ntuix.ntu.ac.sg>
- Organization: Nanyang Technological University - Singapore
- X-Newsreader: TIN [version 1.1 PL6]
- References: <1992Nov13.181654.11692@fcom.cc.utah.edu>
- Date: Tue, 17 Nov 1992 04:29:35 GMT
- Lines: 28
-
- Darren R. Davis (drdavis@u.cc.utah.edu) wrote:
- : I have been pondering an idea for a machine architecture. A processor
- : that has no registers. I am familiar with some architectures that have
- : done this. My twist on this theme is to have a very large cache on chip
- : for memory locations (effectivelly becoming registers). This goes
- : against the RISC idea of having very large register sets with load store
- : instructions. This machine would just reference memory, and the most
- : common addresses becoming cached internally to the processor giving very
- : fast access. Does anyone know of such a machine, and what are your
- : thoughts on this kind of architecture. I envision the cache being
-
- I have been thinking about this for some time now.
- First, you have broken the law as stated by H&P book.
- The major problem that you have to face is the large number of address bits,
- required to access your data. 32-bit per operand is rather large.
-
- To solve this you have 2 choices:
-
- i) stacks,
- ii) data compression,
-
-
- --
- Othman bin Ahmad, School of EEE,
- Nanyang Technological University, Singapore 2263.
- Internet Email: eoahmad@ntuix.ntu.ac.sg
- Bitnet Email: eoahmad@ntuvax.bitnet
-
-