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Text File | 1996-05-28 | 151.4 KB | 4,481 lines |
- #
- # $Id: stl00017.da@ 2.18 1996/05/14 01:54:18 JIMK Stable $
- #
- # Copyright (C) 1995, Diamond Multimedia Systems.
- #
- # File: stl00017.dat
- #
- # Purpose: This file contains the board and mode information for a
- # Stealth 64 Video VRAM: S3 968, 4MB, IBM 526 175Mhz DAC.
- #
- #
-
-
-
-
- [Objects]
- Draweng32=s3x6832.drw
- Dac=ibm525.dac
- Cursor=ibm525.cur
- PixClk=ibm525.clk
- Draweng=s3x68.drw
-
- [BoardInfo]
- wMinimumFormatBltWidth16bpp=8
- wMinimumFormatBltWidth32bpp=8
- bPixelFormatter=1
- bViewports=1
- bNewMMIO=1
- bTwoPtLine=1
- ValidateBAR=YES
- SwapVLA30A25=YES
-
- [Desktops]
- 2048,1536,8
- 2048,768,8
- 1600,1200,16
- 1600,1200,8
- 1280,1024,24
- 1280,1024,16
- 1280,1024,8
- 1152,864,32
- 1152,864,24
- 1152,864,16
- 1152,864,8
- 1024,3072,8
- 1024,1536,16
- 1024,1536,8
- 1024,768,32
- 1024,768,24
- 1024,768,16
- 1024,768,8
- 800,600,32
- 800,600,24
- 800,600,16
- 800,600,8
- 640,480,32
- 640,480,24
- 640,480,16
- 640,480,8
-
- [Viewports]
- 1600,1200,16,82,66
- 1600,1200,16,75,60
- 1600,1200,8,82,66
- 1600,1200,8,75,60
- 1280,1024,24,79,75
- 1280,1024,24,76,72
- 1280,1024,24,74,70
- 1280,1024,24,64,60
- 1280,1024,16,95,90
- 1280,1024,16,79,75
- 1280,1024,16,76,72
- 1280,1024,16,74,70
- 1280,1024,16,64,60
- 1280,1024,8,95,90
- 1280,1024,8,79,75
- 1280,1024,8,76,72
- 1280,1024,8,74,70
- 1280,1024,8,64,60
- 1152,864,32,64,70
- 1152,864,32,56,60
- 1152,864,24,64,70
- 1152,864,24,56,60
- 1152,864,16,82,90
- 1152,864,16,71,75
- 1152,864,16,64,70
- 1152,864,16,56,60
- 1152,864,8,82,90
- 1152,864,8,71,75
- 1152,864,8,64,70
- 1152,864,8,56,60
- 1024,768,32,64,80
- 1024,768,32,60,75
- 1024,768,32,58,72
- 1024,768,32,56,70
- 1024,768,32,48,60
- 1024,768,24,64,80
- 1024,768,24,60,75
- 1024,768,24,58,72
- 1024,768,24,56,70
- 1024,768,24,48,60
- 1024,768,16,96,120
- 1024,768,16,81,100
- 1024,768,16,64,80
- 1024,768,16,60,75
- 1024,768,16,58,72
- 1024,768,16,56,70
- 1024,768,16,48,60
- 1024,768,8,96,120
- 1024,768,8,81,100
- 1024,768,8,64,80
- 1024,768,8,60,75
- 1024,768,8,58,72
- 1024,768,8,56,70
- 1024,768,8,48,60
- 800,600,32,75,120
- 800,600,32,64,100
- 800,600,32,56,90
- 800,600,32,46,75
- 800,600,32,48,72
- 800,600,32,37,60
- 800,600,32,35,56
- 800,600,24,75,120
- 800,600,24,64,100
- 800,600,24,56,90
- 800,600,24,46,75
- 800,600,24,48,72
- 800,600,24,37,60
- 800,600,24,35,56
- 800,600,16,75,120
- 800,600,16,64,100
- 800,600,16,56,90
- 800,600,16,46,75
- 800,600,16,48,72
- 800,600,16,37,60
- 800,600,16,35,56
- 800,600,8,75,120
- 800,600,8,64,100
- 800,600,8,56,90
- 800,600,8,46,75
- 800,600,8,48,72
- 800,600,8,37,60
- 800,600,8,35,56
- 640,480,32,64,120
- 640,480,32,52,100
- 640,480,32,48,90
- 640,480,32,37,75
- 640,480,32,37,72
- 640,480,32,31,60
- 640,480,24,64,120
- 640,480,24,52,100
- 640,480,24,48,90
- 640,480,24,37,75
- 640,480,24,37,72
- 640,480,24,31,60
- 640,480,16,64,120
- 640,480,16,52,100
- 640,480,16,48,90
- 640,480,16,37,75
- 640,480,16,37,72
- 640,480,16,31,60
- 640,480,8,64,120
- 640,480,8,52,100
- 640,480,8,48,90
- 640,480,8,37,75
- 640,480,8,37,72
- 640,480,8,31,60
-
- [TextMode]
- CRT, RUN, EXTENDED_BIOS_FLAGS_2, 1
- SHELL, I10, 0x0003, 0x0000
- CRT, RUN, REG_LOCK_1, 0x48
- CRT, RUN, REG_LOCK_2, 0xA5
-
- [GraphicsEnable]
- CRT, RMW, LAW_CONTROL, 0xEC, 0x13
- CRT, RMW, EXT_MEM_CONTROL_1, 0xE4, 0x18
-
- [GraphicsDisable]
- CRT, RMW, LAW_CONTROL, 0xEC, 0x00
- CRT, RMW, EXT_MEM_CONTROL_1, 0xE4, 0x00
-
- [2048,1536,8]
- # Setting Line Pitch
- CRT,RUN,LOGICAL_LINE_LENGTH,0x00
- CRT,RUN,EXT_MODE,0x00
- CRT,RUN,EXT_SYSTEM_CONTROL_2,0x10
- # Setting Engine Pitch
- CRT,RUN,EXT_SYSTEM_CONTROL_1,0x00
- CRT,RUN,MEM_CONFIG,0x8f
- # Setting Basic Mode Registers.The registers
- # below are neither Desktop or Viewport Regs
- # Unlock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x06
- # Dump Sequencer Registers
- SEQ,RUN,CLOCKING_MODE,0x21,0x0f,0x00,0x0e,0x00
- # Dump Graphics Controller Registers
- GRX,RUN,SET_RESET_DATA,0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f,0xff
- # Dump Attribute Controller Registers
- ATR,RUN,PALETTE_0,0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x01,0x00,0x0f,0x00,0x00
- # Lock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x00
- DAC_IDR, RUN, DAC_OPERATION, 0x02
- DAC_IDR, RUN, VRAM_MASK_LOW, 0x03
- DAC_IDR, RUN, MISC_CONTROL_1, 0x00
- DAC_IDR, RUN, MISC_CONTROL_2, 0x04
- DAC_IDR, RUN, MISC_CONTROL_3, 0x00
- DAC_IDR, RUN, PIXEL_FORMAT, 0x03
- DAC_IDR, RUN, PIXEL_8BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_16BPP_CONTROL, 0xc2
- DAC_IDR, RUN, PIXEL_24BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_32BPP_CONTROL, 0x03
-
- [2048,768,8]
- # Setting Line Pitch
- CRT,RUN,LOGICAL_LINE_LENGTH,0x00
- CRT,RUN,EXT_MODE,0x00
- CRT,RUN,EXT_SYSTEM_CONTROL_2,0x10
- # Setting Engine Pitch
- CRT,RUN,EXT_SYSTEM_CONTROL_1,0x00
- CRT,RUN,MEM_CONFIG,0x8f
- # Setting Basic Mode Registers.The registers
- # below are neither Desktop or Viewport Regs
- # Unlock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x06
- # Dump Sequencer Registers
- SEQ,RUN,CLOCKING_MODE,0x01,0x0f,0x00,0x0e,0x00
- # Dump Graphics Controller Registers
- GRX,RUN,SET_RESET_DATA,0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f,0xff
- # Dump Attribute Controller Registers
- ATR,RUN,PALETTE_0,0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x01,0x00,0x0f,0x00,0x00
- # Lock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x00
- DAC_IDR, RUN, DAC_OPERATION, 0x02
- DAC_IDR, RUN, VRAM_MASK_LOW, 0x03
- DAC_IDR, RUN, MISC_CONTROL_1, 0x00
- DAC_IDR, RUN, MISC_CONTROL_2, 0x04
- DAC_IDR, RUN, MISC_CONTROL_3, 0x00
- DAC_IDR, RUN, PIXEL_FORMAT, 0x03
- DAC_IDR, RUN, PIXEL_8BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_16BPP_CONTROL, 0xc2
- DAC_IDR, RUN, PIXEL_24BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_32BPP_CONTROL, 0x03
-
- [1024,3072,8]
- # Setting Line Pitch
- CRT,RUN,LOGICAL_LINE_LENGTH,0x80
- CRT,RUN,EXT_MODE,0x00
- CRT,RUN,EXT_SYSTEM_CONTROL_2,0x00
- # Setting Engine Pitch
- CRT,RUN,EXT_SYSTEM_CONTROL_1,0x00
- CRT,RUN,MEM_CONFIG,0x09
- # Setting Basic Mode Registers.The registers
- # below are neither Desktop or Viewport Regs
- # Unlock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x06
- # Dump Sequencer Registers
- SEQ,RUN,CLOCKING_MODE,0x01,0x0f,0x00,0x0e,0x00
- # Dump Graphics Controller Registers
- GRX,RUN,SET_RESET_DATA,0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f,0xff
- # Dump Attribute Controller Registers
- ATR,RUN,PALETTE_0,0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x01,0x00,0x0f,0x00,0x00
- # Lock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x00
- DAC_IDR, RUN, DAC_OPERATION, 0x02
- DAC_IDR, RUN, VRAM_MASK_LOW, 0x03
- DAC_IDR, RUN, MISC_CONTROL_1, 0x00
- DAC_IDR, RUN, MISC_CONTROL_2, 0x04
- DAC_IDR, RUN, MISC_CONTROL_3, 0x00
- DAC_IDR, RUN, PIXEL_FORMAT, 0x03
- DAC_IDR, RUN, PIXEL_8BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_16BPP_CONTROL, 0xc2
- DAC_IDR, RUN, PIXEL_24BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_32BPP_CONTROL, 0x03
-
- [1024,1536,8]
- # Setting Line Pitch
- CRT,RUN,LOGICAL_LINE_LENGTH,0x80
- CRT,RUN,EXT_MODE,0x00
- CRT,RUN,EXT_SYSTEM_CONTROL_2,0x00
- # Setting Engine Pitch
- CRT,RUN,EXT_SYSTEM_CONTROL_1,0x00
- CRT,RUN,MEM_CONFIG,0x09
- # Setting Basic Mode Registers.The registers
- # below are neither Desktop or Viewport Regs
- # Unlock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x06
- # Dump Sequencer Registers
- SEQ,RUN,CLOCKING_MODE,0x01,0x0f,0x00,0x0e,0x00
- # Dump Graphics Controller Registers
- GRX,RUN,SET_RESET_DATA,0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f,0xff
- # Dump Attribute Controller Registers
- ATR,RUN,PALETTE_0,0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x01,0x00,0x0f,0x00,0x00
- # Lock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x00
- DAC_IDR, RUN, DAC_OPERATION, 0x02
- DAC_IDR, RUN, VRAM_MASK_LOW, 0x03
- DAC_IDR, RUN, MISC_CONTROL_1, 0x00
- DAC_IDR, RUN, MISC_CONTROL_2, 0x04
- DAC_IDR, RUN, MISC_CONTROL_3, 0x00
- DAC_IDR, RUN, PIXEL_FORMAT, 0x03
- DAC_IDR, RUN, PIXEL_8BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_16BPP_CONTROL, 0xc2
- DAC_IDR, RUN, PIXEL_24BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_32BPP_CONTROL, 0x03
-
- [1024,1536,16]
- # Setting Line Pitch
- CRT,RUN,LOGICAL_LINE_LENGTH,0x00
- CRT,RUN,EXT_MODE,0x00
- CRT,RUN,EXT_SYSTEM_CONTROL_2,0x10
- # Setting Engine Pitch
- CRT,RUN,EXT_SYSTEM_CONTROL_1,0x10
- CRT,RUN,MEM_CONFIG,0x89
- # Setting Basic Mode Registers.The registers
- # below are neither Desktop or Viewport Regs
- # Unlock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x06
- # Dump Sequencer Registers
- SEQ,RUN,CLOCKING_MODE,0x01,0x0f,0x00,0x0e,0x00
- # Dump Graphics Controller Registers
- GRX,RUN,SET_RESET_DATA,0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f,0xff
- # Dump Attribute Controller Registers
- ATR,RUN,PALETTE_0,0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x01,0x00,0x0f,0x00,0x00
- # Lock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x00
- DAC_IDR, RUN, DAC_OPERATION, 0x02
- DAC_IDR, RUN, VRAM_MASK_LOW, 0x03
- DAC_IDR, RUN, MISC_CONTROL_1, 0x00
- DAC_IDR, RUN, MISC_CONTROL_2, 0x00
- DAC_IDR, RUN, MISC_CONTROL_3, 0x00
- DAC_IDR, RUN, PIXEL_FORMAT, 0x04
- DAC_IDR, RUN, PIXEL_8BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_16BPP_CONTROL, 0xc2
- DAC_IDR, RUN, PIXEL_24BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_32BPP_CONTROL, 0x03
-
- [1600,1200,16]
- # Setting Line Pitch
- CRT,RUN,LOGICAL_LINE_LENGTH,0x90
- CRT,RUN,EXT_MODE,0x00
- CRT,RUN,EXT_SYSTEM_CONTROL_2,0x10
- # Setting Engine Pitch
- CRT,RUN,EXT_SYSTEM_CONTROL_1,0x91
- CRT,RUN,MEM_CONFIG,0x8b
- # Setting Basic Mode Registers.The registers
- # below are neither Desktop or Viewport Regs
- # Unlock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x06
- # Dump Sequencer Registers
- SEQ,RUN,CLOCKING_MODE,0x21,0x0f,0x00,0x0e,0x00
- # Dump Graphics Controller Registers
- GRX,RUN,SET_RESET_DATA,0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f,0xff
- # Dump Attribute Controller Registers
- ATR,RUN,PALETTE_0,0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x01,0x00,0x0f,0x00,0x00
- # Lock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x00
- DAC_IDR, RUN, DAC_OPERATION, 0x02
- DAC_IDR, RUN, VRAM_MASK_LOW, 0x03
- DAC_IDR, RUN, MISC_CONTROL_1, 0x00
- DAC_IDR, RUN, MISC_CONTROL_2, 0x00
- DAC_IDR, RUN, MISC_CONTROL_3, 0x00
- DAC_IDR, RUN, PIXEL_FORMAT, 0x04
- DAC_IDR, RUN, PIXEL_8BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_16BPP_CONTROL, 0xc2
- DAC_IDR, RUN, PIXEL_24BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_32BPP_CONTROL, 0x03
-
- [1600,1200,8]
- # Setting Line Pitch
- CRT,RUN,LOGICAL_LINE_LENGTH,0xc8
- CRT,RUN,EXT_MODE,0x00
- CRT,RUN,EXT_SYSTEM_CONTROL_2,0x00
- # Setting Engine Pitch
- CRT,RUN,EXT_SYSTEM_CONTROL_1,0x81
- CRT,RUN,MEM_CONFIG,0x8b
- # Setting Basic Mode Registers.The registers
- # below are neither Desktop or Viewport Regs
- # Unlock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x06
- # Dump Sequencer Registers
- SEQ,RUN,CLOCKING_MODE,0x21,0x0f,0x00,0x0e,0x00
- # Dump Graphics Controller Registers
- GRX,RUN,SET_RESET_DATA,0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f,0xff
- # Dump Attribute Controller Registers
- ATR,RUN,PALETTE_0,0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x01,0x00,0x0f,0x00,0x00
- # Lock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x00
- DAC_IDR, RUN, DAC_OPERATION, 0x02
- DAC_IDR, RUN, VRAM_MASK_LOW, 0x03
- DAC_IDR, RUN, MISC_CONTROL_1, 0x00
- DAC_IDR, RUN, MISC_CONTROL_2, 0x04
- DAC_IDR, RUN, MISC_CONTROL_3, 0x00
- DAC_IDR, RUN, PIXEL_FORMAT, 0x03
- DAC_IDR, RUN, PIXEL_8BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_16BPP_CONTROL, 0xc2
- DAC_IDR, RUN, PIXEL_24BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_32BPP_CONTROL, 0x03
-
- [1280,1024,24]
- # Setting Line Pitch
- CRT,RUN,LOGICAL_LINE_LENGTH,0xe0
- CRT,RUN,EXT_MODE,0x00
- CRT,RUN,EXT_SYSTEM_CONTROL_2,0x10
- # Setting Engine Pitch
- CRT,RUN,EXT_SYSTEM_CONTROL_1,0xe0
- CRT,RUN,MEM_CONFIG,0x8b
- # Setting Basic Mode Registers.The registers
- # below are neither Desktop or Viewport Regs
- # Unlock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x06
- # Dump Sequencer Registers
- SEQ,RUN,CLOCKING_MODE,0x21,0x0f,0x00,0x0e,0x00
- # Dump Graphics Controller Registers
- GRX,RUN,SET_RESET_DATA,0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f,0xff
- # Dump Attribute Controller Registers
- ATR,RUN,PALETTE_0,0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x01,0x00,0x0f,0x00,0x00
- # Lock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x00
- DAC_IDR, RUN, DAC_OPERATION, 0x02
- DAC_IDR, RUN, VRAM_MASK_LOW, 0x03
- DAC_IDR, RUN, MISC_CONTROL_1, 0x00
- DAC_IDR, RUN, MISC_CONTROL_2, 0x00
- DAC_IDR, RUN, MISC_CONTROL_3, 0x00
- DAC_IDR, RUN, PIXEL_FORMAT, 0x05
- DAC_IDR, RUN, PIXEL_8BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_16BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_24BPP_CONTROL, 0x01
- DAC_IDR, RUN, PIXEL_32BPP_CONTROL, 0x00
-
- [1280,1024,16]
- # Setting Line Pitch
- CRT,RUN,LOGICAL_LINE_LENGTH,0x40
- CRT,RUN,EXT_MODE,0x00
- CRT,RUN,EXT_SYSTEM_CONTROL_2,0x10
- # Setting Engine Pitch
- CRT,RUN,EXT_SYSTEM_CONTROL_1,0xd0
- CRT,RUN,MEM_CONFIG,0x8b
- # Setting Basic Mode Registers.The registers
- # below are neither Desktop or Viewport Regs
- # Unlock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x06
- # Dump Sequencer Registers
- SEQ,RUN,CLOCKING_MODE,0x21,0x0f,0x00,0x0e,0x00
- # Dump Graphics Controller Registers
- GRX,RUN,SET_RESET_DATA,0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f,0xff
- # Dump Attribute Controller Registers
- ATR,RUN,PALETTE_0,0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x01,0x00,0x0f,0x00,0x00
- # Lock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x00
- DAC_IDR, RUN, DAC_OPERATION, 0x02
- DAC_IDR, RUN, VRAM_MASK_LOW, 0x03
- DAC_IDR, RUN, MISC_CONTROL_1, 0x00
- DAC_IDR, RUN, MISC_CONTROL_2, 0x00
- DAC_IDR, RUN, MISC_CONTROL_3, 0x00
- DAC_IDR, RUN, PIXEL_FORMAT, 0x04
- DAC_IDR, RUN, PIXEL_8BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_16BPP_CONTROL, 0xc2
- DAC_IDR, RUN, PIXEL_24BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_32BPP_CONTROL, 0x03
-
- [1280,1024,8]
- # Setting Line Pitch
- CRT,RUN,LOGICAL_LINE_LENGTH,0xa0
- CRT,RUN,EXT_MODE,0x00
- CRT,RUN,EXT_SYSTEM_CONTROL_2,0x00
- # Setting Engine Pitch
- CRT,RUN,EXT_SYSTEM_CONTROL_1,0xc0
- CRT,RUN,MEM_CONFIG,0x0b
- # Setting Basic Mode Registers.The registers
- # below are neither Desktop or Viewport Regs
- # Unlock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x06
- # Dump Sequencer Registers
- SEQ,RUN,CLOCKING_MODE,0x21,0x0f,0x00,0x0e,0x00
- # Dump Graphics Controller Registers
- GRX,RUN,SET_RESET_DATA,0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f,0xff
- # Dump Attribute Controller Registers
- ATR,RUN,PALETTE_0,0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x01,0x00,0x0f,0x00,0x00
- # Lock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x00
- DAC_IDR, RUN, DAC_OPERATION, 0x02
- DAC_IDR, RUN, VRAM_MASK_LOW, 0x03
- DAC_IDR, RUN, MISC_CONTROL_1, 0x00
- DAC_IDR, RUN, MISC_CONTROL_2, 0x04
- DAC_IDR, RUN, MISC_CONTROL_3, 0x00
- DAC_IDR, RUN, PIXEL_FORMAT, 0x03
- DAC_IDR, RUN, PIXEL_8BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_16BPP_CONTROL, 0xc2
- DAC_IDR, RUN, PIXEL_24BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_32BPP_CONTROL, 0x03
-
- [1152,864,32]
- CRT,RUN,LOGICAL_LINE_LENGTH,0x40
- CRT,RUN,EXT_MODE,0x00
- CRT,RUN,EXT_SYSTEM_CONTROL_2,0x20
- CRT,RUN,EXT_SYSTEM_CONTROL_1,0x31
- CRT,RUN,MEM_CONFIG,0x89
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x06
- SEQ,RUN,CLOCKING_MODE,0x21,0x0f,0x00,0x0e,0x00
- GRX,RUN,SET_RESET_DATA,0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f,0xff
- ATR,RUN,PALETTE_0,0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x01,0x00,0x0f,0x00,0x00
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x00
- DAC_IDR, RUN, DAC_OPERATION, 0x02
- DAC_IDR, RUN, VRAM_MASK_LOW, 0x03
- DAC_IDR, RUN, MISC_CONTROL_1, 0x00
- DAC_IDR, RUN, MISC_CONTROL_2, 0x04
- DAC_IDR, RUN, MISC_CONTROL_3, 0x00
- DAC_IDR, RUN, PIXEL_FORMAT, 0x06
- DAC_IDR, RUN, PIXEL_8BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_16BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_24BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_32BPP_CONTROL, 0x03
-
- [1152,864,24]
- # Setting Line Pitch
- CRT,RUN,LOGICAL_LINE_LENGTH,0xb0
- CRT,RUN,EXT_MODE,0x00
- CRT,RUN,EXT_SYSTEM_CONTROL_2,0x10
- # Setting Engine Pitch
- CRT,RUN,EXT_SYSTEM_CONTROL_1,0x21
- CRT,RUN,MEM_CONFIG,0x8b
- # Setting Basic Mode Registers.The registers
- # below are neither Desktop or Viewport Regs
- # Unlock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x06
- # Dump Sequencer Registers
- SEQ,RUN,CLOCKING_MODE,0x21,0x0f,0x00,0x0e,0x00
- # Dump Graphics Controller Registers
- GRX,RUN,SET_RESET_DATA,0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f,0xff
- # Dump Attribute Controller Registers
- ATR,RUN,PALETTE_0,0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x01,0x00,0x0f,0x00,0x00
- # Lock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x00
- DAC_IDR, RUN, DAC_OPERATION, 0x02
- DAC_IDR, RUN, VRAM_MASK_LOW, 0x03
- DAC_IDR, RUN, MISC_CONTROL_1, 0x00
- DAC_IDR, RUN, MISC_CONTROL_2, 0x00
- DAC_IDR, RUN, MISC_CONTROL_3, 0x00
- DAC_IDR, RUN, PIXEL_FORMAT, 0x05
- DAC_IDR, RUN, PIXEL_8BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_16BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_24BPP_CONTROL, 0x01
- DAC_IDR, RUN, PIXEL_32BPP_CONTROL, 0x00
-
- [1152,864,16]
- # Setting Line Pitch
- CRT,RUN,LOGICAL_LINE_LENGTH,0x20
- CRT,RUN,EXT_MODE,0x00
- CRT,RUN,EXT_SYSTEM_CONTROL_2,0x10
- # Setting Engine Pitch
- CRT,RUN,EXT_SYSTEM_CONTROL_1,0x11
- CRT,RUN,MEM_CONFIG,0x8b
- # Setting Basic Mode Registers.The registers
- # below are neither Desktop or Viewport Regs
- # Unlock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x06
- # Dump Sequencer Registers
- SEQ,RUN,CLOCKING_MODE,0x21,0x0f,0x00,0x0e,0x00
- # Dump Graphics Controller Registers
- GRX,RUN,SET_RESET_DATA,0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f,0xff
- # Dump Attribute Controller Registers
- ATR,RUN,PALETTE_0,0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x01,0x00,0x0f,0x00,0x00
- # Lock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x00
- DAC_IDR, RUN, DAC_OPERATION, 0x02
- DAC_IDR, RUN, VRAM_MASK_LOW, 0x03
- DAC_IDR, RUN, MISC_CONTROL_1, 0x00
- DAC_IDR, RUN, MISC_CONTROL_2, 0x00
- DAC_IDR, RUN, MISC_CONTROL_3, 0x00
- DAC_IDR, RUN, PIXEL_FORMAT, 0x04
- DAC_IDR, RUN, PIXEL_8BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_16BPP_CONTROL, 0xc2
- DAC_IDR, RUN, PIXEL_24BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_32BPP_CONTROL, 0x03
-
- [1152,864,8]
- # Setting Line Pitch
- CRT,RUN,LOGICAL_LINE_LENGTH,0x90
- CRT,RUN,EXT_MODE,0x00
- CRT,RUN,EXT_SYSTEM_CONTROL_2,0x00
- # Setting Engine Pitch
- CRT,RUN,EXT_SYSTEM_CONTROL_1,0x01
- CRT,RUN,MEM_CONFIG,0x89
- # Setting Basic Mode Registers.The registers
- # below are neither Desktop or Viewport Regs
- # Unlock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x06
- # Dump Sequencer Registers
- SEQ,RUN,CLOCKING_MODE,0x21,0x0f,0x00,0x0e,0x00
- # Dump Graphics Controller Registers
- GRX,RUN,SET_RESET_DATA,0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f,0xff
- # Dump Attribute Controller Registers
- ATR,RUN,PALETTE_0,0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x01,0x00,0x0f,0x00,0x00
- # Lock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x00
- DAC_IDR, RUN, DAC_OPERATION, 0x02
- DAC_IDR, RUN, VRAM_MASK_LOW, 0x03
- DAC_IDR, RUN, MISC_CONTROL_1, 0x00
- DAC_IDR, RUN, MISC_CONTROL_2, 0x04
- DAC_IDR, RUN, MISC_CONTROL_3, 0x00
- DAC_IDR, RUN, PIXEL_FORMAT, 0x03
- DAC_IDR, RUN, PIXEL_8BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_16BPP_CONTROL, 0xc2
- DAC_IDR, RUN, PIXEL_24BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_32BPP_CONTROL, 0x03
-
- [1024,768,32]
- CRT,RUN,LOGICAL_LINE_LENGTH,0x00
- CRT,RUN,EXT_MODE,0x00
- CRT,RUN,EXT_SYSTEM_CONTROL_2,0x20
- CRT,RUN,EXT_SYSTEM_CONTROL_1,0x30
- CRT,RUN,MEM_CONFIG,0x89
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x06
- SEQ,RUN,CLOCKING_MODE,0x21,0x0f,0x00,0x0e,0x00
- GRX,RUN,SET_RESET_DATA,0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f,0xff
- ATR,RUN,PALETTE_0,0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x01,0x00,0x0f,0x00,0x00
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x00
- DAC_IDR, RUN, DAC_OPERATION, 0x02
- DAC_IDR, RUN, VRAM_MASK_LOW, 0x03
- DAC_IDR, RUN, MISC_CONTROL_1, 0x00
- DAC_IDR, RUN, MISC_CONTROL_2, 0x04
- DAC_IDR, RUN, MISC_CONTROL_3, 0x00
- DAC_IDR, RUN, PIXEL_FORMAT, 0x06
- DAC_IDR, RUN, PIXEL_8BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_16BPP_CONTROL, 0xc2
- DAC_IDR, RUN, PIXEL_24BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_32BPP_CONTROL, 0x03
-
- [1024,768,24]
- # Setting Line Pitch
- CRT,RUN,LOGICAL_LINE_LENGTH,0x80
- CRT,RUN,EXT_MODE,0x00
- CRT,RUN,EXT_SYSTEM_CONTROL_2,0x10
- # Setting Engine Pitch
- CRT,RUN,EXT_SYSTEM_CONTROL_1,0x20
- CRT,RUN,MEM_CONFIG,0x89
- # Setting Basic Mode Registers.The registers
- # below are neither Desktop or Viewport Regs
- # Unlock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x06
- # Dump Sequencer Registers
- SEQ,RUN,CLOCKING_MODE,0x21,0x0f,0x00,0x0e,0x00
- # Dump Graphics Controller Registers
- GRX,RUN,SET_RESET_DATA,0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f,0xff
- # Dump Attribute Controller Registers
- ATR,RUN,PALETTE_0,0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x01,0x00,0x0f,0x00,0x00
- # Lock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x00
- DAC_IDR, RUN, DAC_OPERATION, 0x02
- DAC_IDR, RUN, VRAM_MASK_LOW, 0x03
- DAC_IDR, RUN, MISC_CONTROL_1, 0x00
- DAC_IDR, RUN, MISC_CONTROL_2, 0x00
- DAC_IDR, RUN, MISC_CONTROL_3, 0x00
- DAC_IDR, RUN, PIXEL_FORMAT, 0x05
- DAC_IDR, RUN, PIXEL_8BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_16BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_24BPP_CONTROL, 0x01
- DAC_IDR, RUN, PIXEL_32BPP_CONTROL, 0x00
-
- [1024,768,16]
- # Setting Line Pitch
- CRT,RUN,LOGICAL_LINE_LENGTH,0x00
- CRT,RUN,EXT_MODE,0x00
- CRT,RUN,EXT_SYSTEM_CONTROL_2,0x10
- # Setting Engine Pitch
- CRT,RUN,EXT_SYSTEM_CONTROL_1,0x10
- CRT,RUN,MEM_CONFIG,0x89
- # Setting Basic Mode Registers.The registers
- # below are neither Desktop or Viewport Regs
- # Unlock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x06
- # Dump Sequencer Registers
- SEQ,RUN,CLOCKING_MODE,0x21,0x0f,0x00,0x0e,0x00
- # Dump Graphics Controller Registers
- GRX,RUN,SET_RESET_DATA,0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f,0xff
- # Dump Attribute Controller Registers
- ATR,RUN,PALETTE_0,0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x01,0x00,0x0f,0x00,0x00
- # Lock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x00
- DAC_IDR, RUN, DAC_OPERATION, 0x02
- DAC_IDR, RUN, VRAM_MASK_LOW, 0x03
- DAC_IDR, RUN, MISC_CONTROL_1, 0x00
- DAC_IDR, RUN, MISC_CONTROL_2, 0x00
- DAC_IDR, RUN, MISC_CONTROL_3, 0x00
- DAC_IDR, RUN, PIXEL_FORMAT, 0x04
- DAC_IDR, RUN, PIXEL_8BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_16BPP_CONTROL, 0xc2
- DAC_IDR, RUN, PIXEL_24BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_32BPP_CONTROL, 0x03
-
- [1024,768,8]
- # Setting Line Pitch
- CRT,RUN,LOGICAL_LINE_LENGTH,0x80
- CRT,RUN,EXT_MODE,0x00
- CRT,RUN,EXT_SYSTEM_CONTROL_2,0x00
- # Setting Engine Pitch
- CRT,RUN,EXT_SYSTEM_CONTROL_1,0x00
- CRT,RUN,MEM_CONFIG,0x09
- # Setting Basic Mode Registers.The registers
- # below are neither Desktop or Viewport Regs
- # Unlock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x06
- # Dump Sequencer Registers
- SEQ,RUN,CLOCKING_MODE,0x21,0x0f,0x00,0x0e,0x00
- # Dump Graphics Controller Registers
- GRX,RUN,SET_RESET_DATA,0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f,0xff
- # Dump Attribute Controller Registers
- ATR,RUN,PALETTE_0,0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x01,0x00,0x0f,0x00,0x00
- # Lock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x00
- DAC_IDR, RUN, DAC_OPERATION, 0x02
- DAC_IDR, RUN, VRAM_MASK_LOW, 0x03
- DAC_IDR, RUN, MISC_CONTROL_1, 0x00
- DAC_IDR, RUN, MISC_CONTROL_2, 0x04
- DAC_IDR, RUN, MISC_CONTROL_3, 0x00
- DAC_IDR, RUN, PIXEL_FORMAT, 0x03
- DAC_IDR, RUN, PIXEL_8BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_16BPP_CONTROL, 0xc2
- DAC_IDR, RUN, PIXEL_24BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_32BPP_CONTROL, 0x03
-
- [800,600,32]
- # Setting Line Pitch
- CRT,RUN,LOGICAL_LINE_LENGTH,0x90
- CRT,RUN,EXT_MODE,0x00
- CRT,RUN,EXT_SYSTEM_CONTROL_2,0x10
- # Setting Engine Pitch
- CRT,RUN,EXT_SYSTEM_CONTROL_1,0xb0
- CRT,RUN,MEM_CONFIG,0x8b
- # Setting Basic Mode Registers.The registers
- # below are neither Desktop or Viewport Regs
- # Unlock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x06
- # Dump Sequencer Registers
- SEQ,RUN,CLOCKING_MODE,0x21,0x0f,0x00,0x0e,0x00
- # Dump Graphics Controller Registers
- GRX,RUN,SET_RESET_DATA,0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f,0xff
- # Dump Attribute Controller Registers
- ATR,RUN,PALETTE_0,0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x01,0x00,0x0f,0x00,0x00
- # Lock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x00
- DAC_IDR, RUN, DAC_OPERATION, 0x02
- DAC_IDR, RUN, VRAM_MASK_LOW, 0x03
- DAC_IDR, RUN, MISC_CONTROL_1, 0x00
- DAC_IDR, RUN, MISC_CONTROL_2, 0x00
- DAC_IDR, RUN, MISC_CONTROL_3, 0x00
- DAC_IDR, RUN, PIXEL_FORMAT, 0x06
- DAC_IDR, RUN, PIXEL_8BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_16BPP_CONTROL, 0xc2
- DAC_IDR, RUN, PIXEL_24BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_32BPP_CONTROL, 0x03
-
- [800,600,24]
- # Setting Line Pitch
- CRT,RUN,LOGICAL_LINE_LENGTH,0x2c
- CRT,RUN,EXT_MODE,0x00
- CRT,RUN,EXT_SYSTEM_CONTROL_2,0x10
- # Setting Engine Pitch
- CRT,RUN,EXT_SYSTEM_CONTROL_1,0xa0
- CRT,RUN,MEM_CONFIG,0x8b
- # Setting Basic Mode Registers.The registers
- # below are neither Desktop or Viewport Regs
- # Unlock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x06
- # Dump Sequencer Registers
- SEQ,RUN,CLOCKING_MODE,0x21,0x0f,0x00,0x0e,0x00
- # Dump Graphics Controller Registers
- GRX,RUN,SET_RESET_DATA,0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f,0xff
- # Dump Attribute Controller Registers
- ATR,RUN,PALETTE_0,0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x01,0x00,0x0f,0x00,0x00
- # Lock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x00
- DAC_IDR, RUN, DAC_OPERATION, 0x02
- DAC_IDR, RUN, VRAM_MASK_LOW, 0x03
- DAC_IDR, RUN, MISC_CONTROL_1, 0x00
- DAC_IDR, RUN, MISC_CONTROL_2, 0x00
- DAC_IDR, RUN, MISC_CONTROL_3, 0x00
- DAC_IDR, RUN, PIXEL_FORMAT, 0x05
- DAC_IDR, RUN, PIXEL_8BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_16BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_24BPP_CONTROL, 0x01
- DAC_IDR, RUN, PIXEL_32BPP_CONTROL, 0x00
-
- [800,600,16]
- # Setting Line Pitch
- CRT,RUN,LOGICAL_LINE_LENGTH,0xc8
- CRT,RUN,EXT_MODE,0x00
- CRT,RUN,EXT_SYSTEM_CONTROL_2,0x00
- # Setting Engine Pitch
- CRT,RUN,EXT_SYSTEM_CONTROL_1,0x90
- CRT,RUN,MEM_CONFIG,0x8b
- # Setting Basic Mode Registers.The registers
- # below are neither Desktop or Viewport Regs
- # Unlock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x06
- # Dump Sequencer Registers
- SEQ,RUN,CLOCKING_MODE,0x21,0x0f,0x00,0x0e,0x00
- # Dump Graphics Controller Registers
- GRX,RUN,SET_RESET_DATA,0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f,0xff
- # Dump Attribute Controller Registers
- ATR,RUN,PALETTE_0,0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x01,0x00,0x0f,0x00,0x00
- # Lock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x00
- DAC_IDR, RUN, DAC_OPERATION, 0x02
- DAC_IDR, RUN, VRAM_MASK_LOW, 0x03
- DAC_IDR, RUN, MISC_CONTROL_1, 0x00
- DAC_IDR, RUN, MISC_CONTROL_2, 0x00
- DAC_IDR, RUN, MISC_CONTROL_3, 0x00
- DAC_IDR, RUN, PIXEL_FORMAT, 0x04
- DAC_IDR, RUN, PIXEL_8BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_16BPP_CONTROL, 0xc2
- DAC_IDR, RUN, PIXEL_24BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_32BPP_CONTROL, 0x03
-
- [800,600,8]
- # Setting Line Pitch
- CRT,RUN,LOGICAL_LINE_LENGTH,0x64
- CRT,RUN,EXT_MODE,0x00
- CRT,RUN,EXT_SYSTEM_CONTROL_2,0x00
- # Setting Engine Pitch
- CRT,RUN,EXT_SYSTEM_CONTROL_1,0x80
- CRT,RUN,MEM_CONFIG,0x8b
- # Setting Basic Mode Registers.The registers
- # below are neither Desktop or Viewport Regs
- # Unlock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x06
- # Dump Sequencer Registers
- SEQ,RUN,CLOCKING_MODE,0x21,0x0f,0x00,0x0e,0x00
- # Dump Graphics Controller Registers
- GRX,RUN,SET_RESET_DATA,0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f,0xff
- # Dump Attribute Controller Registers
- ATR,RUN,PALETTE_0,0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x01,0x00,0x0f,0x00,0x00
- # Lock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x00
- DAC_IDR, RUN, DAC_OPERATION, 0x02
- DAC_IDR, RUN, VRAM_MASK_LOW, 0x03
- DAC_IDR, RUN, MISC_CONTROL_1, 0x00
- DAC_IDR, RUN, MISC_CONTROL_2, 0x04
- DAC_IDR, RUN, MISC_CONTROL_3, 0x00
- DAC_IDR, RUN, PIXEL_FORMAT, 0x03
- DAC_IDR, RUN, PIXEL_8BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_16BPP_CONTROL, 0xc2
- DAC_IDR, RUN, PIXEL_24BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_32BPP_CONTROL, 0x03
-
- [640,480,32]
- # Setting Line Pitch
- CRT,RUN,LOGICAL_LINE_LENGTH,0x40
- CRT,RUN,EXT_MODE,0x00
- CRT,RUN,EXT_SYSTEM_CONTROL_2,0x10
- # Setting Engine Pitch
- CRT,RUN,EXT_SYSTEM_CONTROL_1,0x70
- CRT,RUN,MEM_CONFIG,0x8b
- # Setting Basic Mode Registers.The registers
- # below are neither Desktop or Viewport Regs
- # Unlock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x06
- # Dump Sequencer Registers
- SEQ,RUN,CLOCKING_MODE,0x21,0x0f,0x00,0x0e,0x00
- # Dump Graphics Controller Registers
- GRX,RUN,SET_RESET_DATA,0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0f,0xff
- # Dump Attribute Controller Registers
- ATR,RUN,PALETTE_0,0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x41,0x00,0x0f,0x00,0x00
- # Lock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x00
- DAC_IDR, RUN, DAC_OPERATION, 0x02
- DAC_IDR, RUN, VRAM_MASK_LOW, 0x03
- DAC_IDR, RUN, MISC_CONTROL_1, 0x00
- DAC_IDR, RUN, MISC_CONTROL_2, 0x00
- DAC_IDR, RUN, MISC_CONTROL_3, 0x00
- DAC_IDR, RUN, PIXEL_FORMAT, 0x06
- DAC_IDR, RUN, PIXEL_8BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_16BPP_CONTROL, 0xc2
- DAC_IDR, RUN, PIXEL_24BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_32BPP_CONTROL, 0x03
-
- [640,480,24]
- # Setting Line Pitch
- CRT,RUN,LOGICAL_LINE_LENGTH,0xf0
- CRT,RUN,EXT_MODE,0x00
- CRT,RUN,EXT_SYSTEM_CONTROL_2,0x00
- # Setting Engine Pitch
- CRT,RUN,EXT_SYSTEM_CONTROL_1,0x60
- CRT,RUN,MEM_CONFIG,0x8b
- # Setting Basic Mode Registers.The registers
- # below are neither Desktop or Viewport Regs
- # Unlock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x06
- # Dump Sequencer Registers
- SEQ,RUN,CLOCKING_MODE,0x21,0x0f,0x00,0x0e,0x00
- # Dump Graphics Controller Registers
- GRX,RUN,SET_RESET_DATA,0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f,0xff
- # Dump Attribute Controller Registers
- ATR,RUN,PALETTE_0,0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x01,0x00,0x0f,0x00,0x00
- # Lock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x00
- DAC_IDR, RUN, DAC_OPERATION, 0x02
- DAC_IDR, RUN, VRAM_MASK_LOW, 0x03
- DAC_IDR, RUN, MISC_CONTROL_1, 0x00
- DAC_IDR, RUN, MISC_CONTROL_2, 0x00
- DAC_IDR, RUN, MISC_CONTROL_3, 0x00
- DAC_IDR, RUN, PIXEL_FORMAT, 0x05
- DAC_IDR, RUN, PIXEL_8BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_16BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_24BPP_CONTROL, 0x01
- DAC_IDR, RUN, PIXEL_32BPP_CONTROL, 0x00
-
-
-
- [640,480,16]
- # Setting Line Pitch
- CRT,RUN,LOGICAL_LINE_LENGTH,0xa0
- CRT,RUN,EXT_MODE,0x00
- CRT,RUN,EXT_SYSTEM_CONTROL_2,0x00
- # Setting Engine Pitch
- CRT,RUN,EXT_SYSTEM_CONTROL_1,0x50
- CRT,RUN,MEM_CONFIG,0x8b
- # Setting Basic Mode Registers.The registers
- # below are neither Desktop or Viewport Regs
- # Unlock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x06
- # Dump Sequencer Registers
- SEQ,RUN,CLOCKING_MODE,0x21,0x0f,0x00,0x0e,0x00
- # Dump Graphics Controller Registers
- GRX,RUN,SET_RESET_DATA,0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0f,0xff
- # Dump Attribute Controller Registers
- ATR,RUN,PALETTE_0,0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x41,0x00,0x0f,0x00,0x00
- # Lock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x00
- DAC_IDR, RUN, DAC_OPERATION, 0x02
- DAC_IDR, RUN, VRAM_MASK_LOW, 0x03
- DAC_IDR, RUN, MISC_CONTROL_1, 0x00
- DAC_IDR, RUN, MISC_CONTROL_2, 0x00
- DAC_IDR, RUN, MISC_CONTROL_3, 0x00
- DAC_IDR, RUN, PIXEL_FORMAT, 0x04
- DAC_IDR, RUN, PIXEL_8BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_16BPP_CONTROL, 0xc2
- DAC_IDR, RUN, PIXEL_24BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_32BPP_CONTROL, 0x03
-
- [640,480,8]
- # Setting Line Pitch
- CRT,RUN,LOGICAL_LINE_LENGTH,0x50
- CRT,RUN,EXT_MODE,0x00
- CRT,RUN,EXT_SYSTEM_CONTROL_2,0x00
- # Setting Engine Pitch
- CRT,RUN,EXT_SYSTEM_CONTROL_1,0x40
- CRT,RUN,MEM_CONFIG,0x8b
- # Setting Basic Mode Registers.The registers
- # below are neither Desktop or Viewport Regs
- # Unlock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x06
- # Dump Sequencer Registers
- SEQ,RUN,CLOCKING_MODE,0x21,0x0f,0x00,0x0e,0x00
- # Dump Graphics Controller Registers
- GRX,RUN,SET_RESET_DATA,0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0f,0xff
- # Dump Attribute Controller Registers
- ATR,RUN,PALETTE_0,0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x41,0x00,0x0f,0x00,0x00
- # Lock Sequencer
- SEQ,RMW,UNLOCK_EXTENSIONS,0x00,0x00
- DAC_IDR, RUN, DAC_OPERATION, 0x02
- DAC_IDR, RUN, VRAM_MASK_LOW, 0x03
- DAC_IDR, RUN, MISC_CONTROL_1, 0x00
- DAC_IDR, RUN, MISC_CONTROL_2, 0x04
- DAC_IDR, RUN, MISC_CONTROL_3, 0x00
- DAC_IDR, RUN, PIXEL_FORMAT, 0x03
- DAC_IDR, RUN, PIXEL_8BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_16BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_24BPP_CONTROL, 0x00
- DAC_IDR, RUN, PIXEL_32BPP_CONTROL, 0x03
-
-
- [1600,1200,16,82,66]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x7d,0x64,0x62,0x00,0x67,0x11,0xe6,0x00,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0xaf,0x0b,0xaf
- CRT,RUN,UNDERLINE_LOCATION,0x00,0xaf,0x00,0xa3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x00,0x10,0x00
- CRT,RUN,MISC_1,0x15,0x78,0x14,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x57
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x04
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0xd3
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [1600,1200,16,75,60]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x7f,0x64,0x62,0x02,0x68,0x12,0xe8,0x00,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0xaf,0x0b,0xaf
- CRT,RUN,UNDERLINE_LOCATION,0x00,0xaf,0x00,0xa3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x00,0x10,0x00
- CRT,RUN,MISC_1,0x15,0x77,0x14,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x57
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x04
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0xcd
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
-
- [1600,1200,8,82,66]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x7d,0x64,0x62,0x00,0x67,0x11,0xe6,0x00,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0xaf,0x0b,0xaf
- CRT,RUN,UNDERLINE_LOCATION,0x00,0xaf,0x00,0xa3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x00,0x10,0x00
- CRT,RUN,MISC_1,0x15,0x78,0x14,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x57
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x19,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x02
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0xd3
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x08
-
- [1600,1200,8,75,60]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x7f,0x64,0x62,0x02,0x68,0x12,0xe8,0x00,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0xaf,0x0b,0xaf
- CRT,RUN,UNDERLINE_LOCATION,0x00,0xaf,0x00,0xa3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x00,0x10,0x00
- CRT,RUN,MISC_1,0x15,0x77,0x14,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x57
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x19,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x02
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0xcd
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x08
-
- [1280,1024,24,79,75]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x9a,0x77,0x78,0x9e,0x7b,0x03,0x29,0x42,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x00,0x07,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x00,0x03,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x10,0x00
- CRT,RUN,MISC_1,0x15,0x94,0x28,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x55
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0xc1
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [1280,1024,24,76,72]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0xa0,0x77,0x78,0x84,0x7c,0x04,0x2c,0x42,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x00,0x07,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x00,0x06,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x10,0x00
- CRT,RUN,MISC_1,0x15,0x9a,0x28,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x55
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0xc1
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [1280,1024,24,74,70]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x9a,0x77,0x78,0x9e,0x80,0x0a,0x28,0x52,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x00,0x05,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x00,0x29,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x10,0x00
- CRT,RUN,MISC_1,0x15,0x94,0x28,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x55
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0xba
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [1280,1024,24,64,60]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- ##CRT,RUN,HORZ_TOTAL,0x9a,0x77,0x78,0x9e,0x7d,0x05,0x34,0x42,0x00,0x40
- CRT,RUN,HORZ_TOTAL,0x9a,0x77,0x78,0x9e,0x7d,0x08,0x28,0x52,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- ##CRT,RUN,VERT_RETRACE_START,0x00,0x07,0xff
- CRT,RUN,VERT_RETRACE_START,0x00,0x03,0xff
- ##CRT,RUN,UNDERLINE_LOCATION,0x00,0x00,0x29,0xe3,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x00,0x29,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x10,0x00
- CRT,RUN,MISC_1,0x15,0x95,0x28,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x55
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- ##CLK_IND, RUN, FREQ_2, 0xab
- CLK_IND, RUN, FREQ_2, 0xa9
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [1280,1024,16,95,90]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x67,0x4f,0x50,0x8b,0x52,0x9a,0x2a,0x42,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x03,0x07,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x00,0x2a,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x10,0x00
- CRT,RUN,MISC_1,0x15,0x62,0x33,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x55
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x19,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0xd0
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [1280,1024,16,79,75]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x64,0x4f,0x50,0x89,0x51,0x9a,0x2c,0x42,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x00,0x03,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x00,0x2c,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x10,0x00
- CRT,RUN,MISC_1,0x15,0x5e,0x33,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x55
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x19,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0xc1
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [1280,1024,16,76,72]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x69,0x4f,0x50,0x8c,0x53,0x98,0x27,0x42,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x05,0x0c,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x00,0x23,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x10,0x00
- CRT,RUN,MISC_1,0x15,0x62,0x33,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x55
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x19,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0xc1
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [1280,1024,16,74,70]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x65,0x4f,0x50,0x8a,0x56,0x9d,0x28,0x52,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x00,0x05,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x00,0x29,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x10,0x00
- CRT,RUN,MISC_1,0x15,0x60,0x33,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x55
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x19,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0xba
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [1280,1024,16,64,60]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- ##CRT,RUN,HORZ_TOTAL,0x66,0x4f,0x50,0x89,0x53,0x98,0x33,0x42,0x00,0x40
- CRT,RUN,HORZ_TOTAL,0x65,0x4f,0x50,0x8a,0x53,0x9a,0x28,0x52,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- ##CRT,RUN,VERT_RETRACE_START,0x00,0x07,0xff
- CRT,RUN,VERT_RETRACE_START,0x00,0x03,0xff
- ##CRT,RUN,UNDERLINE_LOCATION,0x00,0x00,0x28,0xe3,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x00,0x29,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x10,0x00
- ##CRT,RUN,MISC_1,0x15,0x5f,0x33,0x11
- CRT,RUN,MISC_1,0x15,0x60,0x33,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x55
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x19,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- ##CLK_IND, RUN, FREQ_2, 0xab
- CLK_IND, RUN, FREQ_2, 0xa9
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [1280,1024,8,95,90]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x67,0x4f,0x50,0x8b,0x56,0x9f,0x2a,0x42,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x03,0x07,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x00,0x2a,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x18,0x00
- CRT,RUN,MISC_1,0x15,0x62,0x14,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x55
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x19,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x77
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0xd0
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x08
-
- [1280,1024,8,79,75]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x64,0x4f,0x50,0x89,0x54,0x9f,0x2c,0x42,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x00,0x03,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x00,0x2c,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x18,0x00
- CRT,RUN,MISC_1,0x15,0x5e,0x14,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x55
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x19,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x77
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0xc1
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x08
-
- [1280,1024,8,76,72]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x69,0x4f,0x50,0x8c,0x57,0x9c,0x27,0x42,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x05,0x0c,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x00,0x23,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x18,0x00
- CRT,RUN,MISC_1,0x15,0x62,0x14,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x55
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x19,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x77
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0xc1
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x08
-
- [1280,1024,8,74,70]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x65,0x4f,0x50,0x8a,0x5a,0x81,0x28,0x52,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x00,0x05,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x00,0x29,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x18,0x00
- CRT,RUN,MISC_1,0x15,0x60,0x14,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x55
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x19,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x77
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0xba
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x08
-
- [1280,1024,8,64,60]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x66,0x4f,0x50,0x89,0x57,0x9c,0x33,0x42,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- ##CRT,RUN,VERT_RETRACE_START,0x00,0x07,0xff
- CRT,RUN,VERT_RETRACE_START,0x00,0x03,0xff
- ##CRT,RUN,UNDERLINE_LOCATION,0x00,0x00,0x28,0xe3,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x00,0x29,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x18,0x00
- ##CRT,RUN,MISC_1,0x15,0x5f,0x14,0x11
- CRT,RUN,MISC_1,0x15,0x60,0x14,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x55
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x19,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x77
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- ##CLK_IND, RUN, FREQ_2, 0xab
- CLK_IND, RUN, FREQ_2, 0xa9
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x08
-
- [1152,864,32,64,70]
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- CRT,RUN,HORZ_TOTAL,0x57,0x47,0x48,0x9a,0x4a,0x0f,0x92,0xff,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x6b,0x02,0x5f
- CRT,RUN,UNDERLINE_LOCATION,0x60,0x6f,0x7d,0xeb,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x04,0x00
- CRT,RUN,MISC_1,0x15,0x4f,0x9f,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x01,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- DIR,RUN,MISC_WRITE,0x2f
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x9b
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [1152,864,32,56,60]
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- CRT,RUN,HORZ_TOTAL,0x57,0x47,0x48,0x9b,0x49,0x0d,0xac,0xff,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x77,0x10,0x5f
- CRT,RUN,UNDERLINE_LOCATION,0x60,0x6f,0xac,0xeb,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x04,0x00
- CRT,RUN,MISC_1,0x15,0xb1,0x9f,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x01,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- DIR,RUN,MISC_WRITE,0x2f
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x90
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
-
-
- [1152,864,24,64,70]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x85,0x6b,0x6c,0x89,0x6f,0x16,0x92,0xff,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x6b,0x02,0x5f
- CRT,RUN,UNDERLINE_LOCATION,0x60,0x59,0x7d,0xeb,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x10,0x00
- CRT,RUN,MISC_1,0x15,0x7f,0x9f,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x9b
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [1152,864,24,56,60]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x85,0x6b,0x6c,0x89,0x6e,0x14,0xac,0xff,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x77,0x00,0x5f
- CRT,RUN,UNDERLINE_LOCATION,0x60,0x59,0x99,0xeb,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x14,0x00
- CRT,RUN,MISC_1,0x15,0x7f,0x3d,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x15,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x90
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [1152,864,16,82,90]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x59,0x47,0x48,0x9c,0x4a,0x0e,0x95,0xff,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x65,0x04,0x5f
- CRT,RUN,UNDERLINE_LOCATION,0x60,0x6f,0x99,0xeb,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x08,0x00
- CRT,RUN,MISC_1,0x15,0x4f,0x9f,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0xb9
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [1152,864,16,71,75]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x5a,0x47,0x48,0x9d,0x4b,0x0f,0xb7,0xff,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x81,0x00,0x5f
- CRT,RUN,UNDERLINE_LOCATION,0x60,0x6f,0xa2,0xeb,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x08,0x00
- CRT,RUN,MISC_1,0x15,0x4f,0x9f,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0xa9
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [1152,864,16,64,70]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x57,0x47,0x48,0x9a,0x4a,0x0f,0x92,0xff,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x6b,0x02,0x5f
- CRT,RUN,UNDERLINE_LOCATION,0x60,0x6f,0x7d,0xeb,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x08,0x00
- CRT,RUN,MISC_1,0x15,0x4f,0x9f,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x9b
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [1152,864,16,56,60]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xA5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x57,0x47,0x48,0x9b,0x49,0x0d,0xac,0xff,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x77,0x10,0x5f
- CRT,RUN,UNDERLINE_LOCATION,0x60,0x6f,0xac,0xeb,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x08,0x00
- CRT,RUN,MISC_1,0x15,0xb1,0x9f,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x90
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [1152,864,8,82,90]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x59,0x47,0x48,0x9c,0x4f,0x13,0x95,0xff,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x65,0x04,0x5f
- CRT,RUN,UNDERLINE_LOCATION,0x60,0x6f,0x99,0xeb,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x4f,0x9f,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x77
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0xb9
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x08
-
- [1152,864,8,71,75]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x5a,0x47,0x48,0x9d,0x50,0x14,0xb7,0xff,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x81,0x00,0x5f
- CRT,RUN,UNDERLINE_LOCATION,0x60,0x6f,0xa2,0xeb,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x4f,0x9f,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x77
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0xa9
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x08
-
- [1152,864,8,64,70]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x57,0x47,0x48,0x9a,0x4f,0x14,0x92,0xff,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x6b,0x02,0x5f
- CRT,RUN,UNDERLINE_LOCATION,0x60,0x6f,0x7d,0xeb,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x4f,0x9f,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x77
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x9b
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x08
-
- [1152,864,8,56,60]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x57,0x47,0x48,0x9b,0x4e,0x12,0xac,0xff,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x77,0x10,0x5f
- CRT,RUN,UNDERLINE_LOCATION,0x60,0x6f,0xac,0xeb,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x00,0x00
- CRT,RUN,MISC_1,0x15,0xb1,0x9f,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x77
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x90
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x08
-
-
- [1024,768,32,64,80]
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- CRT,RUN,HORZ_TOTAL,0x4e,0x3f,0x40,0x11,0x44,0x0b,0x26,0xf5,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x0a,0x08,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0xff,0x24,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x04,0x00
- CRT,RUN,MISC_1,0x15,0x47,0x25,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x01,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- DIR,RUN,MISC_WRITE,0x2f
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x93
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [1024,768,32,60,75]
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- CRT,RUN,HORZ_TOTAL,0x4d,0x3f,0x40,0x11,0x41,0x07,0x1e,0xf5,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x00,0x03,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0xff,0x1e,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x04,0x00
- CRT,RUN,MISC_1,0x15,0x47,0x25,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x01,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- DIR,RUN,MISC_WRITE,0x2f
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x8c
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [1024,768,32,58,72]
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- CRT,RUN,HORZ_TOTAL,0x4c,0x3f,0x40,0x13,0x42,0x0f,0x20,0xf5,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x00,0x06,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0xff,0x1a,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x04,0x00
- CRT,RUN,MISC_1,0x15,0x45,0x25,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x01,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- DIR,RUN,MISC_WRITE,0x2f
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x88
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [1024,768,32,56,70]
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- CRT,RUN,HORZ_TOTAL,0x4e,0x3f,0x40,0x12,0x41,0x0a,0x24,0xf5,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x02,0x08,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0xff,0x24,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x04,0x00
- CRT,RUN,MISC_1,0x15,0x47,0x25,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x01,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- DIR,RUN,MISC_WRITE,0x2f
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x88
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [1024,768,32,48,60]
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- CRT,RUN,HORZ_TOTAL,0x4f,0x3f,0x40,0x12,0x41,0x0a,0x24,0xf5,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x02,0x08,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0xff,0x24,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x04,0x00
- CRT,RUN,MISC_1,0x15,0x48,0x25,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x01,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- DIR,RUN,MISC_WRITE,0x2f
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x7e
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [1024,768,24,64,80]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x79,0x5f,0x60,0x9d,0x68,0x91,0x1f,0xf5,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x00,0x0e,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0xff,0x1b,0xeb,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x14,0x00
- CRT,RUN,MISC_1,0x15,0x70,0x3d,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x15,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x93
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [1024,768,24,60,75]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x76,0x5f,0x60,0x99,0x62,0x8f,0x1e,0xf1,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0xff,0x05,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0xff,0x1e,0xeb,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x14,0x00
- CRT,RUN,MISC_1,0x15,0x70,0x21,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x15,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x8c
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
-
- [1024,768,24,58,72]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x76,0x5f,0x60,0x9a,0x63,0x8c,0x19,0xf5,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x00,0x06,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0xff,0x11,0xeb,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x14,0x00
- CRT,RUN,MISC_1,0x15,0x70,0x21,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x15,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x88
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [1024,768,24,56,70]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- ##CRT,RUN,HORZ_TOTAL,0x76,0x5f,0x60,0x1b,0x61,0x8e,0x2a,0xf5,0x00,0x60
- CRT,RUN,HORZ_TOTAL,0x79,0x5f,0x60,0x9d,0x63,0x90,0x24,0xfd,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- ##CRT,RUN,VERT_RETRACE_START,0x03,0x09,0xff
- CRT,RUN,VERT_RETRACE_START,0x02,0x08,0xff
- ##CRT,RUN,UNDERLINE_LOCATION,0x00,0xff,0x2a,0xeb,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x00,0x25,0xeb,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x14,0x00
- ##CRT,RUN,MISC_1,0x15,0x71,0x21,0x11
- CRT,RUN,MISC_1,0x15,0x73,0x21,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x15,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- ##CLK_IND, RUN, FREQ_2, 0x88
- CLK_IND, RUN, FREQ_2, 0x89
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [1024,768,24,48,60]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x79,0x5f,0x60,0x9d,0x62,0x8f,0x24,0xf5,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x02,0x08,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0xff,0x24,0xeb,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x14,0x00
- CRT,RUN,MISC_1,0x15,0x73,0x21,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x15,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x7e
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [1024,768,16,96,120]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x4e,0x3f,0x40,0x11,0x43,0x0e,0x28,0xf5,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x00,0x02,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0xff,0x24,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x49,0x20,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0xbd
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [1024,768,16,81,100]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x4f,0x3f,0x40,0x12,0x42,0x0b,0x24,0xf5,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x01,0x07,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0xff,0x24,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x49,0x20,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0xa9
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [1024,768,16,64,80]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x4e,0x3f,0x40,0x11,0x44,0x0b,0x26,0xf5,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x0a,0x08,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0xff,0x24,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x47,0x20,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x93
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [1024,768,16,60,75]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x4d,0x3f,0x40,0x11,0x41,0x07,0x1e,0xf5,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x00,0x03,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0xff,0x1e,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x47,0x20,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x8c
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [1024,768,16,58,72]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x4c,0x3f,0x40,0x13,0x42,0x0f,0x20,0xf5,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x00,0x06,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0xff,0x1a,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x45,0x20,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FREQ_2,0x88
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x88
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
-
-
- [1024,768,16,56,70]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x4e,0x3f,0x40,0x12,0x41,0x0a,0x24,0xf5,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x02,0x08,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0xff,0x24,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x47,0x20,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FREQ_2,0x88
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x88
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [1024,768,16,48,60]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xA5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x4f,0x3f,0x40,0x12,0x41,0x0a,0x24,0xf5,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x02,0x08,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0xff,0x24,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x48,0x20,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x7E
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [1024,768,8,96,120]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x4e,0x3f,0x40,0x11,0x43,0x0e,0x28,0xf5,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x00,0x02,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0xff,0x24,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x49,0x25,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0xbd
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x08
-
- [1024,768,8,81,100]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x4f,0x3f,0x40,0x12,0x42,0x0b,0x24,0xf5,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x01,0x07,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0xff,0x24,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x49,0x25,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0xa9
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x08
-
- [1024,768,8,64,80]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x4e,0x3f,0x40,0x11,0x44,0x0b,0x26,0xf5,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x0a,0x08,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0xff,0x24,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x47,0x25,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x93
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x08
-
- [1024,768,8,60,75]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x4d,0x3f,0x40,0x11,0x41,0x07,0x1e,0xf5,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x00,0x03,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0xff,0x1e,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x47,0x25,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x8c
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x08
-
- [1024,768,8,58,72]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x4c,0x3f,0x40,0x13,0x42,0x0f,0x20,0xf5,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x00,0x06,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0xff,0x1a,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x45,0x25,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x88
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x08
-
- [1024,768,8,56,70]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x4e,0x3f,0x40,0x12,0x41,0x0a,0x24,0xf5,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x02,0x08,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0xff,0x24,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x47,0x25,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x88
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x08
-
- [1024,768,8,48,60]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x4f,0x3f,0x40,0x12,0x41,0x0a,0x24,0xf5,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x02,0x08,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0xff,0x24,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x48,0x25,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x7e
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x08
-
- [800,600,32,75,120]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x39,0x33,0x31,0x00,0x32,0x1a,0x83,0xf0,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x5a,0x0c,0x57
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x57,0x00,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x00,0x04,0x00
- CRT,RUN,MISC_1,0x15,0x34,0x1e,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x05,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x8a
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [800,600,32,64,100]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x3a,0x33,0x31,0x00,0x34,0x1a,0x82,0xf0,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x63,0x02,0x57
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x57,0x00,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x00,0x04,0x00
- CRT,RUN,MISC_1,0x15,0x33,0x1e,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x05,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x7e
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [800,600,32,56,90]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x3b,0x33,0x31,0x00,0x34,0x1a,0x72,0xf0,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x60,0x02,0x57
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x57,0x00,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x00,0x04,0x00
- CRT,RUN,MISC_1,0x15,0x34,0x1e,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x05,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x70
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [800,600,32,46,75]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x3d,0x33,0x31,0x00,0x33,0x18,0x6f,0xe0,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x58,0x0b,0x57
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x57,0x00,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x00,0x04,0x00
- CRT,RUN,MISC_1,0x15,0x36,0x1e,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x08
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x05,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x60
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [800,600,32,48,72]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x3c,0x33,0x31,0x00,0x35,0x1d,0x98,0xf0,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x7c,0x22,0x57
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x57,0x00,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x00,0x04,0x00
- CRT,RUN,MISC_1,0x15,0x36,0x1e,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x05,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x61
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
-
-
- [800,600,32,35,56]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x3b,0x33,0x31,0x00,0x33,0x18,0x6f,0xf0,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x58,0x0a,0x57
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x57,0x00,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x00,0x04,0x00
- CRT,RUN,MISC_1,0x15,0x34,0x1e,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x05,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x45
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [800,600,32,37,60]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xA5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x3d,0x33,0x31,0x00,0x34,0x1c,0x72,0xf0,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x58,0x0c,0x57
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x57,0x00,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x00,0x04,0x00
- CRT,RUN,MISC_1,0x15,0x36,0x1e,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x08
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x05,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x4D
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [800,600,24,75,120]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x58,0x4c,0x4a,0x00,0x4b,0x14,0x82,0xf0,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x59,0x0b,0x57
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x57,0x00,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x00,0x04,0x00
- CRT,RUN,MISC_1,0x15,0x73,0x21,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x15,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x8a
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
-
- [800,600,24,64,100]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x5b,0x4c,0x4a,0x00,0x50,0x19,0x7a,0xf0,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x59,0x08,0x57
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x57,0x00,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x00,0x04,0x00
- CRT,RUN,MISC_1,0x15,0x58,0x2f,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x15,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x7e
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
-
- [800,600,24,56,90]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x5b,0x4c,0x4a,0x00,0x4e,0x1a,0x6f,0xf0,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x57,0x09,0x57
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x57,0x00,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x00,0x04,0x00
- CRT,RUN,MISC_1,0x15,0x55,0x2f,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x15,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x70
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
-
- [800,600,24,46,75]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x5e,0x4c,0x4a,0x00,0x4d,0x15,0x6f,0xe0,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x58,0x0b,0x57
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x57,0x00,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x00,0x04,0x00
- CRT,RUN,MISC_1,0x15,0x58,0x2f,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x15,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x60
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
-
- [800,600,24,48,72]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- ##CRT,RUN,HORZ_TOTAL,0x5e,0x4c,0x4a,0x00,0x4e,0x1a,0x8e,0xf0,0x00,0x60
- CRT,RUN,HORZ_TOTAL,0x5e,0x4c,0x4a,0x80,0x52,0x1d,0x98,0xf0,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- ##CRT,RUN,VERT_RETRACE_START,0x71,0x27,0x57
- CRT,RUN,VERT_RETRACE_START,0x7c,0x02,0x57
- ##CRT,RUN,UNDERLINE_LOCATION,0x00,0x57,0x00,0xe3,0xff
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x58,0x00,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x00,0x04,0x00
- CRT,RUN,MISC_1,0x15,0x58,0x2f,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x15,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- ##CLK_IND, RUN, FREQ_2, 0x61
- CLK_IND, RUN, FREQ_2, 0x62
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [800,600,24,37,60]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x5e,0x4c,0x4a,0x00,0x4e,0x1a,0x72,0xf0,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x58,0x0c,0x57
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x57,0x00,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x00,0x04,0x00
- CRT,RUN,MISC_1,0x15,0x58,0x2f,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x15,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x4d
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
-
- [800,600,24,35,56]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x5b,0x4c,0x4a,0x00,0x4d,0x16,0x72,0xf0,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x58,0x0c,0x57
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x57,0x00,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x00,0x04,0x00
- CRT,RUN,MISC_1,0x15,0x58,0x2f,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x15,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x45
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
-
-
- [800,600,16,75,120]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x39,0x33,0x31,0x00,0x32,0x1a,0x83,0xf0,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x5a,0x0c,0x57
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x57,0x00,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x00,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x34,0x1e,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x15,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x8a
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [800,600,16,64,100]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x3a,0x33,0x31,0x00,0x34,0x1a,0x82,0xf0,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x63,0x02,0x57
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x57,0x00,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x00,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x33,0x1e,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x15,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x7e
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [800,600,16,56,90]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x3b,0x33,0x31,0x00,0x34,0x1a,0x72,0xf0,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x60,0x02,0x57
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x57,0x00,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x00,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x34,0x1e,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x15,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x70
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [800,600,16,46,75]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x3d,0x33,0x31,0x00,0x33,0x18,0x6f,0xe0,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x58,0x0b,0x57
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x57,0x00,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x00,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x36,0x1e,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x08
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x15,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x60
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [800,600,16,48,72]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x3c,0x33,0x31,0x00,0x35,0x1d,0x98,0xf0,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x7c,0x22,0x57
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x57,0x00,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x00,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x36,0x1e,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x15,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x61
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [800,600,16,35,56]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x3b,0x33,0x31,0x00,0x33,0x18,0x6f,0xf0,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x58,0x0a,0x57
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x57,0x00,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x00,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x34,0x1e,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x15,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x45
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [800,600,16,37,60]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xA5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x3d,0x33,0x31,0x00,0x34,0x1c,0x72,0xf0,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x58,0x0c,0x57
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x57,0x00,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x00,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x36,0x1e,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x08
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x15,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x4D
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [800,600,8,75,120]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x39,0x33,0x31,0x00,0x32,0x1a,0x83,0xf0,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x5a,0x0c,0x57
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x57,0x00,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x00,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x34,0x1e,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x8a
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x08
-
- [800,600,8,64,100]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x3a,0x33,0x31,0x00,0x34,0x1a,0x82,0xf0,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x63,0x02,0x57
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x57,0x00,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x00,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x33,0x1e,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x7e
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x08
-
- [800,600,8,56,90]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x3b,0x33,0x31,0x00,0x34,0x1a,0x72,0xf0,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x60,0x02,0x57
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x57,0x00,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x00,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x34,0x1e,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x70
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x08
-
- [800,600,8,46,75]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x3d,0x33,0x31,0x00,0x33,0x18,0x6f,0xe0,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x58,0x0b,0x57
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x57,0x00,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x00,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x36,0x1e,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x08
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x60
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x08
-
- [800,600,8,48,72]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x3c,0x33,0x31,0x00,0x35,0x1d,0x98,0xf0,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x7c,0x22,0x57
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x57,0x00,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x00,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x36,0x1e,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x61
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x08
-
- [800,600,8,37,60]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x3d,0x33,0x31,0x00,0x34,0x1c,0x72,0xf0,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x58,0x0c,0x57
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x57,0x00,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x00,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x36,0x1e,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x08
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x4D
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x08
-
- [800,600,8,35,56]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x3b,0x33,0x31,0x00,0x33,0x18,0x6f,0xf0,0x00,0x60
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0x58,0x0a,0x57
- CRT,RUN,UNDERLINE_LOCATION,0x00,0x57,0x00,0xe3,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x00,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x34,0x1e,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x45
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x08
-
- [640,480,32,64,120]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x2f,0x27,0x28,0x12,0x29,0x0f,0x14,0x3e,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0xef,0x0c,0xdf
- CRT,RUN,UNDERLINE_LOCATION,0x60,0xe7,0x0e,0xab,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x04,0x00
- CRT,RUN,MISC_1,0x15,0x2a,0x16,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x01,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x67
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [640,480,32,52,100]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x2d,0x27,0x28,0x10,0x29,0x0f,0x05,0x3e,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0xec,0x01,0xdf
- CRT,RUN,UNDERLINE_LOCATION,0x60,0xe7,0xff,0xab,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x04,0x00
- CRT,RUN,MISC_1,0x15,0x28,0x16,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x01,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x50
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [640,480,32,48,90]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x2f,0x27,0x28,0x12,0x29,0x0f,0x14,0x3e,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0xf7,0x01,0xdf
- CRT,RUN,UNDERLINE_LOCATION,0x60,0xe7,0x12,0xab,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x04,0x00
- CRT,RUN,MISC_1,0x15,0x2a,0x16,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x01,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x4d
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [640,480,32,37,75]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x2f,0x27,0x28,0x13,0x29,0x0d,0xf6,0x1f,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0xe0,0x03,0xdf
- CRT,RUN,UNDERLINE_LOCATION,0x60,0xe7,0xf6,0xab,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x04,0x00
- CRT,RUN,MISC_1,0x15,0x2a,0x16,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x01,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x3a
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [640,480,32,37,72]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x2f,0x27,0x28,0x13,0x29,0x0c,0x06,0x3e,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0xe8,0x0b,0xdf
- CRT,RUN,UNDERLINE_LOCATION,0x60,0xe7,0x06,0xab,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x04,0x00
- CRT,RUN,MISC_1,0x15,0x2a,0x16,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x01,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x3a
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [640,480,32,31,60]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xA5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x2d,0x27,0x28,0x10,0x29,0x0f,0x0b,0x3e,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0xe9,0x0b,0xdf
- CRT,RUN,UNDERLINE_LOCATION,0x60,0xe7,0x0b,0xab,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x04,0x00
- CRT,RUN,MISC_1,0x15,0x2a,0x16,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x01,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x21
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [640,480,24,64,120]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x49,0x3b,0x3c,0x8e,0x3d,0x03,0x12,0x3e,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0xef,0x0c,0xdf
- CRT,RUN,UNDERLINE_LOCATION,0x60,0xe7,0x0c,0xab,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x04,0x00
- CRT,RUN,MISC_1,0x15,0x58,0x24,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x15,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x67
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
-
- [640,480,24,52,100]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x46,0x3b,0x3c,0x8b,0x3d,0x03,0x06,0x3e,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0xec,0x01,0xdf
- CRT,RUN,UNDERLINE_LOCATION,0x60,0xe7,0x00,0xab,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x04,0x00
- CRT,RUN,MISC_1,0x15,0x43,0x24,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x50
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [640,480,24,48,90]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x49,0x3b,0x3c,0x8e,0x3d,0x03,0x14,0x3e,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0xf7,0x01,0xdf
- CRT,RUN,UNDERLINE_LOCATION,0x60,0xe7,0x12,0xab,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x04,0x00
- CRT,RUN,MISC_1,0x15,0x43,0x24,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x4d
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
-
- [640,480,24,37,75]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x49,0x3b,0x3c,0x8f,0x3d,0x03,0xf2,0x1f,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0xe0,0x03,0xdf
- CRT,RUN,UNDERLINE_LOCATION,0x60,0xe0,0xf3,0xab,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x04,0x00
- CRT,RUN,MISC_1,0x15,0x45,0x24,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x39
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
-
- [640,480,24,37,72]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa0
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x49,0x3b,0x3c,0x8d,0x3d,0x01,0x06,0x3e,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0xe8,0x0b,0xdf
- CRT,RUN,UNDERLINE_LOCATION,0x60,0xe7,0x06,0xab,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x04,0x00
- CRT,RUN,MISC_1,0x15,0x43,0x24,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x3a
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [640,480,24,31,60]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x46,0x3b,0x3c,0x8b,0x3e,0x07,0x0b,0x3e,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0xe9,0x0b,0xdf
- CRT,RUN,UNDERLINE_LOCATION,0x60,0xe0,0x0c,0xab,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x04,0x00
- CRT,RUN,MISC_1,0x15,0x41,0x24,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x72
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xbe,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x1
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x21
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [640,480,16,64,120]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x2f,0x27,0x28,0x12,0x29,0x0f,0x14,0x3e,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0xef,0x0c,0xdf
- CRT,RUN,UNDERLINE_LOCATION,0x60,0xe7,0x0e,0xab,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x2a,0x16,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x67
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [640,480,16,52,100]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x2d,0x27,0x28,0x10,0x29,0x0f,0x05,0x3e,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0xec,0x01,0xdf
- CRT,RUN,UNDERLINE_LOCATION,0x60,0xe7,0xff,0xab,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x28,0x16,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x50
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [640,480,16,48,90]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x2f,0x27,0x28,0x12,0x29,0x0f,0x14,0x3e,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0xf7,0x01,0xdf
- CRT,RUN,UNDERLINE_LOCATION,0x60,0xe7,0x12,0xab,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x2a,0x16,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x4d
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [640,480,16,37,75]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x2f,0x27,0x28,0x13,0x29,0x0d,0xf6,0x1f,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0xe0,0x03,0xdf
- CRT,RUN,UNDERLINE_LOCATION,0x60,0xe7,0xf6,0xab,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x2a,0x16,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x3a
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [640,480,16,37,72]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x2f,0x27,0x28,0x13,0x29,0x0c,0x06,0x3e,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0xe8,0x0b,0xdf
- CRT,RUN,UNDERLINE_LOCATION,0x60,0xe7,0x06,0xab,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x2a,0x16,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x3a
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [640,480,16,31,60]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xA5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x2d,0x27,0x28,0x10,0x29,0x0f,0x0b,0x3e,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0xe9,0x0b,0xdf
- CRT,RUN,UNDERLINE_LOCATION,0x60,0xe7,0x0b,0xab,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x2a,0x16,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x21
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x00
-
- [640,480,8,64,120]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x2f,0x27,0x28,0x12,0x29,0x0f,0x14,0x3e,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0xef,0x0c,0xdf
- CRT,RUN,UNDERLINE_LOCATION,0x60,0xe7,0x0e,0xab,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x2a,0x40,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x67
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x08
-
- [640,480,8,52,100]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x2d,0x27,0x28,0x10,0x29,0x0f,0x05,0x3e,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0xec,0x01,0xdf
- CRT,RUN,UNDERLINE_LOCATION,0x60,0xe7,0xff,0xab,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x28,0x40,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x50
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x08
-
- [640,480,8,48,90]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x2f,0x27,0x28,0x12,0x29,0x0f,0x14,0x3e,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0xf7,0x01,0xdf
- CRT,RUN,UNDERLINE_LOCATION,0x60,0xe7,0x12,0xab,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x2a,0x40,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x4d
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x08
-
- [640,480,8,37,75]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x2f,0x27,0x28,0x13,0x29,0x0d,0xf6,0x1f,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0xe0,0x03,0xdf
- CRT,RUN,UNDERLINE_LOCATION,0x60,0xe7,0xf6,0xab,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x2a,0x40,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x3a
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x08
-
- [640,480,8,37,72]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xa5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x2f,0x27,0x28,0x13,0x29,0x0c,0x06,0x3e,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0xe8,0x0b,0xdf
- CRT,RUN,UNDERLINE_LOCATION,0x60,0xe7,0x06,0xab,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x2a,0x40,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x3a
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x08
-
- [640,480,8,31,60]
- # Unlock CRTC
- CRT,RMW,VERT_RETRACE_END,0x7f,0x00
- CRT,RMW,CRT_REG_LOCK,0xcf,0x00
- CRT,RUN,REG_LOCK_1,0x48,0xA5
- # Dump CRT Controller Registers
- CRT,RUN,HORZ_TOTAL,0x2d,0x27,0x28,0x10,0x29,0x0f,0x0b,0x3e,0x00,0x40
- CRT,RUN,START_ADDRESS_HIGH,0x00,0x00
- CRT,RUN,VERT_RETRACE_START,0xe9,0x0b,0xdf
- CRT,RUN,UNDERLINE_LOCATION,0x60,0xe7,0x0b,0xab,0xff
- CRT,RUN,BACKWARD_COMP_1,0x00,0x20,0x00,0x00
- CRT,RUN,MISC_1,0x15,0x2a,0x16,0x11
- CRT,RUN,MODE_CONTROL,0x02
- CRT,RUN,EXT_MEM_CONTROL_1,0x18,0x38,0x00,0x00,0x00
- CRT,RMW,GENERAL_OUTPUT_PORT,0xF0,0x42
- CRT,RUN,EXT_HORZ_OVERFLOW,0x00
- CRT,RUN,EXT_VERT_OVERFLOW,0x40
- CRT,RUN,EXT_MEM_CONTROL_3,0x14,0x80,0xa1,0x00
- CRT,RUN,EXT_MISC_CONTROL,0x00,0x00,0x11,0xae,0x00,0x00
- CRT,RUN,EXT_MISC_CONTROL_3,0x00
- # Lock CRTC Reg 11 for compatibility
- CRT,RMW,VERT_RETRACE_END,0x7f,0x80
- # Dump ENG Register
- ENG,RUN,ADV_FUNCTION_CONTROL,0x01
- # Dump MISCOUT Register
- DIR,RUN,MISC_WRITE,0xef
- CLK_IND, RUN, MISC_CONTROL_1, 0x01
- CLK_IND, RUN, MISC_CONTROL_2, 0x43
- CLK_IND, RUN, FREQ_2, 0x21
- CLK_IND, RUN, MISC_CLOCK_CONTROL, 0x01
- CLK_IND, RUN, FIXED_PLL_REFDIV, 0x07
- CRT,RUN,LATCH_DATA, 0x08
-