PC World Komputer 1996 February/PCWK0296.iso/sharewar/dos/program/interupt/ports.lst

File List | 1995-08-13 | 197.8 KB | 5,269 lines

PORT LIST            Release 47        Last Change: 8/13/95
[This file was provided by Wim Osterholt (2:512/56 or [e-mail]).]

        XT, AT and PS/2     I/O port addresses

      Do NOT consider this information as complete and accurate.
      If you want to do hardware programming ALWAYS check the
      appropriate data sheets. Be aware that erroneously programming
      can put your hardware or your data at risk.

      There are a few memory mapped addresses in use for I/O functions which
      are listed at the end of this file; see MEMORY.LST for memory-mapped
      I/O accessible from real mode.

---------------------------------------------
 New Format:

PPPPw RW  description

where:    PPPP    is the four-digit hex port number
    w    is blank for byte-size port, 'w' for word, and 'd' for dword
    R    is blank if not readable, 'r' if sometimes readable, 'R' if
        "always" readable, '?' if readability unknown
    W    is blank if not writable, 'w' if sometimes writable, 'W' if
        "always" writable, '?' if writability unknown
[Note: I have not yet completed the format conversion; the heading lines
 will be changed to a form similar to that used by the main list in INTER48:
PORT 0000-001F - DMA 1 - FIRST DIRECT MEMORY ACCESS CONTROLLER (8237)
 and
PORT 0018 - PS/2 - EXTENDED FUNCTION REGISTER]
----------P0000001F--------------------------
0000-001F ----    DMA 1    (first Direct Memory Access controller 8237)

0000  RW  DMA channel 0     address byte  0, then byte 1.
0001  RW  DMA channel 0 word count byte 0, then byte 1.
0002  RW  DMA channel 1     address byte  0, then byte 1.
0003  RW  DMA channel 1 word count byte 0, then byte 1.
0004  RW  DMA channel 2     address byte  0, then byte 1.
0005  RW  DMA channel 2 word count byte 0, then byte 1.
0006  RW  DMA channel 3     address byte  0, then byte 1.
0007  RW  DMA channel 3 word count byte 0, then byte 1.

0008  R      DMA channel 0-3 status register (see #P001)
0008   W  DMA channel 0-3 command register (see #P002)
0009   W  DMA channel 0-3 write request register (see #P003)
000A  RW  DMA channel 0-3 mask register (see #P004)
000B   W  DMA channel 0-3 mode register (see #P005)

000C   W  DMA clear byte pointer flip-flop
000D  R      DMA read temporary register
000D   W  DMA master clear
000E   W  DMA clear mask register
000F   W  DMA write mask register

Bitfields for DMA channel 0-3 status register:
Bit(s)    Description    (Table P001)
 7    channel 3 request active
 6    channel 2 request active
 5    channel 1 request active
 4    channel 0 request active
 3    channel terminal count on channel 3
 2    channel terminal count on channel 2
 1    channel terminal count on channel 1
 0    channel terminal count on channel 0
SeeAlso: #P002,#P059

Bitfields for DMA channel 0-3 command register:
Bit(s)    Description    (Table P002)
 7    DACK sense active high
 6    DREQ sense active high
 5    =1 extended write selection
    =0 late write selection
 4    rotating priority instead of fixed priority
 3    compressed timing
 2    =1 enable controller
    =0 enable memory-to-memory
 1-0    channel number
SeeAlso: #P001,#P004,#P005,#P060

Bitfields for DMA channel 0-3 request register:
Bit(s)    Description    (Table P003)
 7-3    reserved (0)
 2    =0 clear request bit
    =1 set request bit
 1-0    channel number
    00 channel 0 select
    01 channel 1 select
    10 channel 2 select
    11 channel 3 select
SeeAlso: #P004

Bitfields for DMA channel 0-3 mask register:
Bit(s)    Description    (Table P004)
 7-3    reserved (0)
 2    =0 clear mask bit
    =1 set mask bit
 1-0    channel number
    00 channel 0 select
    01 channel 1 select
    10 channel 2 select
    11 channel 3 select
SeeAlso: #P001,#P002,#P003,#P061

Bitfields for DMA channel 0-3 mode register:
Bit(s)    Description    (Table P005)
 7-6    transfer mode
    00 demand mode
    01 single mode
    10 block mode
    11 cascade mode
 5    direction
    =0 address increment select
    =1 address decrement select
 3-2    operation
    00 verify operation
    01 write to memory
    10 read from memory
    11 reserved
 1-0    channel number
    00 channel 0 select
    01 channel 1 select
    10 channel 2 select
    11 channel 3 select
SeeAlso: #P002,#P062
----------P0010001F--------------------------
0010-001F ----    DMA controller (8237) on PS/2 model 60 & 80
----------P0018------------------------------
0018      ----    PS/2 EXTENDED FUNCTION REGISTER

0018   W  PS/2 extended function register
----------P001A------------------------------
001A      ----    PS/2 extended function execute
----------P0020003F--------------------------
0020-003F ----    PIC 1    (Programmable Interrupt Controller 8259A)
SeeAlso: PORT 00A0h-00AFh"PIC 2",INT 08"IRQ0",INT 0F"IRQ7"

0020   W  PIC initialization command word ICW1 (see #P006)
0020   W  PIC output control word OCW2 (see #P011)
0020   W  PIC output control word OCW3 (see #P012)
0020  R      PIC  interrupt request/in-service registers after OCW3
        request register:
         bit 7-0 = 0  no active request for the corresponding int. line
             = 1  active request for corresponding interrupt line
        in-service register:
         bit 7-0 = 0  corresponding line not currently being serviced
             = 1  corresponding int. line currently being serviced

0021   W  PIC ICW2,ICW3,ICW4 immed after ICW1 to 0020 (see #P007,#P008,#P009)
0021  RW  PIC master interrupt mask register OCW1 (see #P010)

Bitfields for PIC initialization command word ICW1:
Bit(s)    Description    (Table P006)
 7-5    0 (only used in 8080/8085 mode)
 4    ICW1 is being issued
 3    (LTIM)
    =0  edge triggered mode
    =1  level triggered mode
 2    interrupt vector size
    =0 successive interrupt vectors use 8 bytes (8080/8085)
    =1 successive interrupt vectors use 4 bytes (80x86)
 1    (SNGL)
    =0  cascade mode
    =1  single mode, no ICW3 needed
 0    ICW4 needed
SeeAlso: #P007,#P008,#P009

Bitfields for PIC initialization command word ICW2:
Bit(s)    Description    (Table P007)
 7-3    address lines A0-A3 of base vector address for PIC
 2-0    reserved
SeeAlso: #P006,#P008,#P009

Bitfields for PIC initialization command word ICW3:
Bit(s)    Description    (Table P008)
 7-0    =0 slave controller not attached to corresponding interrupt pin
    =1 slave controller attached to corresponding interrupt pin
SeeAlso: #P006,#P007,#P009

Bitfields for PIC initialization command word ICW4:
Bit(s)    Description    (Table P009)
 7-5    reserved (0)
 4    running in special fully-nested mode
 3-2    mode
    0x nonbuffered mode
    10 buffered mode/slave
    11 buffered mode/master
 1    Auto EOI
 0    =0  8085 mode
    =1  8086/8088 mode
SeeAlso: #P006,#P007,#P008

Bitfields for PIC output control word OCW1:
Bit(s)    Description    (Table P010)
 7    disable IRQ7 (parallel printer interrupt)
 6    disable IRQ6 (diskette interrupt)
 5    disable IRQ5 (fixed disk interrupt)
 4    disable IRQ4 (serial port 1 interrupt)
 3    disable IRQ3 (serial port 2 interrupt)
 2    disable IRQ2 (video interrupt)
 1    disable IRQ1 (keyboard, mouse, RTC interrupt)
 0    disable IRQ0 (timer interrupt)
SeeAlso: #P011,#P012,#P058

Bitfields for PIC output control word OCW2:
Bit(s)    Description    (Table P011)
 7-5    operation
    000 rotate in auto EOI mode (clear)
    001 (WORD_A) nonspecific EOI
    010 (WORD_H) no operation
    011 (WORD_B) specific EOI
    100 (WORD_F) rotate in auto EOI mode (set)
    101 (WORD_C) rotate on nonspecific EOI command
    110 (WORD_E) set priority command
    111 (WORD_D) rotate on specific EOI command
 4    reserved (0)
 3    reserved (0)
 2-0    interrupt request to which the command applies
    (only used by WORD_B, WORD_D, and WORD_E)
SeeAlso: #P010,#P012

Bitfields for PIC output control word OCW3:
Bit(s)    Description    (Table P012)
 7    reserved (0)
 6-5    special mask
    0x  no operation
    10  reset special mask
    11  set special mask
 4    reserved (0)
 3    reserved (1)
 2    poll command
 1-0    function
    0x  no operation
    10  read interrupt request register on next read from port 0020
    11  read interrupt in-service register on next read from port 0020
SeeAlso: #P010,#P011
----------P00220023--------------------------
0022-0023 ----    Chip Set Data

0022   W  index for accesses to data port
0023  RW  chip set data
----------P00220023--------------------------
0022-0023 ----    Cyrix Cx486SLC/DLC processor Cache Configuration Registers

0022   W  index for accesses to next port (see #P013)
0023  RW  cache configuration register array (indexed by port 0022h)

(Table P013)
Values for Cyrix Cx486SLC/DLC Cache Configuration register number:
 C0h    CR0 (see #P015)
 C1h    CR1 (see #P016)
 C4h    non-cacheable region 1, start address bits 31-24
 C5h    non-cacheable region 1, start address bits 23-16
 C6h    non-cacheable region 1, start addr 15-12, size (low nibble) (see #P014)
 C7h    non-cacheable region 2, start address bits 31-24
 C8h    non-cacheable region 2, start address bits 23-16
 C9h    non-cacheable region 2, start addr 15-12, size (low nibble) (see #P014)
 CAh    non-cacheable region 3, start address bits 31-24
 CBh    non-cacheable region 3, start address bits 23-16
 CCh    non-cacheable region 3, start addr 15-12, size (low nibble) (see #P014)
 CDh    non-cacheable region 4, start address bits 31-24
 CEh    non-cacheable region 4, start address bits 23-16
 CFh    non-cacheable region 4, start addr 15-12, size (low nibble) (see #P014)

(Table P014)
Values for Cyrix Cx486SLC/DLC non-cacheable region sizes:
 00h    disabled
 01h    4K
 02h    8K
 03h    16K
 04h    32K
 05h    64K
 06h    128K
 07h    256K
 08h    512K
 09h    1M
 0Ah    2M
 0Bh    4M
 0Ch    8M
 0Dh    16M
 0Eh    32M
 0Fh    4G
SeeAlso: #P013

Bitfields for Cyrix Cx486SLC/DLC Configuration Register 0:
Bit(s)    Description    (Table P015)
 0    "NC0" first 64K of each 1M noncacheable in real/V86
 1    "NC1" 640K-1M noncacheable
 2    "A20M" enables A20M# input pin
 3    "KEN"  enables KEN# input pin
 4    "FLUSH" enables KEN# input pin
 5    "BARB" enables internal cache flushing on bus holds
 6    "C0" cache direct-mapped instead of 2-way associative
 7    "SUSPEND" enables SUSP# input and SUSPA# output pins
SeeAlso: #P013,#P016

Bitfields for Cyrix Cx486SLC/DLC Configuration Register 1:
Bit(s)    Description    (Table P016)
 0    "RPL" enables output pins RPLSET and RPLVAL#
SeeAlso: #P013,#P015
----------P00220023--------------------------
0022-0023 ----    82359 DRAM controller  from 82358DT 'Mongoose' EISA chipset
Notes:    this chip uses a chip ID of 01
    the LIM register herein use a chip ID of 1A

0022   W  index for accesses to data port (see #P017)
0023  RW  chip set data

(Table P017)
Values for 82359 DRAM contrroller register index:
 00h    bank 0
    bit 7    unknown
    bit 6-4    000 DRAM in bank 0 (standard)
        001 bank 1
        010 bank 2
        011 bank 3
        100 banks 0,1
        101 banks 2,3
        110 banks 0,1,2,3
        111 empty (standard for 1,2,3)
    bit 3-2    unknown
    bit 1-0    00 64K chips used
        01 256K
        10 1M
        11 4M
 01h    bank 1
 02h    bank 2
 03h    bank 3
 21h    chip ID register
----------P00220023--------------------------
0022-0023 ----    chipset from Etec Cheetah ET6000 (single chip)

0022  RW  chip set data
0023  ?W  index for accesses to data port (see #P018)

(Table P018)
Values for Etec Cheetah ET6000 chip set register index:
 10h    system configuration register (see #P019)
 11h    cache configuration & non-cacheable block size register (see #P020)
 12h    non-cacheable block address register
    bit 7-1    non-cacheable address, A25-A19
    bit 0    reserved
 13h    DRAM bank & type configuration register (see #P021)
 14h    DRAM configuration register (see #P022)
 15h    shadow RAM configuration register (see #P023)

Bitfields for Etec Cheetah ET6000 system configuration register:
Bit(s)    Description    (Table P019)
 7-6    00 turbo/non-turbo
    01 local device supported
    10 suspend mode
    11 illegal
 5    reserved
 4    refresh selection
    0 = AT type refresh
    1 = concurrent refresh
 3    slow refresh  95mSec enabled
 2    fast reset delay
    0 = do not use delay
    1 = wait for 2mSec delay
 1    wait for HALT after KBDRST
 0    RAM at A0000-BFFFF
    0 = AT bus cycle
    1 = local bus cycle
SeeAlso: #P018

Bitfields for Etec Cheetah ET6000 cache configuration register:
Bit(s)    Description    (Table P020)
 7-5    000 disabled
    001 512K
    010 1M
    011 2M
    100 4M
    101 8M
    110 16M
    111 32M
 4    DRAM banks
    0 = 2-bank DRAM
    1 = 4-bank DRAM
 3-0    reserved
SeeAlso: #P018

Bitfields for Etec Cheetah ET6000 DRAM bank & type configuration register:
Bit(s)    Description    (Table P021)
 7-6    bank 3 DRAM type
    00 none
    01 256K
    10 1M
    11 4M
 5-4    bank 2 DRAM type
 3-2    bank 1 DRAM type
 1-0    bank 0 DRAM type
SeeAlso: #P018

Bitfields for Etec Cheetah ET6000 DRAM configuration register:
Bit(s)    Description    (Table P022)
 7    on-board memory range 15M to 16M disabled
 6    on-board memory range 512K-640K disabled
 5    ROM chip select at C0000-DFFFF enabled
 4    RAS to CAS time
    0 = 1 SYSCLCK,    not for R0WS
    1 = 2 SYSCLCK
 3    RAS precharge time
    0 = 1.5 SYSCLCK
    1 = 2.5 SYSCLCK
 2-1    read cycle wait state
    00 = 0 wait state
    01 = 1 ws
    10 = 2 ws
    11 = 3 ws
 0    write cycle wait state
    0 = 0 ws
    1 = 1 ws
SeeAlso: #P018

Bitfields for Etec Cheetah ET6000 shadow RAM configuration register:
Bit(s)    Description    (Table P023)
 7    shadow at C0000-FFFFF
    0 = non-cacheable
    1 = cacheable and cache-write-proteced
 6    access ROM/RAM at F0000-FFFFF
    0 = read from ROM, write to RAM
    1 = read from shadow, write is protected
 5    access ROM/RAM at E0000-EFFFF
    0 = access on-board ROM, AT bus cycle
    1 = access shadow E0000-EFFFF enabled
 4    RAM at E0000-EFFFF is read-only
 3    access ROM/RAM at D0000-DFFFF
    0 = access on-board ROM, AT bus cycle
    1 = access shadow D0000-DFFFF enabled
 2    RAM at D0000-DFFFF is read-only
 1    access ROM/RAM at C0000-CFFFF
    0 = access on-board ROM, AT bus cycle
    1 = access shadow C0000-CFFFF enabled
 0    RAM at C0000-CFFFF is read-only
SeeAlso: #P018
----------P00220024--------------------------
0022-0024 ----    chipset from Pico Power, UMC or PCChips

0022  ?W  index for accesses to data port
0024  RW  chip set data
----------P00220025--------------------------
0022-0025 ----    Intel 82360SL Chipset (for 386SL)

0022   W  CPU write mode register
0023  R      configuration status register
        bit 7: 82360 configuration is open
0024   W  82360 configuration index
0025  RW  82360 configuration data

Bitfields for Intel 82360SL CPU write mode register:
Bit(s)    Description    (Table P024)
 0    unlock configuration space
 1    enable selected unit
 3-2    unit
    00 memory configuration
    01 cache
    10 internal bus
    11 external bus
----------P0022002B--------------------------
0022-002B ----    Intel 82355, part of chipset for 386sx
Note:    initialisation in POST will disable these addresses, only a hard
      reset will enable them again.

0022w RW  82335 MCR memory configuration register (if LOCK=0) (see #P025)
0024w RW  82335 RC1 roll compare register (if LOCK=0) (see #P026)
0026w RW  82335 RC2 roll compare register (if LOCK=0) (see #P026)
0028w RW  82335 CC0 address range compare register (if LOCK=0) (see #P027)
002Aw RW  82335 CC1 address range compare register (if LOCK=0) (see #P027)

Bitfields for 82335 MCR memory configuration register:
Bit(s)    Description    (Table P025)
 15-12    reserved
 11    "VRO"    video read only (0=r/w, 1=r/o)
 10    "EN#"
    0=enable video RAM accesses (A0000h-8FFFFh)
    1=disable accesses
 9    "ENADP#"
    0=enable adapter ROM accesses (C0000h-8FFFFh)
    1=disable adapter ROM accesses, shadow enabled
 8    "ROMSIZE" 0=256KB ROM, 1=512KB ROM
 7-6    "INTERL" memory interleaving
    00 = 1 memory bank installed (no interleave)
    01 = 2 memory banks installed
    10 = 3 memory banks installed
    11 = 4 memory banks installed
 5    reserved
 4    "DSIZE"     0=1MBx1DRAMs, 1=256KBx1 or 256KBx4 DRAMs
 3    "S640"     base memory size is 0=512KB, 1=640KB
 2-1    reserved
 0    "ROMEN#" ROM enable
    0 enable BIOS ROM accesses (E0000h-FFFFFh)
    1 disable BIOS ROM accesses, enable shadow
Note:    One of the remaining reserved bits is the LOCK bit, which will be set
      during power on, disabling access to the 82335s registers.

Bitfields for 82335 roll compare register:
Bit(s)    Description    (Table P026)
 15-9    selects address range to be remapped (C23-C17)
 8    reserved
 7-1    selects address bits to be included in re-mapping comparision (M23-M17)
 0    "EN" enables roll address mapping

Bitfields for 82335 address range compare register:
Bit(s)    Description    (Table P027)
 15-11    specifies top of address range (C23-C19)
 10-8    reserved
 7-3    selects address bits to be included in address range comparision
      (M23-M19)
 2-1    reserved
 0    "EN" enable address range comparision
----------P00240028--------------------------
0024-0028 ---- Headland HTK340 Shasta 386/486 Chipset

0024  Rw  data port
0028  ?W  index port to chipset registers (see #P028,#P029)

(Table P028)
Values for Headland HT321 register index:
 00h R    chip/revision,read-only
      bit7-4: reserved (=0)
      bit3-0: chip revision, 0=A, 1=B, 3=D
 01h RW system clocking (default=00h)
      bit7-4: reserved (=0)
      bit3-0: ISA speed set
 02h RW system parameters (default=00h)
      bit7-6: IO recovery time (rev. D+)
      bit5    : parity override
      bit4-3: cycle-width
      bit2    : 0/1 port 92 functionality
      bit1    : IO decode
      bit0    : 0/1 posted backplane MEMWN cycles
 04h RW co-processor (default=00h)
      bit7-3: reserved (=0)
      bit2=1: soft-NPU reset blocked (386 only)
      bit1=1: weitek installed
      bit0=1: 387 installed
 06h RW DMA (default=00h)
      bit7    : reserved (=0)
      bit6    : 1/0 IOCHRDY during master cycle (rev. C+)
      bit5    : 0/1 fast sample DMA
      bit4-3: DMA waitstate 00b=3 .. 11b=0
      bit2    : 0/1 DMA flow-through mode
      bit1    : 0/1 extended DMA page register
      bit0    : DMA clock
 07h RW EPROM (default=00h)
      bit7-6: reserved (=0)
      bit5    : 0/1 EADS CACHE invalidation for EPROM writes (rev. D+)
      bit4    : 0/1 ROMEN for EPROM writes (rev. C+)
      bit3    : 0/1 middle BIOS region of 64KB space below 16MB
      bit2    : ROM-size (0=64KB, 1=128KB)
      bit1    : V-BIOS-add (0=separate, 1=same device)
      bit0    : ROM-access time (0=250ns, 1=125ns)
 08h RW I/O and memory map holes (default=00h)
      bit7-4: reserved (=0)
      bit3    : 0/1 I/O map hole-A
      bit2    : reserved (=0)
      bit1    : 0/1 memory map hole-B
      bit0    : reserved (=0)
 10h RW hole-A low address (default=00h)
 11h RW hole-A high address (default=00h)
 19h RW mem hole-B start address, lower (default=00h)
 1Ah RW mem hole-B start address, higher (default=00h)
      bit7-6: reserved (=0)
      bit5-0: address of mem hole-B start
 1Ch RW mem hole-B end address, lower (default=00h)
 1Dh RW mem hole-B end address, higher (default=00h)
      bit7-6: reserved (=0)
      bit5-0: address of mem hole-B end
SeeAlso: #P029

(Table P029)
Values for Headland HT342 register index:
 20h R    identifier port read
      bit7-4: DRAM controller identifier (0010b)
      bit3-0: revision number (0=A)
 21h R    feature port read    (default=00h)
 24h RW DRAM options port #1 (default=00h)
      bit7    : 0/1 staggered refresh
      bit6    : refresh type
      bit5    : 0/1 DRAM paging
      bit4-2: CAS interleave
      bit1-0: banks
 25h    DRAM options port #2 (default=00h)
      bit7-6: DRAM bank 1 type
      bit5-4: DRAM bank 2 type
      bit3-2: DRAM bank 1?? type
      bit1-0: DRAM bank 0 type
 26h RW DRAM options port #3 (default=FFh)
      bit7    : CAS hold on RAS (CAS before RAS refresh)
      bit6    : CAS precharge
      bit5    : CAS burst delay
      bit4    : CAS delay (writes)
      bit3    : CAS delay (reads)
      bit2    : CAS active time (writes)
      bit1-0: CAS active time (reads)
 27h RW DRAM options port #4 (default=FFh)
      bit7    : RAS delay
      bit6-5: RAS active (writes)
      bit4-2: RAS active (reads)
      bit1-0: RAS precharge
 28h RW data transfer control port (default=00h)
    doubled indexed registers (28h-2Ah)
      bit7    : initiate transfer
      bit6    : read/write transfer
      bit5-4: reserved
      bit3-0: transfer/destination
 29h RW RAM address register (default=00h)
    doubled indexed registers (28h-2Ah)
      bit7-5: reserved
      bit4-0: RAM address registers contents
 2Ah RW data transfer port   (default=00h)
    doubled indexed registers (28h-2Ah)
      bit7-6: reserved
      bit5    : EMS translation
      bit4    : reserved
      bit3    : 0/1 cacheing
      bit2    : 0/1 write
      bit1    : 0/1 read
      bit0    : 0/1 shadow
 2Bh RW other options          (default=00h)
      bit7    : reserved
      bit6    : 0/1 middle BIOS
      bit5    : 0/1 data pipeline
      bit4    : 0/1 data pipeline
      bit3    : IO-decode
      bit2    : reserved
      bit1    : 16bit DMA bridge
      bit0    : 0/1 write buffering
 2Dh RW DRAM options port #5 (default=03h)
      bit7-5: reserved
      bit4    : 0/1 10µs RAS timeout
      bit3-2: BUS speed
      bit1-0: BUS recovery for DRAM cycles
           00b=0: 4-1-1-1    10b=0.5
           01b=1: 4-2-2-2    11b=1??
 82h    read transfer
 C2h    write transfer
SeeAlso: #P028
----------P00260027--------------------------
0026-0027 ----    Power Management

0026   W  index for data port
0027  RW  power management data
----------P002E002F--------------------------
002E-002F ----    Dell Enhanced Parallel Port
SeeAlso: 015C, 026E, 0398

002E   W  index for data port (see #P030)
002F  RW  EPP command data

(Table P030)
Values for Dell Enhanced Parallel Port register index:
 00h    bit 0: ???
 02h    bit 7: port in bidirectional mode
 04h    bits 0 and 2: ECP/EPP mode control
----------P0038003F--------------------------
0038-003F ----    PC radio by CoZet Info Systems
        The I/O address range is dipswitch selectable from:
           038-03F and 0B0-0BF
           078-07F and 0F0-0FF
           138-13F and 1B0-1BF
           178-17F and 1F0-1FF
           238-23F and 2B0-2BF
           278-27F and 2F0-2FF
           338-33F and 3B0-3BF
           378-37F and 3F0-3FF
        All of these addresses show a readout of FF in initial state.
        Once started, all of the addresses show     FB, whatever might
        happen.
----------P0040005F--------------------------
0040-005F ----    PIT  (Programmable Interval Timer  8253, 8254)
         XT & AT uses 40-43    PS/2 uses 40, 42,43,44, 47

0040  RW  PIT  counter 0, counter divisor          (XT, AT, PS/2)
0041  RW  PIT  counter 1, RAM refresh counter    (XT, AT)
            don't set below 3 on PCs (default 12h)
0042  RW  PIT  counter 2, cassette & speaker    (XT, AT, PS/2)
    During normal operation mode (8253) 40h-42h set the counter values on
    write and get the current counter value on read. In 16bit modes two
    consequtive writes/reads must be issued, first with the low byte,
    followed by the high byte. In 8254 read back modes, all selected
    counters and status are latched and must be read out completely
    before normal operation is valid again.     Each counter switches back
    to normal operation after read out.  In 'get status and counter'
    mode the first byte read is the status, followed by one or two
    counter values. (see #P031)
0043  RW  PIT  mode port, control word register for counters 0-2 (see #P032)
    Once a control word has been written (43h), it must be followed
    immediately by performing the corresponding action to the counter
    registers (40h-42h), else the system may hang!!
0044  RW  PIT  counter 3 (PS/2, EISA)
        used as fail-safe timer. generates an NMI on time out.
        for user generated NMI see at 0462.
0047   W  PIT  control word register counter 3 (PS/2, EISA)
         bit 7-6 = 00  counter 3 select
             = 01  reserved
             = 10  reserved
             = 11  reserved
         bit 5-4 = 00  counter latch command counter 3
             = 01  read/write counter bits 0-7 only
             = 1x  reserved
         bit 3-0 = 00
0048      EISA
0049      8254 timer 2, not used (counter 1)
004A      EISA programmable interval timer 2
004B      EISA programmable interval timer 2

Bitfields for 8254 PIT counter status byte:
Bit(s)    Description    (Table P031)
 7    PIN status of OUTx Pins (1=high, 0=low)
 6    counter start value loaded
    =0: yes, so counter latch is valid to be read
    =1: no, wait for counter latch to be set (may last a while)
5-0    counter mode, same as bit5-0 at 43h
SeeAlso: #P032

Bitfields for 8253/8254 PIT mode control word:
Bit(s)    Description    (Table P032)
 7-6    counter select
    00  counter 0 select
    01  counter 1 select      (not PS/2)
    10  counter 2 select
    11  (8253) reserved
        (8254) read back counter (see #P031)
---if counter select---
 5-4    counter access
    00  counter latch command
    01  read/write counter bits 0-7 only
    10  read/write counter bits 8-15 only
    11  read/write counter bits 0-7 first, then 8-15
 3-1    counter mode
    000 mode 0 select - zero detection interrupt
    001 mode 1 select - programmable one shot
    x10 mode 2 select - rate generator
    x11 mode 3 select - square wave generator
        divisor factor 3 not allowed!
    100 mode 4 select - software triggered strobe
    101 mode 5 select - hardware triggered strobe
 0    counting style
    0  binary counter 16 bits
    1  BCD counter (4 decades)
---if read back---
 5-4    what to read
    00 reserved
    01 counter status
    10 counter value
    11 counter status and value
 3    select counter 2
 2    select counter 1
 1    select counter 0
 0    reserved (0)
Note:    after issuing a read back 'get status' command, any new read back
      command is ignored until the status is read from all selected
      counters.
----------P0060006F--------------------------
0060-006F ----    KEYBOARD CONTROLLER 804x (8041, 8042)  (or PPI (8255) on PC,XT)
Note:    XT uses 60-63, AT uses 60-64

0060  RW  KB controller data port or keyboard input buffer (ISA, EISA)
        should only be read from after status port bit0 = 1
        should only be written to if status port bit1 = 0
0060  R      KeyBoard or KB controller data output buffer (via PPI on XT)
        PC: input from port A of 8255, if bit7 in 61h set (see #P045)
        get scancodes, special codes (in PC: with bit7 in 61h cleared)
          (see #P040)

0061  R      KB controller port B control register (ISA, EISA)
        system control port for compatibility with 8255 (see #P042)
0061   W  KB controller port B (ISA, EISA)   (PS/2 port A is at 0092)
        system control port for compatibility with 8255 (see #P041)
0061   W  PPI Programmable Peripheral Interface 8255 (XT only)
        system control port (see #P043)
0062  RW  PPI (XT only) data port C (see #P044)
0063  RW  PPI (XT only) command mode register (see #P046)

0064  R      keyboard controller read status (see #P047,#P048,#P049)
0064   W  keyboard controller input buffer (ISA, EISA) (see #P050)

0064   W  (Amstrad/Schneider PC1512) set 'DIP switch S1' setting
      stored in CMOS RAM that PPI should report for compatibility
0065   W  (Amstrad/Schneider PC1512) set 'DIP switch S2' RAM size setting
      stored in CMOS RAM, that PPI port C (PORT 0064h) should report for
      compatibility

0065  R      communications port (Olivetti M24)

0068   W  (HP-Vectra) control buffer (HP commands) (see #P051)
0069  R      (HP-Vectra) SVC (keyboard request SerViCe port)
006A   W  (HP-Vectra) Acknowledge (clear processing, done)
006C-006F    HP-HIL    (Human Interface Link = async. serial inputs 0-7)

Bitfields for AT keyboard controller input port:
Bit(s)    Description    (Table P033)
 7    =0  keyboard inhibited
 6    =0  CGA, else MDA
 5    =0  manufacturing jumper installed
 4    =0  system RAM 512K, else 640K
 3-0    reserved
SeeAlso: #P034,#P036

Bitfields for AT keyboard controller input port (Compaq):
Bit(s)    Description    (Table P034)
 7    security lock is unlocked
 6    =0  Compaq dual-scan display, 1=non-Compaq display
 5    system board dip switch 5 is OFF
 4    =0  auto speed selected, 1=high speed selected
 3    =0  slow (4MHz), 1 = fast (8MHz)
 2    no math coprocessor installed
 1-0    reserved
SeeAlso: #P035

Bitfields for AT keyboard controller output port:
Bit(s)    Description    (Table P035)
 7    keyboard data output
 6    keyboard clock output
 5    input buffer NOT full
 4    output buffer NOT empty
 3    reserved (see note)
 2    reserved (see note)
 1    gate A20
 0    system reset
Note:    bits 2 and 3 are the turbo speed switch or password lock on
      Award/AMI/Phoenix BIOSes.  These bits make use of nonstandard
      keyboard controller BIOS functionality to manipulate
        pin 23 (8041 port 22) as turbo switch for AWARD
        pin 35 (8041 port 15) as turbo switch/pw lock for Phoenix
SeeAlso: #P033,#P036

Bitfields for HP Vectra keyboard controller output port:
Bit(s)    Description    (Table P036)
 7-5    reserved
 4    output buffer full (OBF) interrupt
 3    HP SVC interrupt
 2    HP-HIL controller AutoPoll
 1    A20 gate
 0    system reset
SeeAlso: #P035,#P037

Bitfields for HP Vectra command byte:
Bit(s)    Description    (Table P037)
 7    reserved (0)
 6    scancode conversion mode (1 = PC/XT, 0 = PC/AT)
 5    unused
 4    disable keyboard (unless bit 3 set)
 3    override keyboard disable
 2    System Flag (may be read from port 0060h)
 1    reserved
 0    OBF interrupt enable
SeeAlso: #P036

(Table P038)
Values for keyboard commands (data also goes to PORT 0060h):
Value    Count    Description
 EDh    double    set/reset mode indicators Caps Num Scrl
        bit 2 = CapsLk, bit 1 = NumLk, bit 0 = ScrlLk
        all other bits must be zero.
 EEh    sngl    diagnostic echo. returns EEh.
 EFh    sngl    NOP (No OPeration). reserved for future use
 EF+26h    double    [Cherry MF2 G80-1501HAD] read 256 bytes of chipcard data
        keyboard must be disabled before this and has to
        be enabled after finished.
 F0h    double    get/set scan code set
        00h get current set
        01h scancode set 1 (PCs and PS/2 mod 30, except Type 2 ctrlr)
        02h scancode set 2 (ATs, PS/2, default)
        03h scancode set 3
 F2h    sngl    read keyboard ID (read two ID bytes)
        AT keyboards returns FA (ACK)
        MF2 returns AB 41 (translation) or
                AB 83 (pass through)
 F3h    double    set typematic rate/delay
        format of the second byte:
        bit7=0 : reserved
        bit6-5 : typemativ delay
             00b=250ms     10b= 750ms
             01b=500ms     11b=1000ms
        bit4-0 : typematic rate
             00000b=30.0   10000b=7.5
             00001b=26.7   10001b=6.7
             00010b=24.0   10010b=6.0
             00011b=21.8   10011b=5.5
             00100b=20.0   10100b=5.0
             00101b=18.5   10101b=4.6
             00110b=17.1   10110b=4.3
             00111b=16.0   10111b=4.0
             01000b=15.0   11000b=3.7
             01001b=13.3   11001b=3.3
             01010b=12.0   11010b=3.0
             01011b=10.9   11011b=2.7
             01100b=10.0   11100b=2.5
             01101b= 9.2   11101b=2.3
             01110b= 8.5   11110b=2.1
             01111b= 8.0   11111b=2.0
 F4h    sngl    enable keyboard
 F5h    sngl    disable keyboard. set default parameters (no keyboard scanning)
 F6h    sngl    set default parameters
 F7h    sngl    [MCA] set all keys to typematic (scancode set 3)
 F8h    sngl    [MCA] set all keys to make/release
 F9h    sngl    [MCA] set all keys to make only
 FAh    sngl    [MCA] set all keys to typematic/make/release
 FBh    sngl    [MCA] set al keys to typematic
 FCh    double    [MCA] set specific key to make/release
 FDh    double    [MCA] set specific key to make only
 FEh    sngl    resend last scancode
 FFh    sngl    perform internal power-on reset function
Note:    each command is acknowledged by FAh (ACK), if not mentioned otherwise.
      See PORT 0060h-R for details.
SeeAlso: #P039

(Table P039)
Values for Mouse functions (for PS/2-like pointing devices):
Value    Count    Description
 E6h    sngl    set mouse scaling to 1:1
 E7h    sngl    set mouse scaling to 2:1
 E8h    double    set mouse resolution
        (00h=1/mm, 01h=2/mm, 02h=4/mm, 03h=8/mm)
 E9h    sngl    get mouse information
        read two status bytes:
          byte 0
            bit 7 unused
            bit 6 remote rather than stream mode
            bit 5 mouse enabled
            bit 4 scaling set to 2:1
            bit 3 unused
            bit 2 left button pressed
            bit 1 unused
            bit 0 right button pressed
          byte 1: resolution
 EAh    sngl    set mouse to stream mode (mouse sends data on any changes)
 EBh    sngl    get mouse data (from mouse to controller)
        on reading, each data packet consists of 8 bytes:
         +0: status
              bit7    : y-data overrun
              bit6    : x-data overrun
              bit5    : y-data negative
              bit4    : x-data negative
              bit3-2=0: reserved
              bit1    : right button pressed
              bit0    : left button pressed
         +1: reserved
         +2: x-data
         +3: reserved
         +4: y-data
         +5: reserved
         +6: z-data (0)
         +7: reserved
 ECh    sngl    reset mouse wrap mode (to normal mode)
 EEh    sngl    set wrap mode
 F0h    sngl    set remote mode (instead of stream mode), mouse sends data
          only on issueing command EBh.
 F2h    sngl    read mouse ID (read one, two?? ID bytes)
        00h=mouse
 F3h    double    set mouse sample rate in reports per second
        0Ah=10/s       50h= 80/s
        14h=20/s       64h=100/s
        28h=40/s       C8h=200/s
        3Ch=60/s
 F4h    sngl    enable mouse (in stream mode)
 F5h    sngl    disable mouse (in steam mode), set default parameters
 F6h    sngl    reset to defaults: 100/s, scaling 1:1, stream-mode, 4/mm,
          disabled
 FEh    sngl    resend last mouse data (8 bytes, see EBh)
 FFh    sngl    reset mouse
Notes:     must issue command D4h to port 64h first to access mouse functions
     all commands except ECh and FFh are acknowledged by FAh (ACK) or
       FEh (Resend); get mouse ID (F2h) returns mouse ID.
SeeAlso: #P038

(Table P040)
Values for keyboard special codes:
 00h    (MF2 in codeset2&3 or AT keyboards) keydetection/overrun error
 00h    (mouse) ID
 AAh    BAT completion code (sent after errorfree Basic Assurance Test)
 ABh    first byte of general MF2 keyboard ID
 EEh    Echo command return
 FAh    Acknowledge (all general commands except Resend and Echo)
 FAh    (mouse) Acknowledge (all commands except commands ECh,F2h,FFh)
 FCh    (MF2) BAT Failure Code (error in second half of the power on self test)
 FDh    (AT-keyboard) BAT Failure Code (error in the second half of the
      power-on self test)
 FEh    Resend: CPU to controller should resend last keyboard-command
 FEh    (mouse) CPU to controller should resend last mouse-command
 FFh    (MF2 in codeset1) keydetection/overrun error
Note:    keyboard stops scanning and waits for next command after returning
      code FCh or FDh
SeeAlso: PORT 0060h-R

Bitfields for KB controller port B (system control port) [output]:
Bit(s)    Description    (Table P041)
 7    pulse to 1 for IRQ1 reset (PC,XT)
 6-4    reserved
 3    I/O channel parity check disable
 2    RAM parity check disable
 1    speaker data enable
 0    timer 2 gate to speaker enable
SeeAlso: PORT 0061h-W,#P042

Bitfields for KB controller port B control register (system control port) [input]:
Bit(s)    Description    (Table P042)
 7    RAM parity error occurred
 6    I/O channel parity error occurred
 5    mirrors timer 2 output condition
 4    toggles with each refresh request
 3    NMI I/O channel check status
 2    NMI parity check status
 1    speaker data status
 0    timer 2 clock gate to speaker status
SeeAlso: PORT 0061h-R,#P041

Bitfields for Progr. Peripheral Interface (8255) system control port [output]:
Bit(s)    Description    (Table P043)
 7    clear keyboard (only pulse, normally kept at 0)
 6    =0  hold keyboard clock low
 5    NMI I/O parity check disable
 4    NMI RAM parity check disable
 3    =0 read low nybble of switches S2
    =1 read high nybble of switches S2
 2    reserved, often used as turbo switch
    original PC: cassette motor off
 1    speaker data enable
 0    timer 2 gate to speaker enable
Note:    bits 2 and 3 are sometimes used as turbo switch
SeeAlso: PORT 0061h-W,#P0051,#P044,#P045,#P046

Bitfields for PPI (XT only) data port C:
Bit(s)    Description    (Table P044)
 7    RAM parity error occurred
 6    I/O channel parity error occurred
 5    timer 2 channel out
 4    reserved
    original PC: cassette data input
---
 3    system board RAM size type 1
 2    system board RAM size type 2
 1    coprocessor installed
 0    loop in POST
---
 3-0    DIL switch S2 high/low nybble (depending on PORT 0061h bit 3)
SeeAlso: PORT 0062h-RW,#P043,#P045,#P046

Bitfields for PPI (PC,XT only) equipment switches [input]:
Bit(s)    Description    (Table P045)
 7-6    number of disk drives
    00  1 diskette drive
    01  2 diskette drives
    10  3 diskette drives
    11  4 diskette drives
 5-4    initial video
    00  reserved (video adapter has on-board BIOS)
    01  40*25 color (mono mode)
    10  80*25 color (mono mode)
    11  MDA 80*25
 3-2    memory size (using 256K chips)
    00  256K
    01  512K
    10  576K
    11  640K
 3-2    memory size (using 64K chips)
    00  64K
    01  128K
    10  192K
    11  256K
 3-2    memory size (original PC)
    00  16K
    01  32K
    10  48K
    11  64K
 1-0    reserved
 1    NPU (math coprocessor) present
 0    boot from floppy
SeeAlso: #P044,#P046,PORT 0060h-R

Bitfields for PPI (8255) command mode register:
Bit(s)    Description    (Table P046)
 7    activation function (0 = bit set/reset, 1 = mode set function)
 6,5    port A mode: 00 = mode0, 01 = mode1, 1x = mode2
 4    port A direction: 0 = output, 1 = input
 3    port C bits 7-4 direction: 0 = output, 1 = input
 2    port B mode: 0 = mode0, 1 = mode1
 1    port B direction: 0 = output, 1 = input
 0    port C bits 3-0 direction: 0 = output, 1 = input
Note:    Attention: Never write anything other than 99h to this port
      (better: never write anything to this port, only during BIOS
      init), as other values may connect multiple output drivers
      and will cause hardware damage in PC/XTs!  By setting command
      word to 99h, PPI will be set in input/output modes as it is
      necessary to support the commonly known IO-ports 60, 61, 62
      as desired.
SeeAlso: #P043,#P044,#P045

Bitfields for keyboard controller read status (ISA, EISA):
Bit(s)    Description    (Table P047)
 7    parity error on transmission from keyboard
 6    receive timeout
 5    transmit timeout
 4    keyboard interface inhibited by keyboard lock
 3    =1 data written to input register is command (PORT 0064h)
    =0 data written to input register is data (PORT 0060h)
 2    system flag status: 0=power up or reset     1=selftest OK
 1    input buffer full (input 60/64 has data for 8042)
    no write access allowed until bit clears
 0    output buffer full (output 60 has data for system)
    bit is cleared after read access
SeeAlso: PORT 0064h-R,#P048,#P049,#P050

Bitfields for keyboard controller read status (MCA):
Bit(s)    Description    (Table P048)
 7    parity error on transmission from keyboard
 6    general timeout
 5    mouse output buffer full
 4    keyboard interface inhibited by keyboard lock
 3    =1 data written to input register is command (PORT 0064h)
    =0 data written to input register is data (PORT 0060h)
 2    system flag status: 0=power up or reset     1=selftest OK
 1    input buffer full (60/64 has data for 804x)
    no write access allowed until bit clears
 0    output buffer full (output 60 has data for system)
    bit is cleared after read access
SeeAlso: #P047,#P049,#P050

Bitfields for keyboard controller read status (Compaq):
Bit(s)    Description    (Table P049)
 7    parity error detected (11-bit format only). If an
      error is detected, a Resend command is sent to the
      keyboard once only, as an attempt to recover.
 6    receive timeout. transmission didn't finish in 2mS.
 5    transmission timeout error
    bit 5,6,7  cause
        1 0 0  No clock
        1 1 0  Clock OK, no response
        1 0 1  Clock OK, parity error
 4    =0 security lock engaged
 3    =1 data in OUTPUT register is command
    =0 data in OUTPUT register is data
 2    system flag status: 0=power up or reset     1=soft reset
 1    input buffer full (60/64 has data for 804x)
    no write access allowed until bit clears
 0    output buffer full (port 60 has data for system)
    bit is cleared after read access
SeeAlso: #P047,#P048,#P050

(Table P050)
Values for keyboard controller commands (data goes to port 0060)::
Value        Description
 20h    read    read byte zero of internal RAM, this is the last KB command
          sent to the 8041/8042
    Compaq    put current command byte on port 0060 (see #P052,#P053)
 21-3F    read    reads the byte specified in the lower 5 bits of the command
          in the 804x's internal RAM
 60-7F    double    writes the data byte to the address specified in the 5 lower
          bits of the command
 60h    Compaq    Load new command (60 to [64], command to [60]) (see #P053)
        (also general AT-class machines)
 A0h    AMI    get ASCIZ copyright message on port 0060
 A1h    AMI    get controller version byte on port 0060
 A1h    Compaq    unknown speedfunction ??
 A2h    Compaq    unknown speedfunction ??
 A2h    AMI    set keyboard controller pins 22 and 23 low
 A3h    Compaq    Enable system speed control
 A3h    AMI    set keyboard controller pins 22 and 23 high
 A4h    MCA    check if password installed
 A4h    Compaq    Toggle speed
 A4h    AMI    set internal system speed flag to low
 A5h    MCA    load password
 A5h    AMI    set internal system speed flag to high
 A5h    Compaq    Special read. the 8042 places the real values of port 2
          except for bits 4 and 5 wich are given a new definition in
          the output buffer. No output buffer full is generated.
            if bit 5 = 0, a 9-bit keyboard is in use
            if bit 5 = 1, an 11-bit keyboard is in use
            if bit 4 = 0, output-buff-full interrupt disabled
            if bit 4 = 1, output-buffer-full interrupt enabled
 A6h    MCA    check password
 A6h    AMI    get internal system speed flag on port 0060
 A6h    Compaq    unknown speedfunction ??
 A7h    MCA    disable mouse port
 A7h    AMI    set internal flag indicating bad write cache
 A8h    MCA    enable mouse port
 A8h    AMI    set internal flag indicating good write cache
 A9h    MCA    test mouse port
 A9h    AMI    get internal flag indicating cache OK to 0060
 AAh    sngl    initiate self-test. will return 55h to data port if self-test
          successful, FCh if failed
 AAh    Compaq    initializes ports 1 and 2, disables the keyboard and clears
          the buffer pointers. It then places 55h in the output buffer.
 ABh    sngl    initiate interface test. result values:
        00h no error
        01h keyboard clock line stuck low
        02h keyboard clock line stuck high
        03h keyboard data line is stuck low
        04h keyboard data line stuck high
        05h (Compaq only) diagnostic feature
 ACh    read    diagnostic dump. the contents of the 804x RAM, output port,
          input port, status word are sent.
 ADh    sngl    disable keyboard (sets bit 4 of commmand byte)
 ADh    Vectra    HP Vectra diagnostic dump
 AEh    sngl    enable keyboard     (resets bit 4 of commmand byte)
 AFh    AWARD    Enhanced Command: read keyboard version
 B1h    AMI    set keyboard controller P11 line low
 B2h    AMI    set keyboard controller P12 line low
 B3h    AMI    set keyboard controller P13 line low
 B4h    AMI    set keyboard controller P22 line low
 B5h    AMI    set keyboard controller P23 line low
 B8h    AMI    set keyboard controller P10 line high
 B9h    AMI    set keyboard controller P11 line high
 BAh    AMI    set keyboard controller P12 line high
 BBh    AMI    set keyboard controller P13 line high
 BCh    AMI    set keyboard controller P22 line high
 BDh    AMI    set keyboard controller P23 line high
 C0h    read    read input port and place on PORT 0060h
        bit 7    keyboard NOT locked
        bit 6    =0 first video is CGA
            =1 first video is MDA
        bit 5    =0 factory testmode
            =1 normal
        bit 4    =0 256KB RAM, 1=512KB
        bit 5,3-0 are used in Intel chipset 386sx machines with
            AMI/Phoenix BIOSes for BIOS specific hardware settings
 C0h    Compaq    places status of input port in output buffer.  Use this
          command only when the output buffer is empty
 C1h    MCA    Enhanced Command: poll input port Low nibble
 C2h    MCA    Enhanced Command: poll input port High nibble
 C8h    AMI    unblock keyboard controller lines P22 and P23
 C9h    AMI    block keyboard controller lines P22 and P23
 CAh    AMI    read keyboard mode, return in 0060 bit 0
          (bit clear if ISA mode, set if PS/2 mode)
 CBh    AMI    set keyboard mode (write back mode byte returned by CAh,
          modifying only bit 0)
 D0h    read    read output port and place on PORT 0060h (see #P054)
 D0h    Compaq    places byte in output port in output buffer. Use this command
          only when the output buffer is empty
 D1h    double    write output port.  The next byte written to port 0060h will
          be written to the 804x output port; the original IBM AT and
          many compatibles use bit 1 of the output port to control
          the A20 gate.
        Important: bit 0 (system reset) should always be set here, as
              the system may hang constantly, use pulse output port
              (FEh) instead.
 D1h    Compaq    the system speed bits are not set by this command use
          commands A1-A6 (!) for speed functions.
 D2h    MCA    Enhanced Command: write keyboard output buffer
 D3h    MCA    Enhanced Command: write pointing device out.buf.
 D4h    MCA    write to mouse/pointing device instead of to keyboard; this
          controller command must precede every PORT 0060h command
          directed to the mouse, otherwise it will be sent to the
          keyboard
 D4h    AWARD    Enhanced Command: write to auxiliary device
 DDh    sngl    disable address line A20 (HP Vectra only???)
        default in Real Mode
 DFh    sngl    enable address line A20 (HP Vectra only???)
 E0h    read    read test inputs.
        bit0 = kbd clock, bit1 = kbd data
 Exxx    AWARD    Enhanced Command: active output port
 EDh    double    this is a two part command to control the state of the
          NumLock, CpasLock and ScrollLock LEDs
        The second byte contains the state to set LEDs.
            bit 7-3    reserved. should be set to 0.
            bit 2 = 0    Caps Lock LED off
            bit 1 = 0    Num Lock LED off
            bit 0 = 0    Scroll Lock LED off
 F0-FF    sngl    pulse output port low for 6 microseconds.
        bits 0-3 contain the mask for the bits to be pulsed.  A bit is
          pulsed if its mask bit is zero
        bit0=system reset. Don't set to zero. Pulse only!
Note:     keyboard controllers are widely different from each other.  You
       cannot generally exchange them between different machines.
     (Award) Derived from Award's Enhanced KB controller advertising sheet.
     (Compaq) Derived from the Compaq Deskpro 386 Tech. Ref. Guide.

(Table P051)
Values for HP Vectra control buffer command code:
 00h-54h insert standard key make code into 8041 scancode buf
 55h-77h insert HP key make code into 8041 scancode buffer
 7Ah    pass through next data byte
 7Bh    set RAM Switch to 0
 7Ch    set RAM Switch to 1 (default)
 7Dh    set CRT Switch to 0
 7Eh    set CRT Switch to 1 (default)
 7Fh    reserved
 80h-D4h insert standard key break code into scancode buffer
 D5h-F7h insert HP key break code into scancode buffer
 F8h    enable AutoPoll
 F9h    disable AutoPoll
 FAh-FEh reserved
 FFh    keyboard overrun
SeeAlso: PORT 0068h-W

Bitfields for Compaq keyboard command byte:
Bit(s)    Description    (Table P052)
 7    reserved
 6    =1 convert KB codes to 8086 scan codes
 5    =0 use 11-bit codes, 1=use 8086 codes
 4    =0 enable keyboard, 1=disable keyboard
 3    ignore security lock state
 2    this bit goes into bit2 status reg.
 1    reserved (0)
 0    generate interrupt when output buffer full
SeeAlso: #P053

Bitfields for keyboard command byte (alternate description):
Bit(s)    Description    (Table P053)
 7    reserved (0)
 6    IBM PC compatibility mode
 5    IBM PC mode
    no parity, no stop bits, no translation
    (PS/2) force mouse clock low
 4    disable keyboard (clock)
 3    inhibit override
    (PS/2) reserved
 2    system flag
 1    reserved (0)
    (PS/2) enable mouse output buffer full interrupt
 0    enable output buffer full interrupt
SeeAlso: #P052,#P054

Bitfields for keyboard controller output port:
Bit(s)    Description    (Table P054)
 7    keyboard data (output)
 6    keyboard clock (output)
 5    input buffer empty
 4    output buffer empty
 3    undefined
 2    undefined
    used by Intel 386sx Chipset with AMI/Phoenix BIOSes for BIOS-specific
      configuration of turbo switch
 1    gate address A20
 0    system reset
Note:    bit 0 (system reset) should always be set when writing the output
      port, as the system may hang constantly; use pulse output port
      (command FEh) instead.
SeeAlso: #P053
----------P0065------------------------------
0065      ----    AT&T 6300+ high/low chip select
----------P0065------------------------------
0065      ----    ???

0065  RW  ???
        bit 2: A20 gate control (set = A20 enabled, clear = disabled)
----------P00660067--------------------------
0066-0067 ----    AT&T 6300+ system configuration switches
----------P0066------------------------------
0066      ----    IBM 4717 Magnetic Stripe Reader - ???
SeeAlso: PORT 0069h"Magnetic Stripe"
----------P0068------------------------------
0068      ----    C&T chipsets, turbo mode control
----------P0069------------------------------
0069      ----    IBM 4717 Magnetic Stripe Reader - ???
SeeAlso: PORT 0066h"Magnetic Stripe"
----------P006B006F--------------------------
006B-006F ----    SSGA control registers

006B  ??  RAM enable/remap
006C  ??  undocumented
006D  ??  undocumented
006E  ??  undocumented
006F  ??  undocumented
----------P0070007F--------------------------
0070-007F ----    CMOS RAM/RTC (Real Time Clock)
Note:    the real-time clock may be either a discrete MC146814, MC146818, or
      an emulation thereof built into the motherboard chipset

0070   W  CMOS RAM index register port (ISA, EISA)
         bit 7    = 1  NMI disabled
            = 0  NMI enabled
         bit 6-0     CMOS RAM index (64 bytes, sometimes 128 bytes)

        any write to 0070 should be followed by an action to 0071
        or the RTC wil be left in an unknown state.

0071  RW  CMOS RAM data port (ISA, EISA) (see #P055)

(Table P055)
Values for Real-Time Clock register number (see also CMOS.LST):
 00h-0Dh clock registers
 0Eh    diagnostics status byte
 0Fh    shutdown status byte
 10h    diskette drive type for A: and B:
 11h    reserved / IBM fixed disk / setup options
 12h    fixed disk drive type for drive 0 and drive 1
 13h    reserved / AMI Extended CMOS setup (AMI Hi-Flex BIOS)
 14h    equipment byte
 15h    LSB of system base memory in Kb
 16h    MSB of system base memory in Kb
 17h    LSB of total extended memory in Kb
 18h    MSB of total extended memory in Kb
 19h    drive C extension byte
 1Ah    drive D extension byte
 1Bh-2Dh reserved
 20h-27h commonly used for first user-configurable drive type
 2Eh    CMOS MSB checksum over 10-2D
 2Fh    CMOS LSB checksum over 10-2D
 30h    LSB of extended memory found above 1Mb at POST
 31h    MSB of extended memory found above 1Mb at POST
 32h    date century in BCD
 33h    information flags
 34h-3Fh    reserved
 35h-3Ch commonly used for second user-configurable drive type
 3Dh-3Eh word to 82335 MCR memory config register at [22] (Phoenix)
 42h-4Ch AMI 1990 Hyundai super-NB368S notebook
    ???
 54h-57h AMI 1990 Hyundai super-NB368S notebook
    ???
 5Ch-5Dh AMI 1990 Hyundai super-NB368S notebook
    ???
 60h-61h AMI 1990 Hyundai super-NB368S notebook
    ???
----------P0073------------------------------
0073      ----    Intel Pentium motherboard ("Neptune" chipset)

0073  RW  ???
        bit 7: ???
        bit 6: ???
        bit 3: ???
----------P00740076--------------------------
0074-0076 ----  secondary CMOS (Compaq), NVRAM (IBM) access
Note:    NVRAM may be 2K, 8K, or 16K
SeeAlso: CMOS.LST

0074   W  secondary CMOS RAM (IBM NVRAM) index, low byte
0075   W  secondary CMOS RAM (IBM NVRAM) index, high byte
0076  RW  secondary CMOS RAM (IBM NVRAM) data byte
----------P0078------------------------------
0078      ----    HP-Vectra  Hard Reset: NMI enable/disable

0078  ?W  NMI enable/disable
        bit 7 = 0  disable & clear hard reset from HP-HIL controller
              = 1  enable hard reset from HP-HIL controller chip
        bit 6-0       reserved
----------P0078007F--------------------------
0078-007F ----    PC radio by CoZet Info Systems
Range:  The I/O address range is dipswitch selectable from:
       038-03F and 0B0-0BF
       078-07F and 0F0-0FF
       138-13F and 1B0-1BF
       178-17F and 1F0-1FF
       238-23F and 2B0-2BF
       278-27F and 2F0-2FF
       338-33F and 3B0-3BF
       378-37F and 3F0-3FF
Note:    All of these addresses show a readout of FFh in initial state.
    Once started, all of the addresses show FBh, whatever might happen.
----------P007C007D--------------------------
007C-007D ----    HP-Vectra  PIC 3   (Programmable Interrupt Controller 8259)
Notes:    cascaded to first controller.
    used for keyboard and input device interface.
SeeAlso: PORT 0020h-0021h

007C  RW  HP-Vectra  PIC 3  see at 0020     PIC 1
007D  RW  HP-Vectra  PIC 3  see at 0021     PIC 1
----------P0080------------------------------
0080      ----    MANUFACTURING DIAGNOSTICS PORT
Note:    sometimes used for a POST hex display

0080   W  Manufacturing Diagnostics port
----------P0080008F--------------------------
0080-008F ----    DMA page registers   (74612)

0080  RW  extra page register (temporary storage)
0081  RW  DMA channel 2 address byte 2
0082  RW  DMA channel 3 address byte 2
0083  RW  DMA channel 1 address byte 2
0084  RW  extra page register
0085  RW  extra page register
0086  RW  extra page register
0087  RW  DMA channel 0 address byte 2
0088  RW  extra page register
0089  RW  DMA channel 6 address byte 2
0089  RW  DMA channel 7 address byte 2
0089  RW  DMA channel 5 address byte 2
008C  RW  extra page register
008D  RW  extra page register
008E  RW  extra page register
008F  RW  DMA refresh page register
----------P0080009F--------------------------
0080-009F ----    Intel386sx chipset 82231
Note:    includes the DMA controller functionality on PORT 0080h to PORT 008Fh
----------P0084------------------------------
0084      ----    Compaq POST Diagnostic
----------P0084------------------------------
0084      ----    EISA Synchronize Bus Cycle
----------P0090009F--------------------------
0090-009F ----    PS/2 POS (Programmable Option Select)

0090  ??  Central arbitration control port
0091  R      Card selection feedback
0092  RW  PS/2 system control port A  (port B is at 0061) (see #P056)
0094   W  system board enable/setup register (see #P057)
0095  --  reserved
0096   W  adapter enable / setup register
         bit 3 = 1  setup adapters
               = 0  enable registers
0097  --  reserved

Bitfields for PS/2 system control port A:
Bit(s)    Description    (Table P056)
 7-6    any bit set to 1 turns activity light on
 5    reserved
 4    watchdog timout occurred
 3    =0 RTC/CMOS security lock (on password area) unlocked
    =1 CMOS locked (done by POST)
 2    reserved
 1    A20 is active
 0    =0 system reset or write
    =1 pulse alternate reset pin (alternate CPU reset)
SeeAlso: #P057

Bitfields for PS/2 system board enable/setup register:
Bit(s)    Description    (Table P057)
 7    =1  enable functions
    =0  setup functions
 5    =1  enables VGA
    =0  setup VGA
SeeAlso: #P056
----------P00A000AF--------------------------
00A0-00AF ----    PIC 2    (Programmable Interrupt Controller 8259A)
SeeAlso: PORT 0020h-003Fh"PIC 1",INT 70"IRQ8",INT 77"IRQ15"

00A0  RW  NMI mask register (XT)
         bit 7 = 0 disabled
               = 1 enabled
00A0  RW  PIC 2     same as 0020 for PIC 1
00A1  RW  PIC 2     same as 0021 for PIC 1 except for OCW1 (see #P058)

Bitfields for PIC2 output control word OCW2:
Bit(s)    Description    (Table P058)
 7    disable IRQ15 (reserved)
 6    disable IRQ14 (fixed disk interrupt)
 5    disable IRQ13 (coprocessor exception interrupt)
 4    disable IRQ12 (mouse interrupt)
 3    disable IRQ11 (reserved)
 2    disable IRQ10 (reserved)
 1    disable IRQ9  (redirect cascade)
 0    disable IRQ8  (real-time clock interrupt)
SeeAlso: #P010
----------P00B000BF--------------------------
00B0-00BF ----    PC radio by CoZet Info Systems
Range:     The I/O address range is dipswitch selectable from:
       038-03F and 0B0-0BF
       078-07F and 0F0-0FF
       138-13F and 1B0-1BF
       178-17F and 1F0-1FF
       238-23F and 2B0-2BF
       278-27F and 2F0-2FF
       338-33F and 3B0-3BF
       378-37F and 3F0-3FF
Notes:    All of these addresses show a readout of FFh in initial state.
    Once started, all of the addresses show    FBh, whatever might happen.
----------P00C0------------------------------
00C0      ----    TI  SN746496 programmable tone/noise generator    PCjr
----------P00C000DF--------------------------
00C0-00DF ----    DMA 2    (second Direct Memory Access controller 8237)

00C0  RW  DMA channel 4 memory address bytes 1 and 0 (low) (ISA, EISA)
00C2  RW  DMA channel 4 transfer count bytes 1 and 0 (low) (ISA, EISA)
00C4  RW  DMA channel 5 memory address bytes 1 and 0 (low) (ISA, EISA)
00C6  RW  DMA channel 5 transfer count bytes 1 and 0 (low) (ISA, EISA)
00C8  RW  DMA channel 6 memory address bytes 1 and 0 (low) (ISA, EISA)
00CA  RW  DMA channel 6 transfer count bytes 1 and 0 (low) (ISA, EISA)
00CC  RW  DMA channel 7 memory address byte 0 (low), then 1 (ISA, EISA)
00CE  RW  DMA channel 7 transfer count byte 0 (low), then 1 (ISA, EISA)

00D0  R      DMA channel 4-7 status register (ISA, EISA) (see #P059)
00D0   W  DMA channel 4-7 command register (ISA, EISA) (see #P060)
00D2   W  DMA channel 4-7 write request register (ISA, EISA)
00D4   W  DMA channel 4-7 write single mask register (ISA, EISA) (see #P061)
00D6   W  DMA channel 4-7 mode register (ISA, EISA) (see #P062)
00D8   W  DMA channel 4-7 clear byte pointer flip-flop (ISA, EISA)

00DA  R      DMA channel 4-7 read temporary register (ISA, EISA)
00DA   W  DMA channel 4-7 master clear (ISA, EISA)
00DC   W  DMA channel 4-7 clear mask register (ISA, EISA)
00DE   W  DMA channel 4-7 write mask register (ISA, EISA)

Bitfields for DMA channel 4-7 status register:
Bit(s)    Description    (Table P059)
 7 = 1    channel 7 request
 6 = 1    channel 6 request
 5 = 1    channel 5 request
 4 = 1    channel 4 request
 3 = 1    terminal count on channel 7
 2 = 1    terminal count on channel 6
 1 = 1    terminal count on channel 5
 0 = 1    terminal count on channel 4
SeeAlso: #P001,#P060

Bitfields for DMA channel 4-7 command register:
Bit(s)    Description    (Table P060)
 7    DACK sense active high
 6    DREQ sense active high
 5    =1  extended write selection
    =0  late write selection
 4    rotating priority instead of fixed priority
 3    compressed timing
 2    =1  enable controller
    =0  enable memory-to-memory transfer
 1-0    channel number (00 = 4 to 11 = 7)
SeeAlso: #P002,#P059,#P061

Bitfields for DMA channel 4-7 write single mask register:
Bit(s)    Description    (Table P061)
 7-3    reserved
 2    =0  clear mask bit
    =1  set mask bit
 1-0    channel select
    00 channel 4 select
    01 channel 5 select
    10 channel 6 select
    11 channel 7 select
SeeAlso: #P004,#P060

Bitfields for DMA channel 4-7 mode register:
Bit(s)    Description    (Table P062)
 7-6    transfer mode
    00  demand mode
    01  single mode
    10  block mode
    11  cascade mode
 5    direction
    0  address increment select
    1  address decrement select
 4    autoinitialisation enabled
 3-2    operation
    00  verify operation
    01  write to memory
    10  read from memory
    11  reserved
 1-0    channel number
    00  channel 4 select
    01  channel 5 select
    10  channel 6 select
    11  channel 7 select
SeeAlso: #P005,#P061
----------P00E000E1--------------------------
00E0-00E1 ----    chipset from ACT

00E0  ?W  index for accesses to data port
00E1  R?  chip set data
----------P00E000E7--------------------------
00E0-00E7 ----    Microchannel

00E0  RW  split address register, memory encoding registers PS/2m80 only
00E1  RW  memory register
00E3  RW  error trace
00E4  RW  error trace
00E5  RW  error trace
00E7  RW  error trace
----------P00EC00ED--------------------------
00EC-00ED ----    Compaq LTE Elite
---------------------------------------------
00ED      ----    ???
Note:    on a number of machines, the BIOS appears to write a copy of any
      data sent to numerous other ports to this port as well

00EDw  ?W  ???
----------P00EF------------------------------
00EF      ----    Hyunday Super-NB386S (AMD386sx with Intel chipset)
Warning: any access to this port causes a cold reset on this machine!
----------P00F000F5--------------------------
00F0-00F5 ----    PCjr Disk Controller

00F0  ??  disk controller
00F2  ??  disk controller control port
00F4  ??  disk controller status register
00F5  ??  disk controller data port
----------P00F000FF--------------------------
00F0-00FF ----    coprocessor (8087..80387)

00F0   W  math coprocessor clear busy latch
00F1   W  math coprocessor reset
00F8  RW  opcode transfer
00FA  RW  opcode transfer
00FC  RW  opcode transfer
----------P00F9------------------------------
00F9      ----    Compaq LTE Elite
----------P00F9------------------------------
00FB      ----    Compaq LTE Elite
----------P00F900FF--------------------------
00F9-00FF ----    PC radio by CoZet Info Systems
Range:    The I/O address range is dipswitch selectable from:
       038-03F and 0B0-0BF
       078-07F and 0F0-0FF
       138-13F and 1B0-1BF
       178-17F and 1F0-1FF
       238-23F and 2B0-2BF
       278-27F and 2F0-2FF
       338-33F and 3B0-3BF
       378-37F and 3F0-3FF
Notes:    All of these addresses show a readout of FFh in initial state.
    Once started, all of the addresses show    FBh, whatever might happen.
----------P0100------------------------------
0100      ----    3COM 3C509 Ethernet card - ID port
Note: this port is present only on the 3C509, not on any other 3COM card
SeeAlso: 0110, 0120
----------P01000107--------------------------
0100-0107 ----    PS/2 POS (Programmable Option Select)
Note:    the default value for PORT 0102h is stored in CMOS 31h

0100  R      POS register 0    Low adapter ID byte
0101  R      POS register 1    High adapter ID byte
0102  RW  POS register 2    option select data byte 1 (see #P063)
0103  RW  POS register 3    option select data byte 2
0104  RW  POS register 4    option select data byte 3
0105  RW  POS register 5    option select data byte 4
         bit 7    channel active (-CHCK)
         bit 6    channel status
0106  RW  POS register 6    Low subaddress extension
0107  RW  POS register 7    High subaddress extension

Bitfields for PS/2 POS register 2, option select data byte 1:
Bit(s)    Description    (Table P063)
 7      0  = unidirectional LPT port
      1  = bidirectional LPT port
 6-5    PS/2 Model 50 and higher
     00b = default LPT port at 3BCh
     01b = ""           378h
     10b = ""           278h
     11b = reserved
 4    reserved
 0    card enable (CDEN)
 0    =1 VGA sleep bit, disconnects output drivers from VGA (usage for VGA
      without monitor)
---ET4000---
 7-4    reserved???
 3    video RAM wait enable
 2    ET4000: ROM BIOS wait enable
 1    ET4000: I/O wait enable
Note:    access to this port is only possible when PORT 0094h bit 7 is low.
---------------------------------------------
0100-010F ----    CompaQ Tape drive adapter. alternate address at 0300
---------------------------------------------
0108-010F ----    IBM PS/2 - 8 digit LED info panel

010F   W  leftmost character on display
010E   W  second character
 ...
0108   W  eighth character
---------------------------------------------
0110      ----    3COM 3C509 Ethernet card - ID port (alternate address)
Note:    this port is present only on the 3C509, not on any other 3COM card
SeeAlso: 0100, 0120
---------------------------------------------
0120      ----    3COM 3C509 Ethernet card - ID port (alternate address)
Note:    this port is present only on the 3C509, not on any other 3COM card
SeeAlso: 0100, 0110
---------------------------------------------
0130-013F ----    CompaQ SCSI adapter. alternate address at 0330
---------------------------------------------
0130-0133 ----    Adaptec 154xB/154xC SCSI adapter.
Range:    alternate address at 0134, 0230, 0234, 0330 and 0334
---------------------------------------------
0134-0137 ----    Adaptec 154xB/154xC SCSI adapter.
Range:    alternate address at 0130, 0230, 0234, 0330 and 0334
---------------------------------------------
0138-013F ----    PC radio by CoZet Info Systems
Range:    The I/O address range is dipswitch selectable from:
       038-03F and 0B0-0BF
       078-07F and 0F0-0FF
       138-13F and 1B0-1BF
       178-17F and 1F0-1FF
       238-23F and 2B0-2BF
       278-27F and 2F0-2FF
       338-33F and 3B0-3BF
       378-37F and 3F0-3FF
Notes:    All of these addresses show a readout of FFh in initial state.
    Once started, all of the addresses show    FBh, whatever might happen.
---------------------------------------------
0140-014F ----    SCSI (alternate Small Computer System Interface) adapter
Note:    first adapter is at 0340-034F
---------------------------------------------
0140-0157 ----    RTC (alternate Real Time Clock for XT)     (1st at 0340-0357)
---------------------------------------------
015C-015D ----    Dell Enhanced Parallel Port
SeeAlso: 002E, 026E, 0398

015C   W  index for data port
015D  RW  EPP command data
---------------------------------------------
015F      ----    ARTEC Handyscanner A400Z.  alternate address at 35F.
---------------------------------------------
0170-0177 ----    HDC 2    (2nd Fixed Disk Controller) (ISA, EISA)
Range:    01F0-01F7 for primary controller, 0170-0177 for secondary controller
SeeAlso: PORT 01F0h-01F7h
---------------------------------------------
0178-0179 ----    Power Management

0178   W  index selection for data port
0179  RW  power management data
---------------------------------------------
0178-017F ----    PC radio by CoZet Info Systems
Range:    The I/O address range is dipswitch selectable from:
       038-03F and 0B0-0BF
       078-07F and 0F0-0FF
       138-13F and 1B0-1BF
       178-17F and 1F0-1FF
       238-23F and 2B0-2BF
       278-27F and 2F0-2FF
       338-33F and 3B0-3BF
       378-37F and 3F0-3FF
Notes:    All of these addresses show a readout of FFh in initial state.
    Once started, all of the addresses show    FBh, whatever might happen.
---------------------------------------------
01CE-01CF ----    ATI Mach32 video chipset - ???

01CE   W  index register
01CF  RW  data register
---------------------------------------------
01E8-01EF ----    Headland HL21 & Acer M5105 chipsets - SYSTEM CONTROL

01ED  RW  select internal register. Data to/from 01EF
01EE  R      ???
01EF  RW  register value
    05h  = 1000xxxx for low CPU clock speed (4MHz on Morse/Mitac)
         = 0xxxxxxx for high CPU clock speed (16MHz on Morse/Mitac)
    10h memory size
       bits 2-0 = size
           (undefined,512K,640K,1024K,2560K,2048K,4096K,undef.)
    14h ???
       bit 2: 384K RAM of first 1024K relocated to top of memory
---------------------------------------------
01F0-01F7 ----    HDC 1    (1st Fixed Disk Controller) (ISA, EISA)
Range:    01F0-01F7 for primary controller, 0170-0177 for secondary controller
SeeAlso: PORT 0170h-0177h

01F0  RW  data register
01F1  R      error register (see #P064)
01F1   W  WPC/4     (Write Precompensation Cylinder divided by 4)
01F2  RW  sector count
01F3  RW  sector number (CHS mode)
      logical block address, bits 0-7 (LBA mode)
01F4  RW  cylinder low (CHS mode)
      logical block address, bits 15-8 (LBA mode)
01F5  RW  cylinder high (CHS mode)
      logical block address, bits 23-16 (LBA mode)
01F6  RW  drive/head (see #P065)
01F7  R      status register (see #P066)
01F7   W  command register (see #P067)

Bitfields for Hard Disk Controller error register:
Bit(s)    Description    (Table P064)
---diagnostic mode errors---
 7    which drive failed (0 = master, 1 = slave)
 6-3    reserved
 2-0    error code
    001    no error detected
    010    formatter device error
    011    sector buffer error
    100    ECC circuitry error
    101    controlling microprocessor error
---operation mode---
 7    bad block detected
 6    uncorrectable ECC error
 5    reserved
 4    ID found
 3    reserved
 2    command aborted prematurely
 1    track 000 not found
 0    DAM not found (always 0 for CP-3022)
SeeAlso: #P065,#P066

Bitfields for hard disk controller drive/head specifier:
Bit(s)    Description    (Table P065)
 7    =1
 6    LBA mode enabled, rather than default CHS mode
 5    =1
 4    drive select (0 = drive 0, 1 = drive 1)
 3-0    head select bits (CHS mode)
    logical block address, bits 27-24 (LBA mode)
SeeAlso: #P064,#P066

Bitfields for hard disk controller status register:
Bit(s)    Description    (Table P066)
 7    controller is executing a command
 6    drive is ready
 5    write fault
 4    seek complete
 3    sector buffer requires servicing
 2    disk data read successfully corrected
 1    index - set to 1 each disk revolution
 0    previous command ended in an error
SeeAlso: #P064,#P067

(Table P067)
Values for hard disk controller command codes:
Command                     class: optional:
 1xh     recalibrate               1      no
 20h     read sectors with retry       1      no
 21h     read sectors without retry       1      no
 22h     read long with retry           1      no
 23h     read long without retry       1      no
 30h     write sectors with retry       2      no
 31h     write sectors without retry       2      no
 32h     write long with retry           2      no
 33h     write long without retry       2      no
 3Ch     write verify        (IDE)       3      yes
 40h     read verify sectors with retry       1      no
 41h     read verify sectors without retry 1      no
 50h     format track               2      no
 7xh     seek                   1      no
 8xh     vendor unique 3    (IDE)
 90h     execute drive diagnostics       1      no
 91h     initialize drive parameters       1      no
 94h E0h standby immediate    (IDE)       1      yes
 95h E1h idle immediate        (IDE)       1      yes
 96h E2h standby        (IDE)       1      yes
 97h E3h idle            (IDE)       1      yes
 98h E5h check power mode    (IDE)       1      yes
 99h E6h set sleep mode        (IDE)       1      yes
 9Ah     vendor unique 1    (IDE)
 C0h-C3h vendor unique 2    (IDE)
 C4h     read multiplec        (IDE)       1      yes
 C5h     write multiple        (IDE)       3      yes
 C6h     set multiple mode    (IDE)       1      yes
 C8h     read DMA with retry    (IDE)       1      yes
 C9h     read DMA without retry (IDE)       1      yes
 CAh     write DMA with retry    (IDE)       3      yes
 CBh     write DMA with retry    (IDE)       3      yes
 E4h     read buffer        (IDE)       1      yes
 E8h     write buffer        (IDE)       2      yes
 E9h     write same        (IDE)       3      yes
 ECh     identify drive        (IDE)       1      yes
 EFh     set features        (IDE)       1      yes
 F0h-F4h EATA standard        (IDE)
 F5h-FFh vendor unique 4    (IDE)
SeeAlso: #P064,#P066
---------------------------------------------
01F8      ----    ???

01F8  RW  ???
        bit 0: A20 gate control (set = A20 enabled, clear = disabled)
---------------------------------------------
01F9-01FF ----    PC radio by CoZet Info Systems
Range:    The I/O address range is dipswitch selectable from:
       038-03F and 0B0-0BF
       078-07F and 0F0-0FF
       138-13F and 1B0-1BF
       178-17F and 1F0-1FF
       238-23F and 2B0-2BF
       278-27F and 2F0-2FF
       338-33F and 3B0-3BF
       378-37F and 3F0-3FF
Notes:    All of these addresses show a readout of FFh in initial state.
    Once started, all of the addresses show    FBh, whatever might happen.
---------------------------------------------
0200-020F ----    Game port reserved I/O address space
0200-0207 ----    Game port, eight identical addresses on some boards

0201  R      read joystick position and status (see #P068)
0201   W  fire joystick's four one-shots
0201  RW  gameport on mc-soundmachine, mc 03-04/1992: Adlib-compatible,
        Covox 'voice master' & 'speech thing' compatible soundcard.
        (enabled if bit1=1 in PORT 038Fh. Because it is disabled on
        power-on, it cannot be found by BIOS) (see PORT 0388h-038Fh)

Bitfields for joystick position and status:
Bit(s)    Description    (Table P068)
 7    status B joystick button 2 / D paddle button
 6    status B joystick button 1 / C paddle button
 5    status A joystick button 2 / B paddle button
 4    status A joystick button 1 / A paddle button
 3    B joystick Y coordinate       / D paddle coordinate
 2    B joystick X coordinate       / C paddle coordinate
 1    A joystick Y coordinate       / B paddle coordinate
 0    A joystick X coordinate       / A paddle coordinate
---------------------------------------------
0200-02FF ----    Sunshine uPW48, programmer for EPROM version CPU's 8748/8749
Range:    4 bit DIP switch installable in the range 20x-2Fx

0200-0203    adresses of the 8255 on the uPW48
0208-020B    adresses of ??? on the uPW48 (all showing zeros)
---------------------------------------------
0208-0209 ----    Intel 82C212B "Neat" chipset - EMS emulation control
Range:    may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, 02E8
---------------------------------------------
020C-020F ----    AIMS LAB PC Radio
Range:    configurable to 020C or 030C
---------------------------------------------
0210-0217 ----    Expansion unit (XT)

0210   W  latch expansion bus data
0210  R      verify expansion bus data
0211   W  clear wait, test latch
0211  R      High byte data address
0212  R      Low byte data address
0213   W  0=enable,  1=disable expansion unit
0214   W  latch data  (receiver card port)
0214  R      read data   (receiver card port)
0215  R      High byte of address, then Low byte    (receiver card port)
---------------------------------------------
0218-0219 ----    Intel 82C212B "Neat" chipset - EMS emulation control
Range:    base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8
---------------------------------------------
0220-0223 ---- Sound Blaster / Adlib port (Stereo)
SeeAlso: 0388-0389

0220  R      Left speaker -- Status port
0220   W  Left speaker -- Address port
0221   W  Left speaker -- Data port
0222  R      Right speaker -- Status port
0222   W  Right speaker -- Address port
0223   W  Right speaker -- Data port
---------------------------------------------
0220-0227 ----    Soundblaster PRO and SSB 16 ASP
---------------------------------------------
0220-022F ----    Soundblaster PRO 2.0
---------------------------------------------
0220-022F ----    Soundblaster PRO 4.0
Note:    the FM music is accessible on 0388/0389 for compatibility.

0220  R      left FM status port
0220   W  left FM music register address port (index)
0221  RW  left FM music data port
0222  R      right FM status port
0222   W  right FM music register address port (index)
0223  RW  right FM music data port
0224   W  mixer register address port (index)
0225  RW  mixer data port
0226   W  DSP reset
0228  R      FM music status port
0228   W  FM music register address port (index)
0229   W  FM music data port
022A  R      DSP read data (voice I/O and Midi)
022C   W  DSP write data / write command
022C  R      DSP write buffer status (bit 7)
022E  R      DSP data available status (bit 7)
---------------------------------------------
022F      ----    mc-soundmachine, mc 03-04/1992 - SPEECH I/O
Note:    An Adlib-compatible Covox 'voice master' & 'speech thing' compatible
      soundcard
SeeAlso: PORT 0378h"Covox",PORT 0388h-038Fh"soundmachine"

022F  RW  Covox compatible speech I/O  (via internal A/D converter,
        each read access starts a new conversion cycle)
        register enabled if bit7=1 in PORT 038Fh
---------------------------------------------
0230-0233 ----    Adaptec 154xB/154xC SCSI adapter.
        alternate address at 0130, 0134, 0230, 0330 and 0334
---------------------------------------------
0234-0237 ----    Adaptec 154xB/154xC SCSI adapter.
        alternate address at 0130, 0134, 0230, 0330 and 0334
---------------------------------------------
0238-023F ----    COM port addresses on UniRAM card by German magazine c't
        selectable from 238, 2E8, 2F8, 338, 3E0, 3E8, 3F8
---------------------------------------------
0238-023x ----    Bus Mouse Port (secondary address)
Note:    secondary address for bus mice from MS and Logitech, and the ATI
      video adapter mouse
---------------------------------------------
023C-023x ----    Bus Mouse Port (primary address)
Note:    primary address for bus mice from MS and Logitech, the ATI video
      adapter mouse, and the Commodore PC30III bus mouse
---------------------------------------------
0240-024F ----    Gravis Ultra Sound by Advanced Gravis
Range:    The I/O address range is dipswitch selectable from:
       0200-020F and 0300-030F
       0210-021F and 0310-031F
       0220-022F and 0320-032F
       0230-023F and 0330-033F
       0240-024F and 0340-034F
       0250-025F and 0350-035F
       0260-026F and 0360-036F
       0270-027F and 0370-037F
SeeAlso: 0340-034F, 0746

0240   W  Mix Control register (see #P069)
0241  R      Read Data
0241   W  Trigger Timer
0246  R      IRQ Status Register (see #P070)
0248  RW  Timer Control Reg
      Same as ADLIB Board (see PORT 0200h)
0249   W  Timer Data (see #P071)
024B   W  IRQ Control Register (0240 bit 6 = 1) (see #P072)
024B   W  DMA Control Register (0240 bit 6 = 0) (see #P073)
024F  RW  Register Controls (rev 3.4+)

Bitfields for Gravis Ultra Sound mix control register:
Bit(s)    Description    (Table P069)
 6       Control Register Select (see 024B)
 5       Enable MIDI Loopback
 4       Combine GF1 IRQ with MIDI IRQ
 3       Enable Latches
 2       Enable MIC IN
 1       Disable LINE OUT
 0       Disable LINE IN
SeeAlso: #P070

Bitfields for Gravis Ultra Sound IRQ status register:
Bit(s)    Description    (Table P070)
 7       DMA TC IRQ
 6       Volume Ramp IRQ
 5       WaveTable IRQ
 3       Timer 2 IRQ
 2       Timer 1 IRQ
 1       MIDI Receive IRQ
 0       MIDI Transmit IRQ
SeeAlso: #P069,#P072,#P073

Bitfields for Gravis Ultra Sound timer data:
Bit(s)    Description    (Table P071)
 7       Reset Timr IRQ
 6       Mask Timer 1
 5       Mask Timer 2
 1       Timer 2 Start
 0       Timer 1 Start
SeeAlso: #P070,#P072

Bitfields for Gravis Ultra Sound IRQ control register:
Bit(s)    Description    (Table P072)
 6    Combine Both IRQ
 5-3    MIDI IRQ Selector
    000  No IRQ
    001  IRQ 2
    010  IRQ 5
    011  IRQ 3
    100  IRQ 7
    101  IRQ 11
    110  IRQ 12
    111  IRQ 15
 2-0    GF1 IRQ Selector
    000  No IRQ
    001  IRQ 2
    010  IRQ 5
    011  IRQ 3
    100  IRQ 7
    101  IRQ 11
    110  IRQ 12
    111  IRQ 15
SeeAlso: #P070,#P073

Bitfields for Gravis Ultra Sound DMA Control Register:
Bit(s)    Description    (Table P073)
 6    Combine Both DMA
 5-3    DMA Select Register 2
    000  No DMA
    001  DMA 1
    010  DMA 3
    011  DMA 5
    100  DMA 6
    101  DMA 7
 2-0    DMA Select Register 1
    000  No DMA
    001  DMA 1
    010  DMA 3
    011  DMA 5
    100  DMA 6
    101  DMA 7
SeeAlso: #P070,#P072,#P075
---------------------------------------------
0240-0257 ----    RTC (alternate Real Time Clock for XT)     (1st at 0340-0357)
        (used by TIMER.COM v1.2 which is the 'standard' timer program)
---------------------------------------------
0258-0259 ----    Intel 82C212B "Neat" chipset - EMS emulation control
Range:    base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8
---------------------------------------------
0258-0259 ---- AT RAMBANK Memory Expansion Board - EXT. MEMORY AND EMS-SUPPORT
Range:    base address may be set to 0218h, 0228h, 0238h, 0258h, 0268h, 0298h,
      or 02A8h
---------------------------------------------
0258-025F ----    Intel Above Board
---------------------------------------------
0260-0268  ----     LPT port address on the UniRAM card by German magazine c't
        selectable from 260, 2E0, 2E8, 2F0, 3E0, 3E8.
---------------------------------------------
0268-0269 ----    Intel 82C212B "Neat" chipset - EMS emulation control
Range:    base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8
---------------------------------------------
026E-026F ----    Dell Enhanced Parallel Port
SeeAlso: 002E, 015C, 0398

026E   W  index for data port
026F  RW  EPP command data
---------------------------------------------
0278      ----    Covox 'Speech Thing' COMPATIBLES
SeeAlso: PORT 022Fh"Covox",PORT 0388h-038Fh"soundmachine"

0278   W  speech data output via printer data port
        (with mc-soundmachine, enabled if bit5=1 in 38F)
---------------------------------------------
0278-027E ----    parallel printer port, same as 0378 and 03BC

0278   W  data port
0279  RW  status port
027A  RW  control port
---------------------------------------------
0280       ----    LCD display on Wyse 2108 PC
---------------------------------------------
0280-0288  ----    non-standard COM port addresses (V20-XT by German magazine c't)
        selectable from 0280, 0288, 0290, 0298, 6A0, 6A8
---------------------------------------------
0288-028F  ----    non-standard COM port addresses (V20-XT by German magazine c't)
0280-0288    selectable from 0280, 0288, 0290, 0298, 06A0, 06A8
0290-0298
0298-029F
---------------------------------------------
02A0-02A7 ----    Sunshine EW-901BN, EW-904BN
        EPROM writer card (release 1986) for EPROMs up to 27512
02A0-02A3    adresses of the 8255 on the EW-90xBN
---------------------------------------------
02A2-02A3 ----    MSM58321RS clock
---------------------------------------------
02A8-02A9 ----    Intel 82C212B "Neat" chipset - EMS emulation control
Range:    base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8
---------------------------------------------
02B0-02BF ----    Trantor SCSI adapter
---------------------------------------------
02B0-02DF ----    alternate EGA,    primary EGA at 03C0
---------------------------------------------
02B8-02B9 ----    Intel 82C212B "Neat" chipset - EMS emulation control
Range: base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8
---------------------------------------------
02C0-02Cx ----    AST-clock
---------------------------------------------
02C0-02DF ----    XT-Real Time Clock 2 (default jumpered address)
---------------------------------------------
02E0-02E8 ----    LPT port address on the UniRAM card by German magazine c't
Range:    base address selectable from 0260, 02E0, 02E8, 02F0, 03E0, and 03E8.
---------------------------------------------
02E0-02EF ----    GPIB (General Purpose Interface Bus, IEEE 488 interface)
        (GAB 0 on XT)
02E1  ??  GPIB (adapter 0)
02E2
02E3
---------------------------------------------
02E0-02EF ----    data aquisition     (AT)

02E2  ??  data aquisition (adapter 0)
02E3  ??  data aquisition (adapter 0)
---------------------------------------------
02E8      ----    S3 86C928 video controller (ELSA Winner 1000)
---------------------------------------------
02E8-02E9 ----    Intel 82C212B "Neat" chipset - EMS emulation control
Range:    base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8
---------------------------------------------
02E8-02EF ----    serial port, same as 02F8, 03E8 and 03F8 (COM4)
---------------------------------------------
02E8-02EF ----    8514/A and compatible video cards (e.g. ATI Graphics Ultra)

02E8  R      display status
02E8   W  horizontal total
02EA  RW  Lookup: DAC mask
02EB   W  Lookup: DAC read index
02EC   W  Lookup: DAC write index
02ED  RW  Lookup: DAC data
---------------------------------------------
02EA      ----    S3 86C928 video controller (ELSA Winner 1000)
---------------------------------------------
02F0-2F8  ----    LPT port address on the UniRAM card by German magazine c't
        selectable from 260, 2E0, 2E8, 2F0, 3E0, 3E8.
---------------------------------------------
02F8-02FF ----    serial port, same as 02E8, 03E8 and 03F8 (COM2)

02F8   W  transmitter holding register
02F8  R      receiver buffer register
02F8  RW  divisor latch, low byte    when DLAB=1
02F9  RW  divisor latch, high byte    when DLAB=1
02F9  RW  interrupt enable register when DLAB=0
02FA  R      interrupt identification register
02FB  RW  line control register
02FC  RW  modem control register
02FD  R      line status register
02FF  RW  scratch register
---------------------------------------------
0300      ----    Award POST Diagnostic
---------------------------------------------
0300-0301 ----    Soundblaster 16 ASP MPU-Midi
---------------------------------------------
0300-???? ----    HP IEC/HP-IB adapter (e.g. for use with tape streamer HP9142)
---------------------------------------------
0300-031F ----    3com Ethernet adapters (default address)
---------------------------------------------
0300-???? ----    NE2000 compatible Ethernet adapters
Range:    may be placed at 0300h, 0320h, 0340h, or 0360h
---------------------------------------------
0300-0303 ----    Panasonic 52x CD-ROM SCSI Miniport
        Alternate addresses at 0320, 0340, 0360, and 0380
---------------------------------------------
0300-030F ----    Philips CD-ROM player CM50
---------------------------------------------
0300-030F ----    CompaQ Tape drive adapter. alternate address at 0100
---------------------------------------------
0300-031F ----    prototype cards
        Periscope hardware debugger
---------------------------------------------
030C-030F ----    AIMS LAB PC Radio

    configurable to 020C or 030C
---------------------------------------------
0310-031F ----    Philips CD-ROM player CM50
---------------------------------------------
0320-0323 ----    XT HDC 1   (Hard Disk Controller)
SeeAlso: PORT 01F0h-01F7h

0320  RW  data register
0321   W  reset controller
0321  R      read controller hardware status (see #P074)
0322  R      read DIPswitch setting on XT controller card
0322   W  generate controller-select pulse
0323   W  write pattern to DMA and INT mask register

Bitfields for XT hard disk controller hardware status:
Bit(s)    Description    (Table P074)
 7-6    always 0
 5    logical unit number
 4-2    always 0
 1    error occurred
 0    always 0
---------------------------------------------
0324-0327 ----    XT HDC 2   (Hard Disk Controller)
---------------------------------------------
0328-032B ----    XT HDC 3   (Hard Disk Controller)
---------------------------------------------
032C-032F ----    XT HDC 4   (Hard Disk Controller)
---------------------------------------------
0330-0331 ----    MIDI interface
---------------------------------------------
0330-0333 ----    Adaptec 154xB/154xC SCSI adapter. default address.
Range:    alternate address at 0130, 0134, 0230, 0234 and 0334
---------------------------------------------
0330-033F ----    CompaQ SCSI adapter. alternate address at 0130
---------------------------------------------
0330-033F ----    Philips CD-ROM player CM50
---------------------------------------------
0334-0337 ----    Adaptec 154xB/154xC SCSI adapter.
Range:    alternate address at 0130, 0134, 0230, 0234 and 0330
---------------------------------------------
0338      ----    AdLib soundblaster card
---------------------------------------------
0338-033F ----    COM port addresses on UniRAM card by German magazine c't
Range:    selectable from 0238, 02E8, 02F8, 0338, 03E0, 03E8, 03F8
---------------------------------------------
0340-034F ----    Philips CD-ROM player CM50
---------------------------------------------
0340-034F ----    SCSI (1st Small Computer System Interface) adapter
Note:    alternate address at 0140-014F
---------------------------------------------
0340-034F ----    Gravis Ultra Sound by Advanced Gravis
Range: The I/O address range is dipswitch selectable from:
       0200-020F and 0300-030F
       0210-021F and 0310-031F
       0220-022F and 0320-032F
       0230-023F and 0330-033F
       0240-024F and 0340-034F
       0250-025F and 0350-035F
       0260-026F and 0360-036F
       0270-027F and 0370-037F
SeeAlso: 0240-024F, 0746

0340   W  MIDI Control (see #P075)
0340  R      MIDI Status (see #P076)
0341   W  MIDI Transmit Data
0341  R      MIDI Receive Data
0342  RW  GF1 Page Register / Voice Select
0343  RW  GF1/Global Register Select (see #P077)
0344  RW  GF1/Global Data Low Byte (16 bits)
0345  RW  GF1/Global Data High Byte (8 bits)
0346   W  Mixer Data Port
0347  RW  GF1 DRAM
         Direct Read Write at Loction pointed with regs 43 and 44

Bitfields for Gravis Ultra Sound MIDI control register:
Bit(s)    Description    (Table P075)
 7       Receive IRQ (1 = enabled)
 5-6   Xmit IRQ
 0-1   Master Reset (1 = enabled)
SeeAlso: #P070,#P072,#P076

Bitfields for Gravis Ultra Sound MIDI status register:
Bit(s)    Description    (Table P076)
 7    Interrupt pending
 5    Overrun Error
 4    Framing Error
 1    Transmit Register Empty
 0    Receive Register Empty
SeeAlso: #P075,#P077

(Table P077)
Values for Gravis Ultra Sound GF1/Global Registers:
---Voice specific registers---
 00h  w        Voice Control (see #P078)
 01h  w        Frequency Control
         bit 15-10     Integer Portion
         bit 9-1     Fractional Portion
 02h  w        Start Address HIGH
         bit 12-0     Address Lines 19-7
 03h  w        Start Address LOW
         bit 15-9     Address Lines 6-0
         bit 8-5     Fractional Part of Start Address
 04h  w        End Address HIGH
         bit 12-0     Address Lines 19-7
 05h  w        End Address LOW
         bit 15-9     Address Lines 6-0
         bit 8-5     Fractional Part of End Address
 06h  w        Volume Ramp Rate
         bit 5-0     Amount added
         bit 7-6     Rate
 07h  w        Volume Ramp Start
         bit 7-4     Exponent
         bit 3-0     Mantissa
 08h  w        Volume Ramp End
         bit 7-4     Exponent
         bit 3-0     Mantissa
 09h  w        Current Volume
         bit 15-12     Exponent
         bit 11-4     Mantissa
 0Ah  w        Current Address HIGH
         bit 12-0     Address Lines 19-7
 0Bh  w        Current Address LOW
         bit 15-9     Address Lines 6-0
         bit 8-0     Fractional Position
 0Ch  w        Pan Position
         bit 3-0     Pan Postion
 0Dh  w        Volume Control (see #P079)
 0Eh  w        Active Voices
         bit 5-0     #Voices -1  (allowed 13 - 31)
 0Fh  w        IRQ Source Register (see #P080)
---NOT voice specific---
 41h  r/w   DRAM DMA Control (see #P081)
 42h  w        DMA Start Address
         bits 15-0     DMA Address Lines 19-4
 43h  w        DRAM I/O Address LOW
 44h  w        DRAM I/O Address HIGH
         bits 0-3     Upper 4 Address Lines
 45h  r/w   Timer Control
         bit 3     Enable Timer 2
         bit 2     Enable Timer 1
 46h  w        Timer 1 Count (granularity of 80 micro sec)
 47h  w        Timer 2 Count (granulatity of 320 micro sec)
 48h  w        Sampling Frequency
         rate = 9878400 / (16 * (FREQ + 2))
 49h  r/w   Sampling Control (see #P082)
 4Bh  w        Joystick Trim DAC
 4Ch  r/w   RESET
         bit 2     GF1 Master IRQ Enable
         bit 1     DAC Enable
         bit 0     Master Reset
---Voice specific registers---
 80h  r        Voice Control (see 00h)
 81h  r        Frequency Control (see 01h)
 82h  r        Start Address HIGH (see 02h)
 83h  r        Start Address LOW (see 03h)
 84h  r        End Address HIGH (see 04h)
 85h  r        End Address LOW (see 05h)
 86h  r        Volume Ramp Rate (see 06h)
 87h  r        Volume Ramp Start (see 07h)
 88h  r        Volume Ramp End (see 08h)
 89h  r        Current Volume (see 09h)
 8Ah  r        Current Address HIGH (see 0Ah)
 8Bh  r        Current Address LOW (see 0Bh)
 8Ch  r        Pan Position (see 0Ch)
 8Dh  r        Volume Control (see 0Dh)
 8Eh  r        Active Voices (see 0Eh)
 8Fh  r        IRQ Status (see 0Fh)
SeeAlso: #P076

Bitfields for Gravis Ultra Sound voice control global register:
Bit(s)    Description    (Table P078)
 7     IRQ pending
 6     Direction
 5     Enable WAVE IRQ
 4     Enable bi-directional Looping
 3     Enable Looping
 2     Size data (8/16 bits)
 1     Stop Voice
 0     Voice Stopped
SeeAlso: #P077,#P079

Bitfields for Gravis Ultra Sound volume control global register:
Bit(s)    Description    (Table P079)
 7     IRQ Pending
 6     Direction
 5     Enable Volume Ramp IRQ
 4     Enable bi-directional Looping
 3     Enable Looping
 2     Rollover Condition
 1     Stop Ramp
 0     Ramp Stopped
SeeAlso: #P077,#P078

Bitfields for Gravis Ultra Sound IRQ source register:
Bit(s)    Description    (Table P080)
 7     WaveTable IRQ pending
 6     Volume Ramp IRQ pending
 4-0     Voice Number
SeeAlso: #P077,#P078,#P081

Bitfields for Gravis Ultra Sound DRAM DMA control register:
Bit(s)    Description    (Table P081)
 7     Invert MSB
 6     Data Size (8/16 bits)
 5     DMA Pending
 3-4     DMA Rate Divider
 2     DMA Channel Width (8/16 bits)
 1     DMA Direction (1 = read)
 0     DMA Enable
SeeAlso: #P077,#P080

Bitfields for Gravis Ultra Sound sampling control register:
Bit(s)    Description    (Table P082)
 7     Invert MSB
 6     DMA IRQ pending
 5     DMA IRQ enable
 2     DMA width (8/16 bits)
 1     Mode (mone/stereo)
 0     Start Sampling
SeeAlso: #P077
---------------------------------------------
0340-0357 ----    RTC (1st Real Time Clock for XT)
        (used by TIMER.COM v1.2 which is the 'standard' timer program)
Range:    alternate at 0240-0257
SeeAlso:  PORT 0240h-0257h

0340  RW  0.001 seconds        0-99
0341  RW  0.1 and 0.01 seconds    0-99
0342  RW  seconds        0-59
0343  RW  minutes        0-59
0343  RW  hours            0-23
0345  RW  day of week        1-7
0346  RW  day of month        1-31
0347  RW  month            1-12
0348  RW  RAM (upper nybble only)
0349  RW  year            0-99
034A  RW  RAM last month storage
034B  RW  RAM year storage (-80)
034C  RW  RAM reserved
034D  RW  RAM not used
034E  RW  RAM not used
034F  RW  RAM not used
0350  R      interrupt status register
0351   W  interrupt control register
0352   W  counter reset
0353   W  RAM reset
0354  R      status bit
0355   W  GO command
0356  ??  standby interrupt
0357  ??  test mode
---------------------------------------------
0348-0357 ----    DCA 3278
---------------------------------------------
034C-034F ----    Gravis UltraMax by Advanced Gravis
Range:    The I/O address range is dipswitch selectable from:
       0200-020F and 0300-030F
       0210-021F and 0310-031F
       0220-022F and 0320-032F
       0230-023F and 0330-033F
       0240-024F and 0340-034F
       0250-025F and 0350-035F
       0260-026F and 0360-036F
       0270-027F and 0370-037F
---------------------------------------------
035A-035B ----    Adaptec AH1520 jumper settings

035A  R      I/O channel setup (see #P083)
035B  R      transfer mode setup (see #P084)

Bitfields for Adaptec AH1520 channel setup jumper settings:
Bit(s)    Description    (Table P083)
 7    SCSI parity disabled
 6-5    DMA channel (00 = channel 0, 01 = 5, 10 = 6, 11 = 7)
 4-3    IRQ number (00 = IRQ9, 01 = IRQ10, 10 = IRQ11, 11 = IRQ12)
 2-0    SCSI ID
SeeAlso: #P084

Bitfields for Adaptec AH1520 transfer mode setup jumper settings:
Bit(s)    Description    (Table P084)
 7    DMA transfer mode (clear for PIO)
 6    boot enabled
 5-4    boot type
    00 ???
    01 boot from floppy
    10 print configured options
    11 boot from hard disk
 3    enable sync negotiation
 2    enable target disconnection
 1-0    unused???
SeeAlso: #P083
---------------------------------------------
035F      ----    ARTEC Handyscanner A400Z.  alternate address at 15F.
---------------------------------------------
0360-036F ----    PC network (AT)
0360-0367 ----    PC network (XT only)
---------------------------------------------
0360-036F ----    National Semiconductor DP8390(1)C/NS3249C network chipset
Note:    cards based on this IEEE 802.3 networking chipset can use any range
      of 16 consecutive addresses, and provide a total of four pages of
      sixteen registers (see #P085,#P086,#P087,#P098

(Table P085)
Values for NS DP8390C/NS3249C network chipset Page 0 registers:
Number    Read Register                Write Register
 00h    Command reg. (see #P089)    CR    Command reg.        CR
 01h    current local DMA address 0    CLDA0    page start reg.        PSTART
 02h    current local DMA address 1    CLDA1    page stop reg.        PSTOP
 03h    boundary pointer        BNRY    boundary pointer    BNRY
 04h    transmit status reg.        TSR    Tx page start address    TPSR
 05h    number of collisions reg.    NCR    Tx byte count reg.0    TBCR0
 06h    FIFO                    Tx byte count reg.1    TBCR1
 07h    interrupt status reg.        ISR    interrupt status reg.    ISR
 08h    current remote DMA address 0    CRDA0    remote start addr.reg.0 RSAR0
 09h    current remote DMA address 1    CRDA1    remote start addr.reg.1 RSAR1
 0Ah    reserved                remote byte count reg.0 RBCR0
 0Bh    reserved                remote byte count reg.1 RBCR1
 0Ch    receive status reg.        RSR    Rx configuration reg.    RCR
 0Dh    tally counter 0 (frame errors)    CNTR0    Tx configuration reg.    TCR
 0Eh    tally counter 1 (CRC errors)    CNTR1    data configuration reg. DCR
 0Fh    tally counter 2 (missed pkt)    CNTR2    interrupt mask reg.    IMR
SeeAlso: #P086,#P087,#P088

(Table P086)
Values for NS DP8390C/NS3249C network chipset Page 1 registers:
Number    Read/Write
 00h    Command            CR (see #P089)
 01h    physical address reg.0    PAR0
 02h    physical address reg.1    PAR1
 03h    physical address reg.2    PAR2
 04h    physical address reg.3    PAR3
 05h    physical address reg.4    PAR4
 06h    physical address reg.5    PAR5
 07h    current page reg.    CURR
 08h    multicast address reg.0 MAR0
 09h    multicast address reg.1 MAR1
 0Ah    multicast address reg.2 MAR2
 0Bh    multicast address reg.3 MAR3
 0Ch    multicast address reg.4 MAR4
 0Dh    multicast address reg.5 MAR5
 0Eh    multicast address reg.6 MAR6
 0Fh    multicast address reg.7 MAR7
SeeAlso: #P085,#P087,#P088

(Table P087)
Values for NS DP8390C/NS3249C network chipset Page 2 registers:
Number    Read Register                Write Register
 00h    Command                CR    Command             CR
 01h    page start reg.            PSTART    current local DMA addr.0 CLDA0
 02h    page stop reg.            BPSTOP    current local DMA addr.1 CLDA1
 03h    remote next packet pointer        remote next packet pointer
 04h    Tx page start address        TPSR    reserved
 05h    local next packet pointer        local next packet pointer
 06h    address counter (upper)            address counter (upper)
 07h    address counter (lower)            address counter (lower)
 08h    reserved                reserved
 09h    reserved                reserved
 0Ah    reserved                reserved
 0Bh    reserved                reserved
 0Ch    Rx configuration reg.        RCR    reserved
 0Dh    Tx configuration reg.        TCR    reserved
 0Eh    data configuration reg.        DCR    reserved
 0Fh    interrupt mask reg.        IMR    reserved
Note:    this is a diagnostics page, and should never be modfied under normal
      operation.
SeeAlso: #P085,#P086,#P088

(Table P088)
Values for NS DP8390C/NS3249C network chipset Page 3 registers:
Number    Read Register                Write Register
 00h    Command CR (see #P089)            Command CR
Note:    Test Page - should never be modified!
SeeAlso: #P085,#P086,#P087

Bitfields for NS DP8390C/NS3249C network chipset command register (00h):
Bit(s)    Description    (Table P089)
 0    software reset command (1=offline, 0=online)
 1    do not activate NIC after reset command
 2    start transmision of a packet
 3-5    remote DMA command
    000 not allowed
    001 remote read
    010 remote write
    011 send packet
    1xx abort/complete rmote DMA
 6-7    page select
    00 register page 0
    01 register page 1
    10 register page 2
    11 register page 3
SeeAlso: #P088
---------------------------------------------
0370-0377 ----    FDC 2  (2nd Floppy Disk Controller)    first FDC at 03F0
Note:    floppy disk controller is usually an 8272, 8272A, NEC765 (or
      compatible), or an 82072 or 82077AA for perpendicular recording at
      2.88M
SeeAlso: PORT 03F0h-03F7h

0370  R      diskette Extra High Density controller board jumpers (AT)
0370  R      diskette controller status A (PS/2, PS/2 model 30)
0371  R      diskette controller status B (PS/2, PS/2 model 30)
0372   W  diskette controller DOR (Digital Output Register)
0374  R      diskette controller main status register
0374   W  diskette controller datarate select register
0375  RW  diskette controller command/data register
0376  RW  (2nd FIXED disk controller status/data register)
0377  RW  (2nd FIXED disk controller drive address register)
0377  R      diskette controller DIR (Digital Input Register)
0377   W  select register for diskette data transfer rate
---------------------------------------------
0378      ----    Covox 'Speech Thing' COMPATIBLE SPEECH OUTPUT
SeeAlso: PORT 022Fh"mc-soundmachine",PORT 0388h-038Fh"soundmachine"

0378   W  speech output via printer port
      (with mc-soundmachine, enabled if bit4=1 in 38F)
---------------------------------------------
0378-037A ----    parallel printer port, same as 0278 and 03BC

0378   W  data port
0379  RW  status port
037A  RW  control port

037B  ??  bit 7: shadow RAM on/off (UniRAM adapter,according to c't 7/90)
---------------------------------------------
0380-038F ----    2nd Binary Synchronous Data Link Control adapter (see 03A0)

0380  RW   on board 8255 port A, internal/external sense
0381  RW   on board 8255 port B, external modem interface
0382  RW   on board 8255 port C, internal control and gating
0383  RW   on board 8255 mode register
0384  RW   on board 8253 channel square wave generator
0385  RW   on board 8253 channel 1 inactivity time-out
0386  RW   on board 8253 channel 2 inactivity time-out
0387  RW   on board 8253 mode register
0388  RW   on board 8273 read: status  write: command
0389  RW   on board 8273 read: response     write: parameter
038A  RW   on board 8273 transmit interrupt status
038B  RW   on board 8273 receiver interrupt status
038C  RW   on board 8273 data
---------------------------------------------
0388-0389 ---- Sound Blaster / Adlib port - MONO OUTPUT
SeeAlso: PORT 0220h-0223h,PORT 0388h-038Fh"soundmachine"

0388  R      both speakers -- Status
        bit7  : interrupt request (IRQ)
        bit6  : timer 1 overflow
        bit5  : timer 2 overflow
        bit4-0: reserved
0388   W  both speakers -- Address port (see #P090)
    index in OPL2 (YMF3812), OPL3 (YMF262), OPL4 (YF278-F)
0389   W  data port

(Table P090)
Values for Sound Blaster dual-speaker address port index:
 01h    Enable waveform control
    bit 7-6: (OPL4, OPL3 in OPL2 mode only) lsi test
    bit 5: (OPL2 only) wave select enable (WS)
           (OPL4, OPL3) lsi test
    bit 4-0: lsi test
 02h    Timer #1 data (OPL2 and OPL3 in OPL2 mode only)
 03h    Timer #2 data (OPL2 and OPL3 in OPL2 mode only)
 04h    Timer control flags (OPL2 and OPL3 in OPL2 mode only)
    bit 7  : reset interrupt (RST)
    bit 6  : timer 1 mask (MASK1)
    bit 5  : timer 2 mask (MASK2)
    bit 4-2: reserved
    bit 1  : start timer 2 (ST2)
    bit 0  : start timer 1 (ST1)
 04h    (OPL3 in OPL3 mode only) connection select
    bit 7-6: reserved
    bit 5-0: connection selection
 05h    (OPL3) compatibility register
    bit 7-1: reserved
    bit 0: enable OPL3 mode (NEW), default disabled
 08h    Speech synthesis mode
    bit 7: (OPL2 only) speech synthesis or FM music mode (CSM)
    bit 6: select keyboard split point (SEL/NTS)
    bit 5-0: reserved
 20h-35h Amplitude Modulation / Vibrato
    bit 7: AM modulation (AM)
    bit 6: vibrato (VIB)
    bit 5: sustain (EG)
    bit 4: keyboard scaling rate (KSR)
    bit 3-0: multi (MF)
 40h-55h Level key scaling / Total level
    bit 7-6: key scale level (KSL)
    bit 5-0: total level (TL)
 60h-75h Attack / Decay rate
    bit 7-4: attack rate
    bit 3-0: decay rate
 80h-95h Sustain / Release rate
    bit 7-4: sustain level
    bit 3-0: release rate
 A0h-A8h Octave / Frequency (LSB)
 A9h-AFh ???
 B0h-B8h Octave / Frequency Number
    bit 7-6: reserved
    bit 5  : key on, mute
    bit 4-2: block, octave
    bit 1-0: f-number (MSB)
 BDh    percussion, vibrato, AM    (OPL2, OPL3 in OPL2 mode only)
    bit 7: amplitude modulation (AM)
    bit 6: vibrato (VIB)
    bit 5: ryhthm, percussion on/off (R)
    bit 4: bass drum on/off (BD)
    bit 3: snare drum on/off (SD)
    bit 2: tom-tom on/off (TOM)
    bit 1: top cymbal on/off (TC)
    bit 0: hi hat on/off (HH)
 C0h-C8h Feedback / Algorithm
    bit 7-4: OPL3: channel D-A
    bit 3-1: feedback
    bit 0: connection
 E0h-F5h Waveform Selection
    bit 7-3: reserved
    bit 2  : (OPL3) waveform bit2
    bit 1-0: waveform
SeeAlso: #P091

(Table P091)
Values for Sound Blaster registers inside groups:
Offset
 +00..+02: operators 1-3    modulator channel 1-3
 +03..+05: operators 4-6    carrier channel 1-3
 +08..+0A: operators 7-9    modulator channel 4-6
 +0B..+0D: operators 10-12  carrier channel 4-6
 +10..+12: operators 13-15  modulator channel 7-9
 +13..+15: operators 16-18  carrier channel 7-9
 +06, +07, +0E, +0F: reserved
SeeAlso: #P090
---------------------------------------------
0388-0389 ---- Soundblaster PRO FM-Chip
---------------------------------------------
0388-038B ---- Soundblaster 16 ASP FM-Chip
---------------------------------------------
0388-038F ----    mc-soundmachine, mc 03-04/1992 - SPEECH I/O
Note:    Adlib-compatible, Covox 'voice master' & 'speech thing' compatible
      soundcard
SeeAlso: PORT 022Fh"soundmachine",PORT 0278h"Covox"

0388   W  Covox 'speech thing'compatible speech output via printer port?
        enabled if bit 6 set in PORT 038Fh
0388  RW  Adlib compatible (YM3812), enabled if bit 0 set in PORT 038Fh
        (see PORT 0388h-0389h"Sound Blaster"
0389   W  Adlib compatible (YM3812), enabled if bit 0 set in PORT 038Fh
        (see PORT 0388h-0389h"Sound Blaster"
038A   W  I²C control for TDA7302 NF-MUX and X24C04 EEPROM
        bit 7: I²C bus SDA out (data),  enabled if bit2=1 in PORT 038Fh
        bit 0: I²C bus SCL out (clock), enabled if bit2=1 in PORT 038Fh
038B  R      I²C status for TDA7302 NF-MUX and X24C04 EEPROM
        bit 7: I²C bus SDA in (data),  enabled if bit2=1 in PORT 038Fh
        bit 0: I²C bus SCL in (clock), enabled if bit2=1 in PORT 038Fh
038F  RW  configuration port (power on default=0, all features disabled)
        bit 7 Covox 'voice master' enabled at PORT 022Fh
        bit 6  ""   'speech thing' enabled at PORT 03BCh
        bit 5  ""           enabled at PORT 0278h
        bit 4  ""           enabled at PORT 0378h
        bit 3  not used (0388???)
        bit 2  I²C bus enabled (PORT 038Ah,PORT 038Bh)
        bit 1  gameport enabled (PORT 0201h)
        bit 0  AdLib registers (PORT 0388h,PORT 0389h) enabled
---------------------------------------------
0390-0397 ----    Sunshine EW-901B, EW-904B
        EPROM writer card for EPROMs up to 27512
0390-0393  ??  adresses of the 8255 on the EW-90xB
---------------------------------------------
0390-039F ----    Cluster adapter (AT)

0390  ??  (adapter 0)    (XT)
0391  ??  (adapter 0)    (XT)
0392  ??  (adapter 0)    (XT)
0393  ??  (adapter 0)    (XT)
---------------------------------------------
0398-0399 ----    Dell Enhanced Parallel Port
SeeAlso: 002E, 015C, 026E

0398   W  index for data port
0399  RW  EPP command data
---------------------------------------------
03A0-03AF ----    1st SDLC (Binary Synchronous Data Link Control adapter)

03A0  RW   on board 8255 port A, internal/external sense
03A1  RW   on board 8255 port B, external modem interface
03A2  RW   on board 8255 port C, internal control and gating
03A3  RW   on board 8255 mode register
03A4  RW   on board 8253 counter 0 unused
03A5  RW   on board 8253 channel 1 inactivity time-out
03A6  RW   on board 8253 channel 2 inactivity time-out
03A7  RW   on board 8253 mode register
03A8  RW   on board 8251 data
03A9  RW   on board 8251 command/mode/status register
---------------------------------------------
03B0-03BF ----    MDA  (Monochrome Display Adapter based on 6845)

03B0   W  same as 03B4
03B1  RW  same as 03B5
03B2   W  same as 03B4
03B3  RW  same as 03B5
03B4   W  MDA CRT index register     (MDA/mono EGA/mono VGA)
        selects which register (0-11h) is to be accessed through 03B5h
        Note: this port is read/write on some VGAs
        bit7-6: VGA: reserved (0)
        bit5  : VGA: reserved for testing (0)
        bit4-0: selects which register is to be accessed through 03B5h
03B5  RW  MDA CRT data register     (MDA/mono EGA/mono VGA)
        selected by port 3B4. registers 0C-0F may be read
        Color adapters are at 3D4/3D5, but are mentioned here for
          better overview.
        There are differences in names and some bits functionality
          on EGA, VGA in their native modes, but clones in their
          emulation modes emulate the original 6845 at bit level. The
          default values are for MDA, HGC, CGA only, if not otherwise
          mentioned.
03B6   W  same as 03B4h
03B7  RW  same as 03B5h
03B8  rW  MDA mode control register (see #P093)
03B9  ?W  reserved for color select register on color adapter
03B9   W  MDA/HGC: set lightpen flipflop (value written is ignored)
        cannot be found on native mono EGA, mono VGA (without
          translation ROM)
03BA  R      CRT status register (see #P094)
        (EGA/VGA) input status 1 register
03BA   W  (mono EGA/mono VGA) feature control register
        (see PORT 03DAh-W for details; VGA, see PORT 03CAh-R)
03BB   W  light pen strobe reset (on any value)

(Table P092)
Values for mono video adapter CRT data register index:
                  defaults:    MDA/HGC    HGC   CGA   CGA      CGA
                         text  graph text1 text2 graph
                           7  720x348  1     3      5,6
 00h    horizontal total              61h    35h   38h   71h      38h
          ET4000: in VGA mode scanlines-5
              in EGA mode scanlines-2
 01h    horizontal displayed              50h    2Dh   28h   50h      28h
          horizontal display end-1 (EGA,VGA)
 02h    horizontal sync position          52h    2Eh   2Dh 5Ah/5Ch 2Dh
 03h    sync pulse width              0Fh 07h/0Fh 0Ah   0Ah      0Ah
           bit7-4 vsync, bit3-0 hsync
          end horizontal blanking (EGA,VGA)
           VGA    : bit7=1      : enable read access to regs
                    10h, 11h (otherwise VGA clones
                    may show lightpen values)
           EGA,VGA: bit6-5=0-3: display enable skew control
            bit4-0      : end blanking
 04h    vertical total (vcycle-1)          19h    5Bh   1Fh   1Fh      7Fh
           bit7 only used on MCGA
          start horizontal retrace (EGA, VGA)
          Genoa SuperEGA only???:
           bit7  : start at odd memory address
           bit6-5: horizontal sync skew
           bit4-0: start retrace+ retrace width
 05h    vertical total adjust              06h    02h   06h   06h      06h
           bit7-5 only used on MCGA
          end horizontal retrace (EGA, VGA)
           bit7  : EGA: start at odd memory address
               VGA: bit5 of end horizontal retrace
           bit6-5: horizontal sync skew
           bit4-0: end horizontal retrace
 06h    vertical displayed              19h    57h   19h   19h      64h
           bit7 only used on MCGA
          EGA: vertical total-1
          VGA: vertical total-2
 07h    vertical sync pulse width-1          19h    57h   1Ch   1Ch 70h/66h
           bit7  only used on MCGA
          controller overflow (EGA,VGA)
           bit7: VGA: bit9 of start vertical retrace (10h)
           bit6: VGA: bit9 of vertical display end (12h)
           bit5: VGA: bit9 of vertical total (06h)
             EGA: bit5 of cursor-position (0Ah)
           bit4: bit8 of line compare (18h)
           bit3: bit8 of start vertical blanking (15h)
           bit2: bit8 of vertical retrace start (10h)
           bit1: bit8 of vertical display end (12h)
           bit0: bit8 of vertical total (06h)
 08h    interlace mode (not MCGA)          02h    02h   02h   02h      02h
           bit7-2: reserved
           bit1  : delay
           bit0=1: interlace on
          preset row scan (EGA, VGA)
           bit7  : reserved
           bit6-5: VGA: byte panning
           bit4-0: start row scan after retrace
 09h    maximum scan lines              0Dh    03h   07h   07h      01h
           bit7  : VGA: double scan active
           bit6  : VGA: bit9 of line compare (18h)
           bit5  : VGA: bit9 of start vertical blanking (15h)
           bit4-0: maximum scan line 00..31 (height-1)
 0Ah    cursor start                  0Bh    00h   06h   06h 06h/00h
           bit7  : reserved
           bit6-5: original 6845: cursor on/off, blink intervall
               (not on all adapters, as original MDA, CGA have
               extra circuitrity to avoid this!!)
           bit6-5: native EGA: not used
           bit6  : VGA: not used
           bit5=0: VGA: cursor on
           bit4-0: first cursor scanline
 0Bh    cursor end                  0Ch    00h   07h   07h 07h/00h
           bit7  : reserved
           bit6-5: EGA, VGA: cursor skew control
           bit4-0: end cursor row
 0Ch    start address high              00h    00h   00h   00h      00h
           bit7-6 not used by original 6845 (MDA,HGC,CGA)
 0Dh    start address low              00h    00h   00h   00h      00h
 0Eh RW    cursor location high              00h    00h   00h   00h      00h
           bit7-4 not used by original 6845 (MDA,HGC,CGA)
           bit5-4 reserved on MCGA
 0Fh RW cursor location low              00h    00h   00h   00h      00h
---for 10h-14h MCGA registers see at 3D4h/3D5h---
 10h R-    light pen high (MDA/CGA/EGA only, some HGC, few VGA
           clones in emulation, not with ET4000)
 10h R-    native VGA with bit7=1 in end horizontal blanking (03h) and ET4000:
           start vertical retrace
 10h R- MCGA at 3D5h only: mode control status register
 10h -W EGA, VGA: start vertical retrace
 10h -W MCGA at 3D5h only: mode control register
 11h R- light pen low (MDA/CGA/EGA only, some HGC, few VGA
           clones in emulation, not with ET4000)
 1xh    according to a info paper by Quarterdeck three extra
         write-only registers are available in HGC+ for controlling
         two extra RAMfont modes. No more info available.
         This might conflict with MCGA/EGA/VGA registers.
 11h R- native VGA with bit7=1 in end horizontal blanking (03h):
           end vertical retrace
 11h -W EGA, VGA: end vertical retrace
           bit7  : VGA: protection bit
                =0 enable write access to 00h-07h
                =1 read only regs 00h-07h with the exception
                   of bit4 in 07h. ET4000: protect 35h also.
           bit6  : VGA: =0 three, =1 five refreshcycles/line
               ET4000: reserved
           bit5=0: (MCGA also) enable vertical interrupt
           bit4=0: (MCGA also) clear vertical interrupt
           =1:           no effect
           bit3-0: (MCGA also) vertical retrace end
 11h RW MCGA at 3D5h only: interrupt control register
 12h    EGA, VGA: vertical display end register
 12h RW MCGA at 3D5h only: character generator/sync pol. register
 12h R- MCGA at 3D5h only: display sense register
           (with bit7=1 in 11h only)
 13h    EGA, VGA: row offset register
           logical screen line width in
        byte mode : bytes/(line/2)
        word mode : bytes/(line/4)
        dword mode: bytes/(line/8)
 13h -W MCGA at 3D5h only: character font pointer register
 14h    EGA, VGA: underline location register
           bit7=0: reserved
           bit6  : VGA: 0=word-mode, 1=dword-mode (see 17h, bit6)
           bit5  : VGA: 0=standard address counter clock
                1=address counter clock/4 (see 17h, bit3)
           bit4-0: horizontal underline row scan
 14h -W MCGA at 3D5h only: number of characters to load during
           vretrace period
 15h    EGA, VGA: start vertical blanking-1
 16h    EGA, VGA: end vertical blanking register
           bit7-5 : EGA: reserved, but used on original EGA???
           bit4-0 : end vertical blanking
 17h    EGA, VGA: mode control register (see #P095)
 18h    EGA, VGA: line compare register
 19h    Genoa SuperEGA only: double scan control
           at 3B5h only in MDA, HGC emulation, but at 3D5h even in
           mono EGA modes.
           bit7-5 : reserved
           bit4   : HR/VR width adjust flag for double scan mode
           bit3-1 : 1=test, 0=normal
           bit0   : double scan enable
 1Bh    ET3000 only: x-zoom start register
          The existence of this register is often used to decide
           between ET3000 and ET4000, as the ET4000 does not offer
           hardware-zoom features.
 1Ch    ET3000 only: x-zoom end register
 1Dh    ET3000 only: y-zoom start register low
 1Eh    ET3000 only: y-zoom end register low
 1Fh    ET3000 only: y-zoom start & end high register
 20h    ET3000 only: zoom start address register low
 21h    ET3000 only: zoom start address register medium
 23h    ET3000 only: extended start address (see 33h)
 24h    ET3000 only: compatibility register (see 34h)
 25h    ET3000 only: overflow high register (see 35h, 07h)
 32h    ET4000: RAS/CAS configuration ('key' protected) (see #P096)
 33h    ET4000: extended start address
          This register is often used to decide between ET4000
          and ET3000, when bit3-0 can be reread after write.
           bit7-4 : reserved
           bit3-2 : cursor address bit 17-16
           bit1-0 : linear start address bits 17-16
 34h    ET4000: 6845 compatibility control register ('key' protected)
      (see #P097)
 35h    ET4000: overflow high register (protected by 11h, bit7) (see #P098)
 36h    ET4000: video system configuration 1 ('key' protected) (see #P099)
 37h    ET4000: video system configuration 2 ('key' protected) (see #P100)
Notes:    MDA, HGC, CGA: 6845 registers 00h-0Dh are write only, 0Eh, 0Fh
           are r/w, and 10h-11h are read only.
           The alternative initial defaults may be used
           sometimes on modern adapters.
    HGC+(RamFont): as with HGC, but 3 (unknown) registers more for
           font control
    emulations   : more registers may be r/w, but most often it's
           the same as with native 6845.
    MCGA (CGA+)  : Though this is a mixture of CGA and VGA, most
           registers are same as with CGA, but with some
           enhancements and incompatibilities to EGA, VGA.
    native EGA   : registers 00h-0Bh are write only, 0Ch-0Fh are
           r/w, 10h-11h are read/write, 12h-18h are write
           only. More regs may be r/w on enhanced clones.
    GenoaSuperEGA: adapter with chips SEQCRT GN006001 and GRAT
           GN006002, e.g. c't Super-EGA adapter. Is EGA
           clone with up to 800x600 and full 6845 emulation.
    native VGA   : all registers 00-18h are r/w, but 00h-07h are
           write-locked if bit7 in 11h is set.
    ET4000         : same as VGA, but with additional r/w registers
           32h-37h, protected by 'key' except 33h, 35h
           (see 3BFh for details). 35h is protected by
           bit7 in 11h. The 'key' must be issued at least
           after each power on or synchronous reset.
SeeAlso: #P093,#P094

Bitfields for mono video adapter mode control register:
Bit(s)    Description    (Table P093)
 7 not used by MDA, page number on HGC
 6    not used
 6  R-O    (mono ET4000 only) report status of bit 1 (enable 2nd page) of
      Hercules compatibility register (PORT 03BFh)
 5    enable blink (0 = intense background, 1 = blink)
 4    not used
 3    video enable
 2    not used
 1    (MDA) not used
    (HGC) graphics enable
    the 6845 has to be reprogrammed completely, if this bit is
      changed, otherwise the TTL-monitor may be damaged by wrong
      sync impulses!
 0    high resolution mode (always set on MDA)
---mono ET4000 only, W-O ---
 7-0    =A0h: second part of 'key', see Hercules compatibility register
      (PORT 03BFh) for details
Note:    this port might be completely or partially readable on very few MDA,
      HGC clones or emulations (e.g. Genoa SuperEGA), but not with the
      majority of original and clone chips.  It cannot be found on
      native mono EGA, mono VGA, but on most clones, where it is usually
      R/W.
SeeAlso: #P092,#P094

Bitfields for mono video adapter CRT status register:
Bit(s)    Description    (Table P094)
 7    HGC: vertical sync pulse in progress
 6-4    adapter identification
    (MSD says) if bit 7 changes within 8000h reads then
        =000 adapter is Hercules or compatible
        =001 adapter is Hercules+
        =101 adapter is Hercules InColor
        else: adapter is unknown
 6-4    =111 on MDA and some HGC clones
 5-4    (mono EGA, mono ET4000) diagnose video display feedback
    select from color plane enable
 3    (MDA,HGC) pixel stream (0=currently black, 1=currently white)
    (mono EGA, mono VGA) vertical retrace in progress
 2-1    (MDA) reserved
 2    (HGC, mono EGA) lightpen flipflop set
    (mono ET4000) reserved (0)
 1    (HGC) lightpen input stream (if set, current value to get from
      PORT 03B5h/10h-11h)
    (mono ET4000) reserved (0)
 0    horizontal drive enabled
SeeAlso: #P092,#P093

Bitfields for EGA,VGA mode control register:
Bit(s)    Description    (Table P095)
 7    0=CRTC reset and stop, 1=resume reset
 6    0=word-mode, 1=byte-mode (VGA: see 14h, bit6)
 5    0=14bit, 1=16bit address wrap
 4    (native VGA only) reserved (0)
 4    (EGA and most VGA clones) output control
    0: video driver active
    1: video driver not active
 3    linear address counter clock (0 = standard, 1 = clock/2)
    (VGA: see register 14h, bit 5)
 2    horizontal retrace clock (0 = standard, 1 = clock/2)
 1    row scan counter
    0: address bit 14 = scan bit 1
    1: address bit 14 not altered
 0    6845 compatibility mode
    0: address bit 13 = scan bit 0 (as with 6845)
    1: address bit 13 not altered
SeeAlso: #P092

Bitfields for ET4000 RAS/CAS configuration register:
Bit(s)    Description    (Table P096)
 7    static column memory
    ET4000/W32i: interleave mode
 6    RAL RAS&CAS column setup time
 5    RCD RAS & CAS time
 4-3    RSP, RAS pre-charge time
 2    CPS, CAS pre-charge time
 1-0    CSW, CAS low pulse width
SeeAlso: #P092,#P097

Bitfields for ET4000 compatibility control register:
Bit(s)    Description    (Table P097)
 7    6845 compatibility enabled
 6    ENBA enable double scan/underline in AT&T mode
 5    ENXL enable translation ROM on writing
 4    ENXR enable translation ROM on reading
 3    ENVS VSE register port address
 2    TRIS tristate ET4000 output pins
 1    CS2 MCLCK clock select 2
 0    EMCK enable translation of CS0 bit
SeeAlso: #P092,#P096,#P098

Bitfields for ET4000 overflow high register:
Bit(s)    Description    (Table P098)
 7    vertical interlace mode
 6    alternate RMW control
 5    external sync reset (gen-lock) the line/chr counter
 4    line compare bit10
 3    vertical sync start bit10
 2    vertical display end bit10
 1    vertical total bit10
 0    vertical blank start bit10
SeeAlso: #P092,#P097,#P099

Bitfields for ET4000 video system configuration 1 register:
Bit(s)    Description    (Table P099)
 7    enable 16bit I/O read/write
 6    enable 16bit display memory read/write
 5    addressing mode (0=IBM, 1=TLI)
 4    0=segment / 1=linear system configuration
 3    font width control (1=up to 16bit, 0=8bit)
 2-0    refresh count per line-1
SeeAlso: #P092,#P098,#P100

Bitfields for ET4000 video system configuration 2 register:
Bit(s)    Description    (Table P100)
 7    DRAM display memory type (1=VRAM, 0=DRAM)
 6    test (1=TLI interal test mode)
 5    priority threshold control (0=more mem BW)
 4    disable block read-ahead
 3    display memory data depth
 2    bus read data latch control
 1-0    display memory data bus width
SeeAlso: #P092,#P099
---------------------------------------------
03BC-03BF ----    PARALLEL PRINTER PORT (MDA's LPT1)
Range:    PORT 0278h, PORT 0378h, or PORT 03BCh

03BC   W  data port
03BC  R      bidirectional port: input from connector
      unidirectional port: last value written to port
03BD  RW  status port (see #P101)
03BE  RW  control port (see #P102)

Bitfields for parallel interface status port:
Bit(s)    Description    (Table P101)
 7    busy
 6    NOT acknowledge (approx. 5us low pulse)
 5    out of paper
 4    printer is selected
 3    *no* error
 2     IRQ has *not* occurred
    (PS/2) printer returned -ACK
 1-0    reserved
SeeAlso: #P102

Bitfields for parallel interface control port:
Bit(s)    Description    (Table P102)
 7-5    reserved
 7    (see PORT 037Bh bit 7)
 5    enable bidirectional port
    (PS/2 also requires enabling via port 0102h)
 4    enable IRQ (via -ACK)
 3    select printer (SLCT IN line)
 2    =0 initialize printer (-RESET line)
 1    automatic line feed
 0    strobe (must be set for minimum of 5 microseconds)
SeeAlso: #P101
---------------------------------------------
03BF      ----    Hercules configuration switch register
Note:    can also be found on EGA and VGA clones in Hercules emulation

03BF   W  configuration switch register (see #P103)
03BF   W  (ET4000) Hercules compatibility register (see #P104)
03BF  RW  (Genoa SuperEGA) miscellaneous register
    Note: only available in MDA, HGC, and CGA emulation; should be
      compatible with Hercules configuration register, but may contain
      additional features

Bitfields for Hercules configuration switch register:
Bit(s)    Description    (Table P103)
 7-2    reserved
 1    =0  disables upper 32K of graphics mode buffer
    =1  enables upper 32K of graphics mode buffer
 0    =0  prevents graphics mode
    =1  allows graphics mode
SeeAlso: #P104

Bitfields for ET4000 compatibility register:
Bit(s)    Description    (Table P104)
 1    =0 disables upper 32K of graphics mode buffer
    =1 enables upper 32K of graphics mode buffer
 0    reserved (not needed for HGC graphics)
 7-0    =03h: first part of 'key' for access to some extra
         ET4000 regs. To issue the 'key', the following
         code must be executed:
          MOV DX, 3BFh
          MOV AL, 3
          OUT DX, AL
          MOV DX, 3D8h  (3B8h in mono mode)
          MOV AL, 0A0h
          OUT DX, AL
SeeAlso: #P103
---------------------------------------------
03C0-03C7 ----    Sunshine EW-901, EW-901A, EW-904, EW-904A
        EPROM writer card for EPROMs up to 27512
03C0-03C3    adresses of the 8255 on the EW-90x
---------------------------------------------
03C0-03CF ----    EGA  (1st Enhanced Graphics Adapter)    alternate at 02C0

!!!
03C0  rW  EGA VGA ATC index/data register
         Every write access to this register will toggle an internal
         index/data selection flipflop, so that consequtive writes to
         index & data is possible through this port. To get a defined
         start condition, each read access to the input status register
         #1 (3BAh in mono / 3DAh in color) resets the flipflop to load
         index. If values are changed during the vertical retrace
         period only no flicker will occur.

        index register (flipflop reset to 'index'): (default 20h)
         bit7-6: reserved
         bit5  : 0=CPU access (screen dark),
             1=video access to registers
         bit4-0: index in ATC (0..31)

        indexed registers in ATC (flipflop set to 'data'):
         00h..0Fh 16 palette registers, each:
             bit7-6: reserved
             bit5  : secondary red video
             bit4  : secondary green/intensity video
             bit3  : secondary blue/mono video
             bit2  : primary red video
             bit1  : primary green video
             bit0  : primary blue video
         10h    mode control register
             bit7  : VGA: SB/SG select
                 (0=4 pages á 64 regs, 1=16 pages á 16 regs)
             bit6  : VGA: PELCLK/2 (0=4bit color, 1=8bit color)
             bit5  : VGA: enable pixel panning
                 (0=all, 1=up to line compare register value)
             bit4  : reserved
             bit3  : background intensity (0=16 colors, 1=blink)
             bit2  : line graphics enable (0=background, 1=line 8=9)
             bit1  : 1=mono, 0=color select
             bit0  : 1=graphics, 0=text select
         11h    EGA: overscan color register (see VGA: 11h) (default: 00h)
             bit7-6: reserved
             bit5  : secondary red (SR)
             bit4  : secondary green (SR) / intensity
             bit3  : secondary blue (SB)
             bit2  : primary red (PR)
             bit1  : primary green (PG)
             bit0  : primary blue (PB)
         11h    VGA: overscan color register (see EGA: 11h) (default: 00h)
             bit7  : secondary intensity border color (SI)
             bit6  : secondary red (SR)
             bit5  : secondary green (SG)
             bit4  : secondary blue (SB)
             bit3  : intensity border color (PI)
             bit2  : primary red (PR)
             bit1  : primary green (PG)
             bit0  : primary blue (PB)
         12h    color enable register
             bit7-6: reserved
             bit5-4: diagnose / video status select
                    EGA:      VGA, ET4000:
                  00b = PR/PB         PR/PB
                  01b = SB/PG         SG/SB
                  10b = SR/SG         PI/PG
                  11b = reserved     SI/SR
             bit3  : enable plane 3
             bit2  : enable plane 2
             bit1  : enable plane 1
             bit0  : enable plane 0
         13h    horizontal pixel panning register
             bit7-4: reserved
             bit3-0: horizontal pixel panning
         14h    VGA: color select register (default: 00h)
             bit7-4: reserved
             bit3  : s-color 7
             bit2  : s-color 6
             bit1  : s-color 5 (only with 16 pages á 16 regs)
             bit0  : s-color 4 (only with 16 pages á 16 regs)
         16h    ET3000, ET4000 only: ATC miscellanenous
             (at least on ET4000 'key' protected)
             This register is also supported by ET3000, but the
             description is proved for ET4000 only.
             bit7  : bypass the internal palette
                 (e.g. for HiColor modes with Sierra RAMDACs)
             bit6  : reserved
             bit5-4: select high resolution / color mode
             bit3-0: reserved
03C1  R      VGA    ATC index/data read register
03C2  R      EGA VGA input status 0 register
             (Genoa SuperEGA in all emulation modes)
             bit6-5 are 'key' protected on ET4000.
             bit7  : CRT interrupt occured
                 EGA: 0=vertical retrace in progress, 1=display
             bit6  : EGA and ET4000: feature control 1 (pin17)
             bit5  : EGA and ET4000: feature control 0 (pin19)
             bit4  : DIP switch sense
                (0=closed, 1=open/switches readable)
             bit3-0: reserved
03C2   W  EGA VGA miscellaneous output register
             (Genoa SuperEGA in all emulation modes)
             bit7-6: vertical resolution
                  00b= 200 lines (EGA)
                  01b= 400 lines (VGA)
                  10b= 350 lines (EGA/VGA)
                  11b= 480 lines (VGA)
                 vsync (bit7) / hsync (bit6) polarity
                  (0=positive, 1=negative)
             bit5  : odd/even pagebit
             bit4  : EGA: 0=video driver on,
                      1=video driver off (feature connector used)
             bit3-2: pixelclock
                  00b= 14/25MHz (EGA/VGA)
                  01b= 16/28Mhz (EGA/VGA)
                  10b= EGA, VGA: external clock (EGA)
                  11b= EGA, VGA: reserved
                  10b= Genoa SuperEGA: 39Mhz
                  11b= Genoa SuperEGA: 26,824Mhz
             bit1=1: enable CPU RAM access
             bit0  : CRTC port address
                  0=3B4 mono
                  1=3D4 color
                    (color EGA: enable feature control at 3DAh,
                        status reg 1 at 3D2h)
03C3  RW  VGA    video subsystem enable (see also port 46E8h)
        for IBM, motherboard VGA only
             bit7-4=0: reserved
             bit3     : select video subsystem (address 46E8h)
             bit2-1     : reserved
             bit0     : select video subsystem (address 03C3)
03C4   W  EGA    TS index register
03C4  RW  VGA    sequencer index register
             bit7-3     : reserved
             bit2-0     : current TS index
03C5   W  EGA    TS data register
03C5  RW  VGA    sequencer data register
        EGA, VGA indexed TS registers:
            00h reset register
             bit7-2 : reserved
             bit1 =0: synchronous reset (EGA/VGA)
             bit0 =0: asynchronous reset (EGA, ET4000)
                  synchronous reset, also (VGA)
            01h clocking mode register / TS mode
             bit7-6 : reserved
             bit5 =1: VGA: screen refresh off
             bit4    : VGA: shift load (0=4x8, 1=1x32)
             bit3    : dot clock (0=normal, 1=clock/2)
             bit2    : serial shift video load (0=4x8, 1=2x16)
             bit1    : EGA: CRTC bandwidth (0=4/5, 1=2/5)
             bit0    : dot clocks (0=9, 1=8) (ET4000: see 06h)
            02h map mask register
             bit7-4 : reserved
             bit4    : Genoa SuperEGA only: plane4 ???
             bit3    : write enable display memory plane 3
             bit2    : write enable display memory plane 2
             bit1    : write enable display memory plane 1
             bit0    : write enable display memory plane 0
            03h character map select register / font select
             bit7-6 : reserved
             bit5    : VGA: bit3 for 2nd text-font
             bit4    : VGA: bit3 for 1st text-font
             bit3-2 : 2nd text-font (attr bit3=1)
             bit1-0 : 1st text-font (attr bit3=0)
                  offset in font memory (4-7: VGA only)
                   0 00b =  0KB
                   0 01b = 16KB
                   0 10b = 32KB
                   0 11b = 48KB
                   1 00b =  8KB
                   1 01b = 24KB
                   1 10b = 40KB
                   1 11b = 56KB
            04h memory mode register
             bit7-4 : reserved
             bit3 =1: VGA: enable chain 4 linear graphics mode
             bit2    : 0=odd/even mode, 1=sequencial mode
             bit1 =1: extended memory (0=64KB, 1=more)
             bit0    : EGA: 1=textmode, 0=graphics mode
            06h ET3000 only: Zoom control register
            06h ET4000 only: TS state control (protected by 'key')
             bit7-3 : reserved
             bit2-1 : timing sequencer state bit2-1
                   (bit0 is bit0 TS mode register)
                   00 0b=  9 dots
                   00 1b=  8 dots
                   01 0b= 10      (10-16 are ET4000 only)
                   01 1b= 11
                   10 0b= 12
                   11 1b= 16
             bit0    : reserved
            07h ET3000/ET4000 only: TS auxiliary mode
             (at least on ET4000 protected by 'key')
             This register is also supported by ET3000, but
             the description is proved on ET4000 only:
             bit7    : 1=VGA, 0=EGA compatibility mode
             bit6    : select MCLK/2 (with bit0=0)
             bit5    : BIOS ROM address map 2
             bit4    : reserved
             bit3    : BIOS ROM address map 1
             bit2 =1: reserved
             bit1    : select SCLK input from MCLK
             bit0    : select MCLK/4 (with bit6=1)
             bit5/3: ROM address
                  00b=C0000-C3FFF
                  01b=disabled
                  10b=C0000-C5FFF, C6800-C7FFF
                  11b=C0000-C7FFF (default)
03C6  RW  (VGA, MCGA) PEL mask register (default FFh)
         VGA:    AND mask for color-register address.
         MCGA:    Never change from the default FFh.
03C6  RW  HiColor ET4000 (Sierra RAMDACs e.g. SC11486, SC11481, SC11488):
         Enable HiColor feature: beside other assignments,
         consequtive read 3C6h 4 times and write magic value 80h to it.
03C7   W  (VGA,MCGA,CEG-VGA) PEL address register (read mode)
         Sets DAC in read mode and assign start of color register
         index (0..255) for following read accesses to 3C9h.
         Don't write to 3C9h while in read mode. Next access to
         03C8h will stop pending mode immediatly.
037C   W  (CEG-Color VGA w/ Edun Labs RAMDACs)
         Enable and set Countinous Edge Graphics Mode:
         Consecutive write the following three key sequences in read
         mode (!) to 3C9h register DEh : 'CEG', 'EDS', 'UNx' (x see
         below). Current CEG mode can be read from palette register
         BFh 'blue', write access to that register will disable CEG
         features.
         In CEG modes by combining old with new colors and dynamically
         changing palette values, the effective colors displayable
         are enhanced dramatically (in EDP modes up to virtually 32bit
         truecolor) on standard 16/256 color VGA. Also, effective
         resolution enhancement takes effect by anti-aliasing.
         Neccessary EDP escape sequences should be moved to image
         border or single colored areas, if possible.

         REP-mode: if pixel are doubled in current video mode
         EDP-mode: pseudo-truecolor with Edsun dynamic palette

         CEG modes:
           x:  mode:     colors:  mix:    pixel depth:  effective colors:
           0 = disabled       256       -         8            256
           1 = A        16      16         8           1920
           2 = A+REP        16      16      8 dblscn       1920
           3 = A+EDP        15      16            truecolor
           4 = reserved         -       -         -             -
           5 = B        16       8         8            960
           6 = B+REP        16       8      8 dblscn        960
           7 = B+EDP        15       8            truecolor
           8 = reserved         -       -         -             -
           9 = C         8       8         4            224
          10 = C+REP         8       8      4 dblscn        224
          11 = C+EDP         7       8            truecolor
          12 = reserved         -       -         -             -
          13 = D       223      32         8         792096
          14 = D+REP       223      32      8 dblscn     792096
          15 = D+EDP       223      32            truecolor

         Codes for mixes:

          Mode A:           |  Mode C:
           mix: new:    old:   |   mix: new:   old:   colorcode:
            0 = 32/32    0/32   |    0 =      -     -     0
            1 = 30/32    2/32   |    1 =      -     -     1
            2 = 28/32    4/32   |    2 =      -     -     2
            3 = 26/32    6/32   |    3 =      -     -     3
            4 = 24/32    8/32   |    4 =      -     -     4
            5 = 22/32  10/32   |    5 =      -     -     5
            6 = 20/32  12/32   |    6 =      -     -     6
            7 = 18/32  14/32   |    7 =      -     -     7/EDP
            8 = 16/32  16/32   |    8 = 30/32    2/32   -
            9 = 14/32  18/32   |    9 = 28/32    4/32   -
           10 = 12/32  20/32   |   10 = 26/32    6/32   -
           11 = 10/32  22/32   |   11 = 24/32    8/32   -
           12 =     8/32  24/32   |   12 = 22/32  10/32   -
           13 =     6/32  26/32   |   13 = 20/32  12/32   -
           14 =     4/32  28/32   |   14 = 18/32  14/32   -
           15 =     2/32  30/32   |   15 = 16/32  16/32   -

          Mode B:           |  Mode D:
           mix: new:    old:   |   mix:          new:   old:  description:
            0 = 30/32    2/32   |   00h..BEh =    -      -   normal color
            1 = 26/32    6/32   |   BFh        =    -      -   EDP
            2 = 22/32  10/32   |   C0h        = 32/32   0/32
            3 = 18/32  14/32   |   C1h        = 31/32   1/32
            4 = 14/32  18/32   |   C2h        = 30/32   2/32
            5 = 10/32  22/32   |   ...        =  ...    ...
            6 =     6/32  26/32   |   DFh        =  0/32  32/32
            7 =     2/32  30/32   |   E0h-FFh  =    -      -   normal color

         Palette-color-register single-byte-format (each 3 times):

          Mode A:          Mode C:
           bit7-4: mix code       bit3     : 0=color, 1=code
           bit3-0: color code       bit2-0: color / mix code

          Mode B:          Mode D:
           bit7-5: mix code       bit7-0: see mix code table
           bit4     : 0=new, 1=old      Non-CEG modes:
           bit3-0: color code       bit7-0: as usual

         In EDP modes, video-memory-palette-changing escape-sequences:

          Mode A:     Mode B:      Mode C:     Mode D:
           7/escape    7/escape       7/escape    0BFh
           red           red       red7-4      red
           green       green       red3-0      green
           blue           blue       green7-4    blue
           address     address       green3-0    address
                       blue7-4
                       blue3-0
                       address
03C7  R      VGA    DAC state register
        bit7-2 reserved
        bit1-0: 00b write palette cycle (write mode)
            01h reserved
            10b reserved
            11b read palette cycle (read mode)
03C8  RW  (VGA,MCGA) PEL address register (write mode)
         Sets DAC in write mode and assign start of color register
         index (0..255) for following write accesses to 3C9h.
         Don't read from 3C9h while in write mode. Next access to
         03C8h will stop pending mode immediatly.
03C8  RW  (Genoa SuperEGA) SuperEGA control register (all emulation modes)
          bit7-2: reserved
          bit1    : 0=EGA mode, 1=backward compatibility mode
          bit0    : not used
03C9  RW  (VGA,MCGA) PEL data register
         Three consequtive reads (in read mode) or writes (in write
         mode) in the order: red, green, blue. The internal DAC index
         is incremented each 3rd access.
          bit7-6: HiColor VGA DACs only: color-value bit7-6
          bit5-0:             color-value bit5-0
03CA   W  EGA    graphics 2 position register
03CA  R      VGA    feature control register (see PORT 03BAh,PORT 03DAh-W)
03CB  RW  (ET4000/W32) GDC segment select register 2 ('key' protected?)
        The existence of this r/w register 0..255 is often
         used to decide between ET4000 and ET4000/W32.
         bit7-6: reserved, but existent
         bit5-4: bits 5-4 of read segment pointer
         bit3-2: reserved, but existent
         bit1-0: bits 5-4 of write segment pointer
03CC   W  EGA    graphics 1 position register
03CC  R      VGA    miscellaneous output register (see PORT 03C2h-W)
03CD  RW  (ET3000, ET4000, ET4000/W32) GDC segment select ('key' protected)
        The existence of this r/w register is often used as
        detection of ET3000, ET4000 and ET4000/W32 chips.
         bit7-4: read segment pointer for mapping to A0000h
         bit3-0: write segment pointer for mapping to A0000h
03CE   W  EGA    GDC index register
03CE  RW  VGA    graphics address register / GDC index
              bit7-4: reserved
              bit3-0: index
03CF   W  EGA    GDC data register
03CF  RW  VGA    other graphics register
        (EGA,VGA) indexed registers in GDC:
         00h set/reset register (default 00h)
              functionality depending on write mode (see 05h)
              bit7-4: reserved
              bit3  : 0=write 00h, 1=write FFh in plane 3
              bit2  : 0=write 00h, 1=write FFh in plane 2
              bit1  : 0=write 00h, 1=write FFh in plane 1
              bit0  : 0=write 00h, 1=write FFh in plane 0
         01h enable set/reset register (default 00h)
              bit7-4: reserved (used on Genoa SuperEGA???)
              bit3  : enable set/reset plane 3
              bit2  : enable set/reset plane 2
              bit1  : enable set/reset plane 1
              bit0  : enable set/reset plane 0
              bit3-0: 0=CPU access, 1=set/reset access to plane
         02h color compare register (default 00h)
              bit7-4: reserved
              bit3  : color compare 3
              bit2  : color compare 2
              bit1  : color compare 1
              bit0  : color compare 0
              bit3-0: color number
         03h data rotate register (default 00h)
              bit7-5: reserved
              bit4-3: logical function select
                   00b= CPU-data overwrites
                   01b= CPU-data AND with latch-register
                   10b= CPU-data OR with latch-register
                   11b= CPU-data XOR with latch-register
              bit2-0: rotate count
         04h read map select register (default 00h)
              bit7-3: reserved
              bit2  : EGA?? & Genoa SuperEGA: map select bit2
              bit1-0: map select (0..3)
         05h mode register
              bit7  : reserved
              bit6  : VGA: 0=standard, 1=enable 256 colors
              bit5  : shift register mode, 0=standard, 1=CGA-graphics
                  (not used on Genoa SuperEGA???)
              bit4=1: enable odd/even address mode
              bit3  : read mode, 0=mode0, 1=mode1
              bit2  : EGA: test condition, 0=standard, 1=output tristate
              bit1-0: write mode
                   00b = mode0, plane source is CPU or set/reset
                   01b = mode1, plane source is latch-register
                   10b = mode2, plane source is CPU as set/reset
                   11b = VGA: mode3, CPU as set/reset AND bitmask
         06h miscellaneous register
              bit7-4: reserved (=0)
              bit3-2: memory map
                   00b = A0000..BFFFF (128KB)
                   01b = A0000..AFFFF (64KB)
                   10b = B0000..B7FFF (32KB)
                   11b = B8000..BFFFF (32KB)
              bit1  : chain odd maps to even, 1=subst addess bit0
              bit0  : 0=testmode, 1=graphics mode
         07h color don't care register
              bit7-4: reserved
              bit3=1: color plane 3 don't care (ignore bit3)
              bit2=1: color plane 2 don't care (ignore bit2)
              bit1=1: color plane 1 don't care (ignore bit1)
              bit0=1: color plane 0 don't care (ignore bit0)
         08h bit mask register (default FFh)
              bit7-0: bitmask for latch/databyte
                  (bit set=change allowed)
         0Fh Paradise SuperVGA only: lock register
             The ability to write and reread 00h..07h to this register
             is often used as detection of Paradise chips.
              bit7-0 = 01h lock/hide Paradise specific registers
                 = 05h unlock Paradise specific registers
              bit7-3: reserved
              bit2-0: flipflops, reserved
---------------------------------------------
03CE-03CF ----    Compaq Qvision - Functionality Level

03CE   W  graphics address register (index for next port)
03CF  RW  other graphics register
    Index
     0Ch  RO    controller version
            2Fh Advanced VGA
            37h early QVision 1024
            71h QVision 1280 or later QVision 1024
     0Dh        extended controller version
     0Eh        extended controller capabilities
     0Fh        environment info
     54h        available memory
     55h        phase-locked-loop clock
     56h-57h    controller capabilities
---------------------------------------------
03D0-03DF ----    CGA   (Color Graphics Adapter)

03D0   W  same as 03D4
03D1  RW  same as 03D5
03D2   W  same as 03D4
03D3  RW  same as 03D5
03D4  rW  CRT (6845) index register   (CGA/MCGA/color EGA/color VGA)
    selects which register (0-11h) is to be accessed through 03D5
    this port is r/w on some VGA, e.g. ET4000
        bit 7-6 =0: VGA: reserved
        bit 5   =0: VGA: reserved for testage
        bit 4-0   : selects which register is to be accessed through 03D5
03D5   W  CRT (6845) data register    (CGA/MCGA/color EGA/color VGA)
        selected by port 03D4h. registers 0C-0F may be read
         (see also PORT 03B5h)
        MCGA, native EGA and VGA use very different defaults from
        those mentioned for the other adapters.
        (for additionally notes and registers 00h-0Fh and EGA, VGAs
        10h-18h and ET4000 32h-37h see at 3B5)
        10h-11h on CGA, EGA, VGA and 12h-14h on EGA, VGA are
        conflictive with MCGA:
        w 10h MCGA only: mode control register (defaults 18h, 1Ah, 19h)
              bit7 = 1: suppress hsync/vsync
              bit6 = 0: reserved
              bit5    : reserved
              bit4 = 1: dot clock rate
              bit3 = 1: refresh calculations in 80x25 modes
              bit2    : reserved
              bit1 = 1: videomode 11h active
              bit0 = 1: videomode 13h active
        r 10h MCGA only: mode control status register
              bit7    : status bit0 CGA mode control register
              bit6    : reserved
              bit5 =1    clockrate 640 pixel, =0: clockrate/2 320 pixel
              bit4 =1 : clock rate is 25,175Mhz
              bit3 =1 : currently in textmode
              bit2 =1 : double-scan activated
              bit1 =1 : videomode 11h active
              bit0 =1 : videomode 13h active
          r/w 11h MCGA only: interrupt control register (default 30h)
              bit7 =1 : set output driver to tristate
                =0: for reading of character generator reg (12h)
                =1: for reading of display sense register (12h)
              bit6    : read only: intr generated by memory controller
              bit5 =0 : requested intr ok to handle
              bit4 =0 : free interrupt latch register
              bit3-0  : reserved
          r/w 12h MCGA only: character generator/sync polarity register
              default 46h in all modes, except 04h in mode 11h.
              bit7 =1 : character generator active
              bit6 =1 : load codepage during display
               =0 : load codepage during retrace
              bit5    : codepage number (0,1)
              bit4 =1 : 512 characters active
               =0 : 256 characters active
              bit3 =0 : reserved
              bit2 =1 : enable hsync/vsync
              bit1 =1 : positive vsync polarity
              bit0 =1 : positive hsync polarity
        r 12h MCGA only: display sense register (11h, bit7=1)
              bit7-2  : not used
              bit1-0  : pins 11 & 12 in monitor cable
                00b = reserved
                01b = analogue monochrom monitor
                10b = analogue color graphics monitor
                11b = no monitor
        w 13h MCGA only: character font pointer register
              only 00h, 10h, 20h, 30h (default 00h) are allowed here
              for textmode fonts at A0000, A2000, A4000, A6000
        w 14h MCGA only: number of characters to load during vretrace
              period (default FFh).
03D6   W  same as 03D4
        (under OS/2, reads return 0 if full-screen DOS session,
        nonzero if windowed DOS session)
03D7  RW  same as 03D5
03D8  RW  CGA mode control register  (except PCjr)
        cannot be found on native color EGA, color VGA, but on most
        clones
         bit7-0=A0h color ET4000: second part of 'key',
                   see hercules compatibility reg (3BFh) for
                   details. For reseting the key, e.g. write
                   01h to 3BFh and 29h to 3D8h.
         bit 7-6      not used
         bit 6     color ET4000 only, read-only: report status of
                   bit1 (enable 2nd page) of hercules compatibility
                   register (3BFh)
         bit 5     = 1  blink enabled instead of foreground high-int.
         bit 4     = 1  640*200 graphics mode
         bit 3     = 1  video enabled (HZ309, see PORT 03DAh bit 0)
         bit 2     = 1  monochrome signal
                   MCGA: in mode 6 and 11h color comes from pal-
                   regs 00 (black) and 07 (white), and can be
                   changed there.
         bit 1     = 0  text mode
             = 1  320*200 graphics mode
         bit 0     = 0  40*25 text mode
             = 1  80*25 text mode
03D9  RW  CGA palette register
      (MCGA) CGA border control register
        Cannot be found on native EGA, VGA (without translation ROM)
        but only most clones. Read access on Genoa SuperEGA is
        'reset'???
         bit 7-6      not used
         bit 5     = 0 active 320x200x4 color set: red, green brown
             = 1 active 320x200x4 color set: cyan, magenta, white
         bit 4         intense colors in graphics, background colors text
         bit 3         intense border in 40*25, intense background in
                 320*200, intense foreground in 640*200
         bit 2         red border in 40*25, red background in 320*200,
                 red foreground in 640*200
         bit 1         green border in 40*25, green background in
                 320*200, green foreground in 640*200
         bit 0         blue border in 40*25, blue background in 320*200,
                 blue foreground in 640*200
03DA  R      CGA status register    color EGA/VGA: input status 1 register
         bit 7-6     not used
         bit 5-4     color EGA, color ET4000: diagnose video display
                  feedback, select from color plane enable
         bit 3 = 1   in vertical retrace
         bit 2 = 1  (CGA,color EGA) light pen switch is off
                (MCGA,color ET4000) reserved (0)
         bit 1 = 1  (CGA,color EGA) positive edge from light pen has
                set trigger
                (MCGA,color ET4000) reserved (0)
         bit 0        horizontal retrace in progress
               = 0   do not use memory
               = 1   memory access without interfering with display
                (Genoa SuperEGA) horizontal or vertical retrace
03DA   W  color EGA/color VGA feature control register
         (at 3BAh w in mono mode, VGA: 3CAh r)
         bit7     : ET4000 only: enable NMI generation ('key' protected)
         bit6-4     : not used
         bit3     : VGA: 0 = normal vsync, 1 = vsync OR display enable
         bit2     : reserved
         bit1     : EGA and ET4000 only:
                FEAT1 control bit1 (pin17 feature connector)
         bit0     : EGA and ET4000 only:
                FEAT0 control bit0 (pin19 feature connector)
03DA   W  HZ309 (MDA/HGC/CGA clone) card from in Heath/Zenith HZ150 PC
         bit7-1=0: unknown, zero is default and known to function
               properly at least in CGA modes.
         bit 0 = 1 override 3x8h bit3 control register that switches
               CRT beam off if bit3 is cleared. So screens always
               stays on.
         bit 0 = 0 3x8h bit3 indicates if CRT beam is on or off.
               No more info available. Might conflict with EGA/VGA.
03DB  rW  clear light pen latch    (not MCGA)
          (R/W only with Genoa SuperEGA)
03DC  RW  (not MCGA) preset light pen latch
03DC   W  (CGA) set light pen latch
03DD   W  (MCGA)  Extended mode control register
      (Plantronics & Genoa SuperEGA: Plantronics ColorPlus control,
                  compatible with MCGA???)
        (default is 00h, in mode 13h: 04h)
         bit7 =1: DAC active, cannot be read
              =0: DAC not active, read allowed
         bit6-3 : reserved
         bit2 =1: videomode 13h with 256 colors active
         bit1    : reserved
         bit0 =0: reserved
03DE  --  (MCGA) reserved
03DE   W  AT&T & color ET4000 in AT&T compatibility mode:
        AT&T mode control register
          (register enabled in ET4000, if bit7=1 in CRTC 3D4h/34h.)
         bit7: reserved
         bit6: underline color attribute enable
               ET4000: enabled, if bit6=1 in CRTC 3D4h/34h.
         bit5: reserved
         bit4: reserved
         bit3: alternate page select (=1: 2nd 16KB page, with bit0=0)
         bit2: alternate font select (0=default font block)
         bit1: reserved
         bit0: double scan line mode
            (0=IBM 200, 1=AT&T 400 line graphics)
            ET4000: enabled, if bit7-6=11b in CRTC 3D4h/34h.
03DF  --  MCGA: reserved
03DF  ?W  CRT/CPU page register     (PCjr only)
---------------------------------------------
03E0-03E8  ----    LPT port address on the UniRAM card by German magazine c't
Range:    selectable from 260, 2E0, 2E8, 2F0, 3E0, 3E8.
---------------------------------------------
03E0-03EF ----    COM port addresses on UniRAM card by German magazine c't
Range:    selectable from 238, 2E8, 2F8, 338, 3E0, 3E8, 3F8
---------------------------------------------
03E8-03EF ----    serial port, same as 02E8, 02F8 and 03F8 (COM3)
SeeAlso: 03F8-03FF
---------------------------------------------
03E8-03EF  ----     LPT port address on the UniRAM card by German magazine c't
Range:    selectable from 260, 2E0, 2E8, 2F0, 3E0, 3E8.
---------------------------------------------
03F0-03F7 ----    FDC 1  (1st Floppy Disk Controller)    second FDC at 0370
Note:    floppy disk controller is usually an 8272, 8272A, NEC765 (or
      compatible), or an 82072 or 82077AA for perpendicular recording at
      2.88M
SeeAlso: PORT 0370h-0377h

03F0  R      diskette EHD controller board jumper settings (82072AA)
         bit 7-6      drive 3
         bit 5-4      drive 2
         bit 3-2      drive 1
         bit 1-0      drive 0
             = 00  1.2Mb
             = 01  720Kb
             = 10  2.8Mb
             = 11  1.4Mb
03F0  R      diskette controller status A (PS/2)
         bit 7     interrupt pending
         bit 6     -DRV2    second drive installed
         bit 5     step
         bit 4     -track 0
         bit 3     head 1 select
         bit 2     -index
         bit 1     -write protect
         bit 0     +direction
03F0  R      diskette controller status A (PS/2 model 30)
         bit 7     interrupt pending
         bit 6     DRQ
         bit 5     step F/F
         bit 4     -track 0
         bit 3     head 1 select
         bit 2     +index
         bit 1     +write protect
         bit 0     -direction
03F1  R      diskette controller status B (PS/2)
         bit 7-6  =1 reserved
         bit 5      drive select (0=A:, 1=B:)
         bit 4      write data
         bit 3      read data
         bit 2      write enable
         bit 1      motor enable 1
         bit 0      motor enable 0
03F1  R      diskette controller status B (PS/2 model 30)
         bit 7      -DRV2 second drive installed
         bit 6      -DS1
         bit 5      -DS0
         bit 4      write data F/F
         bit 3      read data F/F
         bit 2      write enable F/F
         bit 1      -DS3
         bit 0      -DS2
03F2   W  diskette controller DOR (Digital Output Register)
         bit 7-6    reserved on PS/2
         bit 7 = 1  drive 3 motor enable
         bit 6 = 1  drive 2 motor enable
         bit 5 = 1  drive 1 motor enable
         bit 4 = 1  drive 0 motor enable
         bit 3 = 1  diskette DMA enable (reserved PS/2)
         bit 2 = 1  FDC enable    (controller reset)
               = 0  hold FDC at reset
         bit 1-0    drive select (0=A 1=B ..)
03F3  ?W  tape drive register (on the 82077AA)
         bit 7-2      reserved, tri-state
         bit 1-0      tape select
             = 00  none, drive 0 cannot be a tape drive.
             = 01  drive1
             = 10  drive2
             = 11  drive3
03F4  R      diskette controller main status register
         bit 7 = 1  RQM     data register is ready
             0  no access is permitted
         bit 6 = 1  transfer is from controller to system
             0  transfer is from system to controller
         bit 5 = 1  non-DMA mode
         bit 4 = 1  diskette controller is busy
         bit 3 = 1  drive 3 busy (reserved on PS/2)
         bit 2 = 1  drive 2 busy (reserved on PS/2)
         bit 1 = 1  drive 1 busy (= drive is in seek mode)
         bit 0 = 1  drive 0 busy (= drive is in seek mode)
        Note:    in non-DMA mode, all data transfers occur through
              port 03F5h and the status registers (bit 5 here
              indicates data read/write rather than than
              command/status read/write)
03F4   W  diskette controller data rate select register
         bit 7-2      reserved on 8272
         bit 7     = 1  software reset (self clearing)    82072/82077AA
         bit 6     = 1  power down            82072/82077AA
         bit 5     = 0  reserved on 8272 and 82077AA
                  PLL select bit on 82072
         bit 4-2      write precompensation value, 000 default
         bit 1-0      data rate select
             = 00  500 Kb/S MFM    250 Kb/S FM
             = 01  300 Kb/S MFM    150 Kb/S FM
             = 10  250 Kb/S MFM    125 Kb/S FM
             = 11  1Mb/S    MFM    illegal     FM on 8207x
03F5  R      diskette command/data register 0 (ST0)
         bit 7-6      last command status
             = 00  command terminated successfully
             = 01  command terminated abnormally
             = 10  invalid command
             = 11  terminated abnormally by change in ready signal
         bit 5     = 1  seek completed
         bit 4     = 1  equipment check occurred after error
         bit 3     = 1  not ready
         bit 2     = 1  head number at interrupt
         bit 1-0 = 1  unit select (0=A 1=B .. )
                  (on PS/2    01=A  10=B)

        status register 1 (ST1)
         bit 7        end of cylinder; sector# greater then sectors/track
         bit 6 = 0
         bit 5 = 1  CRC error in ID or data field
         bit 4 = 1  overrun
         bit 3 = 0
         bit 2 = 1  sector ID not found
         bit 1 = 1  write protect detected during write
         bit 0 = 1  ID address mark not found

        status register 2 (ST2)
         bit 7 = 0
         bit 6 = 1  deleted Data Address Mark detected
         bit 5 = 1  CRC error in data
         bit 4 = 1  wrong cylinder detected
         bit 3 = 1  scan command equal condition satisfied
         bit 2 = 1  scan command failed, sector not found
         bit 1 = 1  bad cylinder, ID not found
         bit 0 = 1  missing Data Address Mark

        status register 3 (ST3)
         bit 7        fault status signal
         bit 6        write protect status
         bit 5        ready status
         bit 4        track zero status
         bit 3        two sided status signal
         bit 2        side select (head select)
         bit 1-0    unit select (0=A 1=B .. )

03F5   W  diskette command register.  The commands summarized here are
        mostly multibyte commands. This is for brief recognition only.

            MFM = MFM mode selected, opposite to MF mode.
            HDS = head select
            DS  = drive select
            MT  = multi track operation
            SK  = skip deleted data address mark

           Command         # bytes    D7  6    5   4    3   2    1   0
         read track        9    0  MFM    0   0    0   0    1   0
                        0   0    0   0    0 HDS DS1 DS0
         specify        3    0   0    0   O    O   O    1   1
         sense drive status    2    0   0    0   0    0   1    0   0
                        0   0    0   0    0 HDS DS1 DS0
         write data        9    MT MFM    0   0    0   1    0   1
                        0   0    0   0    0 HDS DS1 DS0
         read data        9    MT MFM SK   0    0   1    1   0
                        0   0    0   0    0 HDS DS1 DS0
         recalibrate        2    0   0    0   0    0   1    1   1
                        0   0    0   0    0   0 DS1 DS0
         sense interrupt status 1    0   0    0   0    1   0    0   0
         write deleted data    9    MT MFM    0   0    1   0    0   1
                        0   0    0   0    0 HDS DS1 DS0
         read ID        2    0  MFM    0   0    1   0    1   0
                        0   0    0   0    0 HDS DS1 DS0
         read deleted data    9    MT MFM SK   0    1   1    0   0
                        0   0    0   0    0 HDS DS1 DS0
         format track        10    0  MFM    0   0    1   1    0   1
                        0   0    0   0    0 HDS DS1 DS0
         dumpreg **        1    0   0    0   0    1   1    1   0
         seek            3    0   0    0   0    1   1    1   1
                        0   0    0   0    0 HDS DS1 DS0
         version **        1    0   0    0   1    0   0    0   0
         scan equal *        9    MT MFM SK   1    0   0    0   1
                        0   0    0   0    0 HDS DS1 DS0
         perpendicular mode **    2    0   0    0   1    0   0    1   0
                        0   0    0   0    0   0 WGATE GAP
         configure **        4    0   0    0   1    0   0    1   1
                        0   0    0   0    0   0    0   0
         verify            9    MT MFM SK   1    0   1    1   0
                        EC  0    0   0    0 HDS DS1 DS0
         scan low or equal *    9    MT MFM SK   1    1   0    0   1
                        0   0    0   0    0 HDS DS1 DS0
         scan high or equal *    9    MT MFM SK   1    1   1    0   1
                        0   0    0   0    0 HDS DS1 DS0
         relative seek **    3    1  DIR    0   0    1   1    1   1
                        0   0    0   0    0 HDS DS1 DS0

         BEWARE: not every invalid command is treated as invalid!
         *  Note: the scan commands aren't mentioned for the 82077AA.
         ** Note: EHD controller commands.

03F6  --  reserved on FDC
03F6  rW  FIXED disk controller data register
         bit 7-4    reserved
         bit 3 = 0  reduce write current
             1  head select 3 enable
         bit 2 = 1  disk reset enable
             0  disk reset disable
         bit 1 = 0  disk initialization enable
             1  disk initialization disable
         bit 0        reserved
03F7  RW  harddisk controller
         bit 6       FIXED DISK write gate
         bit 5       FIXED DISK head select 3 / reduced write current
         bit 4       FIXED DISK head select 2
         bit 3       FIXED DISK head select 1
         bit 2       FIXED DISK head select 0
         bit 1       FIXED DISK drive 1 select
         bit 0       FIXED DISK drive 0 select
03F7  R      diskette controller DIR (Digital Input Register, PC/AT mode)
         bit 7 = 1 diskette change
         bit 6-0   tri-state on FDC
03F7  R      diskette controller DIR (Digital Input Register, PS/2 mode)
         bit 7     = 1 diskette change
         bit 6-3 = 1
         bit 2         datarate select1
         bit 1         datarate select0
         bit 0     = 0 high density select (500Kb/s, 1Mb/s)

 conflicts with     bit 0       FIXED DISK drive 0 select

03F7  R      diskette controller DIR (Digital Input Register, PS/2 model 30)
         bit 7     = 0 diskette change
         bit 6-4 = 0
         bit 3         -DMA gate (value from DOR register)
         bit 2         NOPREC (value from CCR register)
         bit 1         datarate select1
         bit 0         datarate select0

 conflicts with     bit 0       FIXED DISK drive 0 select

03F7   W  configuration control register (PC/AT, PS/2)
         bit 7-2       reserved, tri-state
         bit 1-0 = 00  500 Kb/S mode (MFM)
             = 01  300 Kb/S mode (MFM)
             = 10  250 Kb/S mode (MFM)
             = 11  1   Mb/S mode (MFM) (on 82072/82077AA)

 conflicts with     bit 0       FIXED DISK drive 0 select

03F7   W  configuration control register (PS/2 model 30)
         bit 7-3       reserved, tri-state
         bit 2           NOPREC (has no function. set to 0 by hardreset)
         bit 1-0 = 00  500 Kb/S mode (MFM)
             = 01  300 Kb/S mode (MFM)
             = 10  250 Kb/S mode (MFM)
             = 11  1   Mb/S mode (MFM) (on 82072/82077AA)

 conflicts with     bit 0       FIXED DISK drive 0 select
---------------------------------------------
03F8-03FF ----    serial port (8250,8250A,8251,16450,16550,16550A,etc.) COM1
        same as 02E8, 02F8 and 03E8

         chips overview:
         8250  original PC, specified up to 56Kbd, but mostly runs
               only 9600Bd, no scratchregister, bug: sometimes shots
               ints without reasons
         8250A, 16450, 16C451: ATs, most chips run up to 115KBd,
               no bug: shots no causeless ints
         8250B: PC,XT,AT, pseudo bug: shots one causeless int for
            compatibility with 8250, runs up to 56KBd
         16550, 16550N, 16550V: early PS/2, FIFO bugs
         16550A,16550AF,16550AFN,16550C,16C551,16C552: PS/2, FIFO ok
         82510: laptops & industry, multi emulation mode
            (default=16450), special-FIFO.
         8251: completely different synchronous SIO chip, not
            compatible!

03F8   W  serial port, transmitter holding register (THR), which contains the
      character to be sent. Bit 0 is sent first.
        bit 7-0      data bits when DLAB=0 (Divisor Latch Access Bit)
03F8  R      receiver buffer register (RBR), which contains the received
      character. Bit 0 is received first
         bit 7-0   data bits when DLAB=0 (Divisor Latch Access Bit)
03F8  RW  divisor latch low byte (DLL) when DLAB=1

03F9  RW  divisor latch high byte (DLM) when DLAB=1
          some baudrates (using standard 1.8432 Mhz clock)
               baudrate       divisor     DLM  DLL
                50       2304          09h 00h
                75       1536          06h 00h
               110       1047          04h 17h
               134,5    857          03h 59h
               150        768          03h 00h
               300        384          01h 80h
               600        192          00h C0h
              1200         96          00h 60h
              1800         64          00h 40h
              2000         58          00h 3Ah
              2400         48          00h 30h
              3600         32          00h 20h
              4800         24          00h 18h
              7200         16          00h 10h
              9600         12          00h 0Ch
             19200          6          00h 06h
             38400          3          00h 03h
             57600          2          00h 02h
            115200          1          00h 01h

         MIDI baudrate 32250Bd with 4Mhz quarz for c't MIDI interface
         following c't 01/1991
            '14400'              00h 08h

03F9  RW  interrupt enable register (IER) when DLAB=0
         bits 7-4   reserved (0)
         bit 3 = 1  modem-status interrupt enable
         bit 2 = 1  receiver-line-status interrupt enable
         bit 1 = 1  transmitter-holding-register empty interrupt enable
         bit 0 = 1  received-data-available interrupt enable
                (also 16550(A) timeout interrupt)

          - 16550(A) will interrupt with a timeout if data exists in the
        FIFO and isn't read within the time it takes to receive four
        bytes or if no data is received within the time it takes to
        receive four bytes

03FA  R      interrupt identification register. Information about a pending
        interrupt is stored here. When the ID register is addressed,
        the highest priority interrupt is held, and no other interrupts
        are acknowledged until the CPU services that interrupt.
         bit 7-6 = 00  reserved on 8250, 8251, 16450
             = 01  if FIFO queues enabled but unusable (16550 only)
             = 11  if FIFO queues are enabled (16550A only)
         bit 5-4 = 0 reserved
         bit 3     = 0 reserved  8250, 16450
             = 1 16550  timeout int. pending
         bit 2-1 identify pending interrupt with the highest priority
          = 11    receiver line status interrupt. priority=highest
          = 10    received data available register interrupt. pr.=second
          = 01    transmitter holding register empty interrupt. pr.=third
          = 00    modem status interrupt. priority=fourth
         bit 0 = 0  interrupt pending. contents of register can be used
                as a pointer to the appropriate int.service routine
             1  no interrupt pending

          - interrupt pending flag uses reverse logic, 0=pending, 1=none
          - interrupt will occur if any of the line status bits are set
          - THRE bit is set when THRE register is emptied into the TSR

03FA   W  16650 FIFO Control Register (FCR)
         bit 7-6 = received data available interrupt trigger level
            00  1 byte
            01  4 bytes
            10  8 bytes
            11 14 bytes
         bit 5-4 = 00 reserved
         bit 3     = 1  change RXRDY  TXRDY pins from mode 0 to mode 1
         bit 2     = 1  clear XMIT FIFO
         bit 1     = 1  clear RCVR FIFO
         bit 0     = 1  enable clear XMIT and RCVR FIFO queues

          - bit 0 must be set in order to write to other FCR bits
          - bit 1 when set    the RCVR FIFO is cleared and this bit is reset
         the receiver shift register is not cleared
          - bit 2 when set    the XMIT FIFO is cleared and this bit is reset
         the transmit shift register is not cleared
          - due to a hardware bug, 16550 FIFOs don't work correctly (this
        was fixed in the 16550A)
03FB  RW  line control register (LCR)
         bit 7 = 1  divisor latch access bit (DLAB)
             0  receiver buffer, transmitter holding, or interrupt
                enable register access
         bit 6 = 1  set break enable. serial ouput is forced to spacing
                state and remains there.
         bit 5-3 =  PM2 PM1 PM0
                 x     x   0     = no parity
                 0     0   1     = odd parity
                 0     1   1     = even parity
                 1     0   1     = high parity (sticky)
                 1     1   1     = low parity (sticky)
                 x     x   1     = software parity
         bit 2 = stop bit length (STB/SBL)
             0  one stop bit
             1  2 stop bits with (word length 6, 7, 8)
                1.5 stop bits with word length 5
         bit 1-0 (WLS1-0, CL1-0)
             00 word length is 5 bits
             01 word length is 6 bits
             10 word length is 7 bits
             11 word length is 8 bits
03FC  RW  modem control register
         bit 7-5 = 0  reserved
         bit 4 = 1  loopback mode for diagnostic testing of serial port
                output of transmitter shift register is looped back
                to receiver shift register input. In this mode
                transmitted data is received immediately so that
                the CPU can verify the transmit data/receive data
                serial port paths.
                If OUT2 is disabled, there is no officially
                way to generate an IRQ during loopback mode.
         bit 3 = 1  auxiliary user-designated output 2 (OUT2)
                because of external circuity OUT2 must be 1 to
                master-intr-enableing. Bug: Some Toshiba Laptops
                utilize this bit vice versa, newer Toshiba machines
                allow to assign the bits polarity in system setup.
                82050: This bit is only effective, if the chip is
                being used with an externally generated clock.
         bit 2 = 1/0  auxiliary user-designated output 1 (OUT1)
                should generally be cleared!!
                Some external hardware, e.g. c't MIDI interface
                (and compatibles) uses this bit to change the 8250
                input clock from 1,8432 MHz to 4Mhz (enableing
                MIDI conform baudrates) and switching to MIDI
                compatible current loop connectors.
         bit 1 = 1  force request-to-send active (RTS)
         bit 0 = 1  force data-terminal-ready active (DTR)
03FD  R      line status register
         bit 7 = 0  reserved
               = 1  on some chips produced by UMC
         bit 6 = 1  transmitter shift and holding registers empty
         bit 5 = 1  transmitter holding register empty (THRE)
            Controller is ready to accept a new character to send.
         bit 4 = 1  break interrupt. the received data input is held in
                in the zero bit state longer than the time of start
                bit + data bits + parity bit + stop bits.
         bit 3 = 1  framing error (FE). the stop bit that follows the
                last parity or data bit is a zero bit.
         bit 2 = 1  parity error (PE). Character has wrong parity
         bit 1 = 1  overrun error (OE). a character was sent to the
                receiver buffer before the previous character in
                the buffer could be read. This destroys the
                previous character.
         bit 0 = 1  data ready. a complete incoming character has been
                received and sent to the receiver buffer register.
03FE  R      modem status register (MSR)
         bit 7 = 1  data carrier detect (-DCD)
         bit 6 = 1  ring indicator (-RI)
         bit 5 = 1  data set ready (-DSR)
         bit 4 = 1  clear to send (-CTS)
         bit 3 = 1  delta data carrier detect (DDCD)
         bit 2 = 1  trailing edge ring indicator (TERI)
         bit 1 = 1  delta data set ready (DDSR)
         bit 0 = 1  delta clear to send (DCTS)

          - bits 0-3 are reset when the CPU reads the MSR
          - bit 4 is the Modem Control Register RTS during loopback test
          - bit 5 is the Modem Control Register DTR during loopback test
          - bit 6 is the Modem Control Register OUT1 during loopback test
          - bit 7 is the Modem Control Register OUT2 during loopback test
03FF  RW  scratch register (SCR)
        (not used for serial I/O; available to any application using
        16450,16550) (not present on original 8250)
---------------------------------------------

    Adresses above 03FF generally apply to EISA machines only !

         1000-1FFF    slot 1 EISA
         2000-2FFF    slot 2 EISA
         3000-3FFF    slot 3 EISA
         4000-4FFF    slot 4 EISA
         5000-5FFF    slot 5 EISA
         6000-6FFF    slot 6 EISA
         7000-7FFF    slot 7 EISA
---------------------------------------------
0401-04D6 ----    used by EISA systems only

0401  RW  DMA channel 0 word count byte 2 (high)
0403  RW  DMA channel 1 word count byte 2 (high)
0405  RW  DMA channel 2 word count byte 2 (high)
0407  RW  DMA channel 3 word count byte 2 (high)

040A   W  extended DMA chaining mode register, channels 0-3
         bit 7-5      reserved
         bit 4     = 0  generates IRQ13
             = 1  generates terminal count
         bit 3     = 0  do not start chaining
             = 1  programming complete
         bit 2     = 0  disable buffer chaining mode (default)
             = 1  enable buffer chaining mode
         bit 1-0      DMA channel select

040A  R      channel interrupt (IRQ13) status register
         bit 7-5  interrupt on channels 7-5
         bit 4      reserved
         bit 3-0  interrupt on channels 3-0

040B   W  DMA extended mode register for channels 3-0.
        bit settings same as 04D6
         bit 7     = 0  enable stop register
         bit 6     = 0  terminal count is an output for this channel
                (default)
         bit 5-4      DMA cycle timing
             = 00 ISA-compatible (default)
             = 01 type A timing mode
             = 10 type B timing mode
             = 11 burst DMA mode
         bit 3-2      Address mode
             = 00 8-bit I/O, count by bytes (default)
             = 01 16-bit I/O, count by words, address shifted
             = 10 32-bit I/O, count by bytes
             = 11 16-bit I/O, count by bytes
         bit 1-0      DMA channel select
---------------------------------------------
0461-0462 ----    NMI CONTROL

0461  RW  Extended NMI status/control register
         bit 7 = 1  NMI pending from fail-safe timer (read only)
         bit 6 = 1  NMI pending from bus timeout NMI status (read only)
         bit 5 = 1  NMI pending (read only)
         bit 4        reserved
         bit 3 = 1  bus timeout NMI enable (read/write)
         bit 2 = 1  fail-safe NMI enable (read/write)
         bit 1 = 1  NMI I/O port enable (read/write)
         bit 0        RSTDRV. bus reset (read/write)
               = 0  NORMAL bus reset operation
               = 1  reset bus asserted

0462   W  Software NMI register. writing to this register causes an NMI
        if NMI's are enabled
         bit 7 = 1  generates an NMI
---------------------------------------------
0464-0465 ----    EISA BUS MASTER STATUS

0464  R      bus master status latch register (slots 1-8). identifies the
        last bus master that had control of the bus
         bit 7 = 0  slot 8 had control last
         bit 6 = 0  slot 7 had control last
         bit 5 = 0  slot 6 had control last
         bit 4 = 0  slot 5 had control last
         bit 3 = 0  slot 4 had control last
         bit 2 = 0  slot 3 had control last
         bit 1 = 0  slot 2 had control last
         bit 0 = 0  slot 1 had control last

0465  R      bus master status latch register (slots 9-16)
         bit 7 = 0  slot 16 had control last
         bit 6 = 0  slot 15 had control last
         bit 5 = 0  slot 14 had control last
         bit 4 = 0  slot 13 had control last
         bit 3 = 0  slot 12 had control last
         bit 2 = 0  slot 11 had control last
         bit 1 = 0  slot 10 had control last
         bit 0 = 0  slot 9  had control last
---------------------------------------------
0481-048B ---- EISA DMA page registers

0481  RW  DMA channel 2 address byte 3 (high)
0482  RW  DMA channel 3 address byte 3 (high)
0483  RW  DMA channel 1 address byte 3 (high)
0487  RW  DMA channel 0 address byte 3 (high)
0489  RW  DMA channel 6 address byte 3 (high)
048A  RW  DMA channel 7 address byte 3 (high)
048B  RW  DMA channel 5 address byte 3 (high)
---------------------------------------------
04C6-04CF ---- EISA DMA count registers

04C6  RW  DMA channel 5 word count byte 2 (high)
04CA  RW  DMA channel 6 word count byte 2 (high)
04CE  RW  DMA channel 7 word count byte 2 (high)
---------------------------------------------
04D0-04D1 ---- EISA IRQ control

04D0   W  IRQ 0-7 interrupt edge/level registers
         bit 7 = 1  IRQ 7 is level sensitive
         bit 6 = 1  IRQ 6 is level sensitive
         bit 5 = 1  IRQ 5 is level sensitive
         bit 4 = 1  IRQ 4 is level sensitive
         bit 3 = 1  IRQ 3 is level sensitive
         bit 2-0    reserved

04D1   W  IRQ 8-15 interrupt edge/level registers
         bit 7 = 1  IRQ 15 is level sensitive
         bit 6 = 1  IRQ 14 is level sensitive
         bit 5 = 1  reserved
         bit 4 = 1  IRQ 12 is level sensitive
         bit 3 = 1  IRQ 11 is level sensitive
         bit 2 = 1  IRQ 10 is level sensitive
         bit 1 = 1  IRQ 9  is level sensitive
         bit 0        reserved
---------------------------------------------
04D4-04D6 ---- EISA DMA control

04D4  R      DMA chaining status

04D4   W  extended DMA chaining mode register, channels 4-7
         bit 7-5 = 0  reserved
         bit 4     = 0  generates IRQ 13
             = 1  generates terminal count
         bit 3     = 0  do not start chaining
             = 1  programming complete
         bit 2     = 0  disable buffer chaining mode (default)
             = 1  enable buffer chaining mode
         bit 1-0      DMA channel select

04D6   W  DMA extended mode register for channels 4-7
        bit settings same as 04B
         bit 7     = 0  enable stop register
         bit 6     = 0  terminal count is an output for this channel
                (default)
         bit 5-4      DMA cycle timing
             = 00 ISA-compatible (default)
             = 01 type A timing mode
             = 10 type B timing mode
             = 11 burst DMA mode
         bit 3-2      Address mode
             = 00 8-bit I/O, count by bytes (default)
             = 01 16-bit I/O, count by words, address shifted
             = 10 32-bit I/O, count by bytes
             = 11 16-bit I/O, count by bytes
         bit 1-0      DMA channel select
---------------------------------------------
04E0-04FF ---- EISA DMA stop registers

04E0-04E2  RW    channel 0
04E4-04E6  RW    channel 1
04E8-04EA  RW    channel 2
04EC-04EE  RW    channel 3
04F4-04F6  RW    channel 5
04F8-04FA  RW    channel 6
04FC-04FE  RW    channel 7
---------------------------------------------
0530-0533 ----    Gravis Ultra Sound Daughter Card by Advanced Gravis
Range:    dipswitch selectable from 0530-0533, 0604-0607, 0E80-0E83, and
      0F40-0F43

0530  RW  address select
0531  RW  data
0532  RW  status
0533  RW  PIO
---------------------------------------------
0601      ----    Headland HL21, Acer M5105 chipsets - SYSTEM CONTROL

0601   W  system control
        bit 7 = 1  power led on
        bit 6 = 1  LCD backlight off
        bit 5
        bit 4
        bit 3
        bit 2 = 1  video chips disabled, screen blanked.
        bit 1
        bit 0 = 1  will lock up your machine!
0601  R      status
        bit 7 = 0  if screen enabled always these values
        bit 6 = 0
        bit 5 = 0
        bit 4 = 0
        bit 3 = 0
        bit 2 = 1  (=0 at low power)
        bit 1 = 0  power OK
        bit 0 = 0
---------------------------------------------
0620-0627 ----    PC network (adapter 1)
0628-062F ----    PC network (adapter 2)
---------------------------------------------
0680-0681 ----    Microchannel POST Diagnostic (write only)

0680   W  Microchannel POST Diagnostic (write only)
0681   W  secondary MCA POST diagnostic
---------------------------------------------
06A0-06A8  ----    non-standard COM port addresses (V20-XT by German magazine c't)
06A8-06AF    selectable from 0280, 0288, 0290, 0298, 06A0, 06A8
---------------------------------------------
06E2-06E3 ----    data aquisition (adapter 1)
---------------------------------------------
06E8      ----    S3 86C928 video controller (ELSA Winner 1000)
---------------------------------------------
06E8-06EF ----    8514/A and compatible video cards (e.g. ATI Graphics Ultra)
SeeAlso: 02E8-02EF, 0AE8, 96E8, 9AE8

06E8   W  CRT control: horizontal displayed
---------------------------------------------
0746      ----    Gravis Ultra Sound by Advanced Gravis
SeeAlso: 0240-024F, 0340-034F

0746  R      board version (rev 3.7+)
         FF      Pre 3.6 boards, ICS mixer NOT present
         05      Rev 3.7 with ICS Mixer. Some R/L: flip problems.
         06-09      Revision 3.7 and above. ICS Mixer present
         0A-      UltraMax. CS4231 present, no ICS mixer
0746   W  Mixer Control Port
---------------------------------------------
0790-0793 ----    cluster (adapter 1)
---------------------------------------------
0800-08FF ----    I/O port access registers for extended CMOS RAM or SRAM
        (256 bytes at a time)
        Sometimes plain text can be seen here.
---------------------------------------------
0800-08FF ----    reserved for EISA system motherboard
---------------------------------------------
0A20-0A23 ----    Token Ring (adapter 1)
0A24-0A27 ----    Token Ring (adapter 2)
---------------------------------------------
0AE2-0AE3 ----    cluster (adapter 2)
---------------------------------------------
0AE8      ----    S3 86C928 video controller (ELSA Winner 1000)
---------------------------------------------
0AE8-0AEF ----    8514/A and compatible video cards (e.g. ATI Graphics Ultra)

0AE8   W  CRT control: horizontal sync start
---------------------------------------------
0B90-0B93 ----    cluster (adapter 2)
---------------------------------------------
0C00      ----    EISA??? - PAGE REGISTER

0C00  RW  page register to write to SRAM or I/O
---------------------------------------------
0C00-0CFF ----    reserved for EISA system motherboard
---------------------------------------------
0C7C        bit 7-4 (Compaq)
---------------------------------------------
0C80-0C83 ----    EISA system board ID registers
---------------------------------------------
0CF8      ----    Intel Pentium motherboard ("Neptune" chipset)

        SeeAlso: C008
---------------------------------------------
0CFA      ----    Intel Pentium motherboard ("Neptune" chipset)

        SeeAlso: C008
---------------------------------------------
0EE8      ----    S3 86C928 video controller (ELSA Winner 1000)
---------------------------------------------
0EE8-0EEF ----    8514/A and compatible video cards (e.g. ATI Graphics Ultra)

0EE8   W  CRT control: horizontal sync width
---------------------------------------------
1000-10FF ----    available for EISA slot 1
---------------------------------------------
12E8-12EF ----    8514/A and compatible video cards (e.g. ATI Graphics Ultra)

12E8   W  CRT control: vertical total
---------------------------------------------
1390-1393 ----    cluster (adapter 3)
---------------------------------------------
1400-14FF ----    available for EISA slot 1
---------------------------------------------
16E8-16EF ----    8514/A and compatible video cards (e.g. ATI Graphics Ultra)

16E8   W  CRT control: vertical displayed
---------------------------------------------
1800-18FF ----    available for EISA slot 1
---------------------------------------------
1AE8-1AEF ----    8514/A and compatible video cards (e.g. ATI Graphics Ultra)

1AE8   W  CRT cotnrol: vertical sync start
---------------------------------------------
1C00-1CFF ----    available for EISA slot 1
---------------------------------------------
1C65      ----    Compaq Contura Aero
SeeAlso: 2065

1C65  R?  bit 6: operating on battery power
---------------------------------------------
1C80-1C8F ----    VESA XGA Video in EISA slot 1

1C80-1C83  RW    EISA Video ID
1C84  RW    EISA Video expansion board control
1C85  RW    EISA Setup control
1C88  RW    EISA Video Programmable Option Select 0
1C89-1C8F  RW    EISA Video Programmable Option Select 1-7
---------------------------------------------
1C80-1C83    EISA board product ID (board in slot 1)
---------------------------------------------
1C85        Compaq Qvision EISA - Virtual Controller ID
---------------------------------------------
1EE8-1EEF ----    8514/A and compatible video cards (e.g. ATI Graphics Ultra)

1EE8   W  CRT control: vertical sync width
---------------------------------------------
2000-20FF ----    available for EISA slot 2
---------------------------------------------
2065      ----    Compaq Contura Aero
SeeAlso: 1C65, 2465

2065   W  ??? (84h seen)
---------------------------------------------
2100      ----    XGA Video Operating Mode Register
Note:    this port is for the first XGA in the system; 2110-2170 are used for
      the second through eighth XGAs
---------------------------------------------
2101      ----    XGA VIdeo Aperture Control
Note:    this port is for the first XGA in the system; 2111-2171 are used for
      the second through eighth XGAs
---------------------------------------------
2102-2103 ----    XGA ???
Note:    this port is for the first XGA in the system; 211x-217x are used for
      the second through eighth XGAs
---------------------------------------------
2104      ----    XGA Video Interrupt Enable
Note:    this port is for the first XGA in the system; 211x-217x are used for
      the second through eighth XGAs
---------------------------------------------
2105      ----    XGA Video Interrupt Status
Note:    this port is for the first XGA in the system; 211x-217x are used for
      the second through eighth XGAs
---------------------------------------------
2106      ----    XGA Video Virtual Memory Control
Note:    this port is for the first XGA in the system; 211x-217x are used for
      the second through eighth XGAs
---------------------------------------------
2107      ----    XGA Video Virtual Memory Interrupt Status
Note:    this port is for the first XGA in the system; 211x-217x are used for
      the second through eighth XGAs
---------------------------------------------
2108      ----    XGA Video Aperture Index
Note:    this port is for the first XGA in the system; 211x-217x are used for
      the second through eighth XGAs
---------------------------------------------
2109      ----    XGA Video Memory Access Mode
Note:    this port is for the first XGA in the system; 211x-217x are used for
      the second through eighth XGAs
---------------------------------------------
210A      ----    XGA Video Index for Data
Note:    this port is for the first XGA in the system; 211x-217x are used for
      the second through eighth XGAs
---------------------------------------------
210B      ----    XGA Video Data (byte)
Note:    this port is for the first XGA in the system; 211x-217x are used for
      the second through eighth XGAs
---------------------------------------------
210C-210F ----    XGA Video Data (word/dword)
Note:    this port is for the first XGA in the system; 211x-217x are used for
      the second through eighth XGAs
---------------------------------------------
2110-211F ----    IBM XGA (eXtended Graphics Adapter  8514/A) (second installed)
2120-212F ----    IBM XGA (eXtended Graphics Adapter  8514/A) (third installed)
2130-213F ----    IBM XGA (eXtended Graphics Adapter  8514/A) (fourth installed)
2140-214F ----    IBM XGA (eXtended Graphics Adapter  8514/A) (fifth installed)
2150-215F ----    IBM XGA (eXtended Graphics Adapter  8514/A) (sixth installed)
2160-216F ----    IBM XGA (eXtended Graphics Adapter  8514/A) (seventh installed)
2170-217F ----    IBM XGA (eXtended Graphics Adapter  8514/A) (eighth installed)

Notes:    see individual 210x entries above
    c't says default instance number is 6, i.e. addresses 216x
---------------------------------------------
217A-217B ---- ET4000/W32 CRTC-B/Sprite
        Alternative addresses may depend on adapter manufacturer,
        Tseng claims 21xA with x=three address bits, selected by
        IOD2..0 during power up reset.

21xA  RW  ET4000/W32(i) CRTC-B/Sprite index register
           bit7-0: index
21xB  RW  ET4000/W32(i) CRTC-B/Sprite data register
         indexed registers:
          E0h CRTC-B / Sprite Horizontal Pixel Position, Low
           bit7-0: horizontal pixel position bit7-0
          E1h CRTC-B / Sprite Horizontal Pixel Position, High
           bit7-4: reserved
           bit3-0: horizontal pixel position bit11-8
          E2h CRTC-B Width Low / Sprite Horizontal Preset
           bit7-0: width of CRTC-B bit7-0
           bit5-0: horizontal preset for sprite
          E3h CRTC-B Width High / Sprite Horizontal Preset
           bit7-4: reserved
           bit3-0: width of CRTC-B bit11-8
          E4h CRTC-B / Sprite Vertical Pixel Position, Low
           bit7-0: vertical pixel position bit7-0
          E5h CRTC-B / Sprite Vertical Pixel Position, High
           bit7-4: reserved
           bit3-0: vertical pixel position bit11-8
          E6h CRTC-B Height Low / Sprite Vertical Preset
           bit7-0: height of CRTC-B bit7-0
           bit5-0: vertical preset for sprite
          E7h CRTC-B Height High / Sprite Vertical Preset
           bit7-4: reserved
           bit3-0: height of CRTC-B bit11-8
          E8h CRTC-B / Sprite Starting Address Low
           pointer to CRTC-B / sprite image in display memory.
           (maximum size of sprites 64x64x4=1KB with 4 colors:
            00b=color-0, 01b=color-255, 10b=transparent, 11b=reserved)
           bit7-0: startaddress bit7-0
          E9h CRTC-B / Sprite Starting Address Middle
           bit7-0: startaddress bit15-8
          EAh CRTC-B / Sprite Starting Address High
           bit7-4: reserved
           bit3-0: startaddress bit19-16
          EBh CRTC-B / Sprite Row Offset Low
           bit7-0: offset bit7-0
          ECh CRTC-B / Sprite Row Offset High
           bit7-4: revision ID (any ET4000/W32)
                0000b=W32         0100b-1111b reserved
                0001b=W32i
                0010b=W32p
                0011b=W32i, new
           bit3-0: offset bit11-8
          EDh CRTC-B Pixel Panning
           bit7-3: reserved
           bit2-0: CRTC-B pixel panning
          EEh CRTC-B Color-Depth-Register / Hardware-Zoom
           bit7-4: reserved (concerning databook ET4000/W32)
           bit7-6: vertical zoom (undocumented)
               (original ET4000/W32 ok, doesn't work properly
                with some ET4000/W32i)
                00b=zoomx1       10b=zoomx3
                01b=zoomx2       11b=zoomx4
           bit5-4: horizontal zoom (undocumented)
               (original ET4000/W32 ok, doesn't work properly
                with some ET4000/W32i)
                00b=zoomx1       10b=zoomx3
                01b=zoomx2       11b=zoomx4
           bit3-0: bit/pixel
                0000b=1       0011b=8
                0001b=2       0100b=16
                0010b=4
          EFh CRTC-B / Sprite Control
           bit7-2: reserved
           bit1     : 1=2nd CRTC-B image overlays main CRTC-A image
               0=CRTC-B image at pin SP1/0
           bit0     : 1=enable CRTC-B
               0=enable sprite (see F7h)
          F7h Image Port Control
           bit7     : 1=CRTC-B or sprite active
               0=CRTC-B and sprite not active
           bit6-0: reserved
---------------------------------------------
22E8-22EF ----    8514/A and compatible video cards (e.g. ATI Graphics Ultra)

22E8   W  CRT control: display control
---------------------------------------------
2390-2393 ----    cluster (adapter 4)
---------------------------------------------
23C0-23CF ----    Compaq QVision - BitBLT engine
---------------------------------------------
2400-24FF ----    available for EISA slot 2
---------------------------------------------
2465      ----    Compaq Contura Aero
SeeAlso: 1C65, 2065

2465  R      current battery power level
        (166 fully-charged, 130 = LowBat1)
---------------------------------------------
27C6      ----    Compaq LTE Lite - LCD TIMEOUT

27C6  RW  LCD timeout in minutes
---------------------------------------------
2800-28FF ----    available for EISA slot 2
---------------------------------------------
28E9      ----    8514/A - WD Escape Functions
---------------------------------------------
2C80-2C8F ----    VESA XGA Video in EISA slot 2 (see 1C80-1C8F)
---------------------------------------------
2C80-2C83 ----    EISA board product ID (board in slot 2)
---------------------------------------------
3000-30FF ----    available for EISA slot 3
---------------------------------------------
3220-3227 ----    serial port 3, description same as 03F8
3228-322F ----    serial port 4, description same as 03F8
---------------------------------------------
33C0-33CF ----    Compaq QVision - BitBLT engine
---------------------------------------------
3400-34FF ----    available for EISA slot 3
---------------------------------------------
3510-3513 ----    ESDI primary harddisk controller

3510  R      status word
3510   W  command word
3512  R      basic status
3512   W  basic control
3513  R      interrupt status
3513   W  attention
---------------------------------------------
3518-351B ----    ESDI secondary harddisk controller

3518  R      status word
3518   W  command word
351A  R      basis status
351A   W  basic control
351B  R      interrupt status
351B   W  attention
---------------------------------------------
3540-354F ----    IBM SCSI (Small Computer System Interface) adapter
3550-355F ----    IBM SCSI (Small Computer System Interface) adapter
3560-356F ----    IBM SCSI (Small Computer System Interface) adapter
3570-357F ----    IBM SCSI (Small Computer System Interface) adapter
---------------------------------------------
3800-38FF ----    available for EISA slot 3
---------------------------------------------
3C00-3CFF ----    available for EISA slot 3
---------------------------------------------
3C80-3C8F ----    VESA XGA Video in EISA slot 3

3C80-3C83  RW    EISA Video ID
3C84  RW    EISA Video expansion board control
3C85  RW    EISA Setup control
3C88  RW    EISA Video Programmable Option Select 0
3C89-3C8F  RW    EISA Video Programmable Option Select 1-7

SeeAlso: 1C80-1C8F,2C80-2C8F,7C80-7C8F
---------------------------------------------
3C80-3C83 ----    EISA board product ID (board in slot 3)
---------------------------------------------
4000-40FF ----    available for EISA slot 4
---------------------------------------------
4220-4227 ----    serial port, description same as 03F8
4228-422F ----    serial port, description same as 03F8
---------------------------------------------
42E0-42EF ----    GPIB (General Purpose Interface Bus, IEEE 488 interface)

42E1  RW  GPIB (adapter 2)
---------------------------------------------
42E8      ----    8514/A and hardware-compatible video cards

42E8  R      Misc. control: Subsystem Status
42E8   W  Misc. control: Subsystem Control
---------------------------------------------
4400-44FF ----    available for EISA slot 4
---------------------------------------------
46E8      ----    VGA video adapter enable
Note:    IBM uses this port for adapter-card VGAs only, and port 03C3 for
      motherboard VGA only (see 03C3 for details)
SeeAlso: 03C3

46E8  rW  Misc. control: enable flags / select ROM page (8514/A)
        bits 7-5 unused or vendor-specific
        bit 4: setup for POS registers (MCA)
        bit 3: enable video I/O ports and video buffer
        bits 2-0 unused or vendor-specific
---------------------------------------------
46E8      ----    8514/A and compatible video cards (e.g. ATI Graphics Ultra)

46E8   W  ROM page select
---------------------------------------------
4800-48FF ----    available for EISA slot 4
---------------------------------------------
4AE8-4AEF ----    8514/A and compatible video cards (e.g. ATI Graphics Ultra)

4AE8   W  CRT control: Advanced function control
        (02h = VGA mode, 03h = 480-line mode, 07h = 768-line mode)
---------------------------------------------
4C00-4CFF ----    available for EISA slot 4
---------------------------------------------
4C80-4C83    EISA board product ID (board in slot 4)
---------------------------------------------
4C80-4C8F ----    VESA XGA Video in EISA slot 4 (see 3C80-3C8F)

SeeAlso: 1C80-1C8F,6C80-6C8F
---------------------------------------------
5000-50FF ----    available for EISA slot 5
---------------------------------------------
5220-5227 ----    serial port, description same as 03F8
5228-522F ----    serial port, description same as 03F8
---------------------------------------------
5400-54FF ----    available for EISA slot 5
---------------------------------------------
5800-58FF ----    available for EISA slot 5
---------------------------------------------
5C00-5CFF ----    available for EISA slot 5
---------------------------------------------
5C80-5C8F ----    VESA XGA Video in EISA slot 5
SeeAlso: 2C80-2C8F,4C80-4C8F,6C80-6C8F

5C80-5C83 r/w    EISA Video ID
5C84  RW    EISA Video expansion board control
5C85  RW    EISA Setup control
5C88  RW    EISA Video Programmable Option Select 0
5C89-5C8F r/w    EISA Video Programmable Option Select 1-7
---------------------------------------------
5C80-5C83    EISA board product ID (board in slot 5)
---------------------------------------------
6000-60FF ----    available for EISA slot 6
---------------------------------------------
62E0-62EF ----    GPIB (General Purpose Interface Bus, IEEE 488 interface)

62E1  RW  GPIB (adapter 3)
---------------------------------------------
63C0-63CF ----    Compaq QVision - BitBLT engine
---------------------------------------------
6400-64FF ----    available for EISA slot 6
---------------------------------------------
6800-68FF ----    available for EISA slot 6
---------------------------------------------
6C00-6CFF ----    available for EISA slot 6
---------------------------------------------
6C80-6C83 ----    EISA board product ID (board in slot 6)
---------------------------------------------
6C80-6C8F ----    VESA XGA Video in EISA slot 1
SeeAlso: 1C80-1C8F,2C80-2C8F,5C80-5C8F

6C80-6C83 r/w    EISA Video ID
6C84  RW  EISA Video expansion board control
6C85  RW  EISA Setup control
6C88  RW  EISA Video Programmable Option Select 0
6C89-1C8F r/w    EISA Video Programmable Option Select 1-7
---------------------------------------------
7000-70FF ----    available for EISA slot 7
---------------------------------------------
7400-74FF ----    available for EISA slot 7
---------------------------------------------
7800-78FF ----    available for EISA slot 7
---------------------------------------------
7C00-7CFF ----    available for EISA slot 7
---------------------------------------------
7C80-7C83 ----    EISA board product ID (board in slot 7)
---------------------------------------------
7C80-7C8F ----    VESA XGA Video in EISA slot 7
SeeAlso: 1C80-1C8F, 6C80-6C8F

7C80-7C83  RW    EISA Video ID
7C84  RW    EISA Video expansion board control
7C85  RW    EISA Setup control
7C88  RW    EISA Video Programmable Option Select 0
7C89-7C8F  RW    EISA Video Programmable Option Select 1-7
---------------------------------------------
8000-80FF ----    available for EISA slot 8
---------------------------------------------
82E0-82EF ----    GPIB (General Purpose Interface Bus, IEEE 488 interface)

82E1  RW  GPIB (adapter 4)
---------------------------------------------
82E8-82EF ----    8514/A and compatible video cards (e.g. ATI Graphics Ultra)

82E8   W  drawing control: current Y position
---------------------------------------------
82F8-82FF ----    serial port, description same as 03F8
83F8-83FF ----    serial port, description same as 03F8
---------------------------------------------
83C0-83CF ----    Compaq QVision - Line Draw Engine
---------------------------------------------
83C4      ----    Compaq Qvision EISA - Virtual Controller Select
---------------------------------------------
83C6-83C9 ----    Compaq Qvision EISA - DAC color registers
---------------------------------------------
8400-84FF ----    available for EISA slot 8
---------------------------------------------
86E8-86EF ----    8514/A and compatible video cards (e.g. ATI Graphics Ultra)

86E8   W  drawing control: current X position
---------------------------------------------
8800-88FF ----    available for EISA slot 8
---------------------------------------------
8AE8-8AEF ----    8514/A and compatible video cards (e.g. ATI Graphics Ultra)

8AE8   W  drawing control: destination Y position / axial step constant
---------------------------------------------
8C00-8CFF ----    available for EISA slot 8
---------------------------------------------
8C80-8C83 ----    EISA board product ID (board in slot 8)
---------------------------------------------
8EE8-8EEF ----    8514/A and compatible video cards (e.g. ATI Graphics Ultra)

8EE8   W  drawing control: destination X position / axial step constant
---------------------------------------------
9000-90FF ----    available for EISA slot 9
---------------------------------------------
92E8-92EF ----    8514/A and compatible video cards (e.g. ATI Graphics Ultra)

92E8   W  drawing control: error term
---------------------------------------------
9400-94FF ----    available for EISA slot 9
---------------------------------------------
96E8-96EF ----    8514/A and hardware-compatible video cards

96E8  R      enter WD Enhanced Mode
96E8   W  drawing control: major axis pixel count
---------------------------------------------
9800-98FF ----    available for EISA slot 9
---------------------------------------------
9AE8-9AE9 ----    8514/A Graphics Processor Status

9AE8w R      drawing control: graphic processor status
         bit15-10: reserved
         bit9 =1 : hardware busy
         bit8 =1 : data ready
         bit7-0     : status of queue (0=empty, 1=filled)
               (each bit represents a position in queue)
9AE8w  W  drawing control: command register
         bit15-13: command
               000b = no operation
               001b = draw vector
               010b = fast rectangle fill
               011b = rectangle fill vertical #1
               100b = rectangle fill vertical #2 (4 pixels)
               101b = draw vector, 1 pixel/scanline
               110b = copy rectangle
               111b = reserved
         bit12     : 0=high byte first, 1=low byte first (BYTSEQ)
         bit11-10: reserved
         bit9  =1: enable 16bit write access (16BIT)
         bit8     : 0=use 8514/A data, 1=pixel data trans reg (PCDATA)
         bit7     : 0=draw vector above, 1=draw vector below (INC_Y)
         bit6     : 0=x is maj. axis, 1=y is maj. axis (YMAJAXIS)
         bit5     : 0=draw vector left, 1=draw vector right (INC_X)
         bit4     : 0=move only, 1=draw and move (DRAW)
         bit3     : 0=Bresenham line, 1=direct vector (LINETYPE)
         bit2     : 0=draw last pixel, 1=don't draw last pixel (LASTPIX)
         bit1     : 0=single pixel, 1=4pixel (PLANAR)
         bit0     : 0=read data, 1=write data (RD/WR)
---------------------------------------------
9C00-9CFF ----    available for EISA slot 9
---------------------------------------------
9C80-9C83 ----    EISA board product ID (board in slot 9)
---------------------------------------------
9EE8      ----    8514/A and compatible video cards (e.g. ATI Graphics Ultra)

9EE8   W  short line vector transfer
---------------------------------------------
A220      ----    soundblaster support in AMI Hi-Flex BIOS  ????
---------------------------------------------
A2E0-A2EF ----    GPIB (General Purpose Interface Bus, IEEE 488 interface)

A2E1  RW  GPIB (adapter 5)
---------------------------------------------
A2E8-A2EF ----    8514/A and compatible video cards (e.g. ATI Graphics Ultra)

A2E8   W  drawing control: background color
---------------------------------------------
A6E8-A6EF ----    8514/A and compatible video cards (e.g. ATI Graphics Ultra)

A6E8   W  drawing control: foreground color
---------------------------------------------
AAE8-AAEF ----    8514/A and compatible video cards (e.g. ATI Graphics Ultra)

AAE8   W  drawing control: write mask
---------------------------------------------
AEE8-AEEF ----    8514/A and compatible video cards (e.g. ATI Graphics Ultra)

AEE8   W  drawing control: read mask
---------------------------------------------
AFFF      ----    VIDEO REGISTER

AFFF  RW  plane 0-3 system latch (video register)
---------------------------------------------
B220-B227 ----    serial port, description same as 03F8
B228-B22F ----    serial port, description same as 03F8
---------------------------------------------
B2E8-B2EF ----    8514/A and compatible video cards (e.g. ATI Graphics Ultra)

B2E8   W  drawing control: color compare
---------------------------------------------
B6E8-B6EF ----    8514/A and compatible video cards (e.g. ATI Graphics Ultra)

B6E8   W  drawing control: background mix
---------------------------------------------
BAE8-BAEF ----    8514/A and compatible video cards (e.g. ATI Graphics Ultra)

BAE8   W  drawing control: foreground mix
---------------------------------------------
BEE8-BEEF ----    8514/A and compatible video cards (e.g. ATI Graphics Ultra)

BEE8   W  drawing control: multi-function control
---------------------------------------------
C000-C004 ----    Intel Pentium motherboard ("Neptune" chipset)
---------------------------------------------
C008      ----    Intel Pentium motherboard ("Neptune" chipset)

        SeeAlso: 0CF8,0CFA
---------------------------------------------
C050      ----    Intel Pentium motherboard ("Neptune" chipset)

C050  RW  bit 2: ???
---------------------------------------------
C052      ----    Intel Pentium motherboard ("Neptune" chipset)
SeeAlso: 0CF8,0CFA

C052  R?  bits 6,7: ???
---------------------------------------------
C059      ----    Intel Pentium motherboard ("Neptune" chipset)
---------------------------------------------
C065      ----    Intel "Neptune" chipset - MEMORY SIZE???
SeeAlso: INT 15/AX=DA88h

C065  R      system memory in MB??? (10h on a 16MB machine)
---------------------------------------------
C200-C204 ----    Intel Pentium motherboard ("Neptune" chipset)
---------------------------------------------
C220-C227 ----    serial port, description same as 03F8
C228-C22F ----    serial port, description same as 03F8
---------------------------------------------
C244      ----    Intel Pentium motherboard ("Neptune" chipset)
---------------------------------------------
C2E0-C2EF ----    GPIB (General Purpose Interface Bus, IEEE 488 interface)

C2E1  RW  GPIB (adapter 6)
---------------------------------------------
D220-D227 ----    serial port, description same as 03F8
D228-D22F ----    serial port, description same as 03F8
---------------------------------------------
E2E0-E2EF ----    GPIB (General Purpose Interface Bus, IEEE 488 interface)

E2E1  RW  GPIB (adapter 7)
---------------------------------------------
E2E8-E2EF ----    8514/A and compatible video cards (e.g. ATI Graphics Ultra)

E2E8   W  drawing control: pixel data transfer
---------------------------------------------

MEMORY-MAPPED ADDRESSES
---------------------------------------------
80C00000  Compaq Deskpro 386 system memory board register

80C00000  R   Diagnostics register
        bit 7    = 0  memory expansion board is installed
        bit 6    = 0  second 1 MB of system memory board is installed
        bit 5-4 = 00 base memory set to 640 KB
              01 invalid
              10 base memory set to 512 KB
              11 base memory set to 256 KB
        bit 3    = 0  parity error in byte 3
        bit 2    = 0  parity error in byte 2
        bit 1    = 0  parity error in byte 1
        bit 0    = 0  parity error in byte 0 (in 32-bit double word)

80C00000   W  RAM relocation register
        bit 7-2       Reserved, always write 1's.
        bit 1 = 0  Write-protect 128-Kbyte RAM at FE0000.
              = 1  Do not write-protect RAM at FE0000.
        bit 0 = 0  Relocate 128-Kbyte block at FE0000 to address 0E0000
              = 1  128-Kbyte RAM is addressed only at FE0000.
---------------------------------------------
C0000000-C000FFFF    Weitek "Abacus" math coprocessor
---------------------------------------------

--------!----CREDITS-------------------------
Chuck Proctor        <[e-mail]>
Richard W. Watson    <[e-mail]>
Matthias Paul        <[e-mail]>

[Some of the information in this list was extracted from Frank van Gilluwe's
_The_Undocumented_PC_, a must-have book for anyone programming down to the
"bare metal" of a PC.]

[Some of the information in this list from the shareware version of Dave
Williams' DOSREF, v3.0]

[8514/A hardware ports found in FractInt v18.0 source file FR8514A.ASM]

[Compaq QVision info from the _COMPAQ_QVision_Graphics_System_Technical_
_Reference_Guide_, second edition (October 1993).  Compaq part number
073A/0693.  Much more to come!]

[AMI keyboard controller port 0064 commands from the American Megatrends, Inc.
_Version_KF_and_KH_Keyboard_Controller_BIOS_Reference_, available on the
AMI BBS and american.megatrends.com as KFKHMAN.ZIP.]

[Various chipset infos from "Het BIOS Boekje" 2nd edition, by Alle Metzlar,
ISBN 90-72260-59-7 (1995).]
--------!---Admin----------------------------
Highest Table Number = P104
--------!---FILELIST-------------------------
Please redistribute all of the files comprising the interrupt list (listed at
the beginning of the list and in INTERRUP.1ST) unmodified as a group, in a
quartet of archives named INTER47A through INTER47D (preferably the original
authenticated PKZIP archives), and the utility programs in a two additional
archives called INTER47E.ZIP and INTER47F.ZIP

This compilation is Copyright (c) 1989,1990,1991,1992,1993,1994,1995 Ralf Brown
--------!---CONTACT_INFO---------------------
Internet: [e-mail]
UUCP: {uunet,harvard}!telerama.lm.com!ralf
FIDO: Ralf Brown 1:129/26.1
    or post a message to me in the DR_DEBUG echo (I probably won't see it
    unless you address it to me)
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