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.C1. DOWNLOAD FORMATS C This appendix describes downloadable file formats and the .DOC file. o .c2.DOWNLOADABLE FILE FORMATS This section describes the JEDEC, ASCII-hex, and HL standards for data transfer to a device programmer. o .c3.JEDEC Format The JEDEC JC-42.1 standard consists of a transmission that begins with an ASCII Start-of-Text (STX) character, followed by various fields of information: an ASCII End-of-Text (ETX) character, and a transmission checksum. The allowed legal characters consist of printable ASCII characters (hex 20 through 7E) and the four control characters listed in table C-1. Table C-1. Control Characters STX Start-of-Text hex 02 ETX End-of-Text hex 03 LF Line Feed hex 0A CR Carriage Return hex 0D Figure C-1 shows a sample JEDEC file created by using CUPL and CSIM. ------------------------------------------------------------ <STX> Cupl 3.0 Serial # 0-00000-000 Device p16r4 Library DLIB-h-24-11 Created Tue Jul 07 15:22:33 1987 Name WAITGEN Partno P9000183 Revision 02 Date 03/14/85 Designer Osann Company P-CAD Assembly PC Memory Location U106 *QP20 *QF2048 *G0 *F0 *L000 00 101101011101111111001110001 10111 *C0307 *QV*P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 *V0001 CXXXXX110N0HHLLZXXHN * <ETX> 6AA1 ------------------------------------------------------------ Figure C-1. Sample JEDEC File The rest of this section describes the fields in the sample file in Figure C-1. The design specification is the first field in the format. It includes all information between the STX and the first asterisk (*). This information is for documentation purposes only, and consists of the header information from the CUPL source file along with the version number of the compiler and device library. Each of the fields after the design specification field begins with one of the single character identifiers shown in Table C-2. Table C-2. Field Identifiers A - * N - * B - * O - * C - Fuse check sum P - Pin Order D - Device type Q - Value E - * R - * F - Default fuse state S - * G - Security fuse T - * H - * U - * I - * V - Test vector J - * W - * K - * X - * L - Fuse link data Y - * M - * Z - * * - indicates reserved for future use Characters that have not been defined are reserved for future use. Fields can be identified by multiple characters; for example, QF to indicate a value default fuse state. The device field (D) is no longer supported. In CUPL 1.0 the device field contained a four-digit code that identified the device to be programmed. However, lack of consistent support by the device programmer manufacturers led to this field being dropped from the JEDEC file format for CUPL 2.0 and higher. A value field, QP, describes the number of pins for the device; another value field, QF, describes the total number of programmable fuses in the device. Both values are decimal numbers. The security fuse field (G) instructs the programmer to disable (G0) or enable (G1) the programming of the security fuse on the devices that contain this option. A single space follows the number for compatibility with certain manufacturers' equipment. The default fuse state field (F) defines the state of the fuses that are not explicitly defined in the L field. Since CUPL 3.0 does not transmit all fuse states (to speed data transmission on large designs), this field must be recognized by the device programmer. The fuse link field (L) contains the actual data. Each device fuse link is assigned a decimal number, starting with 0000. Each numbered fuse has two possible states: binary 0 specifies a low resistance link (FUSE INTACT) and binary 1 specifies a high resistance link (FUSE BLOWN). ======================================================== Note Some manufacturers specify "test fuses" for purposes of running AC parameter tests on the device before programming. These fuses are not part of the fuse link data. ======================================================== The L identifier begins the field and is followed by the number of the first fuse being defined in the field. When more than one binary value is specified, the additional values are assigned to fuses numbered consecutively from the first fuse number. The next field is a fuse checksum (C) field. The checksum is a 16-bit hexadecimal value which is computed by adding 8-bit words formed from the specified state of each fuse link in the device. Link number 0 is the least-significant bit (lsb) and link number 7 is the most significant bit (msb) of word 0. Unspecified bits in the final 8-bit word are set to zero before computing the checksum. In the Figure C-1 the first thirty-two fuses generate four 8-bit words as follows: msb lsb word 00 1 0 1 0 1 1 0 1 --> AD word 01 1 1 1 1 1 0 1 1 --> FB word 02 0 1 1 1 0 0 1 1 --> 73 word 03 1 1 1 0 1 1 0 0 --> EC ----- 0307 The optional test vector field (V) is created by running CSIM with the -j option flag. It contains functional test information for each device pin. The QV value field defines the number of test vectors which the file contains. Test vectors are numbered starting with 0001 and applied in numerical order to the device being tested. Table C-3 lists the valid conditions for any pin. Table C-3. Test Conditions 0 - Drive input LO (0 volts) 1 - Drive input HI (+5 volts) C - Drive input LO, HI, LO K - Drive input HI, LO, HI L - Test output LO (0 volts) H - Test output HI (+5 volts) Z - Test output for high impedance X - Input undefined, Output untested N - Power pins and Outputs not tested P - Preload registers Value given applied to [Picture] of register The test conditions, as they appear in the vector, are applied to the device pins according to the sequence given in the pin order (P) field. In this example (figure C-1), the first condition is applied to pin 1 and the last to pin 20 of a 20 pin device. The C and K driving signals are presented after all other inputs are stable. The L, H, and Z conditions are tested after all inputs have been stabilized, including C and K. The P driving signal on the clock pin is valid only for those devices capable of preloading registers with a supervoltage. Devices which use dedicated TTL-level preload pins must use the C or K driving signals on these pins to preload the registers. The end of transmission is signified with a non-printing ASCII ETX character followed immediately by a transmission checksum (sum-check) of four ASCII hex characters. The checksum is the 16-bit sum of the ASCII values of all the transmitted characters between, and including, the starting STX and ending ETX characters. In the sample file (figure C-1), the transmission checksum calculates to 46C9, when taking into account a non-printing carriage return and line feed at the end of every line. o .c3.ASCII-Hex Format The ASCII-hex format is generated for PROMs only. Data in this format is organized in sequential bytes separated by the execute character (space). Characters immediately preceding the execute character are interpreted as data bytes. The format may express the data bytes as either a single hex digit (x4 PROMs) or two hex digits (x8 PROM's). An ASCII STX [Ctrl]-[B] character starts the transmission. A four-digit hexadecimal address, preceded by a $ , A , and comma ($A,) starts each line of 16 data bytes. An ASCII ETX [Ctrl]-[C] ends the data portion of the transmission. It is followed by forty spaces. Figure C-2 shows a sample hex file. ^B $A0000,00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F $A0010,10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F $A0020,20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F $A0030,30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F ^C $S07E0, Figure C-2. Sample Hex File o .c3.HL Formats The HL Download Format is generated for Signetics IFL devices only. Each device has its own unique format. All formats begin with STX [Ctrl]-[B] and end with ETX [Ctrl]-[C]. The following sections describe the format for each type of IFL device. 82S100/101 FPLA. The active-level identifier *A is followed by the states of the active levels for F7 to F0, where H denotes active-HI and L denotes active-LO. The product terms are described by the *P identifier followed by a space and the P-term number. The input variable identifier *I is followed by the input variables I15 to I0 and then the output function identifier *F followed by F7 to F0. Figure C-3 shows a sample file in this format. -------------------------------------------------------- ^B *A LHLHLHLH *P 00 *I HHHHLLLLHHHHLLLL *F A.A.A.A. . . *P 47 *I LLLLLLLLLLLLLLLL *F ....AAAA ^C -------------------------------------------------------- Figure C-3. Sample 82S100/101 FPLA File 82S103 FPGA The product terms start with the *G identifier followed by a space and the term number. This is followed by the active-level identifier *A and the active-level data. The input variable identifier *I is followed by the input variables I15 to I0. Figure C-4 shows a sample file in this format. -------------------------------------------------------- ^B *G 00 *A L *I HHHHLLLLHHHHLLLL . . *G 47 *A H *I LLLLLLLLLLLLLLLL ^C -------------------------------------------------------- Figure C-4. Sample 82S103 FPGA File 82S105 FPLS The preset / output enable option is entered using the *A identifier followed by H (preset) or L (output enable). The transition terms are described by the term identifier *T followed by the term number. The complement array identifier *C is followed by the value of this term. The input variables for the term are given with the input variable identifier *I followed by I15 to I0. The present state of the flip-flops is given with *P followed by P5 to P0. The next state values follow with *N and N5 to N0. The output function is described as *F followed by F7 to F0. Figure C-5 shows a sample file in this format. -------------------------------------------------------- ^B *AL *T 00 *C.*ILLLLHHHHLLLLHHH *P HHHLLL *NHHHLLL *F HHHHHHHH . . *T 47 *C A *I LL------- *P LLLLLL *N HHHHHH *F HHHLLL- ^C -------------------------------------------------------- Figure C-5. Sample 82S105 FPLS File 82S151 FPGA The direction of the I/O pins follows the *DIR identifier, and the output polarity follows the *POL identifier. The product terms are described by the *P identifier followed by a space and the P-term number. Control term numbers start with a *D and then the term number. The input variable identifier *I is followed by the input variables I5 to I0 and then the I/O feedback identifier *B followed by B11 to B0. Figure C-6 shows a sample file in this format. -------------------------------------------------------- ^B *DIR HHLLHHLLHLHL *POL HHHHLLLLHHLL *P 00 *I HHLLLL *B HL--HL--LLHH . . *P 11 *I LLLLLL *B HHHHLLLLHHLL *D 02 *I ----HH *B ----LLLLLL- . . *D 00 *I LLLL-- *B HHHHHHLLLL- ^C -------------------------------------------------------- Figure C-6. Sample 82S151 FPGA File 82S153 FPLA The output polarity identifier *POL is followed by the states of the active levels for outputs B9 to B0, where H denotes active-HI and L denotes active-LO. The product terms are described by the *P identifier followed by a space and the P-term number. Control term numbers start with a D and then the term number. The input variable identifier *I is followed by the input variables I7 to I0. The feedback variables B9 to B0 follow the *BI identifier and the output functions B9 to B0 follow the *BO identifier. Figure C-7 shows a sample file in this format. -------------------------------------------------------- ^B *POL HHLLHHLLHH *P 00 *I --HH--LL *BI --HL------ *BO A..A..A..A . . *P 31 *I ------HH *BI HLHLHLHLHL *BO ....AA.... *P D9 *I --HHHHHH *BI ----HHHHLL . . *P D0 *I LLLLLLLL *BI --------- ^C -------------------------------------------------------- Figure C-7. Sample 82S153 FPLA File 82S155 FPLS The output enable modes for groups A and B follow the *E identifier. The flip-flop mode for each register follows an *F/F identifier. The polarity for the output pins follows an *POL identifier. The transition terms are described by the term identifier *T followed by the term number. The complement array identifier *C is followed by the value of this term. The input variables for the term are given with the input variable identifier *I followed by I3 to I0. The I/O feedback data follows the *B identifier. The present state of the flip-flops is given with *QP followed by Q3 to Q0. The next state values follow with *ON and O3 to O0. The preset terms for groups PB and PA follow the preset identifier *P. The reset terms for groups RB and RA follow the reset identifier *R. The output function is described as *BO followed by B7 to B0. The terms for flip-flop control, reset, preset, load, and output enable follow. Figure C-8 shows a sample file in this format. -------------------------------------------------------- ^B *E AA *F/F A.A. *POL HLHLLHLH *T 00 *C . *I HHLL *BI HL--HLHL *QP LH- *QN LLHH *P .. *R .. *BO .A.A.A.A . . *T 31 *C A *I LLHH *BI ----HLHL *QP HHLL *QNHHHH *P .A *R .A *BO ..A.AA.A *T FC *C . *I LLLL *BI LLLLHHHH *QP LLHH *T LB *C . *I HLLL *BI --LL--LL *QP HHHH *T LA *C . *I LL-- *BI LLLLHHHH *QP --LL *T D3 *C . *I LLLL *BI LLLLLLL- *QP LLHH . . *T D0 *C . *I LLLL *BI LLHHHHLL *QP HLLH ^C -------------------------------------------------------- Figure C-8. Sample 82S155 FPLS File 82S157 FPLS The output enable modes for groups A and B follow the *E identifier. The flip-flop mode for each register follows a *F/F identifier. The polarity for the output pins follows a *POL identifier. The transition terms are described by the term identifier *T followed by the term number. The complement array identifier *C is followed by the value of this term. The input variables for the term are given with the the input variable identifier *I followed by I3 to I0. The I/O feedback data follows the *BI identifier. The present state of the flip-flops is given with *QP followed by Q5 to Q0. The next state values follow with *QN and Q5 to Q0. The preset terms for group PA follows the preset identifier *P. The reset terms for group PA follows the reset identifier *R. The output function is described as *BO followed by B5 to B0. The terms for Flip-Flop control, reset, preset, load and output enable follow. Figure C-9 shows a sample file in this format. -------------------------------------------------------- ^B *E AA *F/F A.A. *POL HLHLLHLH *T 00 *C . *I HHLL *BI HL--HL *QP LH--HL *QN LLHHHL *P . *R . *BO .A.A.A . . *T 31 *C A *I LLHH *BI --HLHL *QP HHLLHH *QNHHHHLL *P A *R A *BO ..AA.A *T FC *C . *I LLLL *BI LLLLHH *QP LLHHHH *T PB *C . *I ---- *BI ----HH *QP ----LL *T RB *C . *I HHHL *BI HHLLLL *QP HLLLHH *T LB *C . *I HLLL *BI --L-LL *QP HHHHLL *T LA *C . *I LL-- *BI LLLHHH *QP --LLHH *T D3 *C . *I LLLL *BI LLLLL- *QP LLHH- . . *T D0 *C . *I LLLL *BI LLHHLL *QP HLLHLL ^C -------------------------------------------------------- Figure C-9. Sample 82S157 FPLS File 82S159 FPLS The output enable modes for groups A and B follow the *E identifier. The flip-flop mode for each register follows a *F/F identifier. The polarity for the output pins follows a *POL identifier. The transition terms are described by the term identifier. *T followed by the term number. The complement array identifier *C is followed by the value of this term. The input variables for the term are given with the the input variable identifier *I followed by I3 to I0. The I/O feedback data follows the *BI identifier. The present state of the flip-flops is given with *QP followed by Q7 to Q0. The next state values follow with *QN and Q7 to Q0. The output function is described as *BO followed by B7 to B0. The terms for Flip-Flop control, reset, preset, load and output enable follow. Figure C-10 shows a sample file in this format. -------------------------------------------------------- ^B *E AA *F/F A.A.A.A. *POL LHLH *T 00 *C . *I HHLL *BI HL-- *QP HHLLHH- *QN LLHHLLHH *BO .A.A . . *T 31 *C A *I LLHH *BI ---- *QP --HHHHLL *QN LLLLHHHH *BO ...A *T FC *C . *I LLLL *BI LLLL *QP LLLLHHHH *T PB *C . *I LLLL *BI LLLL *QP LLLLHHHH *T RB *C . *I LLLL *BI LLLL *QP LLLLHHHH *T LB *C . *I LLLL *BI LLLL *QP LLLLHHHH *T PA *C . *I LLLL *BI LLLL *QP LLLLHHHH *T RA *C . *I LLLL *BI LLLL *QP LLLLHHHH *T LA *C . *I LLLL *BI LLLL *QP LLLLHHHH *T D3 *C . *I LLLL *BI LLLL *QP LLLLHHHH . . *T D0 *C . *I LLLL *BI LLLL *QP LLLLHHHH ^C -------------------------------------------------------- Figure C-10. Sample 82S159 FPLS File 82S161 FPLA The active level identifier *A is followed by the states of the active levels for F7 to F0, where H denotes active-HI and L denotes active-LO. The product terms are described by the *P identifier followed by a space and the P-term number. The input variable identifier *I is then followed by the input variables I11 to I0 and the output function identifier *F followed by F7 to F0. Figure C-11 shows a sample file in this format. -------------------------------------------------------- ^B A LHLHLHLH *P 00 *I LLLLHHHHLLLL *F A.A.A.A. . . *P 47 *I LLLLLLLLLLLL *F ....AAAA ^C -------------------------------------------------------- Figure C-11. Sample 82S161 FPLA File 82S162 FPGA The output polarity identifier *POL is followed by the states of the active levels for outputs F4 to F0. The product terms start with the *G identifier followed by a space and the term number. The input variable identifier *I is followed by the input variables I15 to I0. Figure C-12 shows a sample file in this format. -------------------------------------------------------- ^B *POL HHLL *G 00 *I HHHHLLLLHHHHLLLL . . *G 04 *I LLLLLLLLLLLLLLLL ^C -------------------------------------------------------- Figure C-12. Sample 82S162 File 82S163 FPGA The output polarity identifier *POL is followed by the states of the active levels for outputs F8 to F0. The product terms start with the *G identifier followed by a space and the term number. The input variable identifier *I is followed by the input variables I11 to I0. Figure C-13 shows a sample file in this format. -------------------------------------------------------- ^B *G 00 *I HLLLHHHHLLLL . . *G 08 *I LLLLLLLLLLLL ^C -------------------------------------------------------- Figure C-13. Sample 82S163 FPGA File 82S167 FPLS The preset / output enable option is entered using the *A identifier followed by H (preset) or L (output enable). The transition terms are described by the term identifier *T followed by the term number. The complement array identifier *C is followed by the value of this term. The input variables for the term are given with the input variable identifier *I followed by I13 to I0. The present state of the flip-flops is given with *P followed by P7 to P0. The next state values follow with *N and N7 to N0. The output function is then described as *F followed by F3 to F0. Figure C-14 shows a sample file in this format. -------------------------------------------------------- ^B *AL *T 00 *C .*ILLHHHHLLLLHHHH*PHHHLLLHH *NHHHLLLLL *F HHHH . . *T 47 * A *I LL------------ *P --LLLLLL *N HHLLHHHH *F HL- ^C -------------------------------------------------------- Figure C-14. Sample 82S167 FPLS File 82S168 FPLS The preset/output enable option is entered using the *A identifier followed by H (preset) or L (output enable). The transition terms are described by the term identifier *T followed by the term number. The complement array identifier *C is followed by the value of this term. The input variables for the term are given with the input identifier *I followed by I11 to I0. The present state of the flip-flops is given with *P followed by P9 to P0. The next state values follow with *N and N9 to N0. The output function is described as *F followed by F3 to F0. Figure C-15 shows a sample file in this format. -------------------------------------------------------- ^B *AL *T 00 *C.*ILLHHHLLLHHHH*PHHHLLLHHLH *NHHLHHLLLLL *F HHHH . . *T 47 *C A *I LL------------ *P --LLLLLL- *N HHLLHHHH-L *F HL- ^C -------------------------------------------------------- Figure C-15. Sample 82S168 FPLS File 82S173 FPLA The output polarity identifier *POL is followed by the states of the active levels for outputs B9 to B0, where H denotes active-HI and L denotes active-LO. The product terms are described by the *P identifier followed by a space and the P-term number. Control term numbers start with D and then the term number. The input variable identifier *I is followed by the input variables I11 to I0. The feedback variables B9 to B0 follow the *B0 identifier. Figure C-16 shows a sample file in this format. -------------------------------------------------------- ^B *POL HHLLHHLLHH *P 00 *I --HH--LLHH *BI --HL------ *BO A..A..A..A . . *P 31 *I LL------HH *BI HLHLHLHLHL *BO ....AA.... *P D9 *I LL--HHHHHH *BI ----HHHHLL . . *P D0 *I --LLLLLLLL *BI --------- ^C -------------------------------------------------------- Figure C-16. Sample 82S173 FPLA File 82S179 FPLS The output enable modes for groups A and B follow the *E identifier. The flip-flop mode for each register follows a *F/F identifier. The polarity for the output pins follows a *POL identifier. The transition terms are described by the term identifier *T followed by the term number. The complement array identifier *C is followed by the value of this term. The input variables for the term are given with the input variable identifier *I followed by I7 to I0. The I/O feedback data follows the *BI identifier. The present state of the flip-flops is given with *QP followed by Q7 to Q0. The next state values follow with *QN and Q7 to Q0. The output function is described as *BO followed by B7 to B0. The terms for flip-flop control, reset, preset, load, and output enable follow. Figure C-17 shows a sample file in this format. -------------------------------------------------------- ^B *E AA *F/F A.A.A.A. *POL LHLH *T 00 *C . *I HHLLHHLH *BI HL-- *QP HHLLHH- *QN LLHHLLHH *BO .A.A . . *T 31 *C *1 LLH--LHH *BI LLLL *QP --HHHHLL *QN LLLLHHHH *BO ...A *T FC *C . *1 LLLHHHHL *BI LLLL *QP LLLLHHHH *T PB *C . *I LLLHLHLL *BI LLLL *QP LLLLHHHH *T RB *C . *I LLLLLLHL *BI LLLL *QP LLLLHHHH *T LB *C . *I LLLHHHHL *BI LLLL *QP LLLLHHHH *T PA *C . *I LLLLHLHL *BI LLLL *QP LLLLHHHH *T RA *C . *I LLLL---- *BI LLLL *QP *T LA *C . *I LLLL---H *BI LLLL *QP LLLLHHHH *T D3 *C . *I LLLLLLLL *BI LLLL *QP LLLLHHHH . . *T DO *C . *I HHHHHHHH *BI LLLL *QP LLLLHHHH ^C -------------------------------------------------------- Figure C-17. Sample 82S179 FPLS File o .c2.DOCUMENTATION FILE FORMAT This section describes the format for the documentation file (filename .DOC), including fuse plot information. A documentation file can be generated by specifying the -x option flag when running CUPL. Specifying the -f option generates a fuse plot in the documentation file. Figure C-18 shows a sample documentation file. ------------------------------------------------------------ WAITGEN.DOC ******************************************************************************* Sample ******************************************************************************* CUPL 4.2a Serial# MD-34123456 Device p16r4 Library DLIB-h-28-11 Created Wed Dec 18 08:10:07 1991 Name Sample Partno P9000183 Revision 02 Date 03/14/85 Designer Osann Company ATI Assembly PC Memory Location U106 =============================================================================== Expanded Product Terms =============================================================================== memadr => a15 , a14 , a13 , a12 , a11 memreq => memw # memr ram_cs0 => !a11 & !a12 & a13 & !a14 & !a15 & memw # !a11 & !a12 & a13 & !a14 & !a15 & memr ram_cs1 => a11 & !a12 & a13 & !a14 & !a15 & memw # a11 & !a12 & a13 & !a14 & !a15 & memr ready => !wait2 ready.oe => !a13 & !a14 & !a15 & memr rom_cs => !a13 & !a14 & !a15 & memr ------------------------------------------------------------ Figure C-18. Sample Documentation File Sheet 1 of 5 ------------------------------------------------------------ select_rom => !a13 & !a14 & !a15 & memr wait1.d => !memr # a15 # a14 # a13 # reset wait2.d => !memr # a15 # a14 # a13 # !wait1 ram_cs0.oe => 1 ram_cs1.oe => 1 rom_cs.oe => 1 ------------------------------------------------------------ Figure C-18. Sheet 2 of 5 ------------------------------------------------------------ =============================================================================== Symbol Table =============================================================================== Pin Variable Pterms Max Min Pol Name Ext Pin Type Used Pterms Level --- -------- --- --- ---- ------ ------ ----- a11 6 V - - - a12 5 V - - - a13 4 V - - - a14 3 V - - - a15 2 V - - - cpu_clk 1 V - - - memadr 0 F - - - ! memr 8 V - - - memreq 0 I 2 - - ! memw 7 V - - - ! oe 11 V - - - ! ram_cs0 12 V 2 7 1 ! ram_cs1 13 V 2 7 1 ready 18 V 1 7 1 ready oe 18 X 1 1 1 reset 9 V - - - ! rom_cs 19 V 1 7 1 select_rom 0 I 1 - - wait1 15 V - - - wait1 d 15 X 5 8 1 wait2 14 V - - - wait2 d 14 X 5 8 1 ram_cs0 oe 12 D 1 1 0 ram_cs1 oe 13 D 1 1 0 rom_cs oe 19 D 1 1 0 LEGEND D : default variable F : field G : group I : intermediate variable N : node M : extended node U : undefined V : variable X : extended variable T : function ------------------------------------------------------------ Figure C-18. Sheet 3 of 5 ------------------------------------------------------------ =============================================================================== Fuse Plot =============================================================================== Pin #19 00000 -------------------------------- 00032 -x---x---x---------------x------ 00064 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 00096 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 00128 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 00160 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 00192 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 00224 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx Pin #18 00256 -x---x---x---------------x------ 00288 -----------------------x-------- 00320 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 00352 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 00384 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 00416 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 00448 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 00480 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx Pin #17 00512 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 00544 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 00576 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 00608 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 00640 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 00672 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 00704 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 00736 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx Pin #16 00768 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 00800 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 00832 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 00864 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 00896 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 00928 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 00960 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 00992 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx Pin #15 01024 ------------------------x------- 01056 x------------------------------- 01088 ----x--------------------------- 01120 --------x----------------------- 01152 ----------------------------x--- 01184 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 01216 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 01248 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx ------------------------------------------------------------ Figure C-18. Sheet 4 of 5 ------------------------------------------------------------ Pin #14 01280 ------------------------x------- 01312 x------------------------------- 01344 ----x--------------------------- 01376 --------x----------------------- 01408 -------------------x------------ 01440 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 01472 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 01504 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx Pin #13 01536 -------------------------------- 01568 -x---x--x----x--x----x---------- 01600 -x---x--x----x--x--------x------ 01632 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 01664 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 01696 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 01728 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 01760 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx Pin #12 01792 -------------------------------- 01824 -x---x--x----x---x---x---------- 01856 -x---x--x----x---x-------x------ 01888 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 01920 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 01952 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 01984 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 02016 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx LEGEND X : fuse not blown - : fuse blown =============================================================================== Chip Diagram =============================================================================== ______________ | Sample | cpu_clk x---|1 20|---x Vcc a15 x---|2 19|---x !rom_cs a14 x---|3 18|---x ready a13 x---|4 17|---x a12 x---|5 16|---x a11 x---|6 15|---x wait1 !memw x---|7 14|---x wait2 !memr x---|8 13|---x !ram_cs1 reset x---|9 12|---x !ram_cs0 GND x---|10 11|---x !oe |______________| ------------------------------------------------------------ Figure C-18. Sheet 5 of 5 The first part of the file contains archival and revision information that is identical to the header information in the corresponding CUPL source file. The first part also contains version information about the device library and the CUPL program, and the date and time the file was created. The next section of the file, Expanded Product Terms, contains the product terms generated by CUPL from the equations contained in the logic description file. WAITGEN.PLD, contained in the CUPL package, is the source logic description file for the sample documentation file in Figure C-18. Its contents can be viewed in order to compare the original logic equations with the product terms generated by CUPL. CUPL generates product terms for the devices specified on the command line when running CUPL or with the DEVICE keyword in the logic description file. For example, some devices, such as PAL16L8s, contain fixed inverting buffers. .i.DeMorgan's Theorem;In certain cases, to fit the logic to the device, CUPL performs DeMorgan's Theorem. For example, the logic description file is written for a PAL16L8 device; in the pin list, all outputs have been declared as active-HI. The following equation is written to specify an OR function. c = a # b ; However, the PAL16L8 contains a fixed inverting buffer. Because the inverting buffer cannot be changed, CUPL fits the logic to the device by performing a DeMorgan on the OR equation, which generates the following product term: c => !a & !b See Pin Declaration Statements in Chapter 2 for further information on how CUPL generates product terms for devices with fixed inverting buffers, when the output pins are asserted in the pin declaration statement. The next section of the file, Symbol Table, provides information about each variable in the logic description file, including the pin number, extension, type of variable, number of product terms available, number of product terms used, and the minimization level used by CUPL. .i.product terms;If the maximum available product terms for a device is exceeded, CUPL displays an error message during compilation, naming the pin. However, the message doesn't indicate how much the limit was exceeded. The product term availability and use information in the Symbol Table (see Figure C-18) indicates if the number of available product terms was grossly exceeded, or was just slightly over the limit. The next section, Fuse Plot, is generated by specifying the -f option flag when running CUPL. This section provides more detailed fuse information than that contained in the JEDEC file. The four-digit beginning JEDEC number for each product term is the number to use to reference STUCK H and STUCK L (see Fault Simulation in Chapter 4) The last section, Chip Diagram, provides a diagram of the device showing the location of each variable name. o .c2.PDIF FILE FORMAT This section describes the use of the PDIF (P-CAD Database Interchange Format) file (<F59>filename.PDF) generated by CUPL. For a detailed description of the PDIF-format file, see the PDIF User's Manual. A PDIF-format file can be generated by specifying the -p option flag when running CUPL. The PDIF format is used as an interface to the P-CAD schematic capture program PC-CAPS. This is accomplished by translating the CUPL-generated PDIF-format file into a PC-CAPS symbol using the PDIF-IN program. The resulting symbol represents the logical representation of the PLD design. This includes pin packaging information, printed circuit board reference designator, PLD type, and design name. Figure C-19 shows an example of a PC-CAPS symbol generated by PDIF-IN. [Picture] Figure C-19. PC-CAPS Symbol Generated by PDIF-IN Refer to the PDIF User's Manual and the PC-CAPS User's Manual for instructions on running the PDIF-IN and PC-CAPS programs, respectively. o .c2.BERKELEY PLA FILE FORMAT This section describes the format for the Berkeley PLA file (filename.PLA). The Berkeley PLA format is used as an interface format for PLA logic synthesis tools, such as the Berkeley PLA tools. A Berkeley PLA-format file can be generated by specifying the -b option flag when running CUPL. Figure C-20 shows a sample Berkeley PLA-format file. ------------------------------------------------------------ # Berkeley PLA format generated using # # CUPL 4.2a Serial# XX-00000000 # Device p16rp4 Library DLIB-h-28-15 # Created Wed Dec 18 08:35:26 1991 # Name Count10 # Partno CA0018 # Revision 02 # Date 12/19/89 # Designer Kahl # Company Logical Devices, Inc. # Assembly None # Location None # # Inputs 1 Q0 Q1 Q2 # Q3 carry clk clr # dir !oe # Outputs Q0.d Q1.d Q2.d Q3.d # carry carry.oe .i 10 .o 6 .p 19 -0001--0-- 1~~~~~ -0--0--0-- 1~~~~~ -0001--01- ~1~~~~ -10-0--00- ~1~~~~ -01-0--00- ~1~~~~ -11-0--01- ~1~~~~ -0010--01- ~1~~~~ -0001--01- ~~1~~~ -1100--00- ~~1~~~ --010--00- ~~1~~~ -1-10--01- ~~1~~~ -0110--0-- ~~1~~~ -1001--01- ~~~1~~ -0000--01- ~~~1~~ -1110--00- ~~~1~~ -0001--00- ~~~1~~ -0000--01- ~~~~1~ -1001--00- ~~~~1~ 1--------- ~~~~~1 .end ------------------------------------------------------------ Figure C-20. Sample Berkeley PLA-Format File The first part of the file contains archival and revision information. The # character indicates these are comments. This information is identical to the header information in the corresponding CUPL source file. There is also version information about the device library and CUPL program, the date and time the file was created, and a list of the input and outputs to the PLA. The next section consists of a PLA description generated by CUPL from the equations contained in the logic description file, COUNT10.PLD (contained in the CUPL package). Its contents can be viewed to compare the original logic equations with the PLA description generated by CUPL. The PLA description consists of fields to define the number of inputs '.i', outputs '.o', product terms '.p', and a description of the AND and OR planes of the PLA with one line per product term. Connections in the AND plane are represented with a '1' for connection to the non-inverted input line and a '0' for connection to the inverted input line. No connection to an input line is indicated with a '-'. Connections in the OR plane are indicated by a '1'. No connections are indicated with a '0'. The end of the PLA description is indicated with an '.end'.