PC World Komputer 1996 September/pcwk_09_96.iso/demo/elmark/cupl/manual/sb5.txt

Text File | 1992-01-17 | 21KB | 457 lines

.C1.    FPGA AND HIGH DENSITY PLDS                  5

        The STARTER KIT does not support the high density PLDs or FPGAs.
        This information is provided for users of CUPL "PLD Master" or
        "Total Designer".

o .c2.DESIGNING WITH FPGAs and HIGH DENSITY PLDs

    This chapter will provide information on how CUPL is used in
    conjunction with FPGA tools to create FPGA designs. Typically, FPGA
    tools offer limited input formats such as Boolean equations and
    schematic. Higher level state machine designs are often difficult
    with this approach and a language like CUPL can make this process
    much easier.

    In addition, CUPL now has the capability to handle more advanced
    architectures such as MACH from AMD and MAPL from National
    Semiconductor.This capability is made available via the OPEN-PLA
    format and the external fitter technology now built into CUPL. To be
    able to use some of these devices, supplemental tools may have to be
    purchased from LOGICAL DEVICES or from the FPGA manufacturer.  Due
    to DOS memory restrictions and the memory requirements of these
    external fitter programs, there may be cases where the CUPL menu
    system cannot be used. In these cases, the command line version of
    CUPL should be used.

o   .c3.XILINX XNF   INTERFACE
    This section describes how a CUPL source file can be translated into
    an XNF netlist file.  CUPL generates an equivalent PALASM file,
    using the c flag, which can be used as input to PDS2XNF.  PDS2XNF
    will translate the PALASM file into an XNF file to be used by the
    remaining XILINX XACT_ integrated software package.

                    [Picture]
    Figure 5-1. CUPL Design to LCA Translation Data Flow.

.c4.Getting an XNF File
    Just as CUPL .i.PALASM:generating;.i.CU PL:generating PALASM
    output;.i.CUPL Flags:-C;.i.Flags:-C;is run to compile a PLD design,
    it can be run using the -c flag to produce an equivalent PALASM
    format file.  For example, entering the following:

    CUPL -c  EXAMPLE.PLD
        will create the PALASM file EXAMPLE.PDS.

.c4.Translating an Existing PLD File
    Any PLD which can be compiled by CUPL can be translated into PALASM
    format. Because a device must be specified for PLD design, a device
    must also be specified when translating a CUPL file to a PALASM
    format.  In order to preserve the original use of the PLD source
    file, do not change the device name; CUPL will translate the file
    based on the devices that PALASM recognizes. A recognizable device
    is translated into the PDS file using the names given in Table 5-1.
    An unrecognizable or VIRTUAL device is translated into the PDS file
    as USER. The VIRTUAL device should be specified when a source file
    is for XILINX devices.

        Table 5-1. PALASM Device Listing

        PAL6L16
        PAL10H8
        PAL10L8
        PAL10H20G8
        PAL10H20P8
        PAL12H6
        PAL12L6
        PAL12L10
        PAL14H4
        PAL14L4
        PAL14L8
        PAL16C1
        PAL16H2
        PAL16L2
        PAL16L6
        PAL16L8
        PAL16P8
        PAL16R4
        PAL16R6
        PAL16R8
        PAL16RA8
        PAL16RP4
        PAL16RP6
        PAL16RP8
        PAL18L4
        PAL20C1
        PAL20L2
        PAL20L8
        PAL20L10
        PAL20R4
        PAL20R6
        PAL20R8
        PAL20RA10
        PAL20RS4
        PAL20RS10
        PAL20S10
        PAL20X4
        PAL20X8
        PAL20X10
        PAL22RX8
        PAL22V10
        PAL32R16
        PAL32VX10
        PAL64R32
        PMS14R21

.c4.Using a PALASM Device
    .i.PALASM;When a PALASM device is selected, CUPL will generate a
    functionally-equivalent PALASM file, which can then be translated
    into an XNF file.

    When a device is selected that PALASM does not recognize, CUPL will
    insert USER as the device name in the PALASM file.  PDS2XNF
    recognizes this USER device.  Some PLD macro configurations which
    are not supported by PALASM will be ignored or translated into a
    PALASM equivalent.  This will generate a warning message. For
    example, if the extension .i.CKMUX;.i.Extensions:CKM UX;CKMUX is
    used, it is considered to be a CK extension, and a warning message
    is generated. If the extension .i.DFB;.i.Extensions:DFB;D FB is
    used, it is ignored and a warning message is generated.

.c4.Source Files for XILINX Devices
    The following discusses how to create a new CUPL source file for
    XILINX devices.

    .i.XILINX devices;When a new CUPL source file is created, any device
    on the CUPL device list can be specified.  The imaginary PLD9000 or
    the limitless .i.Virtual:device;.i.devic e:virtual;VIRTUAL device
    can also be specified.  Refer to the device support section of the
    CUPL manual for details on these devices.  The CUPL source file
    remains the same except for the following few differences:  Pin
    numbers are not needed when using the VIRTUAL device.  The
    .i.Virtual:pin declarations;.i.PIN:use with virtual device;PIN
    keyword is still used, however, to assign names to the pins of a
    device that will be used later.  For example:

        pin = Input0 ;

    The keyword .i.Keywords:NODE;.i.NODE;N ODE is not used with the
    VIRTUAL device.  The keyword .i.Keywords:PINNODE;.i.PIN NODE;PINNODE
    is, however, still used.

o   .c3.DEVICE   FITTERS
    Newly .i.Device Fitters;.i.Fitter;designed devices are becoming
    increasingly more complex.  The time required to make design tools
    available for these new devices is also therefore increased because
    of more complex software issues.  The solution to this is to have
    the device manufacturer design a backend device .i.Fitter;fitter
    that simply takes the logic description and fits it into the device
    and creates a JEDEC file. The manufacturer can begin work on this
    software at a much earlier stage in the development cycle than the
    tool manufacturers. The trick is to take this fitter tool and plug
    it into the backend of CUPL. CUPL is therefore, relieved of the task
    of figuring out how equations are placed into the device, it merely
    reduces the equations and feeds them to the fitter. The fitter in
    turn uses these equations to create a JEDEC file.

    Although CUPL now has less to worry about in terms of how to fit
    equations into the device, it still has a lot of work to do.  For
    example, when using devices that require fitters, pin numbers are
    not necessary.  If a designer does put pin numbers into the PLD file
    CUPL needs to check to see if these are valid or not. The same
    situation goes for valid extensions. If a designer tries to use T
    registers in a device that does not have the capability, CUPL needs
    to figure this out and let the user know.  Even if the fitter can
    adequately handle a case where a designer tries to use a function
    that does not exist in the device, it is better to trap these design
    errors earlier in the compile cycle because of time.  Why should a
    designer wait for CUPL to compile the design and create an Open PLA
    file then to find out that he made a mistake.

    Another thing that CUPL does is to call the fitter with the correct
    options, sometimes it calls a fitter multiple times using different
    options until it gets a fit or exhausts all possible options.  The
    best part of all this is that the designer does not have to worry
    about calling the fitter at all because CUPL calls the appropriate
    fitter for the device being used. If it were not for the fact that
    the fitter produced screen output, the user would not even be aware
    that a separate fitter was being called.

                    [Picture]
     Figure 5-2. CUPL-Fitter Interaction

    Because of the highly specialized nature and high complexity of
    fitters, software fitters are combined with CUPL as an option. Some
    fitters take many man years of development.

o   .c3.USING CUPL   FOR FPGA2020   DEVELOPMENT

    .i.PLUSTRAN;.i.device:FPGA 2020;CUPL is well suited as an
    enhancement to PLUS LOGIC's PLUSTRAN development tool.  When
    developing using schematic capture it is difficult to implement
    state machines and tables. CUPL may be used to assist the developer
    in these cases and may be easily integrated into the PLUSTRAN
    environment.  This note is meant to assist the developer in the
    integration of CUPL into the PLUSTRAN environment and the assumption
    is made that the user is familiar with PLUSTRAN.

    Once CUPL and PLUSTRAN have been installed, run PLUSTRAN. Under the
    PLUS DIRECTOR ROOT MENU, set up the Design Name to be the same as
    the CUPL source file, and the Design Directory to be the location of
    the CUPL source files.

    [Picture]
     Figure 5-3 PLUS DIRECTOR ROOT MENU

    Now select Options.  Under the OPTIONS MENU, set up the following:b)
    Editor Command (editor of your choice) c) Editor Directoryd)
    Compiler Command (select MCUPL)e) Compiler Directory (use CUPL
    directory)i) Equation File Ext (use PDS)

    [Picture]
     Figure 5-4. OPTIONS  MENU

    MCUPL is the CUPL menu system. It will allow the developer to edit
    and compile CUPL source files from within the PLUSTRAN environment.
    Make sure that when the CUPL file is compiled, that PALASM output is
    selected (-c option flag). This will cause CUPL to create a .PDS
    output file for PLUSTRAN.  Once the options have been set up.
    Return to the ROOT MENU.  Now select Behavioral Entry.

    Under the BEHAVIORAL ENTRY MENU select
    Options.

    [Picture]

     Figure 5-5. BEHAVIORAL     ENTRY MENU

    Under this OPTIONS MENU, use the same setup as above:a) Editor
    Command (editor of your choice) b) Editor Directoryc) Compiler
    Command (select MCUPL)d) Compiler Directory (use CUPL directory)e)
    Equation File Ext (use PDS)

    [Picture]
     Figure 5-6. OPTIONS MENU

    Return to the BEHAVIORAL ENTRY MENU.

    To edit and compile CUPL source files, select Compiler. This will
    run MCUPL. When a design is completed and compiled using CUPL with
    the PALASM output selected, the .PDS file must be edited.

    Select Edit Design from the main MCUPL menu.  Select the design file
    with the .PDS extension.  On the line that contains CHIP <name>
    USER, change the word USER to FPGA , so that the line reads CHIP
    <name> FPGA and save the file.  For most applications this may be
    all that is necessary for PLUSTRAN to compile the .PDS file
    successfully.  Refer to the PLUSTRAN manual for differences between
    PALASM and PLUSASM.

   Note
     Since the PALASM file contains equations already reduced by CUPL
     the user may wish to add the PLUSASM MINIMIZE OFF command for the
     outputs, to disable the PLUSASM minimizer which saves some
     compilation time.

    Once the CUPL PALASM file has been edited, Quit the MCUPL
    environment.  This will return the developer to the PLUSTRAN
    BEHAVIORAL ENTRY MENU.

    Select Assemble from this menu.

    This will compile the source file. Refer to the PLUSTRAN manual if
    errors occur.

    Once the file has been "Assembled" without errors, select Integrate
    Equations from the BEHAVIORAL ENTRY MENU.  This will fit the design
    into the selected PLUS LOGIC component.  Once the design has been
    "Integrated" into a component successfully, return to the PLUS
    DIRECTOR ROOT MENU.  Select Programming from the ROOT MENU.

     [Picture]

     Figure 5-7. PROGRAMMING MENU

    Select a Signature ID from the PROGRAMMING MENU before generating
    the output file. To generate an Intel Hex file, select Export EPROM
    Map.  The design will then be ready to be programmed into the
    selected PLUS LOGIC component.

          [Picture]
     Figure 5-8. Using CUPL with PLUSASM




        Name            PLUS LOGIC Counter;
        Partno          FPGA2020;
        Revision        REV_1;
        Date            July 1991;
        Company         Logical Devices;
        Assembly        None;
        Location        U1;
        device          virtual;
        pin = CLK;
        pin = A;
        pin = B;
        pin = C;
        pin = D;
        pin = LOAD;
        pin = CLRA;
        pin = ENP;
        pin = ENT;
        pin = SCO;
        pin = QA;
        pin = QB;
        pin = QC;
        pin = QD;
        field DataIn = [D,C, B, A];
        field DataOut = [QD, QC, QB,QA];

        sequenced DataOut {
       $repeat State = [0..15]
       present      'd'{State}
       if ENP next  'd'{(State+1)%16};
       default next 'd'{State};
       $repend
        DataOut.ar = CLRA;
        SCO = ENT & DataOut:&;

     Figure 5-9. CUPL Input File

        TITLE           PLUS LOGIC Counter
        PATTERN         FPGA2020
        REVISION        REV_1
        DATE            July 1991
        AUTHOR          Jim Millener
        COMPANY         Logical Devices
        CHIP PLCNTR FPGA
        CLK A B C D LOAD CLRA ENP ENT SCO QA QB QC QD
        MINIMIZE OFF SCO QA QB QC QD

        EQUATIONS
        QA.RSTF = CLRA
        QA := ENP * /QA  + /ENP * QA
        QB.RSTF = CLRA
        QB := /ENP * QA * QB  +  ENP * QA * /QB  +  /QA * QB
        QC.RSTF = CLRA
        QC := /ENP * QA * QB * QC  +  ENP * QA * QB * /QC +  /QA * QB *
                QC  +  /QB * QC
        QD.RSTF = CLRA
        QD := /ENP * QA * QB * QC * QD  + ENP * QA * QB * QC * /QD  +
                QA * QB * /QC * QD  +  /QB * QD  +  /QA * QB * QD
        SCO = ENT * QA * QB * QC * QD

     Figure 5-10. PLUSASM     Output File

o   .c3.USING CUPL   WITH THE MACH   DEVICES
    .i.MACH;.i.device:MACH;The MACH (Macro Array CMOS High-density)
    family provides a way to implement large logic designs in a
    programmable logic device.  Their unique architecture makes these
    devices ideal for replacing large amounts of TTL logic.  They
    provide increased functionality without forcing the designer to
    sacrifice speed and cost.  The MACH devices consist of PAL blocks
    interconnected by a programmable switch matrix.  Designs that
    consist of several interconnected functional modules can be
    efficiently implemented by placing the modules into the PAL blocks.
    Designs that are not as modular can still be implemented since the
    switch matrix provides a high level of connectivity between the PAL
    blocks. This internal arrangement of resources is managed
    automatically by the fitter, so that the designer does not have to
    be concerned with the logic implementation details.

    Designs can be entered using multiple state machine, truth table,
    and Boolean input formats.  Pins and nodes can be left unassigned,
    allowing the fitter to place them in optimal locations.  Signals
    that must be located on critical pins can also be manually placed;
    the fitter will then fit the rest of the design on the remaining
    pins.

    Once the design entry is complete, CUPL will compile and minimize
    the logic, automatically calling the fitter to fit the design into
    the device. A JEDEC file is generated for programming the device and
    a documentation report is generated that describes the final
    implementation.  Unit-delay simulation is provided, allowing the
    designer to verify that the design is operating correctly.  The
    simulation results can be viewed as waveforms for easy analysis.
    JEDEC-format test vectors are also generated, and are added to the
    JEDEC file. It is not critical to do detailed internal timing
    simulations, since the placement and routing of the logic will not
    affect timing.

    To design with MACH devices using CUPL, a separate MACH package is
    required. It contains the MACH device library and a specialized
    fitter.  Included in the package is a complete MACH User's Manual
    that contains detailed information on designing with the MACH
    devices. This package can be obtained by calling Logical Devices.

   .c3.USING CUPL   WITH THE MAPL   DEVICES
    .i.MAPL;.i.FPGA;.i.device:  MAPL;If you have ever had to design a
    medium to large sized sequential state machine or controller in a
    high density PAL-type architecture or programmable gate array, you
    will be familiar with the "product term limitation", "routing", and
    "skew" problems.  By the time that you have dealt with these
    problems you have probably paid a major penalty in overall system
    performance.

    The MAPL devices address the above concerns by providing flexible,
    user-programmable architectures that utilize standard PLD
    development tools and programmer support.  The MAPL devices are a
    family of higher density programmable logic devices. All MAPL
    devices contain a core architecture of multiple interconnected
    pages, that is expandable into a more resourceful and larger
    pin-count packages.  More importantly, the delay time from any input
    to any output via any internal FPLA page is always the same for any
    given MAPL device.  A single MAPL device is also able to integrate
    multiple designs that were implemented in PAL, GAL and discrete
    logic devices.

    When creating a design for a MAPL device using CUPL, you use the
    same familiar state machine or Boolean equations as in any other
    CUPL design.  CUPL will compile this design and then call the MAPL
    fitter program. CUPL will look for the MAPL device mnemonic on the
    command line or in the PLD file header and it will call the
    appropriate fitter program.

    The MAPL fitter will synthesize the necessary logic to incorporate
    the page registers into the design logic. This will then create a
    JEDEC file which contains the completed design.

    To design with the MAPL devices and CUPL, you will need the
    CUPL/MAPL supplemental package from Logical Devices, which contains
    documentation on designing with the MAPL devices, the MAPL fitter
    program and the MAPL device library.

o   .c3.USING CUPL   WITH THE MAX   DEVICES
    .i.MAX;Altera's new Multiple Array MatriX (MAX) family offers a
    combination of logic density, performance, and flexibility that's
    tough to beat. The EPM5000 MAX series of EPLDs comprises eight
    devices with a range of densities to meet logic application needs at
    system clock rates up to 66MHz and pipeline data rates of over 100
    MHz.  A MAX solution is available for every problem--be it a 20-pin
    device ideal for high-speed address decoding and state machines, or
    a over 100 lead device that accommodates several thousand gates. And
    every MAX family member has a fully programmable architecture that
    efficiently fits any mix of TTL functions without the design and
    routing headaches commonly associated with fixed and programmable
    gate arrays.  The most important objective for the MAX architecture
    was to overcome the serious limitations of earlier PLD structures,
    which were unable to achieve higher levels of integration of
    TTL-based designs.  These limitations traditionally have included
    fixed product-term distribution, lack of register control inputs,
    and tight coupling of register and I/O pin resources, to name a few.
    .i.device:EPM5032;The EPM5032 contains 32 MAX macrocells. The
    EPM5032 expander product term array contains 64 expanders.  The I/O
    control block contains 16 bidirectional I/O pins that can be
    configured for dedicated input, dedicated output, or bidirectional
    operation.  All I/O pins feature dual-feedback for maximum pin
    flexibility.  .i.device:EPM5064;.i.devic e:EPM5128;The EPM5064 and
    EPM5128 contain 64 and 128 macrocells respectively. CUPL will
    provide both JEDEC and POF format in support of all MAX devices.
    CUPL will provide the means of implementing designs using these
    devices to most efficiently utilize the expander product terms as
    well as the large selection of macrocells within each device.

    Contact LOGICAL DEVICES, INC.  for availability dates.