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.c1. Using CSIM 2 This chapter explains how to use CSIM program to create test vectors for the programmable logic device under design. Test vectors specify the expected functional operation of a PLD by defining the outputs as a function of the inputs. Test vectors are used both for simulation of the device logic before programming and for functional testing of the device once it has been programmed. CSIM can generate JEDEC-compatible downloadable test vectors. o .c2.INPUT A test specification source file (filename.SI) is the input to CSIM. It contains a functional description of the requirements of the device in the circuit. The source file may be created using a standard text editor like DOS EDLIN or WordStar in non-document mode. The input pin stimuli and output pin test values entered in the source file are compared to the actual values calculated from the logic equations in the CUPL source file. These calculated values are contained in the absolute file (filename.ABS), which is created during CUPL operation when the -a flag on the command line is specified. The absolute file must be created during CUPL operation before running CSIM. CSIM must also be able to access the device library file, CUPL.DL, which contains a description of each of the target devices supported in the current version of CSIM. The library describes the physical characteristics of each device, including internal architecture, number of pins, and type of registers available, and the logical characteristics, including registered and non-registered pins, feedback capabilities, register power-on state and register control features. Reference the target device using device mnemonics. Each mnemonic is composed of a device family prefix and industry-standard part number suffix. Table 2-1 lists the device mnemonic prefixes. Table 2-1. CSIM Device Mnemonic Prefixes Prefix Device Family EP Erasable Programmable Logic Device (EPLD) G Generic Array Logic (GAL) F Field Programmable Logic Array (FPLA) F Field Programmable Gate Array (FPGA) F Field Programmable Logic Sequencer (FPLS) F Field Programmable Sequence Generator (FPSG) P Programmable Logic Array (PAL) P Programmable Logic Device (PLD) P Programmable Electrically Erasable Logic (PEEL) PLD Pseudo Logical Device RA Bipolar Programmable Read-Only Memory (PROM) For example, the device mnemonic for a PAL10L8 is P10L8; for an 82S100 the device mnemonic is F100. For bipolar PROMs, the suffix is the array size. For example, the device mnemonic for a 1024 x 8 bipolar PROM is RA10P8, since there are 10 address input pins and 8 data output pins. o .c2.OUTPUT The simulator output is the following two files: a simulation listing file and an optional JEDEC downloadable fuse link file. A simulation listing file (filename.SO) contains the results of the simulation. It has the same filename as the input test specification file. All header information is displayed in the listing file with any header errors marked appropriately. Each complete vector is assigned a number. Any output tests that failed are flagged with the actual (simulator-determined) output value displayed. Each variable in error is listed along with the expected (user-supplied) value. Any invalid or unexpected test values are listed along with an appropriate error message. The simulator output listing can also be output to the screen (using the -v option on the command line). An optional JEDEC downloadable fuse link file (filename.JED) contains structured test vectors. CSIM appends the test vectors to an existing filename.JED created during CUPL operation. ======================================================== Note CSIM does not support multi-device files as does CUPL. CSIM only simulates the first device of a multi-device file. ======================================================== o .c2.RUNNING CSIM Run CSIM using the following command line format: csim [-flags] [library] [device] source where -flags is the following set of simulator options: -l create listing file. -j append test vectors to JEDEC file. -n use source filename for JEDEC file. -v display simulation results to terminal. -u use specified library for simulation. -w (MS-DOS only) simulate and display output file in waveform. -d (MS-DOS only) display an existing simulation output file in waveform. library is the library name and path name if the -u flag is being used to specify a library other than the default library. device must be the same device mnemonic as was used in the CUPL compilation. Specifying the device is optional; if a device is not specified, CSIM uses the device CUPL compiled (contained in the .ABS file). source is the user-created ASCII test specification file (filename.SI). The extension .SI is assumed for the source file and may be omitted when giving the CSIM command. ======================================================== Note The square brackets indicate optional items. ======================================================== o .c3.Simulator Option Flags Multiple option flags can be specified when running CSIM. A hyphen must be used before the first flag entered, but can be omitted for subsequent flags. Spaces may also be placed between the flags. For example, the following two CSIM command lines are equivalent: csim -l -v -j p16r4 waitgen [Enter] csim -lvj p16r4 waitgen [Enter] CSIM can be typed without any flags, to see the command line format and a list of the option flags. Table 2-2 lists descriptions of the CSIM option flags. Table 2-2. Simulator Option Flags Option Flag Description -j Appends the structured test vectors generated by the simulation onto the existing JEDEC download file. -l Generates a simulation listing file (filename.SO.) The input and output values for each variable are listed. Error messages are listed following each vector, with the signal name in error displayed. -n Allows the source filename to be used as the JEDEC filename instead of using the name in the NAME field of the source file. -v Displays the contents of the listing file to the screen. When the simulation data begins to appear on the screen, type [Picture]-[ Picture] to stop the display (and any key to start it again) or [Picture] -[Picture] to cancel the simulation. -u Overrides the default device library specified in the environment . Specify the complete path and library name. This option is of particular use on systems that have special libraries created for unique or custom devices. -d (MS-DOS only) Displays an existing simulation output file in waveform. -w (MS-DOS only). Generates a simulation listing file and displays the output in waveform. o .c3.Viewing Waveform(MS-DOS) Running CSIMwith the -w or -d flag generates waveform output on the screen. The view of the waveform can be changed by using the following keys: cursor right Scroll right cursor left Scroll left cursor down Scroll down cursor up Scroll up PgUp Shift screen up PgDn Shift screen down F1 Decrease scale horizontally F2 Enlarge scale horizontally F3 Change current signal layer F4 Exit to DOS F5 Shift screen left F6 Shift screen right F7 Change signal orders F8 Group signals into bus F9 Create Waveform Hardcopy F10 Waveform Legend HOME Show/hide fixed markers INS Show/hide moving marker CNTL-cursor right Move marker to the right CNTL-cursor left Move marker to the left Any printable character key: Waveform Labels o .c4.Change Signal Order The CSIM waveform display allows signal orders to be changed. To change signals, press the F7 key. The cursor appears on the signal window instead of the waveform window. Position the cursor over the desired signal, and then press [Return] to select the signal. The selected signal is indicated as <Sel: signal-name> on the lower right portion of the screen (Refer to Figure 2-1). Move the cursor to the desired position and press the [Insert] key. The selected signal is inserted into the cursor position, and the signals below the cursor are shifted one position down. As an example, refer to Figure 2-1. [Picture] Figure 2-1. Moving a Signal [Picture] Figure 2-2. Signal After Being Moved In this figure, Result 3 is selected. Result 3 is to be placed between Numbers3 and Numbers4. Move the cursor to Numbers4 and press [Insert]. Figure 2-2 shows the result. To quit the change signal mode, press [Escape]. The cursor returns to the waveform window. o .c4.Group Signals into Bus Grouping signals into bus is another useful feature. This feature allows the grouping of up to eight signals into a bus, and the hex value can be displayed on the screen. Figure 2-3 shows the grouping of Numbers0 to Numbers7 into a bus called INPUT_BUS. [Picture] Figure 2-3. Making a Bus [Picture] Figure 2-4. Moving a Bus To group signals, first press F8, and a bus window pops up onto the screen (see Figure 3). Type the bus name INPUT_BUS at Bus1 and press [Return]. The cursor moves to the signal window. Move the cursor to Numbers0 and press [Return]. This signal is grouped into bus INPUT_BUS as the least significant bit. Now move the cursor to Numbers1 and press [Return]. This becomes the second least significant bit of INPUT_BUS. Continue this procedure until the eighth signal, Numbers7, is selected. After all signals are selected, a new bus-type signal called INPUT_BUS is placed after the last signal, as shown in Figure 2-4. If fewer than eight signals are to be grouped into a bus, press [Esc] after all the desired signals have been selected. The new bus-type signal is placed after the last signal. The maximum number of busses that can be created is four, and the maximum number of signals that can be grouped into a bus is eight. A sixteen-signal bus can be created as two busses of high-order and low-order. o .c4.Create Waveform Hardcopy The F9 function key does not cause an immediate print-out. When activated, F9 creates a file with an extension .prt. This file can then be sent to the printer. The printer must be capable of handling extended ASCII characters. o .c4.Changing Color Signal When F3 key is used it brings up a color selection window. You can select the color for the current signal (the one the cursor is currently sitting on). If the signal is not a bus, three columns of colors are displayed (correct, unstable output and error)< otherwise only one column is available. A checkmark indicates the actual colors of the signal. Select new colors by moving the prompter up, down and from one column to another with the arrow keys. Press ESC once you've completed the color selection The default colors for signals and busses can be changed by pressing END key. This causes a color selection window to be displayed; this window contains four columns of colors (correct, unstable output, error, busses). The method of selection is the same as the one discussed above. Once the selection is completed, the new default colors are saved in a configuration file: WCSIM.INI. o .c4.Fixed Markers The CSIM waveform display allows vectors to be marked; the markers are placed in the .SI file, using the $MSG"mark" directive, and are displayed on the screen as fixed vertical lines, one character wide. Use the HOME key to switch between show and hide markers. o .c4.Moving Marker The ability to display a moving marker is available. This marker can be brought to the screen by pressing the INS key. Move to the left or to the right with CTL/<- AND CTL/-> keys. Hide by pressing INS once more. The marker is displayed as a vertical line, one pixel wide. o .c4.Waveform Labeling Labels can be placed on waveforms in the following manner: - place the cursor in the waveform window on the desired signal - turn the moving marker on and place it on the desired vector - enter the character you want to use as a label The entered character will be displayed on the waveform prompted by the cursor at its intersection with the moving marker. o Saving Waveform Configuration The waveform configuration can be saved before exiting to DOS. The configuration file has the same name as the simulation input file and the "CFG" extension. Signal colors, signal order, busses, labels, scale, markers are saved and will be restored by a subsequent waveform display for the source file. o .c4.Help Menu The question mark ( ? ) key can be used to bring up the help menu. This menu provides a description of the function keys. o Waveform Legend The following figure defines the waveforms that may appear during view waveform. The waveform legend screen appears when the F10 key is depressed. [Picture] Figure 2-5. Waveform Legend o .c2.TEST SPECIFICATION FILE The test specification file (filename.SI) may be created using a text editing program. The filename is the same as the corresponding CUPL logic description source file. Put the following information into the test specification file: _ Header information _ Comments _ Variable ordering _ Base sets _ Test vectors _ Simulator directives o .c3.Header Information Header information which is entered must be identical to the information in the corresponding CUPL logic description file. If any header information is different, a warning message appears, stating that the status of the logic equations could be inconsistent with the current test vectors in the test specification file. Table 2-3 lists the keywords used for header information (see the subtopic, Header Information in Chapter 1): Table 2-3. CSIM Header Keywords PARTNO NAME REVISION DATE DESIGNER COMPANY ASSEMBLY LOCATION DEVICE FORMAT When creating a test specification file, begin by copying the contents of the corresponding CUPL source file to the test specification file, to assure proper header information. Then delete everything except the header information from the test specification file. o .c3.Comments Comments can be placed anywhere within the test specification file. Comments can be used to explain the contents of the specification file or the function of certain test vectors. A comment begins with a slash-asterisk (/*) and ends with an asterisk-slash (*/). Comments can span multiple lines and are not terminated by the end of a line. However, comments cannot be nested. o .c3.Statements CSIM provides the keywords, ORDER, BASE, and VECTORS to write statements in the source file that determine the simulation output and how it is displayed. The following sections describe how to write statements with the CUPL keywords. .c4.ORDER Statement Use the ORDER keyword to list the variables to be used in the simulation table, and to define how they are displayed. Typically, the variable names are the same as those in the corresponding CUPL logic description file. Place a colon after ORDER, separate each variable in the list with a comma, and terminate the list with a semicolon. The following is an example of an ORDER statement: ORDER: inputA, inputB, output ; Only those variables that are actually used in the simulation must be listed. The polarity of the variable name can be different than was declared in the CUPL logic description file, allowing simulation of active-LO outputs with an active-HI simulation vector. The variable names can be entered in any order; CSIM automatically creates the proper order and polarity of the resulting vector to match the requirements of the JEDEC download format for the device. When indexed variables are used in the ORDER statement, they can be expressed in list notation format. However, since the ORDER statement is already in list form, square brackets are not needed to delimit the ORDER set. The following is an example of two equivalent ORDER statements; the first statement lists all the variables, and the second is written in list form. ORDER: A0, A1, A2, A3, SELECT, !OUT0, !OUT1; ORDER: A0..3, SELECT, !OUT0..1 ; In list notation format, the polarity of the first indexed variable (!OUT0 in the above example) determines the polarity for the entire list. Bit fields that are declared in the CUPL logic description file can be referenced by their single variable name. Bit fields can also be declared in the test specification file for CSIM, using FIELD declaration statements (see Bit Field Declaration Statements in Chapter 2). The .i.simulation:field;FIELD statement must appear before the ORDER statement. The ORDER statement can be used to specify the format of the vector results in the simulator listing file (or on the screen if screen output is specified.) By default, variable values are displayed without spaces between columns. For example, the following ORDER statement ORDER: clock, input, output ; generates the following display in the output file (using sample values): 0001: C0H 0002: C1L Spaces can be inserted between columns by using the % symbol and a decimal value between 1 and 80. For example, the following ORDER statement ORDER: clock, %2, input, %2, output ; generates the following display in the output file: 0001: C 0 H 0002: C 1 L ======================================================== Note The ORDER statement must be terminated by a semicolon. ======================================================== Text can be inserted into the output file by putting a character string, enclosed by double quotes (" ",) into the ORDER statement. (Do not place text in the ORDER statement if waveform output will be used.) For example, the following ORDER statement ORDER: "Clock is ", clock, " and input is ", input, " output goes ", output ; produces the following result in the output file: 0001: Clock is C and input is 0 output goes H 0002: Clock is C and input is 1 output goes L .c4.BASE Statement In most cases, each variable in the ORDER statement (except for FIELD variables) has a corresponding single character test value that appears in the test vector table of the output file. Multiple test vector values can be represented with quoted numbers. Use single quotes for input values and double quotes for output values. Enter a BASE statement to specify how each quoted number is expanded. The format for the BASE statement is: BASE: name; where name is either octal, decimal or hex. Follow BASE with a colon. ======================================================== Note The base statement must be terminated by a semicolon. ======================================================== The default base for quoted test values is hexadecimal. The BASE statement must appear in the file before the ORDER statement. If the base is decimal or hexadecimal, quoted numbers expand to four digits; if the base is octal, they expand to three digits. For example, a test vector entered as '7' is interpreted as follows: 1 1 1 Base is octal or 0 1 1 1 Base is decimal or 0 1 1 1 Base is hex More than one hexadecimal or octal digit may be entered between quotes. For example, '563' expands to the following: 1 0 1 1 1 0 0 1 1 Base is octal or 0 1 0 1 0 1 1 0 0 0 1 1 Base is decimal or 0 1 0 1 0 1 1 0 0 0 1 1 Base is hex Quoted values may also be used with all other test values. For example, if the base is set to octal "XX" expands to X X X X X X "LL" expands to L L L L L L "45" expands to H L L H L H ======================================================== Note Quoted values cannot contain *. ======================================================== Test values for FIELD variables can be expressed either individually (for example, 001, HHLL) or with quoted values (for example, '1', "C"). When quoted values are used, the value is automatically expanded to the number of variables in the field. For example, for the following address field FIELD address = [A0..5] ; A test value of /* A A A A A A 5 4 3 2 1 0 --------------------------------*/ 1 1 1 0 0 1 could be written using single test values, or'39' using quoted test values. .c4.VECTORS Statement Use the VECTORS keyword to prefix the test vector table. Following the keyword, include test vectors made up of single test values or quoted test values (see the subtopic, Base Statement in this chapter). Each vector must be contained on a single line. No semicolons follow the vector. Table 2-4 lists allowable test vector values. Table 2-4. Test Vector Values Test Value Description 0 Drive input LO (0 volts) (negate active-HI input) 1 Drive input HI (+5 volts) (assert active-HI input) C Drive (clock) input LO, HI, LO K Drive (clock) input HI, LO, HI L Test output LO (0 volts) (active-HI output negated) H Test output HI (+5 volts) (active-HI output asserted) Z Test output for high impedance X Input HI or LO, output HI or LO. NOTE: Not all device programmers treat X on inputs the same; some put it to 0, some allow input to be pulled to 1, and some leave it at the previous value. N Output not tested P Preload internal registers (value is applied to !Q output) * Outputs only -simulator determines test value and substitutes in vector '' Enclose input values to be expanded to a specified BASE (octal, decimal, or hex). Valid values are 0-F and X. "" Enclose output values to be expanded to a specified BASE (octal, decimal, or hex.) Valid values are 0-F, H, L, Z, and X. The following is an example of a test vector table: VECTORS: 0 0 1 1 1 'F' Z "H" /* test outputs HI */ 0 1 1 0 0 '0' Z "L" /* test outputs LO */ Unlike many other simulators, CSIM treats the DON'T-CARE (state X) as any other value. State X is not assumed to be 0 on input and N on the output. The X state allows specific determination of which inputs affect the output value, according to the rules listed in the truth tables in Figure 2-6. [Picture] Figure 2-6. Vector Truth Tables .c4.Preload Use the P test value on the clock pin of a registered device to preload internal registers of a state machine or counter design to a known state, if the device does not have a dedicated TTL-level preload pin. The device programmer uses a supervoltage to actually load the registers. All input pins to the device are ignored and hence should be defined as X. The values that appear for registered variables are loaded into the !Q output of the register. These values (0 or 1) are absolute levels and are not affected by output polarity nor inverting buffers. The following is an example of a preload sequence for an active-LO output variable in a device with an inverting buffer between the register Q output and device pin: ORDER: clock, input1, input2 , !output ; VECTORS: P X X 1 /* reset flip-flop */ /* !Q goes to 1 */ /* Q goes to 0 */ 0 X X H /* output is HI due to */ /* inverting buffer */ ======================================================== Note CSIM can simulate and generate preload test vectors even for devices that do not have preload capability. However, not all PLDs are capable of preload using a supervoltage. Some devices have dedicated preload pins to use for this purpose. CSIM does not verify whether the device under simulation is actually capable of preload because parts from different manufacturers exhibit different characteristics. Before using the preload capability, determine whether the device being tested is physically capable of supervoltage preloading. ======================================================== .c4.Clocks Most synchronous devices (devices containing registers with a common clock tied to an output pin) use an active-HI (positive edge triggered) clock. To assure proper CSIM operation for these devices, always use a C test value (not a 1 or 0) on the clock pin. For synchronous devices with an active-LO (negative edge triggered) clock, use the K test value on the clock pin. .c4.Asynchronous Vectors When writing test vectors for a circuit with asynchronous feedback, changing two test values at once can create a spike condition that produces anomalous results. (See Figure 2-7. It shows the diagram for a circuit with three inputs [A, B, and C] and an output at Y that feeds back.) [Picture] Figure 2-7. Circuit with Feedback The equation for the output at Y is as follows: Y = A & B & C # C & Y The vectors table in Figure 2-8 shows an expected low output at Y based on the specified input values. [Picture] Figure 2-8. Vectors Table for Circuit with Feedback Because one of the inputs is 0 in each of the vectors, the AND gate defined by A, B, and C produces a low output. The low value feeding back from the Y output keeps the other AND gate low also. Therefore, the OR gate (driven by the output of the two AND gates) and consequently the output at Y remain low for the specified test vectors. However, when the programmer operates on the test vectors, it applies values serially, beginning with the first pin. Because two test values change between vectors, the programmer creates intermediate results (labeled "a" in Figure 2-9). [Picture] Figure 2-9. Vectors Table with Intermediate Results The intermediate result, [0002a], produces a high value for the output at Y. This high value feeds back and combines with the "1" value specified for input C in vector [0003] to produce a high output for the AND gate and consequently for the OR gate and for the output at Y. This high value conflicts with the expected low value specified in the third test vector, and the result is a spike condition. By taking care to always change only one value between test vectors, the spike condition described above can be avoided. Also, in the source specification file, it is possible to specify a TRACE value of 1, 2, or 3 (rather than the default value of 0) that instructs CSIM to display intermediate results in the output file (see "TRACE" in the following section, Simulator Directives). .c4.I/O Pin simulation When writing test vectors for a design that has input/output capability and a controllable output enable (OE), the test vector value placed at the I/O pin will depend on the value of the output enable. If the output enable is active, the I/O pin needs an output test value (L, H, *,...). If the output enable becomes inactive, a Hi-Z (Z) will appear on the I/O pin. At this time, input test values (0, 1, ...) can be placed on the I/O pin allowing that pin to behave as an input pin. When the output enable is activated again, the test values for that pin will reflect the output of the macrocell. [Picture] Figure 2-10. I/O Pin Simulation The following equations express the boolean equation representation of Figure 2-10: Y = B; Y.OE = A; When A is TRUE, the output of the macrocell (B) will appear at the pin (Y). When A is FALSE, the output enable will be deactivated and a Hi-Z will appear at the pin (Y). After the output enable is deactivated, input values can be placed on the pin. Here is an example of what the simulation file will look like: Order: A, %1, B, %3, Y; Vectors: 1 0 L /* OE is ON */ 1 1 H 0 0 Z /* OE is OFF */ 0 0 1 /* a valid input value can be placed on pin Y */ 1 0 L /* OE is ON again */ o .c3.Simulator Directives CSIM provides six directives that can be placed on any row of the file after the VECTOR statement. All directive names begin with a dollar sign and each directive statement must end with a semicolon. Table 2-5 lists the CSIM directives. Table 2-5. CSIM Directives $MSG $REPEAT $TRACE $SIMOFF $SIMON $EXIT .c4.$MSG Use the $MSG directive to place documentation messages or formatting information into the simulator output file. For example, a header for the simulator function table, listing the variable names, may be created. The format is as follows: $MSG "any text string" ; In the output table, the text string appears without the double quotes. Blank lines can be inserted into the output, for example, between vectors, by using the following format: $MSG "" ; The $MSG directive can be also used to place markers in the simulator output file. The markers will be displayed on the screen at display waveform time (if the "w" flag was set). To mark a vector, place the following statement on the line preceding the vector to be marked: $MSG"mark" .c4.$REPEAT The $REPEAT directive causes a vector to be repeated a specified number of times. Its format is: $REPEAT n ; where n is a decimal value between 1 and 9999. The vector following the $REPEAT directive is repeated the specified number of times. The $REPEAT directive is particularly useful for testing counters and state transitions. Use the asterisk (*) to represent output test values supplied by CSIM. The following example shows a a 2-bit counter from a CUPL source file, and a VECTORS statement using the $REPEAT directive to test it. From CUPL: Q0.d = !Q0 ; Q1.d = !Q1 & Q0 # Q1 & !Q0 ; In CSIM: ORDER: clock, input, Q1, Q0 ; VECTORS: 0 0 X X /* power-on condition */ P X 1 1 /* reset the flip-flops */ 0 0 H H $REPEAT 4 ; /* clock 4 times */ C 0 * * The above file generates the following test vectors: 0 0 X X P X 1 1 0 0 H H C 0 L L C 0 L H C 0 H L C 0 H H CSIM supplies four sets of vector values. .c4.$TRACE Use the $TRACE directive to set the amount of information that CSIM prints for the vectors during simulation. The format is $TRACE n ; where n is a decimal value between 0 and 4. Trace level 0 (the default) turns off any additional information and only the resulting test vectors are printed. When non-registered feedback is used in a design, the value for the output feeding back is unknown for the first evaluation pass of the vector. If the new feedback value changes any output value, the vector is evaluated again. All outputs must be identical for two passes before the vector is determined to be stable. Trace level 1 prints the intermediate results for any vector that requires more than one evaluation pass to become stable. Any vector that requires more than twenty evaluation passes is considered unstable. Trace level 2 identifies three phases of simulation for designs using registers. The first phase is "Before the Clock," where intermediate vectors using non-registered feedback are resolved. The second phase is "At the Clock," where the values of the registers are given immediately after the clock. The third phase is "After the Clock," where the outputs utilizing feedback are resolved as in trace level 1. Trace level 3 provides the highest level of display information possible from CSIM. Each simulation phase of "Before Clock," "At Clock," and "After Clock" is printed and the individual product term for each variable is listed. The output value for the AND gate is listed along with the value of the inputs to the AND array. Trace level 4 provides the ability to watch the logical value before the output buffer. Using $TRACE 4, CSIM only reports the true output pin values, and assigns a "?" to inputs and buried nodes. For combinatorial output, trace level 4 displays the results of the OR term. For registered outputs, trace level 4 shows the Q output of the register. The following example uses a p22v10: pin 1 = CLK; pin 2 = IN2; pin 3 = IN3; .... pin 14 = OUT14; pin 15 = OUT15; .... OUT14.D = IN2; OUT14.AR = IN3; OUT14.OE = IN4; .... Figure 2-11. Using P22V10. Figure 2-12 shows the simulation result file: order CLK, IN2, IN3, IN4, OUT14, OUT15; ****** before output buffer ****** ???? ..LL...0001: 0011 ..HH........ ******before output buffer****** ???? HH...0004 C100 ...ZZ..... Figure 2-12. Simulation File. Figure 2-13 shows the virtual observation points when using trace level 4 with either a combinatorial configuration or a register configuration. [Picture] Figure 2-13. Observation Points Using Trace Level 4. .c4.$EXIT Use the $EXIT directive to abort the simulation at any point. Test vectors appearing after the $EXIT directive are ignored. This directive is useful in debugging registered designs in which a false transition in one vector causes an error in every vector thereafter. Placing a $EXIT command after the vector in error directs attention to the true problem, instead of to the many false errors caused by the incorrect transition. .c4.$SIMOFF Use the $SIMOFF simulator directive to turn off test vector evaluation. Test vectors appearing after the $SIMOFF directive are only evaluated for invalid test values and the correct number of test values. This directive is useful in testing asynchronously clocked designs in which CSIM is unable to correctly evaluate registered outputs. .c4.$SIMON Use the $SIMON simulator directive to cancel the effects of the $SIMOFF directive. Test vectors appearing after the $SIMON directive are evaluated fully. o .c3.Fault Simulation An internal fault can be simulated for any product term, to determine fault coverage for the test vectors. The format for this option is as follows: STUCKL n ; or STUCKH n ; where n is the JEDEC fuse number for the first fuse in the product term. The documentation file (filename.DOC) fuse map lists the fuse numbers for the first fuse in each product term in the device. Format 1 forces the product term to be stuck-at-0. Format 2 forces the product term to be stuck-at-1. The STUCK command must be placed between the ORDER and VECTORS statements.