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Chip 2011 November
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SpeedFan
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STRING
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4060.txt
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2011-07-13
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W3rd level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sectorI1st level data cache: 32 KBytes, 8-way set associative, 64 byte line sizeP1st level instruction cache: 32 KBytes, 8-way set associative, 64 byte line sizeU2nd-level cache: 128 KBytes, 4-way set associative, sectored cache, 64-byte line sizeU2nd-level cache: 192 KBytes, 6-way set associative, sectored cache, 64-byte line sizeU2nd-level cache: 128 KBytes, 2-way set associative, sectored cache, 64-byte line sizeU2nd-level cache: 256 KBytes, 4-way set associative, sectored cache, 64-byte line sizeU2nd-level cache: 384 KBytes, 6-way set associative, sectored cache, 64-byte line sizeU2nd-level cache: 512 KBytes, 4-way set associative, sectored cache, 64-byte line sizeXNo 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cacheE2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line sizeE2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line sizeE2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line sizeC2nd-level cache: 1 MBytes, 4-way set associative, 32 byte line sizeC2nd-level cache: 2 MBytes, 4-way set associative, 32 byte line sizeC3rd-level cache: 4 MBytes, 4-way set associative, 64 byte line size