GameStar 2005 May/Gamestar_73_2005-05_dvd.iso/Programy/ATITool_0.0.23.exe/ATITool.exe/1031/BINARY/50011

Text File | 2005-01-10 | 4KB | 280 lines

R480

MEM_TRCDRD
0x144
3:0
Activate to Read, RAS to CAS Read delay.
COMBO
3 clock=0x0
4 clocks=0x1
5 clocks=0x2
6 clocks=0x3
7 clocks=0x4
8 clocks=0x5
9 clocks=0x6
10 clocks=0x7
11 clocks=0x8
12 clocks=0x9
13 clocks=0xa
14 clocks=0xb
15 clocks=0xc
Reserved=0xd
Reserved=0xe
Reserved=0xf

MEM_TRCDWR
0x144
7:4
Activate to Write, RAS to CAS Write delay.
COMBO
1 clock=0x0
2 clocks=0x1
3 clocks=0x2
4 clocks=0x3
5 clocks=0x4
6 clocks=0x5
7 clocks=0x6
8 clocks=0x7
9 clocks=0x8
10 clocks=0x9
11 clocks=0xa
12 clocks=0xb
13 clocks=0xc
14 clocks=0xd
15 clocks=0xe
Reserved=0xf

MEM_TRP
0x144
11:8
Precharge to Activate/Refresh, Row Precharge Time.
COMBO
3 clock=0x0
4 clocks=0x1
5 clocks=0x2
6 clocks=0x3
7 clocks=0x4
8 clocks=0x5
9 clocks=0x6
10 clocks=0x7
11 clocks=0x8
12 clocks=0x9
13 clocks=0xa
14 clocks=0xb
15 clocks=0xc
Reserved=0xd
Reserved=0xe
Reserved=0xf

MEM_TRAS
0x144
16:12
Activate to Precharge, ROW active time.
COMBO
6 clocks=0x0
7 clocks=0x1
8 clocks=0x2
9 clocks=0x3
10 clocks=0x4
11 clocks=0x5
12 clocks=0x6
13 clocks=0x7
14 clocks=0x8
15 clocks=0x9
16 clocks=0xa
17 clocks=0xb
18 clocks=0xc
19 clocks=0xd
20 clocks=0xe
21 clocks=0xf
22 clocks=0x10
23 clocks=0x11
24 clocks=0x12
25 clocks=0x13
26 clocks=0x14
27 clocks=0x15
28 clocks=0x16
29 clocks=0x17
30 clocks=0x18
31 clocks=0x19
Reserved=0x1a
Reserved=0x1b
Reserved=0x1c
Reserved=0x1d
Reserved=0x1e
Reserved=0x1f

MEM_TRRD
0x144
19:17
Activate to Activate (other bank), Row active to row active command period.
COMBO
2 clock=0x0
3 clocks=0x1
4 clocks=0x2
5 clocks=0x3
6 clocks=0x4
7 clocks=0x5
8 clocks=0x6
9 clocks=0x7

MEM_TWR
0x144
23:20
Write to Precharge, Write Recovery Time.
COMBO
1 clock=0x0
2 clocks=0x1
3 clocks=0x2
4 clocks=0x3
5 clocks=0x4
6 clocks=0x5
7 clocks=0x6
8 clocks=0x7
9 clocks=0x8
10 clocks=0x9
11 clocks=0xa
12 clocks=0xb
13 clocks=0xc
14 clocks=0xd
15 clocks=0xe
Reserved=0xf

MEM_TR2W
0x144
25:24
Read to Write Turnaround Time
COMBO
CL+2 clock=0x0
CL+3 clocks=0x1
CL+4 clocks=0x2
CL+5 clocks=0x3

MEM_TW2R
0x144
28:26
Write to Read Turnaround Time.
COMBO
1 clock=0x0
2 clocks=0x1
3 clocks=0x2
4 clocks=0x3
5 clocks=0x4
6 clocks=0x5
7 clocks=0x6
8 clocks=0x7

MEM_TW2R_SAME_BANK
0x144
29:29
Write to Read Turnaround Time for the same Bank.
COMBO
Use TW2R Rule=0x0
Use TWR Rule=0x1

MEM_TR2R
0x144
31:30
Read to Read Turnaround Time, different banks.
COMBO
1 clock=0x0
2 clocks=0x1
3 clocks=0x2
4 clocks=0x3

MEM_WR_LATENCY
0x158
19:16
Defines the delay period between the memory Write Command and appearance of Data and Data Mask on MC I/O pins.
COMBO
0   clocks=0x0
0.5 clock=0x1
1.0 clock=0x2
1.5 clocks=0x3
2.0 clocks=0x4
2.5 clocks=0x5
3.0 clocks=0x6
3.5 clocks=0x7
4.0 clocks=0x8
4.5 clocks=0x9
5.0 clocks=0xa
5.5 clocks=0xb
6.0 clocks=0xc
6.5 clocks=0xd
7.0 clocks=0xe
7.5 clocks=0xf

MEM_CAS_LATENCY
0x158
22:20
CAS Latency
COMBO
3 clocks=0x0
4 clocks=0x1
5 clocks=0x2
6 clocks=0x3
7 clocks=0x4
8 clocks=0x5
9 clocks=0x6
10 clocks=0x7

MEM_CMD_LATENCY
0x158
23:23
Command Latency
COMBO
0 clocks=0x0
1/2 clock=0x1

MEM_STR_LATENCY
0x158
24:24
Defines the delay period during the Write cycle, between the rising edge of the memory clk and the appearance of the QS signals on MC I/O pins.
COMBO
WR Latency=0x0
WR Latency + 1/2 CLK=0x1

MEM_REFRESH_RATE
0x178
7:0
ROW refresh will be performed to all banks every 64 MCLKs * REFRESH_RATE in all channels.
EDIT

MEM_TRFC
0x178
15:11
Refresh Row Cycle Time.
COMBO
13 clocks=0x0
14 clocks=0x1
15 clocks=0x2
16 clocks=0x3
17 clocks=0x4
18 clocks=0x5
19 clocks=0x6
20 clocks=0x7
21 clocks=0x8
22 clocks=0x9
23 clocks=0xa
24 clocks=0xb
25 clocks=0xc
26 clocks=0xd
27 clocks=0xe
28 clocks=0xf
29 clocks=0x10
30 clocks=0x11
31 clocks=0x12
32 clocks=0x13
33 clocks=0x14
34 clocks=0x15
35 clocks=0x16
36 clocks=0x17
37 clocks=0x18
38 clocks=0x19
39 clocks=0x1a
40 clocks=0x1b
41 clocks=0x1c
42 clocks=0x1d
43 clocks=0x1e
44 clocks=0x1f