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Assembly Source File | 1993-01-20 | 103.3 KB | 2,827 lines

; **************************************************************************** ; * * ; * 6510.ASM - 386 6510 emulator * ; * * ; * R.F. van Ee (1993) * ; * * ; **************************************************************************** .model small .386c ; **************************************************************************** ; Includes include 6510.INC ; **************************************************************************** ; Labels .data public Int_Flags public OpCodes public _A public _X public _Y public _Flags public _PC public _SP extrn _WriteTable extrn _ReadTable .code public _Emul6510 public _6510Quit public Interrupt extrn Start extrn ZPWrite ; **************************************************************************** ; Opcode jump table .data OpCodes dw BRK ; 00 dw ORA_IND_X ; 01 dw KIL ; 02 dw SLO_IND_X ; 03 dw DOP ; 04 dw ORA_ZP ; 05 dw ASL_ZP ; 06 dw SLO_ZP ; 07 dw PHP ; 08 dw ORA_IMM ; 09 dw ASL_A ; 0A dw ANC_IMM ; 0B dw TOP ; 0C dw ORA_ABS ; 0D dw ASL_ABS ; 0E dw SLO_ABS ; 0F dw BPL ; 10 dw ORA_IND_Y ; 11 dw KIL ; 12 dw SLO_IND_Y ; 13 dw DOP ; 14 dw ORA_ZP_X ; 15 dw ASL_ZP_X ; 16 dw SLO_ZP_X ; 17 dw CLC_ ; 18 dw ORA_ABS_Y ; 19 dw NOP_ ; 1A dw SLO_ABS_Y ; 1B dw TOP ; 1C dw ORA_ABS_X ; 1D dw ASL_ABS_X ; 1E dw SLO_ABS_X ; 1F dw JSR ; 20 dw AND_IND_X ; 21 dw KIL ; 22 dw RLA_IND_X ; 23 dw BIT_ZP ; 24 dw AND_ZP ; 25 dw ROL_ZP ; 26 dw RLA_ZP ; 27 dw PLP ; 28 dw AND_IMM ; 29 dw ROL_A ; 2A dw ANC_IMM ; 2B dw BIT_ABS ; 2C dw AND_ABS ; 2D dw ROL_ABS ; 2E dw RLA_ABS ; 2F dw BMI ; 30 dw AND_IND_Y ; 31 dw KIL ; 32 dw RLA_IND_Y ; 33 dw DOP ; 34 dw AND_ZP_X ; 35 dw ROL_ZP_X ; 36 dw RLA_ZP_X ; 37 dw SEC ; 38 dw AND_ABS_Y ; 39 dw NOP_ ; 3A dw RLA_ABS_Y ; 3B dw TOP ; 3C dw AND_ABS_X ; 3D dw ROL_ABS_X ; 3E dw RLA_ABS_X ; 3F dw RTI ; 40 dw EOR_IND_X ; 41 dw KIL ; 42 dw SRE_IND_X ; 43 dw DOP ; 44 dw EOR_ZP ; 45 dw LSR_ZP ; 46 dw SRE_ZP ; 47 dw PHA ; 48 dw EOR_IMM ; 49 dw LSR_A ; 4A dw ASR_IMM ; 4B dw JMP_ABS ; 4C dw EOR_ABS ; 4D dw LSR_ABS ; 4E dw SRE_ABS ; 4F dw BVC ; 50 dw EOR_IND_Y ; 51 dw KIL ; 52 dw SRE_IND_Y ; 53 dw DOP ; 54 dw EOR_ZP_X ; 55 dw LSR_ZP_X ; 56 dw SRE_ZP_X ; 57 dw CLI_ ; 58 dw EOR_ABS_Y ; 59 dw NOP_ ; 5A dw SRE_ABS_Y ; 5B dw TOP ; 5C dw EOR_ABS_X ; 5D dw LSR_ABS_X ; 5E dw SRE_ABS_X ; 5F dw RTS ; 60 dw ADC_IND_X ; 61 dw KIL ; 62 dw RRA_IND_X ; 63 dw DOP ; 64 dw ADC_ZP ; 65 dw ROR_ZP ; 66 dw RRA_ZP ; 67 dw PLA ; 68 dw ADC_IMM ; 69 dw ROR_A ; 6A dw ARR_IMM ; 6B dw JMP_IND ; 6C dw ADC_ABS ; 6D dw ROR_ABS ; 6E dw RRA_ABS ; 6F dw BVS ; 70 dw ADC_IND_Y ; 71 dw KIL ; 72 dw RRA_IND_Y ; 73 dw DOP ; 74 dw ADC_ZP_X ; 75 dw ROR_ZP_X ; 76 dw RRA_ZP_X ; 77 dw SEI ; 78 dw ADC_ABS_Y ; 79 dw NOP_ ; 7A dw RRA_ABS_Y ; 7B dw TOP ; 7C dw ADC_ABS_X ; 7D dw ROR_ABS_X ; 7E dw RRA_ABS_X ; 7F dw DOP ; 80 dw STA_IND_X ; 81 dw DOP ; 82 dw SAX_IND_X ; 83 dw STY_ZP ; 84 dw STA_ZP ; 85 dw STX_ZP ; 86 dw SAX_ZP ; 87 dw DEY ; 88 dw DOP ; 89 dw TXA ; 8A dw AXA_IMM ; 8B dw STY_ABS ; 8C dw STA_ABS ; 8D dw STX_ABS ; 8E dw SAX_ABS ; 8F dw BCC ; 90 dw STA_IND_Y ; 91 dw KIL ; 92 dw SAH_IND_Y ; 93 dw STY_ZP_X ; 94 dw STA_ZP_X ; 95 dw STX_ZP_Y ; 96 dw SAX_ZP_Y ; 97 dw TYA ; 98 dw STA_ABS_Y ; 99 dw TXS ; 9A dw SSH_ABS_Y ; 9B dw SYH_ABS_X ; 9C dw STA_ABS_X ; 9D dw SXH_ABS_Y ; 9E dw SAH_ABS_Y ; 9F dw LDY_IMM ; A0 dw LDA_IND_X ; A1 dw LDX_IMM ; A2 dw LAX_IND_X ; A3 dw LDY_ZP ; A4 dw LDA_ZP ; A5 dw LDX_ZP ; A6 dw LAX_ZP ; A7 dw TAY ; A8 dw LDA_IMM ; A9 dw TAX ; AA dw LAX_IMM ; AB dw LDY_ABS ; AC dw LDA_ABS ; AD dw LDX_ABS ; AE dw LAX_ABS ; AF dw BCS ; B0 dw LDA_IND_Y ; B1 dw KIL ; B2 dw LAX_IND_Y ; B3 dw LDY_ZP_X ; B4 dw LDA_ZP_X ; B5 dw LDX_ZP_Y ; B6 dw LAX_ZP_Y ; B7 dw CLV_ ; B8 dw LDA_ABS_Y ; B9 dw TSX ; BA dw AST_ABS_Y ; BB dw LDY_ABS_X ; BC dw LDA_ABS_X ; BD dw LDX_ABS_Y ; BE dw LAX_ABS_Y ; BF dw CPY_IMM ; C0 dw CMP_IND_X ; C1 dw DOP ; C2 dw DCP_IND_X ; C3 dw CPY_ZP ; C4 dw CMP_ZP ; C5 dw DEC_ZP ; C6 dw DCP_ZP ; C7 dw INY ; C8 dw CMP_IMM ; C9 dw DEX ; CA dw ASX_IMM ; CB dw CPY_ABS ; CC dw CMP_ABS ; CD dw DEC_ABS ; CE dw DCP_ABS ; CF dw BNE ; D0 dw CMP_IND_Y ; D1 dw KIL ; D2 dw DCP_IND_Y ; D3 dw DOP ; D4 dw CMP_ZP_X ; D5 dw DEC_ZP_X ; D6 dw DCP_ZP_X ; D7 dw CLD_ ; D8 dw CMP_ABS_Y ; D9 dw NOP_ ; DA dw DCP_ABS_Y ; DB dw TOP ; DC dw CMP_ABS_X ; DD dw DEC_ABS_X ; DE dw DCP_ABS_X ; DF dw CPX_IMM ; E0 dw SBC_IND_X ; E1 dw DOP ; E2 dw ISC_IND_X ; E3 dw CPX_ZP ; E4 dw SBC_ZP ; E5 dw INC_ZP ; E6 dw ISC_ZP ; E7 dw INX ; E8 dw SBC_IMM ; E9 dw NOP_ ; EA dw SBC_IMM ; EB dw CPX_ABS ; EC dw SBC_ABS ; ED dw INC_ABS ; EE dw ISC_ABS ; EF dw BEQ ; F0 dw SBC_IND_Y ; F1 dw KIL ; F2 dw ISC_IND_Y ; F3 dw DOP ; F4 dw SBC_ZP_X ; F5 dw INC_ZP_X ; F6 dw ISC_ZP_X ; F7 dw SED ; F8 dw SBC_ABS_Y ; F9 dw NOP_ ; FA dw ISC_ABS_Y ; FB dw TOP ; FC dw SBC_ABS_X ; FD dw INC_ABS_X ; FE dw ISC_ABS_X ; FF ; **************************************************************************** ; _Emul6510: the 6510 emulator .data Int_Flags db 000h ; b0 = IRQ; b1 = NMI _A db 000h _X db 000h _Y db 000h _Flags db 024h ; Interrupts disabled _SP dw 001ffh _PC dw BOOTOFFSET .code _Emul6510 proc near sub ebx,ebx ; Clear ebx mov ch,byte ptr _A ; Load accumulator mov cl,byte ptr _X ; Load X register mov dl,byte ptr _Y ; Load Y register mov si,word ptr _PC ; Load PC mov bp,word ptr _SP ; Load SP cld Encode_Flags _Flags ; Load flags: 6510 -> emulator Fetch ; Fetch first instruction _6510Quit: Decode_Flags al ; Emulator -> 6510 mov byte ptr _A,ch mov byte ptr _X,cl mov byte ptr _Y,dl mov byte ptr _Flags,al mov word ptr _PC,si mov word ptr _SP,bp ret _Emul6510 endp ; **************************************************************************** ; 6510 interrupt handler align 4 Interrupt proc near cmp byte ptr Int_Flags,NMI_Flag jae NMI Interrupt endp ; **************************************************************************** ; 6510 IRQ handler IRQ proc near test dh,CPU_I ; IRQ enabled? jz IRQ_enabled ; Yes mov bl,es:[si] ; Get opcode (bh = 0 already) inc si ; PC++ jmp word ptr [ebx][ebx] ; Jump to opcode routine align 4 IRQ_enabled: Push_Int ; Push PC and P mov si,es:[IRQ_VECTOR] or dh,CPU_I ; Disable interrupts and byte ptr Int_Flags,Not (IRQ_Flag) ; Clear IRQ flag mov bl,es:[si] ; Get opcode inc si ; PC++ jmp word ptr [ebx][ebx] ; Jump to opcode routine IRQ endp ; **************************************************************************** ; 6510 NMI handler align 4 NMI proc near Push_Int ; Push PC and P mov si,es:[NMI_VECTOR] or dh,CPU_I ; Disable interrupts and byte ptr Int_Flags,Not (NMI_Flag) ; Clear NMI flag Fetch ; Fetch next instruction NMI endp ; **************************************************************************** ; Opcode routines align 4 ANC_IMM proc near and ch,es:[si] lahf and dh,Not (CPU_N + CPU_Z + CPU_C) and ah,CPU_N + CPU_Z or dh,ah rol ah,1 inc si and ah,CPU_C or dh,ah Fetch ANC_IMM endp align 4 ADC_ABS proc near Read_ABS OpADC ADC_ABS endp align 4 ADC_ZP proc near Read_ZP al OpADC ADC_ZP endp align 4 ADC_IMM proc near Read_IMM al OpADC ADC_IMM endp align 4 ADC_ABS_X proc near Read_ABS_X OpADC ADC_ABS_X endp align 4 ADC_ABS_Y proc near Read_ABS_Y OpADC ADC_ABS_Y endp align 4 ADC_IND_X proc near Read_IND_X OpADC ADC_IND_X endp align 4 ADC_IND_Y proc near Read_IND_Y OpADC ADC_IND_Y endp align 4 ADC_ZP_X proc near Read_ZP_X al OpADC ADC_ZP_X endp align 4 AND_ABS proc near Read_ABS and ch,al Flgnz Fetch AND_ABS endp align 4 AND_ZP proc near mov bl,es:[si] inc si and ch,es:[bx] Flgnz Fetch AND_ZP endp align 4 AND_IMM proc near and ch,es:[si] Flgnz inc si Fetch AND_IMM endp align 4 AND_ABS_X proc near Read_ABS_X and ch,al Flgnz Fetch AND_ABS_X endp align 4 AND_ABS_Y proc near Read_ABS_Y and ch,al Flgnz Fetch AND_ABS_Y endp align 4 AND_IND_X proc near Read_IND_X and ch,al Flgnz Fetch AND_IND_X endp align 4 AND_IND_Y proc near Read_IND_Y and ch,al Flgnz Fetch AND_IND_Y endp align 4 AND_ZP_X proc near mov bl,es:[si] add bl,cl inc si and ch,es:[bx] Flgnz Fetch AND_ZP_X endp align 4 ARR_IMM proc near mov ah,dh and ch,es:[si] ; AND # and dh,Not (CPU_N + CPU_V + CPU_Z + CPU_C) sahf rcr ch,1 ; ROR inc ch ; RCR doesn't affect inc si dec ch ; the N and Z flags jnz ARR_IMM1 or dh,CPU_Z ; Set Z flag Fetch align 4 ARR_IMM1: mov al,ch shr al,1 xor al,ch shr al,2 ; Shift to V position and al,CPU_V or dh,al ; Set V flag mov al,ch shl al,2 adc dh,0 ; Set C flag mov al,ch and al,CPU_N or dh,al ; Set N flag Fetch ARR_IMM endp align 4 ASL_A proc near add ch,ch Flgnzc Fetch ASL_A endp align 4 ASL_ABS proc near Read_ABS add al,al Flgnzc RMW_write ASL_ABS endp align 4 ASL_ZP proc near mov bl,es:[si] inc si mov al,es:[bx] add es:[bx],al Flgnzc Fetch ASL_ZP endp align 4 ASL_ABS_X proc near Read_ABS_X add al,al Flgnzc RMW_write ASL_ABS_X endp align 4 ASL_ZP_X proc near mov bl,es:[si] add bl,cl mov al,es:[bx] inc si add es:[bx],al Flgnzc Fetch ASL_ZP_X endp align 4 ASR_IMM proc near and ch,es:[si] ; AND # shr ch,1 ; LSR Flgnzc inc si Fetch ASR_IMM endp align 4 AST_ABS_Y proc near Read_ABS_Y and ax,bp ; And with stack register mov ah,01h mov bp,ax ; Store in stack reg, mov ch,al ; accu and mov cl,al ; x reg or ch,ch ; Set flags Flgnz Fetch AST_ABS_Y endp align 4 ASX_IMM proc near and cl,ch ; AND X,A sub cl,es:[si] cmc Flgnzc ; V unaffected! inc si Fetch ASX_IMM endp align 4 AXA_IMM proc near mov ch,cl ; TXA and ch,es:[si] ; AND # Flgnz inc si Fetch AXA_IMM endp align 4 BCC proc near test dh,CPU_C jnz BCC_DontJump movsx ax,byte ptr es:[si] add si,ax BCC_DontJump: inc si Fetch BCC endp align 4 BCS proc near test dh,CPU_C jz BCS_DontJump movsx ax,byte ptr es:[si] add si,ax BCS_DontJump: inc si Fetch BCS endp align 4 BEQ proc near test dh,CPU_Z jz BEQ_DontJump movsx ax,byte ptr es:[si] add si,ax BEQ_DontJump: inc si Fetch BEQ endp align 4 BIT_ABS proc near Read_ABS and dh,Not (CPU_N + CPU_V + CPU_Z) ; Reset N, V and Z flags test al,ch jnz BIT_ABS_nz or dh,CPU_Z ; Set Z flag BIT_ABS_nz: mov ah,al and ah,CPU_N ; Keep nothing but bit 7 or dh,ah ; Set N flag if necessary shr al,3 ; Shift bit 6 to V position and al,CPU_V ; Keep nothing but bit 3 or dh,al ; Set V flag if necessary Fetch BIT_ABS endp align 4 BIT_ZP proc near Read_ZP al and dh,Not (CPU_N + CPU_V + CPU_Z) ; Reset N, V and Z flags test al,ch jnz BIT_ZP_nz or dh,CPU_Z ; Set Z flag BIT_ZP_nz: mov ah,al and ah,CPU_N ; Keep nothing but bit 7 or dh,ah ; Set N flag if necessary shr al,3 ; Shift bit 6 to V position and al,CPU_V ; Keep nothing but bit 3 or dh,al ; Set V flag if necessary Fetch BIT_ZP endp align 4 BMI proc near test dh,CPU_N jz BMI_DontJump movsx ax,byte ptr es:[si] add si,ax BMI_DontJump: inc si Fetch BMI endp align 4 BNE proc near test dh,CPU_Z jnz BNE_DontJump movsx ax,byte ptr es:[si] add si,ax BNE_DontJump: inc si Fetch BNE endp align 4 BPL proc near test dh,CPU_N jnz BPL_DontJump movsx ax,byte ptr es:[si] add si,ax BPL_DontJump: inc si Fetch BPL endp align 4 BRK proc near inc si ; Advance PC one more address or dh,CPU_B ; Set B flag Push_Int ; Push PC and flags and dh,Not (CPU_B) ; Reset B flag again mov si,es:[IRQ_VECTOR] or dh,CPU_I ; Disable interrupts mov bl,es:[si] ; Get opcode inc si ; PC++ jmp word ptr [ebx][ebx] ; Jump to opcode routine BRK endp align 4 BVC proc near test dh,CPU_V jnz BVC_DontJump movsx ax,byte ptr es:[si] add si,ax BVC_DontJump: inc si Fetch BVC endp align 4 BVS proc near test dh,CPU_V jz BVS_DontJump movsx ax,byte ptr es:[si] add si,ax BVS_DontJump: inc si Fetch BVS endp align 4 CLC_ proc near and dh,Not (CPU_C) Fetch CLC_ endp align 4 CLD_ proc near and dh,Not (CPU_M) Fetch CLD_ endp align 4 CLI_ proc near and dh,Not (CPU_I) Fetch CLI_ endp align 4 CLV_ proc near and dh,Not (CPU_V) Fetch CLV_ endp align 4 CMP_ABS proc near Read_ABS cmp ch,al cmc Flgnzc Fetch CMP_ABS endp align 4 CMP_ZP proc near mov bl,es:[si] inc si cmp ch,es:[bx] cmc Flgnzc Fetch CMP_ZP endp align 4 CMP_IMM proc near cmp ch,es:[si] cmc Flgnzc inc si Fetch CMP_IMM endp align 4 CMP_ABS_X proc near Read_ABS_X cmp ch,al cmc Flgnzc Fetch CMP_ABS_X endp align 4 CMP_ABS_Y proc near Read_ABS_Y cmp ch,al cmc Flgnzc Fetch CMP_ABS_Y endp align 4 CMP_IND_X proc near Read_IND_X cmp ch,al cmc Flgnzc Fetch CMP_IND_X endp align 4 CMP_IND_Y proc near Read_IND_Y cmp ch,al cmc Flgnzc Fetch CMP_IND_Y endp align 4 CMP_ZP_X proc near mov bl,es:[si] add bl,cl inc si cmp ch,es:[bx] cmc Flgnzc Fetch CMP_ZP_X endp align 4 CPX_ABS proc near Read_ABS cmp cl,al cmc Flgnzc Fetch CPX_ABS endp align 4 CPX_ZP proc near mov bl,es:[si] inc si cmp cl,es:[bx] cmc Flgnzc Fetch CPX_ZP endp align 4 CPX_IMM proc near cmp cl,es:[si] cmc Flgnzc inc si Fetch CPX_IMM endp align 4 CPY_ABS proc near Read_ABS cmp dl,al cmc Flgnzc Fetch CPY_ABS endp align 4 CPY_ZP proc near mov bl,es:[si] inc si cmp dl,es:[bx] cmc Flgnzc Fetch CPY_ZP endp align 4 CPY_IMM proc near cmp dl,es:[si] cmc Flgnzc inc si Fetch CPY_IMM endp align 4 DCP_ABS proc near Read_ABS dec al cmp ch,al cmc Flgnzc RMW_write DCP_ABS endp align 4 DCP_ZP proc near mov bl,es:[si] inc si mov al,es:[bx] dec al cmp ch,al mov es:[bx],al cmc Flgnzc Fetch DCP_ZP endp align 4 DCP_ABS_X proc near Read_ABS_X dec al cmp ch,al cmc Flgnzc RMW_write DCP_ABS_X endp align 4 DCP_ABS_Y proc near Read_ABS_Y dec al cmp ch,al cmc Flgnzc RMW_write DCP_ABS_Y endp align 4 DCP_IND_X proc near Read_IND_X dec al cmp ch,al cmc Flgnzc RMW_write DCP_IND_X endp align 4 DCP_IND_Y proc near Read_IND_Y dec al cmp ch,al cmc Flgnzc RMW_write DCP_IND_Y endp align 4 DCP_ZP_X proc near mov bl,es:[si] add bl,cl inc si mov al,es:[bx] dec al cmp ch,al mov es:[bx],al cmc Flgnzc Fetch DCP_ZP_X endp align 4 DEC_ABS proc near Read_ABS dec al Flgnz RMW_write DEC_ABS endp align 4 DEC_ZP proc near mov bl,es:[si] inc si dec byte ptr es:[bx] Flgnz Fetch DEC_ZP endp align 4 DEC_ABS_X proc near Read_ABS_X dec al Flgnz RMW_write DEC_ABS_X endp align 4 DEC_ZP_X proc near mov bl,es:[si] add bl,cl inc si dec byte ptr es:[bx] Flgnz Fetch DEC_ZP_X endp align 4 DEX proc near dec cl Flgnz Fetch DEX endp align 4 DEY proc near dec dl Flgnz Fetch DEY endp align 4 DOP proc near inc si ; Advance one byte! Fetch DOP endp align 4 EOR_ABS proc near Read_ABS xor ch,al Flgnz Fetch EOR_ABS endp align 4 EOR_ZP proc near mov bl,es:[si] inc si xor ch,es:[bx] Flgnz Fetch EOR_ZP endp align 4 EOR_IMM proc near xor ch,es:[si] Flgnz inc si Fetch EOR_IMM endp align 4 EOR_ABS_X proc near Read_ABS_X xor ch,al Flgnz Fetch EOR_ABS_X endp align 4 EOR_ABS_Y proc near Read_ABS_Y xor ch,al Flgnz Fetch EOR_ABS_Y endp align 4 EOR_IND_X proc near Read_IND_X xor ch,al Flgnz Fetch EOR_IND_X endp align 4 EOR_IND_Y proc near Read_IND_Y xor ch,al Flgnz Fetch EOR_IND_Y endp align 4 EOR_ZP_X proc near mov bl,es:[si] add bl,cl inc si xor ch,es:[bx] Flgnz Fetch EOR_ZP_X endp align 4 INC_ABS proc near Read_ABS inc al Flgnz RMW_write INC_ABS endp align 4 INC_ZP proc near mov bl,es:[si] inc si inc byte ptr es:[bx] Flgnz Fetch INC_ZP endp align 4 INC_ABS_X proc near Read_ABS_X inc al Flgnz RMW_write INC_ABS_X endp align 4 INC_ZP_X proc near mov bl,es:[si] add bl,cl inc si inc byte ptr es:[bx] Flgnz Fetch INC_ZP_X endp align 4 INX proc near inc cl Flgnz Fetch INX endp align 4 INY proc near inc dl Flgnz Fetch INY endp align 4 ISC_ABS proc near Read_ABS mov ah,dh test dh,CPU_M ; Decimal mode? jnz ISC_ABS1 inc al mov bh,al ; Save al sahf cmc sbb ch,al cmc Flgnvzc mov al,bh ; Restore al mov bh,0 RMW_write ; Store al align 4 ISC_ABS1: inc al mov bh,al ; Store al xchg al,ch sahf cmc sbb al,ch das ; Adjust al for packed BCD sub cmc mov ch,al Flgnvzc mov al,bh ; Restore al mov bh,0 RMW_write ; Store al ISC_ABS endp align 4 ISC_ZP proc near mov bl,es:[si] mov ah,dh inc si mov al,es:[bx] test dh,CPU_M ; Decimal mode? jnz ISC_ZP1 inc al mov bh,al ; Store al sahf cmc sbb ch,al cmc Flgnvzc mov al,bh ; Restore al mov bh,0 mov es:[bx],al ; Store al Fetch align 4 ISC_ZP1: inc al mov bh,al ; Store al xchg al,ch sahf cmc sbb al,ch das ; Adjust al for packed BCD sub cmc mov ch,al Flgnvzc mov al,bh ; Restore al mov bh,0 mov es:[bx],al ; Store al Fetch ISC_ZP endp align 4 ISC_ABS_X proc near Read_ABS_X mov ah,dh test dh,CPU_M ; Decimal mode? jnz ISC_ABS_X1 inc al mov bh,al ; Save al sahf cmc sbb ch,al cmc Flgnvzc mov al,bh ; Restore al mov bh,0 RMW_write ; Store al align 4 ISC_ABS_X1: inc al mov bh,al ; Store al xchg al,ch sahf cmc sbb al,ch das ; Adjust al for packed BCD sub cmc mov ch,al Flgnvzc mov al,bh ; Restore al mov bh,0 RMW_write ; Store al ISC_ABS_X endp align 4 ISC_ABS_Y proc near Read_ABS_Y mov ah,dh test dh,CPU_M ; Decimal mode? jnz ISC_ABS_Y1 inc al mov bh,al ; Save al sahf cmc sbb ch,al cmc Flgnvzc mov al,bh ; Restore al mov bh,0 RMW_write ; Store al align 4 ISC_ABS_Y1: inc al mov bh,al ; Store al xchg al,ch sahf cmc sbb al,ch das ; Adjust al for packed BCD sub cmc mov ch,al Flgnvzc mov al,bh ; Restore al mov bh,0 RMW_write ; Store al ISC_ABS_Y endp align 4 ISC_IND_X proc near Read_IND_X mov ah,dh test dh,CPU_M ; Decimal mode? jnz ISC_IND_X1 inc al mov bh,al ; Save al sahf cmc sbb ch,al cmc Flgnvzc mov al,bh ; Restore al mov bh,0 RMW_write ; Store al align 4 ISC_IND_X1: inc al mov bh,al ; Store al xchg al,ch sahf cmc sbb al,ch das ; Adjust al for packed BCD sub cmc mov ch,al Flgnvzc mov al,bh ; Restore al mov bh,0 RMW_write ; Store al ISC_IND_X endp align 4 ISC_IND_Y proc near Read_IND_Y mov ah,dh test dh,CPU_M ; Decimal mode? jnz ISC_IND_Y1 inc al mov bh,al ; Save al sahf cmc sbb ch,al cmc Flgnvzc mov al,bh ; Restore al mov bh,0 RMW_write ; Store al align 4 ISC_IND_Y1: inc al mov bh,al ; Store al xchg al,ch sahf cmc sbb al,ch das ; Adjust al for packed BCD sub cmc mov ch,al Flgnvzc mov al,bh ; Restore al mov bh,0 RMW_write ; Store al ISC_IND_Y endp align 4 ISC_ZP_X proc near mov bl,es:[si] mov ah,dh add bl,cl inc si mov al,es:[bx] test dh,CPU_M ; Decimal mode? jnz ISC_ZP_X1 inc al mov bh,al ; Store al sahf cmc sbb ch,al cmc Flgnvzc mov al,bh ; Restore al mov bh,0 mov es:[bx],al ; Store al Fetch align 4 ISC_ZP_X1: inc al mov bh,al ; Store al xchg al,ch sahf cmc sbb al,ch das ; Adjust al for packed BCD sub cmc mov ch,al Flgnvzc mov al,bh ; Restore al mov bh,0 mov es:[bx],al ; Store al Fetch ISC_ZP_X endp align 4 JMP_ABS proc near mov si,es:[si] Fetch JMP_ABS endp align 4 JMP_IND proc near mov bx,es:[si] mov al,es:[bx] inc bl mov ah,es:[bx] mov bh,0 mov si,ax Fetch JMP_IND endp align 4 JSR proc near mov ax,es:[si] inc si ; 1 instead of 2 bytes! xchg ax,si Push_16 Fetch JSR endp align 4 KIL proc near jmp _6510Quit KIL endp align 4 LAX_ABS proc near Read_ABS mov ch,al ; Load to accu mov cl,al ; and to x reg or al,al Flgnz Fetch LAX_ABS endp align 4 LAX_ZP proc near mov bl,es:[si] inc si mov ch,es:[bx] mov cl,ch or ch,ch Flgnz Fetch LAX_ZP endp align 4 LAX_IMM proc near mov ch,es:[si] ; Load to accu mov cl,ch ; and to x reg or ch,ch Flgnz inc si Fetch LAX_IMM endp align 4 LAX_ABS_Y proc near Read_ABS_Y mov ch,al mov cl,al or al,al Flgnz Fetch LAX_ABS_Y endp align 4 LAX_IND_X proc near Read_IND_X mov ch,al mov cl,al or al,al Flgnz Fetch LAX_IND_X endp align 4 LAX_IND_Y proc near Read_IND_Y mov ch,al mov cl,al or al,al Flgnz Fetch LAX_IND_Y endp align 4 LAX_ZP_Y proc near mov bl,es:[si] add bl,dl inc si mov ch,es:[bx] mov cl,ch or ch,ch Flgnz Fetch LAX_ZP_Y endp align 4 LDA_ABS proc near Read_ABS mov ch,al or al,al Flgnz Fetch LDA_ABS endp align 4 LDA_ZP proc near mov bl,es:[si] inc si mov ch,es:[bx] or ch,ch Flgnz Fetch LDA_ZP endp align 4 LDA_IMM proc near mov ch,es:[si] inc si or ch,ch Flgnz Fetch LDA_IMM endp align 4 LDA_ABS_X proc near Read_ABS_X mov ch,al or al,al Flgnz Fetch LDA_ABS_X endp align 4 LDA_ABS_Y proc near Read_ABS_Y mov ch,al or al,al Flgnz Fetch LDA_ABS_Y endp align 4 LDA_IND_X proc near Read_IND_X mov ch,al or al,al Flgnz Fetch LDA_IND_X endp align 4 LDA_IND_Y proc near Read_IND_Y mov ch,al or al,al Flgnz Fetch LDA_IND_Y endp align 4 LDA_ZP_X proc near mov bl,es:[si] add bl,cl inc si mov ch,es:[bx] or ch,ch Flgnz Fetch LDA_ZP_X endp align 4 LDX_ABS proc near Read_ABS mov cl,al or al,al Flgnz Fetch LDX_ABS endp align 4 LDX_ZP proc near mov bl,es:[si] inc si mov cl,es:[bx] or cl,cl Flgnz Fetch LDX_ZP endp align 4 LDX_IMM proc near mov cl,es:[si] inc si or cl,cl Flgnz Fetch LDX_IMM endp align 4 LDX_ABS_Y proc near Read_ABS_Y mov cl,al or al,al Flgnz Fetch LDX_ABS_Y endp align 4 LDX_ZP_Y proc near mov bl,es:[si] add bl,dl inc si mov cl,es:[bx] or cl,cl Flgnz Fetch LDX_ZP_Y endp align 4 LDY_ABS proc near Read_ABS mov dl,al or al,al Flgnz Fetch LDY_ABS endp align 4 LDY_ZP proc near mov bl,es:[si] inc si mov dl,es:[bx] or dl,dl Flgnz Fetch LDY_ZP endp align 4 LDY_IMM proc near mov dl,es:[si] inc si or dl,dl Flgnz Fetch LDY_IMM endp align 4 LDY_ABS_X proc near Read_ABS_X mov dl,al or al,al Flgnz Fetch LDY_ABS_X endp align 4 LDY_ZP_X proc near mov bl,es:[si] add bl,cl inc si mov dl,es:[bx] or dl,dl Flgnz Fetch LDY_ZP_X endp align 4 LSR_A proc near shr ch,1 Flgnzc Fetch LSR_A endp align 4 LSR_ABS proc near Read_ABS shr al,1 Flgnzc RMW_write LSR_ABS endp align 4 LSR_ZP proc near mov bl,es:[si] inc si shr byte ptr es:[bx],1 Flgnzc Fetch LSR_ZP endp align 4 LSR_ABS_X proc near Read_ABS_X shr al,1 Flgnzc RMW_write LSR_ABS_X endp align 4 LSR_ZP_X proc near mov bl,es:[si] add bl,cl inc si shr byte ptr es:[bx],1 Flgnzc Fetch LSR_ZP_X endp align 4 NOP_ proc near Fetch NOP_ endp align 4 ORA_ABS proc near Read_ABS or ch,al Flgnz Fetch ORA_ABS endp align 4 ORA_ZP proc near mov bl,es:[si] inc si or ch,es:[bx] Flgnz Fetch ORA_ZP endp align 4 ORA_IMM proc near or ch,es:[si] Flgnz inc si Fetch ORA_IMM endp align 4 ORA_ABS_X proc near Read_ABS_X or ch,al Flgnz Fetch ORA_ABS_X endp align 4 ORA_ABS_Y proc near Read_ABS_Y or ch,al Flgnz Fetch ORA_ABS_Y endp align 4 ORA_IND_X proc near Read_IND_X or ch,al Flgnz Fetch ORA_IND_X endp align 4 ORA_IND_Y proc near Read_IND_Y or ch,al Flgnz Fetch ORA_IND_Y endp align 4 ORA_ZP_X proc near mov bl,es:[si] add bl,cl inc si or ch,es:[bx] Flgnz Fetch ORA_ZP_X endp align 4 PHA proc near Push_8 ch Fetch PHA endp align 4 PHP proc near mov bl,dh mov al,FlgDecodeTable[bx] Push_8 al Fetch PHP endp align 4 PLA proc near Pop_8 ch or ch,ch Flgnz Fetch PLA endp align 4 PLP proc near mov bx,bp inc bl mov bp,bx movzx bx,byte ptr es:[bx] mov dh,FlgEncodeTable[bx] Fetch PLP endp align 4 RLA_ABS proc near Read_ABS mov ah,dh and dh,Not (CPU_N + CPU_Z + CPU_C) sahf adc al,al ; Shift data left adc dh,0 ; Update Carry and ch,al ; AND with accu lahf and ah,CPU_N + CPU_Z or dh,ah RMW_write RLA_ABS endp align 4 RLA_ZP proc near mov bl,es:[si] mov ah,dh inc si mov al,es:[bx] and dh,Not (CPU_N + CPU_Z + CPU_C) sahf adc al,al ; Shift data left adc dh,0 ; Update carry and ch,al ; AND with accu lahf mov es:[bx],al ; Store result and ah,CPU_N + CPU_Z or dh,ah Fetch RLA_ZP endp align 4 RLA_ABS_X proc near Read_ABS_X mov ah,dh and dh,Not (CPU_N + CPU_Z + CPU_C) sahf adc al,al ; Shift data left adc dh,0 and ch,al ; AND with accu lahf and ah,CPU_N + CPU_Z or dh,ah RMW_write RLA_ABS_X endp align 4 RLA_ABS_Y proc near Read_ABS_Y mov ah,dh and dh,Not (CPU_N + CPU_Z + CPU_C) sahf adc al,al ; Shift data left adc dh,0 and ch,al ; AND with accu lahf and ah,CPU_N + CPU_Z or dh,ah RMW_write RLA_ABS_Y endp align 4 RLA_IND_X proc near Read_IND_X mov ah,dh and dh,Not (CPU_N + CPU_Z + CPU_C) sahf adc al,al ; Shift data left adc dh,0 and ch,al ; AND with accu lahf and ah,CPU_N + CPU_Z or dh,ah RMW_write RLA_IND_X endp align 4 RLA_IND_Y proc near Read_IND_Y mov ah,dh and dh,Not (CPU_N + CPU_Z + CPU_C) sahf adc al,al ; Shift data left adc dh,0 and ch,al ; AND with accu lahf and ah,CPU_N + CPU_Z or dh,ah RMW_write RLA_IND_Y endp align 4 RLA_ZP_X proc near mov bl,es:[si] mov ah,dh add bl,cl inc si mov al,es:[bx] and dh,Not (CPU_N + CPU_Z + CPU_C) sahf adc al,al ; Shift data left adc dh,0 and ch,al ; AND with accu lahf mov es:[bx],al and ah,CPU_N + CPU_Z or dh,ah Fetch RLA_ZP_X endp align 4 ROL_A proc near mov ah,dh sahf adc ch,ch Flgnzc Fetch ROL_A endp align 4 ROL_ABS proc near Read_ABS mov ah,dh sahf adc al,al Flgnzc RMW_write ROL_ABS endp align 4 ROL_ZP proc near mov bl,es:[si] mov ah,dh inc si mov al,es:[bx] sahf adc es:[bx],al Flgnzc Fetch ROL_ZP endp align 4 ROL_ABS_X proc near Read_ABS_X mov ah,dh sahf adc al,al Flgnzc RMW_write ROL_ABS_X endp align 4 ROL_ZP_X proc near mov bl,es:[si] mov ah,dh add bl,cl inc si mov al,es:[bx] sahf adc es:[bx],al Flgnzc Fetch ROL_ZP_X endp align 4 ROR_A proc near mov ah,dh sahf rcr ch,1 inc ch dec ch Flgnzc Fetch ROR_A endp align 4 ROR_ABS proc near Read_ABS mov ah,dh sahf rcr al,1 inc al dec al Flgnzc RMW_write ROR_ABS endp align 4 ROR_ZP proc near mov bl,es:[si] mov ah,dh inc si sahf mov al,es:[bx] rcr al,1 mov es:[bx],al inc al dec al Flgnzc Fetch ROR_ZP endp align 4 ROR_ABS_X proc near Read_ABS_X mov ah,dh sahf rcr al,1 inc al dec al Flgnzc RMW_write ROR_ABS_X endp align 4 ROR_ZP_X proc near mov bl,es:[si] mov ah,dh add bl,cl inc si sahf mov al,es:[bx] rcr al,1 mov es:[bx],al inc al dec al Flgnzc Fetch ROR_ZP_X endp align 4 RRA_ABS proc near Read_ABS mov ah,dh test dh,CPU_M ; Decimal mode? jnz RRA_ABS1 sahf rcr al,1 ; Rotate data right mov bh,al ; Save al adc ch,al Flgnvzc mov al,bh ; Restore al mov bh,0 RMW_write ; Store al align 4 RRA_ABS1: sahf rcr al,1 ; Rotate data right mov bh,al ; Store al adc al,ch daa ; Adjust al for packed BCD add mov ch,al Flgnvzc mov al,bh ; Restore al mov bh,0 RMW_write ; Store al RRA_ABS endp align 4 RRA_ZP proc near mov bl,es:[si] mov ah,dh inc si mov al,es:[bx] test dh,CPU_M ; Decimal mode? jnz RRA_ZP1 sahf ; Set/reset real carry rcr al,1 ; Rotate data right mov bh,al ; Store al adc ch,al Flgnvzc mov al,bh ; Restore al mov bh,0 mov es:[bx],al ; Store al Fetch align 4 RRA_ZP1: sahf ; Set/reset real carry rcr al,1 ; Rotate data right mov bh,al ; Store al adc al,ch daa ; Adjust al for packed BCD add mov ch,al Flgnvzc mov al,bh ; Restore al mov bh,0 mov es:[bx],al ; Store al Fetch RRA_ZP endp align 4 RRA_ABS_X proc near Read_ABS_X mov ah,dh test dh,CPU_M ; Decimal mode? jnz RRA_ABS_X1 sahf ; Set/reset real carry rcr al,1 mov bh,al ; Store al adc ch,al Flgnvzc mov al,bh ; Restore al mov bh,0 RMW_write ; Store al align 4 RRA_ABS_X1: sahf ; Set/reset real carry rcr al,1 mov bh,al ; Store al adc al,ch daa ; Adjust al for packed BCD add mov ch,al Flgnvzc mov al,bh ; Restore al mov bh,0 RMW_write ; Store al RRA_ABS_X endp align 4 RRA_ABS_Y proc near Read_ABS_Y mov ah,dh test dh,CPU_M ; Decimal mode? jnz RRA_ABS_Y1 sahf ; Set/reset real carry rcr al,1 mov bh,al ; Store al adc ch,al Flgnvzc mov al,bh ; Restore al mov bh,0 RMW_write ; Store al align 4 RRA_ABS_Y1: sahf ; Set/reset real carry rcr al,1 mov bh,al ; Store al adc al,ch daa ; Adjust al for packed BCD add mov ch,al Flgnvzc mov al,bh ; Restore al mov bh,0 RMW_write ; Store al RRA_ABS_Y endp align 4 RRA_IND_X proc near Read_IND_X mov ah,dh test dh,CPU_M ; Decimal mode? jnz RRA_IND_X1 sahf ; Set/reset real carry rcr al,1 mov bh,al ; Store al adc ch,al Flgnvzc mov al,bh ; Restore al mov bh,0 RMW_write ; Store al align 4 RRA_IND_X1: sahf ; Set/reset real carry rcr al,1 mov bh,al ; Store al adc al,ch daa ; Adjust al for packed BCD add mov ch,al Flgnvzc mov al,bh ; Restore al mov bh,0 RMW_write ; Store al RRA_IND_X endp align 4 RRA_IND_Y proc near Read_IND_Y mov ah,dh test dh,CPU_M ; Decimal mode? jnz RRA_IND_Y1 sahf ; Set/reset real carry rcr al,1 mov bh,al ; Store al adc ch,al Flgnvzc mov al,bh ; Restore al mov bh,0 RMW_write ; Store al align 4 RRA_IND_Y1: sahf ; Set/reset real carry rcr al,1 mov bh,al ; Store al adc al,ch daa ; Adjust al for packed BCD add mov ch,al Flgnvzc mov al,bh ; Restore al mov bh,0 RMW_write ; Store al RRA_IND_Y endp align 4 RRA_ZP_X proc near mov bl,es:[si] mov ah,dh add bl,cl inc si mov al,es:[bx] test dh,CPU_M ; Decimal mode? jnz RRA_ZP_X1 sahf ; Set/reset real carry rcr al,1 mov bh,al ; Store al adc ch,al Flgnvzc mov al,bh ; Restore al mov bh,0 mov es:[bx],al ; Store al Fetch align 4 RRA_ZP_X1: sahf ; Set/reset real carry rcr al,1 mov bh,al ; Store al adc al,ch daa ; Adjust al for packed BCD add mov ch,al Flgnvzc mov al,bh ; Restore al mov bh,0 mov es:[bx],al ; Store al Fetch RRA_ZP_X endp align 4 RTI proc near Pop_Int Fetch RTI endp align 4 RTS proc near Pop_16 inc ax ; Advance one byte! mov si,ax Fetch RTS endp align 4 SAH_ABS_Y proc near mov al,ch mov ah,es:[si+1] ; Hi-byte and al,cl ; AND A,X inc ah and al,ah Flgnz Write_ABS_Y SAH_ABS_Y endp align 4 SAH_IND_Y proc near mov al,ch mov ah,es:[si+1] ; Hi-byte and al,cl ; AND A,X inc ah and al,ah Flgnz Write_IND_Y SAH_IND_Y endp align 4 SAX_ABS proc near mov al,ch and al,cl Flgnz Write_ABS SAX_ABS endp align 4 SAX_ZP proc near mov al,ch and al,cl Flgnz Write_ZP al SAX_ZP endp align 4 SAX_ZP_Y proc near mov al,ch and al,cl Flgnz Write_ZP_Y al SAX_ZP_Y endp align 4 SAX_IND_X proc near mov al,ch and al,cl Flgnz Write_IND_X SAX_IND_X endp align 4 SBC_ABS proc near Read_ABS OpSBC SBC_ABS endp align 4 SBC_ZP proc near Read_ZP al OpSBC SBC_ZP endp align 4 SBC_IMM proc near Read_IMM al OpSBC SBC_IMM endp align 4 SBC_ABS_X proc near Read_ABS_X OpSBC SBC_ABS_X endp align 4 SBC_ABS_Y proc near Read_ABS_Y OpSBC SBC_ABS_Y endp align 4 SBC_IND_X proc near Read_IND_X OpSBC SBC_IND_X endp align 4 SBC_IND_Y proc near Read_IND_Y OpSBC SBC_IND_Y endp align 4 SBC_ZP_X proc near Read_ZP_X al OpSBC SBC_ZP_X endp align 4 SEC proc near or dh,CPU_C Fetch SEC endp align 4 SEI proc near or dh,CPU_I Fetch SEI endp align 4 SED proc near or dh,CPU_M Fetch SED endp align 4 SLO_ABS proc near Read_ABS and dh,Not (CPU_N + CPU_Z + CPU_C) add al,al ; Shift data left adc dh,0 ; Update Carry or ch,al ; OR with accu lahf and ah,CPU_N + CPU_Z or dh,ah RMW_write SLO_ABS endp align 4 SLO_ZP proc near mov bl,es:[si] inc si mov al,es:[bx] and dh,Not (CPU_N + CPU_Z + CPU_C) add al,al ; Shift data left adc dh,0 ; Update carry or ch,al ; OR with accu lahf mov es:[bx],al ; Store result and ah,CPU_N + CPU_Z or dh,ah Fetch SLO_ZP endp align 4 SLO_ABS_X proc near Read_ABS_X and dh,Not (CPU_N + CPU_Z + CPU_C) add al,al ; Shift data left adc dh,0 or ch,al ; OR with accu lahf and ah,CPU_N + CPU_Z or dh,ah RMW_write SLO_ABS_X endp align 4 SLO_ABS_Y proc near Read_ABS_Y and dh,Not (CPU_N + CPU_Z + CPU_C) add al,al ; Shift data left adc dh,0 or ch,al ; OR with accu lahf and ah,CPU_N + CPU_Z or dh,ah RMW_write SLO_ABS_Y endp align 4 SLO_IND_X proc near Read_IND_X and dh,Not (CPU_N + CPU_Z + CPU_C) add al,al ; Shift data left adc dh,0 or ch,al ; OR with accu lahf and ah,CPU_N + CPU_Z or dh,ah RMW_write SLO_IND_X endp align 4 SLO_IND_Y proc near Read_IND_Y and dh,Not (CPU_N + CPU_Z + CPU_C) add al,al ; Shift data left adc dh,0 or ch,al ; OR with accu lahf and ah,CPU_N + CPU_Z or dh,ah RMW_write SLO_IND_Y endp align 4 SLO_ZP_X proc near mov bl,es:[si] add bl,cl inc si mov al,es:[bx] and dh,Not (CPU_N + CPU_Z + CPU_C) add al,al ; Shift data left adc dh,0 or ch,al ; OR with accu lahf mov es:[bx],al and ah,CPU_N + CPU_Z or dh,ah Fetch SLO_ZP_X endp align 4 SRE_ABS proc near Read_ABS and dh,Not (CPU_N + CPU_Z + CPU_C) shr al,1 ; Shift data right adc dh,0 ; Update Carry xor ch,al ; XOR with accu lahf and ah,CPU_N + CPU_Z or dh,ah RMW_write SRE_ABS endp align 4 SRE_ZP proc near mov bl,es:[si] inc si mov al,es:[bx] and dh,Not (CPU_N + CPU_Z + CPU_C) shr al,1 ; Shift data right adc dh,0 ; Update carry xor ch,al ; XOR with accu lahf mov es:[bx],al ; Store result and ah,CPU_N + CPU_Z or dh,ah Fetch SRE_ZP endp align 4 SRE_ABS_X proc near Read_ABS_X and dh,Not (CPU_N + CPU_Z + CPU_C) shr al,1 ; Shift data right adc dh,0 xor ch,al ; XOR with accu lahf and ah,CPU_N + CPU_Z or dh,ah RMW_write SRE_ABS_X endp align 4 SRE_ABS_Y proc near Read_ABS_Y and dh,Not (CPU_N + CPU_Z + CPU_C) shr al,1 ; Shift data right adc dh,0 xor ch,al ; XOR with accu lahf and ah,CPU_N + CPU_Z or dh,ah RMW_write SRE_ABS_Y endp align 4 SRE_IND_X proc near Read_IND_X and dh,Not (CPU_N + CPU_Z + CPU_C) shr al,1 ; Shift data right adc dh,0 xor ch,al ; XOR with accu lahf and ah,CPU_N + CPU_Z or dh,ah RMW_write SRE_IND_X endp align 4 SRE_IND_Y proc near Read_IND_Y and dh,Not (CPU_N + CPU_Z + CPU_C) shr al,1 ; Shift data right adc dh,0 xor ch,al ; XOR with accu lahf and ah,CPU_N + CPU_Z or dh,ah RMW_write SRE_IND_Y endp align 4 SRE_ZP_X proc near mov bl,es:[si] add bl,cl inc si mov al,es:[bx] and dh,Not (CPU_N + CPU_Z + CPU_C) shr al,1 ; Shift data right adc dh,0 xor ch,al ; XOR with accu lahf mov es:[bx],al and ah,CPU_N + CPU_Z or dh,ah Fetch SRE_ZP_X endp align 4 SSH_ABS_Y proc near mov al,ch and al,cl ; AND A,X mov ah,001h mov bp,ax ; Store in SP mov ah,es:[si+1] ; High-byte inc ah and al,ah Write_ABS_Y Fetch SSH_ABS_Y endp align 4 SXH_ABS_Y proc near mov al,es:[si+1] ; High-byte inc al and al,cl ; AND HI+1,X Write_ABS_Y SXH_ABS_Y endp align 4 SYH_ABS_X proc near mov al,es:[si+1] ; High-byte inc al and al,dl ; AND HI+1,Y Write_ABS_X SYH_ABS_X endp align 4 STA_ABS proc near mov al,ch Write_ABS STA_ABS endp align 4 STA_ZP proc near Write_ZP ch STA_ZP endp align 4 STA_ABS_X proc near mov al,ch Write_ABS_X STA_ABS_X endp align 4 STA_ABS_Y proc near mov al,ch Write_ABS_Y STA_ABS_Y endp align 4 STA_IND_X proc near mov al,ch Write_IND_X STA_IND_X endp align 4 STA_IND_Y proc near mov al,ch Write_IND_Y STA_IND_Y endp align 4 STA_ZP_X proc near Write_ZP_X ch STA_ZP_X endp align 4 STX_ABS proc near mov al,cl Write_ABS STX_ABS endp align 4 STX_ZP proc near Write_ZP cl STX_ZP endp align 4 STX_ZP_Y proc near Write_ZP_Y cl STX_ZP_Y endp align 4 STY_ABS proc near mov al,dl Write_ABS STY_ABS endp align 4 STY_ZP proc near Write_ZP dl STY_ZP endp align 4 STY_ZP_X proc near Write_ZP_X dl STY_ZP_X endp align 4 TAX proc near mov cl,ch or ch,ch Flgnz Fetch TAX endp align 4 TAY proc near mov dl,ch or ch,ch Flgnz Fetch TAY endp align 4 TOP proc near add si,2 ; Advance two bytes! Fetch TOP endp align 4 TSX proc near mov ax,bp mov cl,al or al,al Flgnz Fetch TSX endp align 4 TXA proc near mov ch,cl or cl,cl Flgnz Fetch TXA endp align 4 TXS proc near mov al,cl mov ah,01h mov bp,ax Fetch TXS endp align 4 TYA proc near mov ch,dl or dl,dl Flgnz Fetch TYA endp ; **************************************************************************** ; Flag decode table .data FlgDecodeTable db 00100000b BitPattern = 00000001b rept 255 Decode BitPattern BitPattern = BitPattern + 1 endm ; **************************************************************************** ; Flag encode table FlgEncodeTable db 00000000b BitPattern = 00000001b rept 255 Encode BitPattern BitPattern = BitPattern + 1 endm end Start