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Internet Message Format | 1990-12-28 | 60.7 KB

From: markz@ssc.UUCP (Mark Zenier) Newsgroups: alt.sources Subject: Frankenstein Cross Assemblers, Zilog Z8 flavor, Part 1 of 1 Message-ID: <608@ssc.UUCP> Date: 5 Dec 90 06:19:51 GMT ---- Cut Here and feed the following to sh ---- #!/bin/sh # This is Frankasm/Asz8, a shell archive (shar 3.43) # made 12/04/1990 08:46 UTC by markz@ssc.uucp # Source directory /usr/mark/frank.shar # # existing files will NOT be overwritten unless -c is specified # This format requires very little intelligence at unshar time. # "if test", "echo", "true", and "sed" may be needed. # # This shar contains: # length mode name # ------ ---------- ------------------------------------------ # 1463 -r--r----- asz8.1 # 8593 -r--r----- asz8.doc # 3548 -r--r----- asz8.tst # 7110 -r--r----- asz8.tut # 36629 -r--r--r-- asz8.y # # ============= asz8.1 ============== if test -f 'asz8.1' -a X"$1" != X"-c"; then echo 'x - skipping asz8.1 (File already exists)' else echo 'x - extracting asz8.1 (Text)' sed 's/^X//' << 'SHAR_EOF' > 'asz8.1' && X.TH ASZ8 1L X.SH NAME Xasz8 \- cross assemblers for microcomputers X.SH SYNOPSIS X.nf Xasz8 [-p cpu] [-l listfile] [-o hexfile] [-d] [-s symbolfile] input X.fi X.SH DESCRIPTION XThe asz8 command assembles the input file into a Xtext output file representing the program memory for a microcomputer. X XOptions X.IP "-p cpu" XOverride the instruction set selection. X.RS 10 XValid Values for Cpu X.RS 5 Xz8600, z8, Z8, UPC, upc, Z8090 X.RE X.RE X.IP "-l listfile" XOutput a file formated with the memory address, data, and source input lines. X.IP "-o hexfile" XOutput the memory data image in a form accepted by most prom programmers. X.IP "-h hexfile" XSame as \-o. X.IP \-d XSave the intermediate data file (see FILE) and abort the execution at the Xend of processing. X.IP "-s symbolfile" XPrint the symbol table values and names, one per line in the specified file. X.SH FILES X/usr/tmp/frtXXXXXX X.SH SEE ALSO XFrankenstein Cross Assemblers Users Manual (file base.doc) XAppendix for asz8 Frankenstein Assembler (file asz8.doc) X.SH NOTES XThere is only one input file. X XThe program can select which subset of instructions is accepted. XThe program first uses the name with which it is invoked. XThis is scanned for a substring which indicates which set to use. XThe -p options overrides this selction by performing the same substring Xsearch. XFinally the input file can select which subset to use with the CPU statement. X XThere should only be one executable file with all of its names linked to it. SHAR_EOF true || echo 'restore of asz8.1 failed' fi # ============= asz8.doc ============== if test -f 'asz8.doc' -a X"$1" != X"-c"; then echo 'x - skipping asz8.doc (File already exists)' else echo 'x - extracting asz8.doc (Text)' sed 's/^X//' << 'SHAR_EOF' > 'asz8.doc' && X.HM A 1 1 1 1 1 1 X.H 1 "Appendix for asz8 Frankenstein Assembler" X.H 2 "Pseudo Operations" X.H 3 "Standard Pseudo Operation Mnemonics" X.VL 40 5 1 X.LI "End" XEND X.LI "File Inclusion" XINCL XINCLUDE X.LI "If" XIF X.LI "Else" XELSE X.LI "End If" XENDI X.LI "Equate" XEQU X.LI "Set" XSET X.LI "Org" XORG X.LI "Reserve Memory" XRESERVE XRMB X.LI "Define Byte Data" XBYTE XDB XFCB X.LI "Define Word Data" XDW XFDB XWORD X.LI "Define String Data" XFCC XSTRING X.LI "Define Character Set Translation" XCHARSET X.LI "Define Character Value" XCHARDEF XCHD X.LI "Use Character Translation" XCHARUSE X.LE X.H 3 "Machine Dependent Pseudo Operations" X.H 4 "Register Symbol Definitions" X.DS I N XLabel REG RegisterSymbol XLabel RREG RegisterSymbol XLabel REG expression XLabel RREG expression XLabel REG XLabel RREG X.DE X.P XSymbols in the register address space are defined with the REG, and RREG Xpseudooperations. XThe symbol in the label field is added to the symbol table as a register Xsymbol. XThe symbols defined with the REG are single byte registers. XThe symbols defined with RREG are double registers, and must be on even Xboundries. X.P XThe operand can be in three forms. X.P XWhen the operand is a register symbol, the label symbol is defined with Xthe same register address as the symbol, with the size determined by which Xpseudoop is used. XAliases to working registers must use this form. X.P XWhen the operand is an expression, the label symbol is defined at the Xvalue of the expression, with the size determined by which pseudoop is used. XThe value must be in the range 0 to 127 (or 223 for the UPC register set), Xor 240 to 255, and must be defined at the first pass. X.P XWith no operand, the label symbol is defined at the register address Xfollowing the previous REG or RREG instruction. XIf a previous Register Definition used a working register as its operand, Xthe current definition will be in the working set, otherwise it will be Xin the register file. X.P XRegister Symbols must be surrounded by parenthesis when used in expressions. X.H 4 "Register Set Selection" X.DS I N XCPU string X.DE XThe register set can be specified in the source file with the CPU Xpseudooperation. XThe string, delimited by quotes or apostrophes, is scanned for a Xsubstring which selects which register set is used. XWhen the program is invoked, this operation is performed on the name of Xthe program, then the -p optional arguement, if any, and then any CPU Xstatements. XThe last one selects the which subset of the registers the assembler will Xaccept. X.VL 30 5 1 X.LI "Register Architecture" XSubstrings X.SP X.LI "z8" X86 Xz8 XZ8 X.SP X.LI "Universal" XUPC Xupc X9 X.LI "Peripheral" X.LI "Controller" X.LE X.H 2 "Instructions" X.H 3 "Instruction List" X.TS H X; Xl l l. XOpcode Syntax Selection Criteria X.sp X.TH X.sp XADC '@' REGISTER ',' '#' expr XADC REGISTER ',' '#' expr XADC REGISTER ',' '@' REGISTER XADC REGISTER ',' '@' REGISTER SRCWORK+DSTWORK XADC REGISTER ',' REGISTER XADC REGISTER ',' REGISTER SRCWORK+DSTWORK X.sp XADD '@' REGISTER ',' '#' expr XADD REGISTER ',' '#' expr XADD REGISTER ',' '@' REGISTER XADD REGISTER ',' '@' REGISTER SRCWORK+DSTWORK XADD REGISTER ',' REGISTER XADD REGISTER ',' REGISTER SRCWORK+DSTWORK X.sp XAND '@' REGISTER ',' '#' expr XAND REGISTER ',' '#' expr XAND REGISTER ',' '@' REGISTER XAND REGISTER ',' '@' REGISTER SRCWORK+DSTWORK XAND REGISTER ',' REGISTER XAND REGISTER ',' REGISTER SRCWORK+DSTWORK X.sp XCALL '@' REGISTER DSTDBL XCALL expr X.sp XCCF X.sp XCLR '@' REGISTER XCLR REGISTER X.sp XCOM '@' REGISTER XCOM REGISTER X.sp XCP '@' REGISTER ',' '#' expr XCP REGISTER ',' '#' expr XCP REGISTER ',' '@' REGISTER XCP REGISTER ',' '@' REGISTER SRCWORK+DSTWORK XCP REGISTER ',' REGISTER XCP REGISTER ',' REGISTER SRCWORK+DSTWORK X.sp XDA '@' REGISTER XDA REGISTER X.sp XDEC '@' REGISTER XDEC REGISTER X.sp XDECW '@' REGISTER XDECW REGISTER DSTDBL X.sp XDI X.sp XDJNZ REGISTER ',' expr DSTWORK X.sp XEI X.sp XINC '@' REGISTER XINC REGISTER XINC REGISTER DSTWORK X.sp XINCW '@' REGISTER XINCW REGISTER DSTDBL X.sp XIRET X.sp XJP '@' REGISTER DSTDBL XJP CONDITION ',' expr XJP expr X.sp XJR CONDITION ',' expr XJR expr X.sp XLD '@' REGISTER ',' '#' expr XLD '@' REGISTER ',' REGISTER XLD '@' REGISTER ',' REGISTER DSTWORK+SRCWORK XLD REGISTER ',' '#' expr XLD REGISTER ',' '#' expr DSTWORK XLD REGISTER ',' '@' REGISTER XLD REGISTER ',' '@' REGISTER DSTWORK+SRCWORK XLD REGISTER ',' REGISTER XLD REGISTER ',' REGISTER DSTWORK XLD REGISTER ',' REGISTER SRCWORK XLD REGISTER ',' expr '(' REGISTER ')' DSTWORK+SRCWORK XLD expr '(' REGISTER ')' ',' REGISTER DSTWORK+SRCWORK X.sp XLDC '@' REGISTER ',' REGISTER DSTWORK+SRCWORK XLDC REGISTER ',' '@' REGISTER DSTWORK+SRCWORK X.sp XLDCI '@' REGISTER ',' '@' REGISTER DSTDBL+DSTWORK+SRCWORK XLDCI '@' REGISTER ',' '@' REGISTER SRCDBL+DSTWORK+SRCWORK X.sp XLDE '@' REGISTER ',' REGISTER DSTWORK+SRCWORK XLDE REGISTER ',' '@' REGISTER DSTWORK+SRCWORK X.sp XLDEI '@' REGISTER ',' '@' REGISTER DSTDBL+DSTWORK+SRCWORK XLDEI '@' REGISTER ',' '@' REGISTER SRCDBL+DSTWORK+SRCWORK X.sp XNOP X.sp XOR '@' REGISTER ',' '#' expr XOR REGISTER ',' '#' expr XOR REGISTER ',' '@' REGISTER XOR REGISTER ',' '@' REGISTER SRCWORK+DSTWORK XOR REGISTER ',' REGISTER XOR REGISTER ',' REGISTER SRCWORK+DSTWORK X.sp XPOP '@' REGISTER XPOP REGISTER X.sp XPUSH '@' REGISTER XPUSH REGISTER X.sp XRCF X.sp XRET X.sp XRL '@' REGISTER XRL REGISTER X.sp XRLC '@' REGISTER XRLC REGISTER X.sp XRR '@' REGISTER XRR REGISTER X.sp XRRC '@' REGISTER XRRC REGISTER X.sp XSBC '@' REGISTER ',' '#' expr XSBC REGISTER ',' '#' expr XSBC REGISTER ',' '@' REGISTER XSBC REGISTER ',' '@' REGISTER SRCWORK+DSTWORK XSBC REGISTER ',' REGISTER XSBC REGISTER ',' REGISTER SRCWORK+DSTWORK X.sp XSCF X.sp XSRA '@' REGISTER XSRA REGISTER X.sp XSRP '#' expr X.sp XSUB '@' REGISTER ',' '#' expr XSUB REGISTER ',' '#' expr XSUB REGISTER ',' '@' REGISTER XSUB REGISTER ',' '@' REGISTER SRCWORK+DSTWORK XSUB REGISTER ',' REGISTER XSUB REGISTER ',' REGISTER SRCWORK+DSTWORK X.sp XSWAP '@' REGISTER XSWAP REGISTER X.sp XTCM '@' REGISTER ',' '#' expr XTCM REGISTER ',' '#' expr XTCM REGISTER ',' '@' REGISTER XTCM REGISTER ',' '@' REGISTER SRCWORK+DSTWORK XTCM REGISTER ',' REGISTER XTCM REGISTER ',' REGISTER SRCWORK+DSTWORK X.sp XTM '@' REGISTER ',' '#' expr XTM REGISTER ',' '#' expr XTM REGISTER ',' '@' REGISTER XTM REGISTER ',' '@' REGISTER SRCWORK+DSTWORK XTM REGISTER ',' REGISTER XTM REGISTER ',' REGISTER SRCWORK+DSTWORK X.sp XXOR '@' REGISTER ',' '#' expr XXOR REGISTER ',' '#' expr XXOR REGISTER ',' '@' REGISTER XXOR REGISTER ',' '@' REGISTER SRCWORK+DSTWORK XXOR REGISTER ',' REGISTER XXOR REGISTER ',' REGISTER SRCWORK+DSTWORK X.TE X.H 3 "Selection Criteria Keywords" X.VL 25 5 X.LI DSTWORK XThe instruction will use the short form if Xthe register is in the working set. X.LI DSTDBL XThe instruction requires that the destination register be a double register. X.LI SRCWORK XThe instruction will use the short form if Xthe register is in the working set. X.LI SRCDBL XThe instruction requires that the source register be a double register. X.LE X.H 3 "Apostrophes" XThe apostrophes in the syntax field are a notation used for the Xparser generator and are not put in the assembler source statement. X.H 2 "Notes" X.H 3 "Registers" XRegisters are treated as symbols with a different syntactic type than Xmemory addresses. XThis seperates symbols which would have the same numeric value into the Xdifferent address spaces, register and memory. XUsing a symbol that is already defined as a Register as a statement label Xfor an instruction or a SET/EQU will result in a "Syntax Error". X.P XRegisters are represented by the reserved symbols R0 thru R15 and RR0 thru XRR14 for the working set registers. XOther registers are defined with the REG and RREG pseudooperations. X.P XRegister Symbols must be surrounded by parenthesis when used in expressions. XConverted register values are meaningless as ROM or Data memory addresses. XWorking set registers have a value between 0e0h and 0efh. X.DS I N XExample X.SP Xld r3, #(buffstart) X.DE X.H 3 "Data Memory" XROM and Data memory addresses are not differentiated. X.H 3 "Conditions" XConditions are represented by the reserved symbols F, C, NC, Z, NZ, PL, MI, XOV, NOV, EQ, NE, GE, LT, GT, LE, UGE, ULT, UGT, ULE X.P XNote that the EQ, NE, GT, LE, GE, LT operators are not available in this Xassembler, the =, <>, >, <=, >=, < special character representations must Xbe used. X.H 3 "Reserved Symbols" X.H 4 "Machine Dependent Reserved Symbols" XAND XC XDEFINED XEQ XF XGE XGT XHIGH XLE XLOW XLT XMI XMOD XNC XNE XNOT XNOV XNZ XOR XOV XPL XR0 XR1 XR10 XR11 XR12 XR13 XR14 XR15 XR2 XR3 XR4 XR5 XR6 XR7 XR8 XR9 XRR0 XRR10 XRR12 XRR14 XRR2 XRR4 XRR6 XRR8 XSHL XSHR XUGE XUGT XULE XULT XXOR XZ Xand Xdefined Xhigh Xlow Xmod Xnot Xor Xshl Xshr Xxor X.TC 1 1 7 SHAR_EOF true || echo 'restore of asz8.doc failed' fi # ============= asz8.tst ============== if test -f 'asz8.tst' -a X"$1" != X"-c"; then echo 'x - skipping asz8.tst (File already exists)' else echo 'x - extracting asz8.tst (Text)' sed 's/^X//' << 'SHAR_EOF' > 'asz8.tst' && Ximmed equ 11H Xxdest reg $2d Xxsrc reg $1c Xxddest rreg $44 X adc @ xdest , # immed X adc R13, @ R12 X adc R13, R12 X adc xdest , # immed X adc xdest, @ xsrc X adc xdest, xsrc X add @ xdest , # immed X add R13, @ R12 X add R13, R12 X add xdest , # immed X add xdest, @ xsrc X add xdest, xsrc X and @ xdest , # immed X and R13, @ R12 X and R13, R12 X and xdest , # immed X and xdest, @ xsrc X and xdest, xsrc X call @ xddest X call jmpdst X ccf X clr @ xdest X clr xdest X com @ xdest X com xdest X cp @ xdest , # immed X cp R13, @ R12 X cp R13, R12 X cp xdest , # immed X cp xdest, @ xsrc X cp xdest, xsrc X da @ xdest X da xdest X dec @ xdest X dec xdest X decw @ xddest X decw xddest X di X djnz R0, *+56 X djnz R1, *+56 X djnz R10, *+56 X djnz R11, *+56 X djnz R12, *+56 X djnz R13, *+56 X djnz R14, *+56 X djnz R15, *+56 X djnz R2, *+56 X djnz R3, *+56 X djnz R4, *+56 X djnz R5, *+56 X djnz R6, *+56 X djnz R7, *+56 X djnz R8, *+56 X djnz R9, *+56 X ei X inc @ xdest X inc R0 X inc R1 X inc R10 X inc R11 X inc R12 X inc R13 X inc R14 X inc R15 X inc R2 X inc R3 X inc R4 X inc R5 X inc R6 X inc R7 X inc R8 X inc R9 X inc xdest X incw @ xddest X incw xddest X iret X jp @ xddest X jp jmpdst X jp C, jmpdst X jp EQ, jmpdst X jp F, jmpdst X jp GE, jmpdst X jp GT, jmpdst X jp LE, jmpdst X jp LT, jmpdst X jp MI, jmpdst X jp NC, jmpdst X jp NE, jmpdst X jp NOV, jmpdst X jp NZ, jmpdst X jp OV, jmpdst X jp PL, jmpdst X jp UGE, jmpdst X jp UGT, jmpdst X jp ULE, jmpdst X jp ULT, jmpdst X jp Z, jmpdst X jr *+56 X jr C, *+56 X jr EQ, *+56 X jr F, *+56 X jr GE, *+56 X jr GT, *+56 X jr LE, *+56 X jr LT, *+56 X jr MI, *+56 X jr NC, *+56 X jr NE, *+56 X jr NOV, *+56 X jr NZ, *+56 X jr OV, *+56 X jr PL, *+56 X jr UGE, *+56 X jr UGT, *+56 X jr ULE, *+56 X jr ULT, *+56 X jr Z, *+56 X ld R13, $44(R12) X ld $55(R13), R12 X ld R13, @ R12 X ld xdest, xsrc X ld xdest, @ xsrc X ld xdest, # immed X ld @ xdest, # immed X ld @ R13, R12 X ld @ xdest, xsrc X ld R0, # immed X ld R0, xsrc X ld R1, # immed X ld R1, xsrc X ld R10, # immed X ld R10, xsrc X ld R11, # immed X ld R11, xsrc X ld R12, # immed X ld R12, xsrc X ld R13, # immed X ld R13, xsrc X ld R14, # immed X ld R14, xsrc X ld R15, # immed X ld R15, xsrc X ld R2, # immed X ld R2, xsrc X ld R3, # immed X ld R3, xsrc X ld R4, # immed X ld R4, xsrc X ld R5, # immed X ld R5, xsrc X ld R6, # immed X ld R6, xsrc X ld R7, # immed X ld R7, xsrc X ld R8, # immed X ld R8, xsrc X ld R9, # immed X ld R9, xsrc X ld xdest, R0 X ld xdest, R1 X ld xdest, R10 X ld xdest, R11 X ld xdest, R12 X ld xdest, R13 X ld xdest, R14 X ld xdest, R15 X ld xdest, R2 X ld xdest, R3 X ld xdest, R4 X ld xdest, R5 X ld xdest, R6 X ld xdest, R7 X ld xdest, R8 X ld xdest, R9 X ldc @ RR10, R13 X ldc R13, @RR10 X ldci @ R13, @RR10 X ldci @ RR10, @ R13 X lde @ RR10, R13 X lde R13, @RR10 X ldei @ R13, @RR10 X ldei @ RR10, @ R13 X nop X or @ xdest , # immed X or R13, @ R12 X or R13, R12 X or xdest , # immed X or xdest, @ xsrc X or xdest, xsrc X pop @ xdest X pop xdest X push @ xdest X push xdest X rcf X ret X rl @ xdest X rl xdest X rlc @ xdest X rlc xdest X rr @ xdest X rr xdest X rrc @ xdest X rrc xdest X sbc @ xdest , # immed X sbc R13, @ R12 X sbc R13, R12 X sbc xdest , # immed X sbc xdest, @ xsrc X sbc xdest, xsrc X scf X sra @ xdest X sra xdest X srp # 112 X sub @ xdest , # immed X sub R13, @ R12 X sub R13, R12 X sub xdest , # immed X sub xdest, @ xsrc X sub xdest, xsrc X swap @ xdest X swap xdest X tcm @ xdest , # immed X tcm R13, @ R12 X tcm R13, R12 X tcm xdest , # immed X tcm xdest, @ xsrc X tcm xdest, xsrc X tm @ xdest , # immed X tm R13, @ R12 X tm R13, R12 X tm xdest , # immed X tm xdest, @ xsrc X tm xdest, xsrc X xor @ xdest , # immed X xor R13, @ R12 X xor R13, R12 X xor xdest , # immed X xor xdest, @ xsrc X xor xdest, xsrc Xjmpdst SHAR_EOF true || echo 'restore of asz8.tst failed' fi # ============= asz8.tut ============== if test -f 'asz8.tut' -a X"$1" != X"-c"; then echo 'x - skipping asz8.tut (File already exists)' else echo 'x - extracting asz8.tut (Text)' sed 's/^X//' << 'SHAR_EOF' > 'asz8.tut' && X00000011 immed 0000002d xdest 0000001c xsrc X00000244 xddest 0000020a jmpdst X 0x11 immed equ 11H X 0x2d xdest reg $2d X 0x1c xsrc reg $1c X 0x44 xddest rreg $44 X0000 17 2d 11 adc @ xdest , # immed X0003 13 dc adc R13, @ R12 X0005 12 dc adc R13, R12 X0007 16 2d 11 adc xdest , # immed X000a 15 1c 2d adc xdest, @ xsrc X000d 14 1c 2d adc xdest, xsrc X0010 07 2d 11 add @ xdest , # immed X0013 03 dc add R13, @ R12 X0015 02 dc add R13, R12 X0017 06 2d 11 add xdest , # immed X001a 05 1c 2d add xdest, @ xsrc X001d 04 1c 2d add xdest, xsrc X0020 57 2d 11 and @ xdest , # immed X0023 53 dc and R13, @ R12 X0025 52 dc and R13, R12 X0027 56 2d 11 and xdest , # immed X002a 55 1c 2d and xdest, @ xsrc X002d 54 1c 2d and xdest, xsrc X0030 d4 44 call @ xddest X0032 d6 02 0a call jmpdst X0035 ef ccf X0036 b1 2d clr @ xdest X0038 b0 2d clr xdest X003a 61 2d com @ xdest X003c 60 2d com xdest X003e a7 2d 11 cp @ xdest , # immed X0041 a3 dc cp R13, @ R12 X0043 a2 dc cp R13, R12 X0045 a6 2d 11 cp xdest , # immed X0048 a5 1c 2d cp xdest, @ xsrc X004b a4 1c 2d cp xdest, xsrc X004e 41 2d da @ xdest X0050 40 2d da xdest X0052 01 2d dec @ xdest X0054 00 2d dec xdest X0056 81 44 decw @ xddest X0058 80 44 decw xddest X005a 8f di X005b 0a 36 djnz R0, *+56 X005d 1a 36 djnz R1, *+56 X005f aa 36 djnz R10, *+56 X0061 ba 36 djnz R11, *+56 X0063 ca 36 djnz R12, *+56 X0065 da 36 djnz R13, *+56 X0067 ea 36 djnz R14, *+56 X0069 fa 36 djnz R15, *+56 X006b 2a 36 djnz R2, *+56 X006d 3a 36 djnz R3, *+56 X006f 4a 36 djnz R4, *+56 X0071 5a 36 djnz R5, *+56 X0073 6a 36 djnz R6, *+56 X0075 7a 36 djnz R7, *+56 X0077 8a 36 djnz R8, *+56 X0079 9a 36 djnz R9, *+56 X007b 9f ei X007c 21 2d inc @ xdest X007e 0e inc R0 X007f 1e inc R1 X0080 ae inc R10 X0081 be inc R11 X0082 ce inc R12 X0083 de inc R13 X0084 ee inc R14 X0085 fe inc R15 X0086 2e inc R2 X0087 3e inc R3 X0088 4e inc R4 X0089 5e inc R5 X008a 6e inc R6 X008b 7e inc R7 X008c 8e inc R8 X008d 9e inc R9 X008e 20 2d inc xdest X0090 a1 44 incw @ xddest X0092 a0 44 incw xddest X0094 bf iret X0095 30 44 jp @ xddest X0097 8d 02 0a jp jmpdst X009a 7d 02 0a jp C, jmpdst X009d 6d 02 0a jp EQ, jmpdst X00a0 0d 02 0a jp F, jmpdst X00a3 9d 02 0a jp GE, jmpdst X00a6 ad 02 0a jp GT, jmpdst X00a9 2d 02 0a jp LE, jmpdst X00ac 1d 02 0a jp LT, jmpdst X00af 5d 02 0a jp MI, jmpdst X00b2 fd 02 0a jp NC, jmpdst X00b5 ed 02 0a jp NE, jmpdst X00b8 cd 02 0a jp NOV, jmpdst X00bb ed 02 0a jp NZ, jmpdst X00be 4d 02 0a jp OV, jmpdst X00c1 dd 02 0a jp PL, jmpdst X00c4 fd 02 0a jp UGE, jmpdst X00c7 bd 02 0a jp UGT, jmpdst X00ca 3d 02 0a jp ULE, jmpdst X00cd 7d 02 0a jp ULT, jmpdst X00d0 6d 02 0a jp Z, jmpdst X00d3 8b 36 jr *+56 X00d5 7b 36 jr C, *+56 X00d7 6b 36 jr EQ, *+56 X00d9 0b 36 jr F, *+56 X00db 9b 36 jr GE, *+56 X00dd ab 36 jr GT, *+56 X00df 2b 36 jr LE, *+56 X00e1 1b 36 jr LT, *+56 X00e3 5b 36 jr MI, *+56 X00e5 fb 36 jr NC, *+56 X00e7 eb 36 jr NE, *+56 X00e9 cb 36 jr NOV, *+56 X00eb eb 36 jr NZ, *+56 X00ed 4b 36 jr OV, *+56 X00ef db 36 jr PL, *+56 X00f1 fb 36 jr UGE, *+56 X00f3 bb 36 jr UGT, *+56 X00f5 3b 36 jr ULE, *+56 X00f7 7b 36 jr ULT, *+56 X00f9 6b 36 jr Z, *+56 X00fb c7 dc 44 ld R13, $44(R12) X00fe d7 cd 55 ld $55(R13), R12 X0101 e3 dc ld R13, @ R12 X0103 e4 1c 2d ld xdest, xsrc X0106 e5 1c 2d ld xdest, @ xsrc X0109 e6 2d 11 ld xdest, # immed X010c e7 2d 11 ld @ xdest, # immed X010f f3 dc ld @ R13, R12 X0111 f5 1c 2d ld @ xdest, xsrc X0114 0c 11 ld R0, # immed X0116 08 1c ld R0, xsrc X0118 1c 11 ld R1, # immed X011a 18 1c ld R1, xsrc X011c ac 11 ld R10, # immed X011e a8 1c ld R10, xsrc X0120 bc 11 ld R11, # immed X0122 b8 1c ld R11, xsrc X0124 cc 11 ld R12, # immed X0126 c8 1c ld R12, xsrc X0128 dc 11 ld R13, # immed X012a d8 1c ld R13, xsrc X012c ec 11 ld R14, # immed X012e e8 1c ld R14, xsrc X0130 fc 11 ld R15, # immed X0132 f8 1c ld R15, xsrc X0134 2c 11 ld R2, # immed X0136 28 1c ld R2, xsrc X0138 3c 11 ld R3, # immed X013a 38 1c ld R3, xsrc X013c 4c 11 ld R4, # immed X013e 48 1c ld R4, xsrc X0140 5c 11 ld R5, # immed X0142 58 1c ld R5, xsrc X0144 6c 11 ld R6, # immed X0146 68 1c ld R6, xsrc X0148 7c 11 ld R7, # immed X014a 78 1c ld R7, xsrc X014c 8c 11 ld R8, # immed X014e 88 1c ld R8, xsrc X0150 9c 11 ld R9, # immed X0152 98 1c ld R9, xsrc X0154 09 2d ld xdest, R0 X0156 19 2d ld xdest, R1 X0158 a9 2d ld xdest, R10 X015a b9 2d ld xdest, R11 X015c c9 2d ld xdest, R12 X015e d9 2d ld xdest, R13 X0160 e9 2d ld xdest, R14 X0162 f9 2d ld xdest, R15 X0164 29 2d ld xdest, R2 X0166 39 2d ld xdest, R3 X0168 49 2d ld xdest, R4 X016a 59 2d ld xdest, R5 X016c 69 2d ld xdest, R6 X016e 79 2d ld xdest, R7 X0170 89 2d ld xdest, R8 X0172 99 2d ld xdest, R9 X0174 d2 da ldc @ RR10, R13 X0176 c2 da ldc R13, @RR10 X0178 c3 da ldci @ R13, @RR10 X017a d3 da ldci @ RR10, @ R13 X017c 92 da lde @ RR10, R13 X017e 82 da lde R13, @RR10 X0180 83 da ldei @ R13, @RR10 X0182 93 da ldei @ RR10, @ R13 X0184 ff nop X0185 47 2d 11 or @ xdest , # immed X0188 43 dc or R13, @ R12 X018a 42 dc or R13, R12 X018c 46 2d 11 or xdest , # immed X018f 45 1c 2d or xdest, @ xsrc X0192 44 1c 2d or xdest, xsrc X0195 51 2d pop @ xdest X0197 50 2d pop xdest X0199 71 2d push @ xdest X019b 70 2d push xdest X019d cf rcf X019e af ret X019f 91 2d rl @ xdest X01a1 90 2d rl xdest X01a3 11 2d rlc @ xdest X01a5 10 2d rlc xdest X01a7 e1 2d rr @ xdest X01a9 e0 2d rr xdest X01ab c1 2d rrc @ xdest X01ad c0 2d rrc xdest X01af 37 2d 11 sbc @ xdest , # immed X01b2 33 dc sbc R13, @ R12 X01b4 32 dc sbc R13, R12 X01b6 36 2d 11 sbc xdest , # immed X01b9 35 1c 2d sbc xdest, @ xsrc X01bc 34 1c 2d sbc xdest, xsrc X01bf df scf X01c0 d1 2d sra @ xdest X01c2 d0 2d sra xdest X01c4 31 70 srp # 112 X01c6 27 2d 11 sub @ xdest , # immed X01c9 23 dc sub R13, @ R12 X01cb 22 dc sub R13, R12 X01cd 26 2d 11 sub xdest , # immed X01d0 25 1c 2d sub xdest, @ xsrc X01d3 24 1c 2d sub xdest, xsrc X01d6 f1 2d swap @ xdest X01d8 f0 2d swap xdest X01da 67 2d 11 tcm @ xdest , # immed X01dd 63 dc tcm R13, @ R12 X01df 62 dc tcm R13, R12 X01e1 66 2d 11 tcm xdest , # immed X01e4 65 1c 2d tcm xdest, @ xsrc X01e7 64 1c 2d tcm xdest, xsrc X01ea 77 2d 11 tm @ xdest , # immed X01ed 73 dc tm R13, @ R12 X01ef 72 dc tm R13, R12 X01f1 76 2d 11 tm xdest , # immed X01f4 75 1c 2d tm xdest, @ xsrc X01f7 74 1c 2d tm xdest, xsrc X01fa b7 2d 11 xor @ xdest , # immed X01fd b3 dc xor R13, @ R12 X01ff b2 dc xor R13, R12 X0201 b6 2d 11 xor xdest , # immed X0204 b5 1c 2d xor xdest, @ xsrc X0207 b4 1c 2d xor xdest, xsrc X 0x20a jmpdst X ERROR SUMMARY - ERRORS DETECTED 0 X - WARNINGS 0 SHAR_EOF true || echo 'restore of asz8.tut failed' fi # ============= asz8.y ============== if test -f 'asz8.y' -a X"$1" != X"-c"; then echo 'x - skipping asz8.y (File already exists)' else echo 'x - extracting asz8.y (Text)' sed 's/^X//' << 'SHAR_EOF' > 'asz8.y' && X%{ X X/* XHEADER: ; XTITLE: Frankenstein Cross Assemblers; XVERSION: 2.0; XDESCRIPTION: " Reconfigurable Cross-assembler producing Intel (TM) X Hex format object records. "; XKEYWORDS: cross-assemblers, 1805, 2650, 6301, 6502, 6805, 6809, X 6811, tms7000, 8048, 8051, 8096, z8, z80; XSYSTEM: UNIX, MS-Dos ; XFILENAME: asz8.y; XWARNINGS: "This software is in the public domain. X Any prior copyright claims are relinquished. X X This software is distributed with no warranty whatever. X The author takes no responsibility for the consequences X of its use. X X Yacc (or Bison) required to compile." ; XSEE-ALSO: asz8.doc,frasmain.c; XAUTHORS: Mark Zenier; XCOMPILERS: Microport Sys V/AT, ATT Yacc, Turbo C V1.5, Bison (CUG disk 285) X (previous versions Xenix, Unisoft 68000 Version 7, Sun 3); X*/ X/* z8 instruction generation file */ X/* November 17, 1990 */ X X/* X description frame work parser description for framework cross X assemblers X history February 2, 1988 X September 11, 1990 - merge table definition X September 12, 1990 - short file names X September 14, 1990 - short variable names X September 17, 1990 - use yylex as external X*/ X#include <stdio.h> X#include "frasmdat.h" X#include "fragcon.h" X X#define yylex lexintercept X X/* X file critz8.h X author Mark Zenier X description Selection criteria and syntax type constants for X the z8 framework assembler X usage Unix X history October 28, 1987 X*/ X X/* 0000.0000.0000.000x destination register is in working set */ X#define DSTWORK 0x1 X X/* 0000.0000.0000.00x0 destination is double register */ X#define DSTDBL 0x2 X X/* 0000.0000.0000.0x00 source register is in working set */ X#define SRCWORK 0x4 X X/* 0000.0000.0000.x000 source is double register */ X#define SRCDBL 0x8 X X/* type flags for symbol table value for registers */ X#define REGFLGSHFT 8 X#define REGDFLGSH REGFLGSHFT X#define REGSFLGSH (REGFLGSHFT -2) X#define REGFLGS ((DSTWORK|DSTDBL)<<REGFLGSHFT) X#define REGDEFWRK (DSTWORK<<REGFLGSHFT) X#define REGDEFDBL (DSTDBL<<REGFLGSHFT) X#define REGBITS 0xff X#define REGWORKBITS 0xf X X#define CPU8600 1 /* use z8 register set */ X#define CPU8090 2 /* use UPC register set */ X#define ST_CEXP 0x1 X#define ST_EXP 0x2 X#define ST_INH 0x4 X#define ST_IR1 0x8 X#define ST_IRIM 0x10 X#define ST_IRIR 0x20 X#define ST_IRR 0x40 X#define ST_R1 0x80 X#define ST_R2 0x100 X#define ST_REXP 0x200 X#define ST_RIMM 0x400 X#define ST_RIR 0x800 X#define ST_RX 0x1000 X#define ST_XR 0x2000 X#define ST_IMM 0x1 X X int cpuselect = CPU8600; X static char genbdef[] = "[1=];"; X static char genwdef[] = "[1=]x"; X char ignosyn[] = "[Xinvalid syntax for instruction"; X char ignosel[] = "[Xinvalid operands"; X int prevregwork = 0; X int regloccnt = 0; X X long labelloc; X static int satsub; X int ifstkpt = 0; X int fraifskip = FALSE; X X struct symel * endsymbol = SYMNULL; X X%} X%union { X int intv; X long longv; X char *strng; X struct symel *symb; X} X X%token <intv> REGISTER X%token <intv> CONDITION X X%type <intv> regdefop regoperand X X%token <intv> KOC_BDEF X%token <intv> KOC_ELSE X%token <intv> KOC_END X%token <intv> KOC_ENDI X%token <intv> KOC_EQU X%token <intv> KOC_IF X%token <intv> KOC_INCLUDE X%token <intv> KOC_ORG X%token <intv> KOC_RESM X%token <intv> KOC_SDEF X%token <intv> KOC_SET X%token <intv> KOC_WDEF X%token <intv> KOC_CHSET X%token <intv> KOC_CHDEF X%token <intv> KOC_CHUSE X%token <intv> KOC_REG X%token <intv> KOC_RREG X%token <intv> KOC_CPU X%token <intv> KOC_opcode X%token <intv> KOC_srp X X%token <longv> CONSTANT X%token EOL X%token KEOP_AND X%token KEOP_DEFINED X%token KEOP_EQ X%token KEOP_GE X%token KEOP_GT X%token KEOP_HIGH X%token KEOP_LE X%token KEOP_LOW X%token KEOP_LT X%token KEOP_MOD X%token KEOP_MUN X%token KEOP_NE X%token KEOP_NOT X%token KEOP_OR X%token KEOP_SHL X%token KEOP_SHR X%token KEOP_XOR X%token KEOP_locctr X%token <symb> LABEL X%token <strng> STRING X%token <symb> SYMBOL X X%token KTK_invalid X X%right KEOP_HIGH KEOP_LOW X%left KEOP_OR KEOP_XOR X%left KEOP_AND X%right KEOP_NOT X%nonassoc KEOP_GT KEOP_GE KEOP_LE KEOP_LT KEOP_NE KEOP_EQ X%left '+' '-' X%left '*' '/' KEOP_MOD KEOP_SHL KEOP_SHR X%right KEOP_MUN X X X%type <intv> expr exprlist stringlist X X%start file X X%% X Xfile : file allline X | allline X ; X Xallline : line EOL X { X clrexpr(); X } X | EOL X | error EOL X { X clrexpr(); X yyerrok; X } X ; X Xline : LABEL KOC_END X { X endsymbol = $1; X nextreadact = Nra_end; X } X | KOC_END X { X nextreadact = Nra_end; X } X | KOC_INCLUDE STRING X { X if(nextfstk >= FILESTKDPTH) X { X fraerror("include file nesting limit exceeded"); X } X else X { X infilestk[nextfstk].fnm = savestring($2,strlen($2)); X if( (infilestk[nextfstk].fpt = fopen($2,"r")) X ==(FILE *)NULL ) X { X fraerror("cannot open include file"); X } X else X { X nextreadact = Nra_new; X } X } X } X | LABEL KOC_EQU expr X { X if($1 -> seg == SSG_UNDEF) X { X pevalexpr(0, $3); X if(evalr[0].seg == SSG_ABS) X { X $1 -> seg = SSG_EQU; X $1 -> value = evalr[0].value; X prtequvalue("C: 0x%lx\n", X evalr[0].value); X } X else X { X fraerror( X "noncomputable expression for EQU"); X } X } X else X { X fraerror( X "cannot change symbol value with EQU"); X } X } X | LABEL KOC_SET expr X { X if($1 -> seg == SSG_UNDEF X || $1 -> seg == SSG_SET) X { X pevalexpr(0, $3); X if(evalr[0].seg == SSG_ABS) X { X $1 -> seg = SSG_SET; X $1 -> value = evalr[0].value; X prtequvalue("C: 0x%lx\n", X evalr[0].value); X } X else X { X fraerror( X "noncomputable expression for SET"); X } X } X else X { X fraerror( X "cannot change symbol value with SET"); X } X } X | KOC_IF expr X { X if((++ifstkpt) < IFSTKDEPTH) X { X pevalexpr(0, $2); X if(evalr[0].seg == SSG_ABS) X { X if(evalr[0].value != 0) X { X elseifstk[ifstkpt] = If_Skip; X endifstk[ifstkpt] = If_Active; X } X else X { X fraifskip = TRUE; X elseifstk[ifstkpt] = If_Active; X endifstk[ifstkpt] = If_Active; X } X } X else X { X fraifskip = TRUE; X elseifstk[ifstkpt] = If_Active; X endifstk[ifstkpt] = If_Active; X } X } X else X { X fraerror("IF stack overflow"); X } X } X X | KOC_IF X { X if(fraifskip) X { X if((++ifstkpt) < IFSTKDEPTH) X { X elseifstk[ifstkpt] = If_Skip; X endifstk[ifstkpt] = If_Skip; X } X else X { X fraerror("IF stack overflow"); X } X } X else X { X yyerror("syntax error"); X YYERROR; X } X } X X | KOC_ELSE X { X switch(elseifstk[ifstkpt]) X { X case If_Active: X fraifskip = FALSE; X break; X X case If_Skip: X fraifskip = TRUE; X break; X X case If_Err: X fraerror("ELSE with no matching if"); X break; X } X } X X | KOC_ENDI X { X switch(endifstk[ifstkpt]) X { X case If_Active: X fraifskip = FALSE; X ifstkpt--; X break; X X case If_Skip: X fraifskip = TRUE; X ifstkpt--; X break; X X case If_Err: X fraerror("ENDI with no matching if"); X break; X } X } X | LABEL KOC_ORG expr X { X pevalexpr(0, $3); X if(evalr[0].seg == SSG_ABS) X { X locctr = labelloc = evalr[0].value; X if($1 -> seg == SSG_UNDEF) X { X $1 -> seg = SSG_ABS; X $1 -> value = labelloc; X } X else X fraerror( X "multiple definition of label"); X prtequvalue("C: 0x%lx\n", X evalr[0].value); X } X else X { X fraerror( X "noncomputable expression for ORG"); X } X } X | KOC_ORG expr X { X pevalexpr(0, $2); X if(evalr[0].seg == SSG_ABS) X { X locctr = labelloc = evalr[0].value; X prtequvalue("C: 0x%lx\n", X evalr[0].value); X } X else X { X fraerror( X "noncomputable expression for ORG"); X } X } X | LABEL KOC_CHSET X { X if($1 -> seg == SSG_UNDEF) X { X $1 -> seg = SSG_EQU; X if( ($1->value = chtcreate()) <= 0) X { X fraerror( "cannot create character translation table"); X } X prtequvalue("C: 0x%lx\n", $1 -> value); X } X else X { X fraerror( "multiple definition of label"); X } X } X | KOC_CHUSE X { X chtcpoint = (int *) NULL; X prtequvalue("C: 0x%lx\n", 0L); X } X | KOC_CHUSE expr X { X pevalexpr(0, $2); X if( evalr[0].seg == SSG_ABS) X { X if( evalr[0].value == 0) X { X chtcpoint = (int *)NULL; X prtequvalue("C: 0x%lx\n", 0L); X } X else if(evalr[0].value < chtnxalph) X { X chtcpoint = chtatab[evalr[0].value]; X prtequvalue("C: 0x%lx\n", evalr[0].value); X } X else X { X fraerror("nonexistent character translation table"); X } X } X else X { X fraerror("noncomputable expression"); X } X } X | KOC_CHDEF STRING ',' exprlist X { X int findrv, numret, *charaddr; X char *sourcestr = $2, *before; X X if(chtnpoint != (int *)NULL) X { X for(satsub = 0; satsub < $4; satsub++) X { X before = sourcestr; X X pevalexpr(0, exprlist[satsub]); X findrv = chtcfind(chtnpoint, &sourcestr, X &charaddr, &numret); X if(findrv == CF_END) X { X fraerror("more expressions than characters"); X break; X } X X if(evalr[0].seg == SSG_ABS) X { X switch(findrv) X { X case CF_UNDEF: X { X if(evalr[0].value < 0 || X evalr[0].value > 255) X { X frawarn("character translation value truncated"); X } X *charaddr = evalr[0].value & 0xff; X prtequvalue("C: 0x%lx\n", evalr[0].value); X } X break; X X case CF_INVALID: X case CF_NUMBER: X fracherror("invalid character to define", X before, sourcestr); X break; X X case CF_CHAR: X fracherror("character already defined", X before, sourcestr); X break; X } X } X else X { X fraerror("noncomputable expression"); X } X } X X if( *sourcestr != '\0') X { X fraerror("more characters than expressions"); X } X } X else X { X fraerror("no CHARSET statement active"); X } X X } X | LABEL X { X if($1 -> seg == SSG_UNDEF) X { X $1 -> seg = SSG_ABS; X $1 -> value = labelloc; X prtequvalue("C: 0x%lx\n", labelloc); X X } X else X fraerror( X "multiple definition of label"); X } X | labeledline X ; X Xlabeledline : LABEL genline X { X if($1 -> seg == SSG_UNDEF) X { X $1 -> seg = SSG_ABS; X $1 -> value = labelloc; X } X else X fraerror( X "multiple definition of label"); X labelloc = locctr; X } X X | genline X { X labelloc = locctr; X } X ; X Xgenline : KOC_BDEF exprlist X { X genlocrec(currseg, labelloc); X for( satsub = 0; satsub < $2; satsub++) X { X pevalexpr(1, exprlist[satsub]); X locctr += geninstr(genbdef); X } X } X | KOC_SDEF stringlist X { X genlocrec(currseg, labelloc); X for(satsub = 0; satsub < $2; satsub++) X { X locctr += genstring(stringlist[satsub]); X } X } X | KOC_WDEF exprlist X { X genlocrec(currseg, labelloc); X for( satsub = 0; satsub < $2; satsub++) X { X pevalexpr(1, exprlist[satsub]); X locctr += geninstr(genwdef); X } X } X | KOC_RESM expr X { X pevalexpr(0, $2); X if(evalr[0].seg == SSG_ABS) X { X locctr = labelloc + evalr[0].value; X prtequvalue("C: 0x%lx\n", labelloc); X } X else X { X fraerror( X "noncomputable result for RMB expression"); X } X } X ; X Xexprlist : exprlist ',' expr X { X exprlist[nextexprs ++ ] = $3; X $$ = nextexprs; X } X | expr X { X nextexprs = 0; X exprlist[nextexprs ++ ] = $1; X $$ = nextexprs; X } X ; X Xstringlist : stringlist ',' STRING X { X stringlist[nextstrs ++ ] = $3; X $$ = nextstrs; X } X | STRING X { X nextstrs = 0; X stringlist[nextstrs ++ ] = $1; X $$ = nextstrs; X } X ; X X X Xline : LABEL regdefop regoperand X { X if($1 -> seg == SSG_UNDEF) X { X $1 -> value = ( $3 & REGBITS ) X | ( $3 & REGDEFWRK ) X | ($2 == 2 ? REGDEFDBL : 0); X $1 -> seg = SSG_RESV; X $1 -> tok = REGISTER; X X if($3 & REGDEFWRK) X { X if(($3 & 0xf0) != 0xe0) X fraerror( X "invalid working register address"); X } X else X { X switch(cpuselect) X { X case CPU8600: X if( ($3 & REGBITS) > 0x7f && X ($3 & REGBITS) < 0xf0) X { X fraerror( X "unimplemented register address"); X } X break; X X case CPU8090: X if( ($3 & REGBITS) > 0xdf && X ($3 & REGBITS) < 0xf0) X { X fraerror( X "unimplemented register address"); X } X break; X X } X } X X if( ( $1 -> value & REGDEFDBL) && ( $1 -> value & 1) ) X fraerror("double register not on even boundry"); X X prtequvalue("C: 0x%x\n",REGBITS & ((int) $1->value)); X } X else X { X fraerror("multiple definition of label"); X } X prevregwork = $3 & REGDEFWRK; X regloccnt = ($3 & REGBITS) + $2; X } X ; X Xregdefop : KOC_REG X { X $$ = 1; X } X | KOC_RREG X { X $$ = 2; X } X ; X Xregoperand : REGISTER X { X $$ = $1; X } X | expr X { X $$ = 0; X pevalexpr(0, $1); X if(evalr[0].seg != SSG_ABS) X { X fraerror("noncomputable value for REG"); X } X else X { X if(evalr[0].value >= 0 && evalr[0].value <= 255) X $$ = evalr[0].value; X else X fraerror("value out of range"); X } X } X | X { X if(regloccnt <= 255) X $$ = regloccnt | prevregwork ; X else X { X $$ = 0; X fraerror("register location counter out of range"); X } X } X ; X Xline : KOC_CPU STRING X { X if( ! cpumatch($2)) X { X fraerror("unknown cpu type, z8 assumed"); X cpuselect = CPU8600; X } X } X ; Xgenline : KOC_opcode CONDITION ',' expr X { X genlocrec(currseg, labelloc); X evalr[1].value = $2; X pevalexpr(2, $4); X locctr += geninstr(findgen($1, ST_CEXP, 0)); X } X ; Xgenline : KOC_opcode expr X { X genlocrec(currseg, labelloc); X pevalexpr(1, $2); X locctr += geninstr(findgen($1, ST_EXP, 0)); X } X ; Xgenline : KOC_opcode X { X genlocrec(currseg, labelloc); X locctr += geninstr(findgen($1, ST_INH, 0)); X } X ; Xgenline : KOC_opcode '@' REGISTER X { X genlocrec(currseg, labelloc); X evalr[1].value = $3 & REGBITS; X evalr[2].value = $3 & REGWORKBITS; X locctr += geninstr(findgen($1, ST_IR1, X ($3 & REGFLGS) >> REGDFLGSH )); X } X ; Xgenline : KOC_opcode '@' REGISTER ',' '#' expr X { X genlocrec(currseg, labelloc); X evalr[1].value = $3 & REGBITS; X evalr[3].value = $3 & REGWORKBITS; X pevalexpr(2, $6); X locctr += geninstr(findgen($1, ST_IRIM, X ($3 & REGFLGS) >> REGDFLGSH )); X } X ; Xgenline : KOC_opcode '@' REGISTER ',' '@' REGISTER X { X genlocrec(currseg, labelloc); X evalr[1].value = $3 & REGBITS; X evalr[2].value = $3 & REGWORKBITS; X evalr[3].value = $6 & REGBITS; X evalr[4].value = $6 & REGWORKBITS; X locctr += geninstr(findgen($1, ST_IRIR, X ( ($3 & REGFLGS) >> REGDFLGSH ) | X ( ($6 & REGFLGS) >> REGSFLGSH ) )); X } X ; Xgenline : KOC_opcode '@' REGISTER ',' REGISTER X { X genlocrec(currseg, labelloc); X evalr[1].value = $3 & REGBITS; X evalr[2].value = $3 & REGWORKBITS; X evalr[3].value = $5 & REGBITS; X evalr[4].value = $5 & REGWORKBITS; X locctr += geninstr(findgen($1, ST_IRR, X ( ($3 & REGFLGS) >> REGDFLGSH ) | X ( ($5 & REGFLGS) >> REGSFLGSH ) )); X } X ; Xgenline : KOC_opcode REGISTER X { X genlocrec(currseg, labelloc); X evalr[1].value = $2 & REGBITS; X evalr[2].value = $2 & REGWORKBITS; X locctr += geninstr(findgen($1, ST_R1, X ($2 & REGFLGS) >> REGDFLGSH )); X } X ; Xgenline : KOC_opcode REGISTER ',' REGISTER X { X genlocrec(currseg, labelloc); X evalr[1].value = $2 & REGBITS; X evalr[2].value = $2 & REGWORKBITS; X evalr[3].value = $4 & REGBITS; X evalr[4].value = $4 & REGWORKBITS; X locctr += geninstr(findgen($1, ST_R2, X ( ($2 & REGFLGS) >> REGDFLGSH ) | X ( ($4 & REGFLGS) >> REGSFLGSH ) )); X } X ; Xgenline : KOC_opcode REGISTER ',' expr X { X genlocrec(currseg, labelloc); X evalr[1].value = $2 & REGBITS; X pevalexpr(2, $4); X evalr[3].value = $2 & REGWORKBITS; X locctr += geninstr(findgen($1, ST_REXP, X ($2 & REGFLGS) >> REGDFLGSH )); X } X ; Xgenline : KOC_opcode REGISTER ',' '#' expr X { X genlocrec(currseg, labelloc); X evalr[1].value = $2 & REGBITS; X evalr[3].value = $2 & REGWORKBITS; X pevalexpr(2, $5); X locctr += geninstr(findgen($1, ST_RIMM, X ($2 & REGFLGS) >> REGDFLGSH )); X } X ; Xgenline : KOC_opcode REGISTER ',' '@' REGISTER X { X genlocrec(currseg, labelloc); X evalr[1].value = $2 & REGBITS; X evalr[2].value = $2 & REGWORKBITS; X evalr[3].value = $5 & REGBITS; X evalr[4].value = $5 & REGWORKBITS; X locctr += geninstr(findgen($1, ST_RIR, X ( ($2 & REGFLGS) >> REGDFLGSH ) | X ( ($5 & REGFLGS) >> REGSFLGSH ) )); X } X ; Xgenline : KOC_opcode REGISTER ',' expr '(' REGISTER ')' X { X genlocrec(currseg, labelloc); X evalr[1].value = $2 & REGWORKBITS; X pevalexpr(2, $4); X evalr[3].value = $6 & REGWORKBITS; X locctr += geninstr(findgen($1, ST_RX, X ( ($2 & REGFLGS) >> REGDFLGSH ) | X ( ($6 & REGFLGS) >> REGSFLGSH ) )); X } X ; Xgenline : KOC_opcode expr '(' REGISTER ')' ',' REGISTER X { X genlocrec(currseg, labelloc); X pevalexpr(1, $2); X evalr[2].value = $4 & REGWORKBITS; X evalr[3].value = $7 & REGWORKBITS; X locctr += geninstr(findgen($1, ST_XR, X ( ($4 & REGFLGS) >> REGDFLGSH ) | X ( ($7 & REGFLGS) >> REGSFLGSH ) )); X } X ; Xgenline : KOC_srp '#' expr X { X pevalexpr(1, $3); X if(evalr[1].seg != SSG_ABS) X { X fraerror("noncomputable value for SRP"); X } X else X { X switch(( (int) evalr[1].value ) & REGBITS) X { X case 0x80: X case 0x90: X case 0xa0: X case 0xb0: X case 0xc0: X case 0xd0: X if(cpuselect == CPU8600) X { X fraerror("invalid value for SRP"); X break; X } X /* fall thru */ X case 0x00: X case 0x10: X case 0x20: X case 0x30: X case 0x40: X case 0x50: X case 0x60: X case 0x70: X case 0xf0: X genlocrec(currseg, labelloc); X locctr += geninstr(findgen($1, ST_IMM, 0)); X break; X default: X fraerror("invalid value for SRP"); X break; X } X } X } X ; Xexpr : '+' expr %prec KEOP_MUN X { X $$ = $2; X } X | '-' expr %prec KEOP_MUN X { X $$ = exprnode(PCCASE_UN,$2,IFC_NEG,0,0L, X SYMNULL); X } X | KEOP_NOT expr X { X $$ = exprnode(PCCASE_UN,$2,IFC_NOT,0,0L, X SYMNULL); X } X | KEOP_HIGH expr X { X $$ = exprnode(PCCASE_UN,$2,IFC_HIGH,0,0L, X SYMNULL); X } X | KEOP_LOW expr X { X $$ = exprnode(PCCASE_UN,$2,IFC_LOW,0,0L, X SYMNULL); X } X | expr '*' expr X { X $$ = exprnode(PCCASE_BIN,$1,IFC_MUL,$3,0L, X SYMNULL); X } X | expr '/' expr X { X $$ = exprnode(PCCASE_BIN,$1,IFC_DIV,$3,0L, X SYMNULL); X } X | expr '+' expr X { X $$ = exprnode(PCCASE_BIN,$1,IFC_ADD,$3,0L, X SYMNULL); X } X | expr '-' expr X { X $$ = exprnode(PCCASE_BIN,$1,IFC_SUB,$3,0L, X SYMNULL); X } X | expr KEOP_MOD expr X { X $$ = exprnode(PCCASE_BIN,$1,IFC_MOD,$3,0L, X SYMNULL); X } X | expr KEOP_SHL expr X { X $$ = exprnode(PCCASE_BIN,$1,IFC_SHL,$3,0L, X SYMNULL); X } X | expr KEOP_SHR expr X { X $$ = exprnode(PCCASE_BIN,$1,IFC_SHR,$3,0L, X SYMNULL); X } X | expr KEOP_GT expr X { X $$ = exprnode(PCCASE_BIN,$1,IFC_GT,$3,0L, X SYMNULL); X } X | expr KEOP_GE expr X { X $$ = exprnode(PCCASE_BIN,$1,IFC_GE,$3,0L, X SYMNULL); X } X | expr KEOP_LT expr X { X $$ = exprnode(PCCASE_BIN,$1,IFC_LT,$3,0L, X SYMNULL); X } X | expr KEOP_LE expr X { X $$ = exprnode(PCCASE_BIN,$1,IFC_LE,$3,0L, X SYMNULL); X } X | expr KEOP_NE expr X { X $$ = exprnode(PCCASE_BIN,$1,IFC_NE,$3,0L, X SYMNULL); X } X | expr KEOP_EQ expr X { X $$ = exprnode(PCCASE_BIN,$1,IFC_EQ,$3,0L, X SYMNULL); X } X | expr KEOP_AND expr X { X $$ = exprnode(PCCASE_BIN,$1,IFC_AND,$3,0L, X SYMNULL); X } X | expr KEOP_OR expr X { X $$ = exprnode(PCCASE_BIN,$1,IFC_OR,$3,0L, X SYMNULL); X } X | expr KEOP_XOR expr X { X $$ = exprnode(PCCASE_BIN,$1,IFC_XOR,$3,0L, X SYMNULL); X } X | KEOP_DEFINED SYMBOL X { X $$ = exprnode(PCCASE_DEF,0,IGP_DEFINED,0,0L,$2); X } X | SYMBOL X { X $$ = exprnode(PCCASE_SYMB,0,IFC_SYMB,0,0L,$1); X } X | '*' X { X $$ = exprnode(PCCASE_PROGC,0,IFC_PROGCTR,0, X labelloc, SYMNULL); X } X | CONSTANT X { X $$ = exprnode(PCCASE_CONS,0,IGP_CONSTANT,0,$1, X SYMNULL); X } X | STRING X { X char *sourcestr = $1; X long accval = 0; X X if(strlen($1) > 0) X { X accval = chtran(&sourcestr); X if(*sourcestr != '\0') X { X accval = (accval << 8) + X chtran(&sourcestr); X } X X if( *sourcestr != '\0') X { X frawarn("string constant in expression more than 2 characters long"); X } X } X $$ = exprnode(PCCASE_CONS, 0, IGP_CONSTANT, 0, X accval, SYMNULL); X } X | '(' expr ')' X { X $$ = $2; X } X ; X Xexpr : '(' REGISTER ')' X { X $$ = exprnode(PCCASE_CONS,0,IGP_CONSTANT,0, X (long) (REGBITS & $2), X SYMNULL); X } X ; X X%% X Xlexintercept() X/* X description intercept the call to yylex (the lexical analyzer) X and filter out all unnecessary tokens when skipping X the input between a failed IF and its matching ENDI or X ELSE X globals fraifskip the enable flag X*/ X{ X#undef yylex X X int rv; X X if(fraifskip) X { X for(;;) X { X X switch(rv = yylex()) X X { X case 0: X case KOC_END: X case KOC_IF: X case KOC_ELSE: X case KOC_ENDI: X case EOL: X return rv; X default: X break; X } X } X } X else X return yylex(); X#define yylex lexintercept X} X X X Xsetreserved() X{ X X reservedsym("and", KEOP_AND, 0); X reservedsym("defined", KEOP_DEFINED,0); X reservedsym("high", KEOP_HIGH, 0); X reservedsym("low", KEOP_LOW, 0); X reservedsym("mod", KEOP_MOD, 0); X reservedsym("not", KEOP_NOT, 0); X reservedsym("or", KEOP_OR, 0); X reservedsym("shl", KEOP_SHL, 0); X reservedsym("shr", KEOP_SHR, 0); X reservedsym("xor", KEOP_XOR, 0); X reservedsym("AND", KEOP_AND, 0); X reservedsym("DEFINED", KEOP_DEFINED,0); X reservedsym("HIGH", KEOP_HIGH, 0); X reservedsym("LOW", KEOP_LOW, 0); X reservedsym("MOD", KEOP_MOD, 0); X reservedsym("NOT", KEOP_NOT, 0); X reservedsym("OR", KEOP_OR, 0); X reservedsym("SHL", KEOP_SHL, 0); X reservedsym("SHR", KEOP_SHR, 0); X reservedsym("XOR", KEOP_XOR, 0); X reservedsym("F", CONDITION, 0); X reservedsym("C", CONDITION, 0x7); X reservedsym("NC", CONDITION, 0xf); X reservedsym("Z", CONDITION, 0x6); X reservedsym("NZ", CONDITION, 0xe); X reservedsym("PL", CONDITION, 0xd); X reservedsym("MI", CONDITION, 0x5); X reservedsym("OV", CONDITION, 0x4); X reservedsym("NOV", CONDITION, 0xc); X reservedsym("EQ", CONDITION, 0x6); X reservedsym("NE", CONDITION, 0xe); X reservedsym("GE", CONDITION, 0x9); X reservedsym("LT", CONDITION, 0x1); X reservedsym("GT", CONDITION, 0xa); X reservedsym("LE", CONDITION, 0x2); X reservedsym("UGE", CONDITION, 0xf); X reservedsym("ULT", CONDITION, 0x7); X reservedsym("UGT", CONDITION, 0xb); X reservedsym("ULE", CONDITION, 0x3); X reservedsym("R0", REGISTER, REGDEFWRK + 0xe0); X reservedsym("R1", REGISTER, REGDEFWRK + 0xe1); X reservedsym("R2", REGISTER, REGDEFWRK + 0xe2); X reservedsym("R3", REGISTER, REGDEFWRK + 0xe3); X reservedsym("R4", REGISTER, REGDEFWRK + 0xe4); X reservedsym("R5", REGISTER, REGDEFWRK + 0xe5); X reservedsym("R6", REGISTER, REGDEFWRK + 0xe6); X reservedsym("R7", REGISTER, REGDEFWRK + 0xe7); X reservedsym("R8", REGISTER, REGDEFWRK + 0xe8); X reservedsym("R9", REGISTER, REGDEFWRK + 0xe9); X reservedsym("R10", REGISTER, REGDEFWRK + 0xea); X reservedsym("R11", REGISTER, REGDEFWRK + 0xeb); X reservedsym("R12", REGISTER, REGDEFWRK + 0xec); X reservedsym("R13", REGISTER, REGDEFWRK + 0xed); X reservedsym("R14", REGISTER, REGDEFWRK + 0xee); X reservedsym("R15", REGISTER, REGDEFWRK + 0xef); X reservedsym("RR0", REGISTER, REGDEFWRK + REGDEFDBL + 0xe0); X reservedsym("RR2", REGISTER, REGDEFWRK + REGDEFDBL + 0xe2); X reservedsym("RR4", REGISTER, REGDEFWRK + REGDEFDBL + 0xe4); X reservedsym("RR6", REGISTER, REGDEFWRK + REGDEFDBL + 0xe6); X reservedsym("RR8", REGISTER, REGDEFWRK + REGDEFDBL + 0xe8); X reservedsym("RR10", REGISTER, REGDEFWRK + REGDEFDBL + 0xea); X reservedsym("RR12", REGISTER, REGDEFWRK + REGDEFDBL + 0xec); X reservedsym("RR14", REGISTER, REGDEFWRK + REGDEFDBL + 0xee); X} X X Xcpumatch(str) X char * str; X{ X int msub; X X static struct X { X char * mtch; X int cpuv; X } matchtab[] = X { X {"86", CPU8600 }, X {"z8", CPU8600 }, X {"Z8", CPU8600 }, X {"upc", CPU8090 }, X {"UPC", CPU8090 }, X {"9", CPU8090 }, X {"", 0} X }; X X for(msub = 0; matchtab[msub].cpuv != 0; msub++) X { X if(strcontains(str, matchtab[msub].mtch)) X { X cpuselect = matchtab[msub].cpuv; X return TRUE; X } X } X X return FALSE; X} X X Xstrcontains(s1, sm) X char * s1, *sm; X{ X int l1 = strlen(s1), lm = strlen(sm); X X for(; l1 >= lm; l1--, s1++) X { X if(strncmp(s1, sm, lm) == 0) X { X return TRUE; X } X } X return FALSE; X} X X/* X description Opcode and Instruction generation tables X usage Unix, framework crossassembler X history September 25, 1987 X*/ X X#define NUMOPCODE 70 X#define NUMSYNBLK 102 X#define NUMDIFFOP 130 X Xint gnumopcode = NUMOPCODE; X Xint ophashlnk[NUMOPCODE]; X Xstruct opsym optab[NUMOPCODE+1] X = { X {"invalid", KOC_opcode, 2, 0 }, X {"ADC", KOC_opcode, 4, 2 }, X {"ADD", KOC_opcode, 4, 6 }, X {"AND", KOC_opcode, 4, 10 }, X {"BYTE", KOC_BDEF, 0, 0 }, X {"CALL", KOC_opcode, 2, 14 }, X {"CCF", KOC_opcode, 1, 16 }, X {"CHARDEF", KOC_CHDEF, 0, 0 }, X {"CHARSET", KOC_CHSET, 0, 0 }, X {"CHARUSE", KOC_CHUSE, 0, 0 }, X {"CHD", KOC_CHDEF, 0, 0 }, X {"CLR", KOC_opcode, 2, 17 }, X {"COM", KOC_opcode, 2, 19 }, X {"CP", KOC_opcode, 4, 21 }, X {"CPU", KOC_CPU, 0, 0 }, X {"DA", KOC_opcode, 2, 25 }, X {"DB", KOC_BDEF, 0, 0 }, X {"DEC", KOC_opcode, 2, 27 }, X {"DECW", KOC_opcode, 2, 29 }, X {"DI", KOC_opcode, 1, 31 }, X {"DJNZ", KOC_opcode, 1, 32 }, X {"DW", KOC_WDEF, 0, 0 }, X {"EI", KOC_opcode, 1, 33 }, X {"ELSE", KOC_ELSE, 0, 0 }, X {"END", KOC_END, 0, 0 }, X {"ENDI", KOC_ENDI, 0, 0 }, X {"EQU", KOC_EQU, 0, 0 }, X {"FCB", KOC_BDEF, 0, 0 }, X {"FCC", KOC_SDEF, 0, 0 }, X {"FDB", KOC_WDEF, 0, 0 }, X {"IF", KOC_IF, 0, 0 }, X {"INC", KOC_opcode, 2, 34 }, X {"INCL", KOC_INCLUDE, 0, 0 }, X {"INCLUDE", KOC_INCLUDE, 0, 0 }, X {"INCW", KOC_opcode, 2, 36 }, X {"IRET", KOC_opcode, 1, 38 }, X {"JP", KOC_opcode, 3, 39 }, X {"JR", KOC_opcode, 2, 42 }, X {"LD", KOC_opcode, 7, 44 }, X {"LDC", KOC_opcode, 2, 51 }, X {"LDCI", KOC_opcode, 1, 53 }, X {"LDE", KOC_opcode, 2, 54 }, X {"LDEI", KOC_opcode, 1, 56 }, X {"NOP", KOC_opcode, 1, 57 }, X {"OR", KOC_opcode, 4, 58 }, X {"ORG", KOC_ORG, 0, 0 }, X {"POP", KOC_opcode, 2, 62 }, X {"PUSH", KOC_opcode, 2, 64 }, X {"RCF", KOC_opcode, 1, 66 }, X {"REG", KOC_REG, 0, 0 }, X {"RESERVE", KOC_RESM, 0, 0 }, X {"RET", KOC_opcode, 1, 67 }, X {"RL", KOC_opcode, 2, 68 }, X {"RLC", KOC_opcode, 2, 70 }, X {"RMB", KOC_RESM, 0, 0 }, X {"RR", KOC_opcode, 2, 72 }, X {"RRC", KOC_opcode, 2, 74 }, X {"RREG", KOC_RREG, 0, 0 }, X {"SBC", KOC_opcode, 4, 76 }, X {"SCF", KOC_opcode, 1, 80 }, X {"SET", KOC_SET, 0, 0 }, X {"SRA", KOC_opcode, 2, 81 }, X {"SRP", KOC_srp, 1, 83 }, X {"STRING", KOC_SDEF, 0, 0 }, X {"SUB", KOC_opcode, 4, 84 }, X {"SWAP", KOC_opcode, 2, 88 }, X {"TCM", KOC_opcode, 4, 90 }, X {"TM", KOC_opcode, 4, 94 }, X {"WORD", KOC_WDEF, 0, 0 }, X {"XOR", KOC_opcode, 4, 98 }, X { "", 0, 0, 0 }}; X Xstruct opsynt ostab[NUMSYNBLK+1] X = { X/* invalid 0 */ { 0, 1, 0 }, X/* invalid 1 */ { 0xffff, 1, 1 }, X/* ADC 2 */ { ST_IRIM, 1, 2 }, X/* ADC 3 */ { ST_R2, 2, 3 }, X/* ADC 4 */ { ST_RIMM, 1, 5 }, X/* ADC 5 */ { ST_RIR, 2, 6 }, X/* ADD 6 */ { ST_IRIM, 1, 8 }, X/* ADD 7 */ { ST_R2, 2, 9 }, X/* ADD 8 */ { ST_RIMM, 1, 11 }, X/* ADD 9 */ { ST_RIR, 2, 12 }, X/* AND 10 */ { ST_IRIM, 1, 14 }, X/* AND 11 */ { ST_R2, 2, 15 }, X/* AND 12 */ { ST_RIMM, 1, 17 }, X/* AND 13 */ { ST_RIR, 2, 18 }, X/* CALL 14 */ { ST_EXP, 1, 20 }, X/* CALL 15 */ { ST_IR1, 1, 21 }, X/* CCF 16 */ { ST_INH, 1, 22 }, X/* CLR 17 */ { ST_IR1, 1, 23 }, X/* CLR 18 */ { ST_R1, 1, 24 }, X/* COM 19 */ { ST_IR1, 1, 25 }, X/* COM 20 */ { ST_R1, 1, 26 }, X/* CP 21 */ { ST_IRIM, 1, 27 }, X/* CP 22 */ { ST_R2, 2, 28 }, X/* CP 23 */ { ST_RIMM, 1, 30 }, X/* CP 24 */ { ST_RIR, 2, 31 }, X/* DA 25 */ { ST_IR1, 1, 33 }, X/* DA 26 */ { ST_R1, 1, 34 }, X/* DEC 27 */ { ST_IR1, 1, 35 }, X/* DEC 28 */ { ST_R1, 1, 36 }, X/* DECW 29 */ { ST_IR1, 1, 37 }, X/* DECW 30 */ { ST_R1, 1, 38 }, X/* DI 31 */ { ST_INH, 1, 39 }, X/* DJNZ 32 */ { ST_REXP, 1, 40 }, X/* EI 33 */ { ST_INH, 1, 41 }, X/* INC 34 */ { ST_IR1, 1, 42 }, X/* INC 35 */ { ST_R1, 2, 43 }, X/* INCW 36 */ { ST_IR1, 1, 45 }, X/* INCW 37 */ { ST_R1, 1, 46 }, X/* IRET 38 */ { ST_INH, 1, 47 }, X/* JP 39 */ { ST_CEXP, 1, 48 }, X/* JP 40 */ { ST_EXP, 1, 49 }, X/* JP 41 */ { ST_IR1, 1, 50 }, X/* JR 42 */ { ST_CEXP, 1, 51 }, X/* JR 43 */ { ST_EXP, 1, 52 }, X/* LD 44 */ { ST_IRIM, 1, 53 }, X/* LD 45 */ { ST_IRR, 2, 54 }, X/* LD 46 */ { ST_R2, 3, 56 }, X/* LD 47 */ { ST_RIMM, 2, 59 }, X/* LD 48 */ { ST_RIR, 2, 61 }, X/* LD 49 */ { ST_RX, 1, 63 }, X/* LD 50 */ { ST_XR, 1, 64 }, X/* LDC 51 */ { ST_IRR, 1, 65 }, X/* LDC 52 */ { ST_RIR, 1, 66 }, X/* LDCI 53 */ { ST_IRIR, 2, 67 }, X/* LDE 54 */ { ST_IRR, 1, 69 }, X/* LDE 55 */ { ST_RIR, 1, 70 }, X/* LDEI 56 */ { ST_IRIR, 2, 71 }, X/* NOP 57 */ { ST_INH, 1, 73 }, X/* OR 58 */ { ST_IRIM, 1, 74 }, X/* OR 59 */ { ST_R2, 2, 75 }, X/* OR 60 */ { ST_RIMM, 1, 77 }, X/* OR 61 */ { ST_RIR, 2, 78 }, X/* POP 62 */ { ST_IR1, 1, 80 }, X/* POP 63 */ { ST_R1, 1, 81 }, X/* PUSH 64 */ { ST_IR1, 1, 82 }, X/* PUSH 65 */ { ST_R1, 1, 83 }, X/* RCF 66 */ { ST_INH, 1, 84 }, X/* RET 67 */ { ST_INH, 1, 85 }, X/* RL 68 */ { ST_IR1, 1, 86 }, X/* RL 69 */ { ST_R1, 1, 87 }, X/* RLC 70 */ { ST_IR1, 1, 88 }, X/* RLC 71 */ { ST_R1, 1, 89 }, X/* RR 72 */ { ST_IR1, 1, 90 }, X/* RR 73 */ { ST_R1, 1, 91 }, X/* RRC 74 */ { ST_IR1, 1, 92 }, X/* RRC 75 */ { ST_R1, 1, 93 }, X/* SBC 76 */ { ST_IRIM, 1, 94 }, X/* SBC 77 */ { ST_R2, 2, 95 }, X/* SBC 78 */ { ST_RIMM, 1, 97 }, X/* SBC 79 */ { ST_RIR, 2, 98 }, X/* SCF 80 */ { ST_INH, 1, 100 }, X/* SRA 81 */ { ST_IR1, 1, 101 }, X/* SRA 82 */ { ST_R1, 1, 102 }, X/* SRP 83 */ { ST_IMM, 1, 103 }, X/* SUB 84 */ { ST_IRIM, 1, 104 }, X/* SUB 85 */ { ST_R2, 2, 105 }, X/* SUB 86 */ { ST_RIMM, 1, 107 }, X/* SUB 87 */ { ST_RIR, 2, 108 }, X/* SWAP 88 */ { ST_IR1, 1, 110 }, X/* SWAP 89 */ { ST_R1, 1, 111 }, X/* TCM 90 */ { ST_IRIM, 1, 112 }, X/* TCM 91 */ { ST_R2, 2, 113 }, X/* TCM 92 */ { ST_RIMM, 1, 115 }, X/* TCM 93 */ { ST_RIR, 2, 116 }, X/* TM 94 */ { ST_IRIM, 1, 118 }, X/* TM 95 */ { ST_R2, 2, 119 }, X/* TM 96 */ { ST_RIMM, 1, 121 }, X/* TM 97 */ { ST_RIR, 2, 122 }, X/* XOR 98 */ { ST_IRIM, 1, 124 }, X/* XOR 99 */ { ST_R2, 2, 125 }, X/* XOR 100 */ { ST_RIMM, 1, 127 }, X/* XOR 101 */ { ST_RIR, 2, 128 }, X { 0, 0, 0 } }; X Xstruct igel igtab[NUMDIFFOP+1] X = { X/* invalid 0 */ { 0 , 0, X "[Xnullentry" }, X/* invalid 1 */ { 0 , 0, X "[Xinvalid opcode" }, X/* ADC 2 */ { 0 , 0, X "17;[1#];[2=];" }, X/* ADC 3 */ { SRCWORK+DSTWORK , SRCWORK+DSTWORK, X "12;[2#4#];" }, X/* ADC 4 */ { 0 , 0, X "14;[3#];[1#];" }, X/* ADC 5 */ { 0 , 0, X "16;[1#];[2=];" }, X/* ADC 6 */ { SRCWORK+DSTWORK , SRCWORK+DSTWORK, X "13;[2#4#];" }, X/* ADC 7 */ { 0 , 0, X "15;[3#];[1#];" }, X/* ADD 8 */ { 0 , 0, X "07;[1#];[2=];" }, X/* ADD 9 */ { SRCWORK+DSTWORK , SRCWORK+DSTWORK, X "02;[2#4#];" }, X/* ADD 10 */ { 0 , 0, X "04;[3#];[1#];" }, X/* ADD 11 */ { 0 , 0, X "06;[1#];[2=];" }, X/* ADD 12 */ { SRCWORK+DSTWORK , SRCWORK+DSTWORK, X "03;[2#4#];" }, X/* ADD 13 */ { 0 , 0, X "05;[3#];[1#];" }, X/* AND 14 */ { 0 , 0, X "57;[1#];[2=];" }, X/* AND 15 */ { SRCWORK+DSTWORK , SRCWORK+DSTWORK, X "52;[2#4#];" }, X/* AND 16 */ { 0 , 0, X "54;[3#];[1#];" }, X/* AND 17 */ { 0 , 0, X "56;[1#];[2=];" }, X/* AND 18 */ { SRCWORK+DSTWORK , SRCWORK+DSTWORK, X "53;[2#4#];" }, X/* AND 19 */ { 0 , 0, X "55;[3#];[1#];" }, X/* CALL 20 */ { 0 , 0, X "d6;[1=]x" }, X/* CALL 21 */ { DSTDBL , DSTDBL, X "d4;[1#];" }, X/* CCF 22 */ { 0 , 0, X "ef;" }, X/* CLR 23 */ { 0 , 0, X "b1;[1#];" }, X/* CLR 24 */ { 0 , 0, X "b0;[1#];" }, X/* COM 25 */ { 0 , 0, X "61;[1#];" }, X/* COM 26 */ { 0 , 0, X "60;[1#];" }, X/* CP 27 */ { 0 , 0, X "a7;[1#];[2=];" }, X/* CP 28 */ { SRCWORK+DSTWORK , SRCWORK+DSTWORK, X "a2;[2#4#];" }, X/* CP 29 */ { 0 , 0, X "a4;[3#];[1#];" }, X/* CP 30 */ { 0 , 0, X "a6;[1#];[2=];" }, X/* CP 31 */ { SRCWORK+DSTWORK , SRCWORK+DSTWORK, X "a3;[2#4#];" }, X/* CP 32 */ { 0 , 0, X "a5;[3#];[1#];" }, X/* DA 33 */ { 0 , 0, X "41;[1#];" }, X/* DA 34 */ { 0 , 0, X "40;[1#];" }, X/* DEC 35 */ { 0 , 0, X "01;[1#];" }, X/* DEC 36 */ { 0 , 0, X "00;[1#];" }, X/* DECW 37 */ { 0 , 0, X "81;[1#];" }, X/* DECW 38 */ { DSTDBL , DSTDBL, X "80;[1#];" }, X/* DI 39 */ { 0 , 0, X "8f;" }, X/* DJNZ 40 */ { DSTWORK , DSTWORK, X "[3#]a;[2=].Q.1+-r" }, X/* EI 41 */ { 0 , 0, X "9f;" }, X/* INC 42 */ { 0 , 0, X "21;[1#];" }, X/* INC 43 */ { DSTWORK , DSTWORK, X "[2#]e;" }, X/* INC 44 */ { 0 , 0, X "20;[1#];" }, X/* INCW 45 */ { 0 , 0, X "a1;[1#];" }, X/* INCW 46 */ { DSTDBL , DSTDBL, X "a0;[1#];" }, X/* IRET 47 */ { 0 , 0, X "bf;" }, X/* JP 48 */ { 0 , 0, X "[1#]d;[2=]x" }, X/* JP 49 */ { 0 , 0, X "8d;[1=]x" }, X/* JP 50 */ { DSTDBL , DSTDBL, X "30;[1#];" }, X/* JR 51 */ { 0 , 0, X "[1#]b;[2=].Q.1+-r" }, X/* JR 52 */ { 0 , 0, X "8b;[1=].Q.1+-r" }, X/* LD 53 */ { 0 , 0, X "e7;[1#];[2=];" }, X/* LD 54 */ { DSTWORK+SRCWORK , DSTWORK+SRCWORK, X "f3;[2#4#];" }, X/* LD 55 */ { 0 , 0, X "f5;[3#];[1#];" }, X/* LD 56 */ { DSTWORK , DSTWORK, X "[2#]8;[3#];" }, X/* LD 57 */ { SRCWORK , SRCWORK, X "[4#]9;[1#];" }, X/* LD 58 */ { 0 , 0, X "e4;[3#];[1#];" }, X/* LD 59 */ { DSTWORK , DSTWORK, X "[3#]c;[2=];" }, X/* LD 60 */ { 0 , 0, X "e6;[1#];[2=];" }, X/* LD 61 */ { DSTWORK+SRCWORK , DSTWORK+SRCWORK, X "e3;[2#4#];" }, X/* LD 62 */ { 0 , 0, X "e5;[3#];[1#];" }, X/* LD 63 */ { DSTWORK+SRCWORK , DSTWORK+SRCWORK, X "c7;[1#3#];[2=];" }, X/* LD 64 */ { DSTWORK+SRCWORK , DSTWORK+SRCWORK, X "d7;[3#2#];[1=];" }, X/* LDC 65 */ { DSTWORK+SRCWORK , DSTWORK+SRCWORK, X "d2;[4#2#];" }, X/* LDC 66 */ { DSTWORK+SRCWORK , DSTWORK+SRCWORK, X "c2;[2#4#];" }, X/* LDCI 67 */ { SRCDBL+DSTDBL+DSTWORK+SRCWORK , SRCDBL+DSTWORK+SRCWORK, X "c3;[2#4#];" }, X/* LDCI 68 */ { SRCDBL+DSTDBL+DSTWORK+SRCWORK , DSTDBL+DSTWORK+SRCWORK, X "d3;[4#2#];" }, X/* LDE 69 */ { DSTWORK+SRCWORK , DSTWORK+SRCWORK, X "92;[4#2#];" }, X/* LDE 70 */ { DSTWORK+SRCWORK , DSTWORK+SRCWORK, X "82;[2#4#];" }, X/* LDEI 71 */ { SRCDBL+DSTDBL+DSTWORK+SRCWORK , SRCDBL+DSTWORK+SRCWORK, X "83;[2#4#];" }, X/* LDEI 72 */ { SRCDBL+DSTDBL+DSTWORK+SRCWORK , DSTDBL+DSTWORK+SRCWORK, X "93;[4#2#];" }, X/* NOP 73 */ { 0 , 0, X "ff;" }, X/* OR 74 */ { 0 , 0, X "47;[1#];[2=];" }, X/* OR 75 */ { SRCWORK+DSTWORK , SRCWORK+DSTWORK, X "42;[2#4#];" }, X/* OR 76 */ { 0 , 0, X "44;[3#];[1#];" }, X/* OR 77 */ { 0 , 0, X "46;[1#];[2=];" }, X/* OR 78 */ { SRCWORK+DSTWORK , SRCWORK+DSTWORK, X "43;[2#4#];" }, X/* OR 79 */ { 0 , 0, X "45;[3#];[1#];" }, X/* POP 80 */ { 0 , 0, X "51;[1#];" }, X/* POP 81 */ { 0 , 0, X "50;[1#];" }, X/* PUSH 82 */ { 0 , 0, X "71;[1#];" }, X/* PUSH 83 */ { 0 , 0, X "70;[1#];" }, X/* RCF 84 */ { 0 , 0, X "cf;" }, X/* RET 85 */ { 0 , 0, X "af;" }, X/* RL 86 */ { 0 , 0, X "91;[1#];" }, X/* RL 87 */ { 0 , 0, X "90;[1#];" }, X/* RLC 88 */ { 0 , 0, X "11;[1#];" }, X/* RLC 89 */ { 0 , 0, X "10;[1#];" }, X/* RR 90 */ { 0 , 0, X "e1;[1#];" }, X/* RR 91 */ { 0 , 0, X "e0;[1#];" }, X/* RRC 92 */ { 0 , 0, X "c1;[1#];" }, X/* RRC 93 */ { 0 , 0, X "c0;[1#];" }, X/* SBC 94 */ { 0 , 0, X "37;[1#];[2=];" }, X/* SBC 95 */ { SRCWORK+DSTWORK , SRCWORK+DSTWORK, X "32;[2#4#];" }, X/* SBC 96 */ { 0 , 0, X "34;[3#];[1#];" }, X/* SBC 97 */ { 0 , 0, X "36;[1#];[2=];" }, X/* SBC 98 */ { SRCWORK+DSTWORK , SRCWORK+DSTWORK, X "33;[2#4#];" }, X/* SBC 99 */ { 0 , 0, X "35;[3#];[1#];" }, X/* SCF 100 */ { 0 , 0, X "df;" }, X/* SRA 101 */ { 0 , 0, X "d1;[1#];" }, X/* SRA 102 */ { 0 , 0, X "d0;[1#];" }, X/* SRP 103 */ { 0 , 0, X "31;[1=];" }, X/* SUB 104 */ { 0 , 0, X "27;[1#];[2=];" }, X/* SUB 105 */ { SRCWORK+DSTWORK , SRCWORK+DSTWORK, X "22;[2#4#];" }, X/* SUB 106 */ { 0 , 0, X "24;[3#];[1#];" }, X/* SUB 107 */ { 0 , 0, X "26;[1#];[2=];" }, X/* SUB 108 */ { SRCWORK+DSTWORK , SRCWORK+DSTWORK, X "23;[2#4#];" }, X/* SUB 109 */ { 0 , 0, X "25;[3#];[1#];" }, X/* SWAP 110 */ { 0 , 0, X "f1;[1#];" }, X/* SWAP 111 */ { 0 , 0, X "f0;[1#];" }, X/* TCM 112 */ { 0 , 0, X "67;[1#];[2=];" }, X/* TCM 113 */ { SRCWORK+DSTWORK , SRCWORK+DSTWORK, X "62;[2#4#];" }, X/* TCM 114 */ { 0 , 0, X "64;[3#];[1#];" }, X/* TCM 115 */ { 0 , 0, X "66;[1#];[2=];" }, X/* TCM 116 */ { SRCWORK+DSTWORK , SRCWORK+DSTWORK, X "63;[2#4#];" }, X/* TCM 117 */ { 0 , 0, X "65;[3#];[1#];" }, X/* TM 118 */ { 0 , 0, X "77;[1#];[2=];" }, X/* TM 119 */ { SRCWORK+DSTWORK , SRCWORK+DSTWORK, X "72;[2#4#];" }, X/* TM 120 */ { 0 , 0, X "74;[3#];[1#];" }, X/* TM 121 */ { 0 , 0, X "76;[1#];[2=];" }, X/* TM 122 */ { SRCWORK+DSTWORK , SRCWORK+DSTWORK, X "73;[2#4#];" }, X/* TM 123 */ { 0 , 0, X "75;[3#];[1#];" }, X/* XOR 124 */ { 0 , 0, X "b7;[1#];[2=];" }, X/* XOR 125 */ { SRCWORK+DSTWORK , SRCWORK+DSTWORK, X "b2;[2#4#];" }, X/* XOR 126 */ { 0 , 0, X "b4;[3#];[1#];" }, X/* XOR 127 */ { 0 , 0, X "b6;[1#];[2=];" }, X/* XOR 128 */ { SRCWORK+DSTWORK , SRCWORK+DSTWORK, X "b3;[2#4#];" }, X/* XOR 129 */ { 0 , 0, X "b5;[3#];[1#];" }, X { 0,0,""} }; X/* end fraptabdef.c */ SHAR_EOF true || echo 'restore of asz8.y failed' fi exit 0