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Text File | 1995-02-22 | 1.5 MB | 44,629 lines

Text Truncated. Only the first 1MB is shown below. Download the file for the complete contents. diff -r -u -H -N gcc-2.6.3/Makefile.in gcc-i2.6.3/Makefile.in --- gcc-2.6.3/Makefile.in Mon Nov 28 18:54:06 1994 +++ gcc-i2.6.3/Makefile.in Tue Dec 20 16:04:58 1994 @@ -46,7 +46,7 @@ # to the stage2 and stage3 compilations # XCFLAGS is used for most compilations but not when using the GCC just built. XCFLAGS = -CFLAGS = -g +CFLAGS = -O2 BOOT_CFLAGS = -O $(CFLAGS) # These exists to be overridden by the x-* and t-* files, respectively. X_CFLAGS = diff -r -u -H -N gcc-2.6.3/c-decl.c gcc-i2.6.3/c-decl.c --- gcc-2.6.3/c-decl.c Fri Nov 11 17:52:25 1994 +++ gcc-i2.6.3/c-decl.c Wed Feb 15 22:46:38 1995 @@ -2122,6 +2122,8 @@ ? 0 : DECL_INITIAL (oldglobal)); DECL_SAVED_INSNS (x) = DECL_SAVED_INSNS (oldglobal); DECL_FRAME_SIZE (x) = DECL_FRAME_SIZE (oldglobal); + /* intel1 */ + DECL_FRAME_SIZE (x) = DECL_FRAME_SIZE (oldglobal); DECL_ARGUMENTS (x) = DECL_ARGUMENTS (oldglobal); DECL_RESULT (x) = DECL_RESULT (oldglobal); TREE_ASM_WRITTEN (x) = TREE_ASM_WRITTEN (oldglobal); diff -r -u -H -N gcc-2.6.3/c-parse.c gcc-i2.6.3/c-parse.c --- gcc-2.6.3/c-parse.c Sat Aug 27 13:51:56 1994 +++ gcc-i2.6.3/c-parse.c Tue Nov 8 15:47:57 1994 @@ -1290,23 +1290,8 @@ #endif #line 184 "/usr/local/lib/bison.simple" - -/* The user can define YYPARSE_PARAM as the name of an argument to be passed - into yyparse. The argument should have type void *. - It should actually point to an object. - Grammar actions can access the variable by casting it - to the proper pointer type. */ - -#ifdef YYPARSE_PARAM -#define YYPARSE_PARAM_DECL void *YYPARSE_PARAM; -#else -#define YYPARSE_PARAM -#define YYPARSE_PARAM_DECL -#endif - int -yyparse(YYPARSE_PARAM) - YYPARSE_PARAM_DECL +yyparse() { register int yystate; register int yyn; @@ -3335,7 +3320,7 @@ break;} } /* the action file gets copied in in place of this dollarsign */ -#line 480 "/usr/local/lib/bison.simple" +#line 465 "/usr/local/lib/bison.simple" yyvsp -= yylen; yyssp -= yylen; diff -r -u -H -N gcc-2.6.3/cexp.c gcc-i2.6.3/cexp.c --- gcc-2.6.3/cexp.c Fri Sep 23 14:10:27 1994 +++ gcc-i2.6.3/cexp.c Tue Nov 8 15:47:37 1994 @@ -521,23 +521,8 @@ #endif #line 184 "/usr/local/lib/bison.simple" - -/* The user can define YYPARSE_PARAM as the name of an argument to be passed - into yyparse. The argument should have type void *. - It should actually point to an object. - Grammar actions can access the variable by casting it - to the proper pointer type. */ - -#ifdef YYPARSE_PARAM -#define YYPARSE_PARAM_DECL void *YYPARSE_PARAM; -#else -#define YYPARSE_PARAM -#define YYPARSE_PARAM_DECL -#endif - int -yyparse(YYPARSE_PARAM) - YYPARSE_PARAM_DECL +yyparse() { register int yystate; register int yyn; @@ -1061,7 +1046,7 @@ break;} } /* the action file gets copied in in place of this dollarsign */ -#line 480 "/usr/local/lib/bison.simple" +#line 465 "/usr/local/lib/bison.simple" yyvsp -= yylen; yyssp -= yylen; diff -r -u -H -N gcc-2.6.3/combine.c gcc-i2.6.3/combine.c --- gcc-2.6.3/combine.c Wed Nov 30 19:13:30 1994 +++ gcc-i2.6.3/combine.c Wed Feb 15 23:01:12 1995 @@ -96,6 +96,10 @@ #include "recog.h" #include "real.h" +/* intel1 */ +static int in_recombine=0; +extern FILE *combine_dump_file; + /* It is not safe to use ordinary gen_lowpart in combine. Use gen_lowpart_for_combine instead. See comments there. */ #define gen_lowpart dont_use_gen_lowpart_you_dummy @@ -377,6 +381,29 @@ static int n_occurrences; +/* intel2 - begin */ + +#define INSN_SETS_REGNO(INSN, REGNO) dead_or_set_regno_p (INSN, REGNO) +#define INSN_USES_REGNO(INSN, REGNO) refers_to_regno_p (REGNO, \ + REGNO + 1, \ + PATTERN (INSN), \ + 0) + +/* if this flag is set do not recombine unscheded riscified insns, which their + * original insn's destination was a memory. + */ +extern int flag_risc_mem_dest; + +/* if this flag is set try to riscify stores of CONST_INTs */ +extern int flag_risc_const; + +void update_free_regs (rtx); +static void update_regno_holds_mem (rtx insn, rtx pat); +static int remove_redundant_store (rtx mem, int block); +static void update_entries (rtx reg); + +/* intel2 - end */ + static void init_reg_last_arrays PROTO(()); static void setup_incoming_promotions PROTO(()); static void set_nonzero_bits_and_sign_copies PROTO((rtx, rtx)); @@ -436,6 +463,14 @@ static void distribute_notes PROTO((rtx, rtx, rtx, rtx, rtx, rtx)); static void distribute_links PROTO((rtx)); static void mark_used_regs_combine PROTO((rtx)); +/* intel2 */ +#if 0 +static void dump_free_registers (); +#endif +int find_free_reg(); +static int find_regno_holds_mem (rtx, enum machine_mode); +/* intel1 */ +static int try_backwards_replace (); /* Main entry point for combiner. F is the first insn of the function. NREGS is the first unused pseudo-reg number. */ @@ -867,6 +902,9 @@ /* Don't eliminate a store in the stack pointer. */ if (dest == stack_pointer_rtx + /* intel1 + || (in_recombine && GET_CODE (dest) == REG + && reg_used_between_p (dest, insn, i3)) */ /* If we couldn't eliminate a field assignment, we can't combine. */ || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART /* Don't combine with an insn that sets a register to itself if it has @@ -1045,6 +1083,8 @@ On machines where SMALL_REGISTER_CLASSES is defined, we don't combine if the destination of a SET is a hard register that isn't a user variable. + intel2 - This is true unless we are in recombine (indicated by + in_recombine) Before doing the above check, we first try to expand a field assignment into a set of logical operations. @@ -1114,12 +1154,26 @@ CALL operation. */ || (GET_CODE (inner_dest) == REG && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER + /* intel2 - begin */ + /* if we are in the recombine phase, we should not eliminate the + * possibility for combine if the destination is a hard register. + */ + && (!in_recombine) + /* intel2 - end */ && (! HARD_REGNO_MODE_OK (REGNO (inner_dest), GET_MODE (inner_dest)) #ifdef SMALL_REGISTER_CLASSES || (GET_CODE (src) != CALL && ! REG_USERVAR_P (inner_dest)) #endif )) + + /* intel2 - begin */ + /* if we want to leave mem-dest riscified instructions untouched... */ + || (in_recombine + && flag_risc_mem_dest + && GET_CODE (inner_dest) == MEM) + /* intel2 - end */ + || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))) return 0; @@ -1372,6 +1426,25 @@ return 0; } + /* intel1 */ + if (in_recombine) + { + if (i1 && GET_CODE (PATTERN (i1)) == SET + && GET_CODE (SET_DEST (PATTERN (i1))) == REG + && reg_used_between_p (SET_DEST (PATTERN (i1)), i1, i2)) + { + undo_all (); + return 0; + } + if (i2 && GET_CODE (PATTERN (i2)) == SET + && GET_CODE (SET_DEST (PATTERN (i2))) == REG + && reg_used_between_p (SET_DEST (PATTERN (i2)), i2, i3)) + { + undo_all (); + return 0; + } + } + /* Record whether I2DEST is used in I2SRC and similarly for the other cases. Knowing this will help in register status updating below. */ i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src); @@ -1993,6 +2066,46 @@ insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); } + /* intel1 , maybe we can rearrange memory so it is recognized */ +#ifdef REWRITE_ADDRESS + if (insn_code_number==-1 && GET_CODE(newpat)==SET && i1==NULL) + { + rtx copy_of_newpat,try_to_make_good(); /* see loop.c */ + rtx new_src_copy,new_dest_copy; + int dummy; + char * storage; + storage = (char *) oballoc(0); + copy_of_newpat = copy_rtx (newpat); + new_src_copy = SET_SRC (copy_of_newpat); + try_to_make_good (SET_SRC (copy_of_newpat)); + try_to_make_good (SET_DEST (copy_of_newpat)); + if (recog (copy_of_newpat, i3, &dummy) != -1) + { + newpat = copy_of_newpat; + insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); + } + else if (GET_CODE (new_src_copy) != MEM) + { + new_src_copy = gen_rtx (MEM, GET_MODE( new_src_copy), new_src_copy); + try_to_make_good (new_src_copy); + SET_SRC (copy_of_newpat) = XEXP (new_src_copy,0); + if (recog (copy_of_newpat,i3,&dummy) != -1) + { + newpat = copy_of_newpat; + insn_code_number = recog_for_combine (&newpat,i3,&new_i3_notes); + } + else + { + obfree (storage); + } + } + else + { + obfree (storage); + } + } +#endif /* REWRITE_ADDRESS */ + /* If it still isn't recognized, fail and change things back the way they were. */ if ((insn_code_number < 0 @@ -2003,6 +2116,30 @@ return 0; } + /* intel2 - begin */ +#ifdef REGISTER_CONSTRAINTS + /* check if the combined insn is a legal one */ + if (in_recombine) + { + register rtx temp_pat = PATTERN (i3); + register int temp_code_number = INSN_CODE (i3); + + /* change it only for the following check */ + PATTERN (i3) = newpat; + INSN_CODE (i3) = insn_code_number; + insn_extract (i3); + /* restore the data */ + PATTERN (i3) = temp_pat; + INSN_CODE (i3) = temp_code_number; + if (! constrain_operands (insn_code_number, 1)) + { + undo_all(); + return 0; + } + } +#endif + /* intel2 - end */ + /* If we had to change another insn, make sure it is valid also. */ if (undobuf.other_insn) { @@ -4197,6 +4334,14 @@ int other_changed = 0; enum machine_mode compare_mode = GET_MODE (dest); + /* intel1 */ +#ifdef HAVE_cc0 + if(SET_DEST (x) == cc0_rtx && compare_mode==VOIDmode) + { + compare_mode = GET_MODE (SET_SRC (x)); + } +#endif + if (GET_CODE (src) == COMPARE) op0 = XEXP (src, 0), op1 = XEXP (src, 1); else @@ -9712,7 +9857,13 @@ for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) { if (REG_NOTE_KIND (link) == REG_DEAD - && GET_CODE (XEXP (link, 0)) == REG) + /* intel2 - begin */ + /* if in_recombine we might encounter a REG_DEAD note of memory! + */ + && (! in_recombine + || GET_CODE (XEXP (link, 0)) == REG) + /* intel2 - end */ + ) { int regno = REGNO (XEXP (link, 0)); int endregno @@ -10544,13 +10695,26 @@ } else { + /* intel1 making this into reg_unused causes + bug in scheduler since sched will see this + as a reg_dead */ +#if 0 PUT_REG_NOTE_KIND (note, REG_UNUSED); +#endif +#if 0 /* If there isn't already a REG_UNUSED note, put one here. */ if (! find_regno_note (tem, REG_UNUSED, REGNO (XEXP (note, 0)))) place = tem; +#else + /* If there isn't already a REG_DEAD note, put one + here. */ + if (! find_regno_note (tem, REG_DEAD, + REGNO (XEXP (note, 0)))) + place = tem; +#endif break; } } @@ -10817,4 +10981,2580 @@ (file, "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n", total_attempts, total_merges, total_extras, total_successes); +} + +/* intel1 */ +/* intel1 - those split insns that remained consecutive should now + be combined +*/ +void +combine_unscheded (f, nregs) + rtx f; + int nregs; +{ + register rtx insn, next, prev; + register int i; + register rtx links, nextlinks, note; + + in_recombine = 1; + combine_attempts = 0; + combine_merges = 0; + combine_extras = 0; + combine_successes = 0; + + combine_max_regno = nregs; + + reg_last_death = (rtx *) alloca (nregs * sizeof (rtx)); + reg_last_set = (rtx *) alloca (nregs * sizeof (rtx)); + reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx)); + reg_last_set_table_tick = (int *) alloca (nregs * sizeof (int)); + reg_last_set_label = (int *) alloca (nregs * sizeof (int)); + reg_last_set_invalid = (char *) alloca (nregs * sizeof (char)); + + bzero (reg_last_death, nregs * sizeof (rtx)); + bzero (reg_last_set, nregs * sizeof (rtx)); + bzero (reg_last_set_value, nregs * sizeof (rtx)); + bzero (reg_last_set_table_tick, nregs * sizeof (short)); + bzero (reg_last_set_invalid, nregs * sizeof (char)); + + init_recog_no_volatile (); + + /* Compute maximum uid value so uid_cuid can be allocated. */ + + for (insn = f, i = 0; insn; insn = NEXT_INSN (insn)) + if (INSN_UID (insn) > i) + i = INSN_UID (insn); + + uid_cuid = (int *) alloca ((i + 1) * sizeof (int)); + + /* Compute the mapping from uids to cuids. + Cuids are numbers assigned to insns, like uids, + except that cuids increase monotonically through the code. + + Scan all SETs and see if we can deduce anything about what + bits are significant for some registers. */ + + for (insn = f, i = 0; insn; insn = NEXT_INSN (insn)) + { + INSN_CUID (insn) = ++i; + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') + note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies); + } + + + label_tick = 1; + last_call_cuid = 0; + mem_last_set = 0; + /* Now scan all the insns in forward order. */ + for (insn = f; insn; insn = NEXT_INSN (insn)) + { + if (GET_CODE (insn) == CODE_LABEL) + label_tick++; + if(GET_CODE (insn) == INSN) + { + /* Try this insn with each insn it links back to. */ + for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) + { + if(REG_NOTE_KIND (links) != REG_DEP_ANTI + /*&& REG_NOTE_KIND (links) != REG_DEP_OUTPUT + && */ && (GET_CODE (XEXP (links, 0)) == INSN + && next_nonnote_insn (XEXP (links, 0)) + == ORG_NEXT_INSN (XEXP (links, 0))) + && GET_CODE (PATTERN (XEXP (links, 0))) == SET + && GET_CODE (SET_DEST (PATTERN (XEXP (links, 0)))) + == REG + && (note + = find_regno_note (insn, + REG_DEAD, + REGNO(SET_DEST (PATTERN (XEXP (links, 0)))))) + && rtx_equal_p (XEXP (note, 0), + SET_DEST (PATTERN (XEXP (links, 0)))) + /* intel2 - begin */ + /* combine only insns that were created by memory_simplify. + */ + && (RTX_IS_RISC_P (XEXP (links, 0))) + /* intel2 - end */ + ) + { + /* intel2 - begin */ + rtx inner_link = LOG_LINKS (XEXP (links, 0)); + int three_insns = 0; + + /* Check that we consider the case of three-insns riscified + * insn + */ + if (inner_link) + { + for (; inner_link; inner_link = XEXP (inner_link, 1)) + { + rtx temp_insn = XEXP (inner_link, 0); + + if (REG_NOTE_KIND (inner_link) != REG_DEP_ANTI + /*&& REG_NOTE_KIND (inner_link) != REG_DEP_OUTPUT + &&*/ && (GET_CODE (temp_insn) == INSN + && next_nonnote_insn (temp_insn) == + ORG_NEXT_INSN (temp_insn)) + && RTX_IS_RISC_P (temp_insn) + && GET_CODE (PATTERN (temp_insn)) == SET + && GET_CODE (SET_DEST (PATTERN (temp_insn))) + == REG + && (note + = find_regno_note (insn, + REG_DEAD, + REGNO(SET_DEST (PATTERN (temp_insn))))) + && rtx_equal_p (XEXP (note, 0), + SET_DEST (PATTERN (temp_insn))) + ) + { + try_combine (insn, XEXP (links, 0), temp_insn); + three_insns = 1; + } + } + } + + if (! three_insns) + { + /* intel2 - end */ + try_combine (insn, XEXP (links, 0), 0); + } + } + } + } + if(GET_CODE (insn) == INSN || + GET_CODE (insn) == CALL_INSN || + GET_CODE (insn) == JUMP_INSN) + record_dead_and_set_regs (insn); + } + + in_recombine = 0; + +} + + + +/* intel2 - begin */ + +/* we will probably need this - check it and remvoe it if not... */ + +/*#include "hard-reg-set.h"*/ + +/* Set of registers that are free and ready to use at this moment. */ + +HARD_REG_SET free_regs; + +/* Set of registers that are not recommended for allocating at this moment. */ + +static HARD_REG_SET not_recommended_regs; + +typedef struct { + rtx mem; /* mem rtx, this regno holds */ + rtx insn_dead; /* insn in which this regno dies */ + rtx insn_load; /* insn in which this regno is loaded */ + rtx insn_store; /* insn in which this regno is stored */ +} MEM_HOLDER; + +/* Indexed by regno, indicates which register currently, holds a copy of + memory and the rtx represents this memory, as well as the insn loaded it, + and the insn in which this register was dead. */ + +MEM_HOLDER regno_holds_mem[FIRST_PSEUDO_REGISTER]; +/* Perform simplification of memory accessed instructions by replacing them + with risc-like instructions. + FILE is a file to output debugging information on, + or zero if such output is not desired. */ + +void +memory_simplify (file, f) + FILE *file; + rtx f; +{ + register int block, j; + int regno, limit; + int i; /* intel1 */ + int nregs; /* intel1 */ + char * fmt; /* intel1 */ + MEM_HOLDER *mhp; + rtx copy_reg = NULL; + rtx t_insn; + + /* record which is the last register used for a spill reload */ + static int last_load_reg; + /* Initialize reg_holds_mem */ + + bzero (regno_holds_mem, sizeof regno_holds_mem); + + /* since all registers now are hard registers, FIRST_PSEUDO_REGISTER is a + valid initialization value */ + + last_load_reg = FIRST_PSEUDO_REGISTER; + + hard_reg_flow_analysis (f, file, 0 /* no pseudo registers' info. save */ ); + + if (n_basic_blocks <= 0) + { + return ; + } + /* To determine which registers are live after any insn, start from + the beginning of the basic block and scan insns, noting + which registers are set by each insn and which die there. */ + for (block = 0; block < n_basic_blocks; block++) + { + register rtx insn; + int end_of_block_f; + + if (file) + fprintf (file, "\nblock number: %d:\n", block); + + last_load_reg = FIRST_PSEUDO_REGISTER; + /* since we cannot remove stores before a jump, we clean all the + insn_store data */ + + for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) + regno_holds_mem[regno].insn_store = 0; + + for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) + /* at the beginning of a block, each non-live hard register is + considered free. */ + { + register int offset = regno / REGSET_ELT_BITS; + register int bit = 1 << (regno % REGSET_ELT_BITS); + if (basic_block_live_at_start[block][offset] & bit) + CLEAR_HARD_REG_BIT (free_regs, regno); + else + SET_HARD_REG_BIT (free_regs, regno); + } + + /* Traverse the block, an insn by insn, check for memory references, + and find whether a risc-like insns instead are valid. If yes, + replace the insn by another insn(s). */ + + end_of_block_f = 0; /* signals the end of block reached */ + + for (insn = basic_block_head[block]; + !end_of_block_f; + insn = NEXT_INSN (insn)) + { + rtx note, next, mem_opr = 0; + rtx pat = PATTERN (insn); + int regno, old_regno; + int saved_code; + + /* try to eliminate as much stores as we can using the free_regs + and regno_holds_mem information */ + + if (GET_CODE (insn) == INSN + && GET_CODE (pat) == SET + && GET_CODE (SET_DEST (pat)) == MEM + && GET_CODE (SET_SRC (pat)) == REG + && GET_CODE (XEXP (SET_DEST (pat), 0)) != PRE_DEC + && GET_CODE (XEXP (SET_DEST (pat), 0)) != PRE_INC + && GET_CODE (XEXP (SET_DEST (pat), 0)) != POST_DEC + && GET_CODE (XEXP (SET_DEST (pat), 0)) != POST_INC + && (i = remove_redundant_store (SET_DEST (pat), block)) + && file) + fprintf (file, + "insn %d caused a deletion of a redundant store: %d\n", + INSN_UID (insn), + i); + + /* Try to eliminate as much loads as we can using the free_regs + and regno_holds_mem information */ + + else if (GET_CODE (insn) == INSN + && GET_CODE (pat) == SET + && (GET_CODE (SET_DEST (pat)) == REG + || GET_CODE (SET_DEST (pat)) == MEM) + && (GET_CODE (SET_SRC (pat)) == MEM + || (GET_CODE (SET_SRC (pat)) == CONST_INT + && flag_risc_const))) + { + int simple_copy_f = 0; + rtx set_src = SET_SRC (pat); + rtx set_dest = SET_DEST (pat); + enum machine_mode mode = GET_MODE (set_dest); + + if (GET_CODE (SET_DEST (pat)) == REG) + old_regno = REGNO (set_dest); + else + old_regno = FIRST_PSEUDO_REGISTER; + + if (old_regno != FIRST_PSEUDO_REGISTER + && (next = next_nonnote_insn (insn)) + && GET_RTX_CLASS (GET_CODE (next)) == 'i' + && ((note = find_regno_note (next, REG_DEAD, old_regno)) + || + (GET_CODE (PATTERN (next)) == SET && + rtx_equal_p (set_dest, SET_DEST (PATTERN (next))))) + /* tevid */ + && (note == NULL + || mode == GET_MODE (XEXP (note, 0)))) + { + rtx new_reg = NULL; + rtx old_reg = set_dest; + int stop_replacement = 0; + + /* if this load is redundant (i.e. the memory loaded + exists in any register, and the register we're loading + to will die in the next insn), we can replace loaded + register in the next insn with the already loaded register, + and delete this insn. + */ + if ((regno = find_regno_holds_mem (set_src, mode)) + != FIRST_PSEUDO_REGISTER + && HARD_REGNO_NREGS (regno, mode) == 1 + && regno_holds_mem[regno].insn_load +#ifdef STACK_REGS + && (STACK_REG_P (old_reg) + || NON_STACK_REG_P (new_reg = gen_rtx (REG, + mode, + regno))) + +#endif + && TEST_HARD_REG_BIT (free_regs, regno)) + { +#ifdef STACK_REGS + if (!new_reg) + new_reg = gen_rtx (REG, mode, regno); +#endif + + /* replace this register in the next insn */ + init_undo_buf (); + saved_code = INSN_CODE (next); + subst_in_insn (next, + PATTERN (next), + old_reg, + new_reg, + 0, + 0); + if (note == NULL) + { /* Then the dest of next must remain old_reg */ + SET_DEST (PATTERN (next)) = old_reg; + } + +#ifdef REGISTER_CONSTRAINTS + + INSN_CODE (next) = recog (PATTERN (next), next, 0); + if (INSN_CODE (next) != -1) + insn_extract (next); + + if (INSN_CODE (next) == -1 + || !constrain_operands (INSN_CODE (next), 1)) + { + /* restore the previous situation */ + loop_undo_all(); + INSN_CODE (next) = saved_code; + stop_replacement = 1; + } +#endif + if (!stop_replacement) + { + + if (regno != old_regno) + { + if (note != NULL) + { + /* The regno in the REG_DEAD note should be + also changed */ + + XEXP (note, 0) = new_reg; + + /* Now, if we replaced a REG_DEAD note, and + the new_reg is the destination of the next + insn, we should remove this note */ + + if (GET_CODE (SET_DEST (PATTERN (next))) + == REG + && REGNO (SET_DEST (PATTERN (next))) + == regno) + remove_death (regno, next); + } + /* replace the registers in the free_register + list */ + + nregs = HARD_REGNO_NREGS (old_regno, mode); + for (i = 0; i < nregs; i++) + SET_HARD_REG_BIT (free_regs, old_regno + i); + nregs = HARD_REGNO_NREGS (regno, mode); + for (i = 0; i < nregs; i++) + CLEAR_HARD_REG_BIT (free_regs, regno + i); + } /* if (regno != old_regno) */ + else + /* regno == old_regno */ + { + /* mark that regno is not free anymore */ + nregs = HARD_REGNO_NREGS (regno, mode); + for (i = 0; i < nregs; i++) + CLEAR_HARD_REG_BIT (free_regs, regno + i); + } + + /* now we can delete this insn ... */ + + if (basic_block_head[block] == insn) + basic_block_head[block] = NEXT_INSN (insn); + + mhp = ®no_holds_mem[regno]; + /* we should reset the RISC flag on the insns + added for risc, so that they will not be + recombined later */ + + + if (mhp -> insn_dead) + { + t_insn = PREV_INSN (mhp->insn_dead); + while (t_insn && RTX_IS_RISC_P (t_insn)) + { + RTX_IS_RISC_P (t_insn) = 0; + t_insn = PREV_INSN (t_insn); + } + remove_death (regno, mhp -> insn_dead); + if (! t_insn) + /* something went wrong */ + abort (); + } + + if (file) + fprintf (file, + "insn %d: deleted - redundant " + "load encountered (insn %d)\n", + INSN_UID (insn), + INSN_UID (mhp -> insn_load)); + + PUT_CODE (insn, NOTE); + NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (insn) = 0; + + /* ... and start working on the next insn */ + + continue; + + } /* if (!stop_replacement) */ + + } /* if ((regno = find_regno_holds_mem (set_src)) != + FIRST_PSEUDO_REGISTER + && TEST_HARD_REG_BIT (free_regs, regno)) */ + + else if (regno != FIRST_PSEUDO_REGISTER) + /* regno holds the appropriate value but is not free, + so we can use its contents to + convert this insn to a simple reg to reg copy */ + { + copy_reg = gen_rtx (REG, mode, regno); +#ifdef STACK_REGS + if (GET_CODE (SET_DEST (pat)) != REG + || (STACK_REG_P (SET_DEST (pat)) + == STACK_REG_P (copy_reg))) +#endif + { + simple_copy_f = 1; + } + } + + else if (old_regno == last_load_reg + && (regno = + find_free_reg (GET_MODE (SET_DEST (pat)))) != + FIRST_PSEUDO_REGISTER + && regno != old_regno) + { + new_reg = gen_rtx (REG, mode, regno); + + /* replace this insn's register with regno */ + + SET_DEST (pat) = new_reg; + + /* replace this register in the next insn and its + REG_NOTES */ + init_undo_buf (); + saved_code = INSN_CODE (next); + subst_in_insn (next, + PATTERN (next), + old_reg, + new_reg, + 0, + 0); + if (note == NULL) + { /* Then the dest of next must remain old_reg */ + SET_DEST (PATTERN (next)) = old_reg; + } + +#ifdef REGISTER_CONSTRAINTS + if ((INSN_CODE (next) = recog (PATTERN (next), + next, + 0)) != -1) + insn_extract (next); + + if (INSN_CODE (next) == -1 + || !constrain_operands (INSN_CODE (next), 1)) + { + /* restore the previous situation */ + SET_DEST (pat) = old_reg; + loop_undo_all (); + INSN_CODE (next) = saved_code; + stop_replacement = 1; + } +#endif + if (!stop_replacement) + { + if (note != NULL) + { + /* The regno in the REG_DEAD note should be + changed */ + + XEXP (note, 0) = new_reg; + + /* Now, if we replaced a REG_DEAD note, and the + new_reg is the destination of the next insn, we + should remove this note */ + + if (GET_CODE (SET_DEST (PATTERN (next))) == REG + && REGNO (SET_DEST (PATTERN (next))) == regno) + remove_death (regno, next); + } + /* replace the registers in the free_register + list */ + + nregs = HARD_REGNO_NREGS (regno, mode); + for (i = 0; i < nregs; i++) + CLEAR_HARD_REG_BIT (free_regs, regno + i); + nregs = HARD_REGNO_NREGS (old_regno, mode); + for (i = 0; i < nregs; i++) + SET_HARD_REG_BIT (free_regs, old_regno + i); + + /* replace relevant data in regno_holds_mem */ + regno_holds_mem[regno].mem = set_src; + regno_holds_mem[regno].insn_load = insn; + regno_holds_mem[regno].insn_dead = next; + + if (file) + fprintf (file, + "insn %d: replacing reload register %d with register %d\n", + INSN_UID (insn), old_regno, regno); + } /* if (!stop_replacement) */ + + } /* else if (old_regno == last_load_reg + && (regno = + find_free_reg (GET_MODE (set_dest))) != + FIRST_PSEUDO_REGISTER) + */ + + else if (old_regno == last_load_reg + && file) + fprintf (file, + "insn %d: no free register found for reload." + "\n", + INSN_UID (insn)); + + } /* if ((next = next_nonnote_insn (insn)) + && GET_RTX_CLASS (GET_CODE (next)) == 'i' + && (note = find_regno_note (next, REG_DEAD, old_regno))) + */ + + else if ((regno = find_regno_holds_mem (set_src, mode)) + != FIRST_PSEUDO_REGISTER + && HARD_REGNO_NREGS (regno, mode) == 1) + { + copy_reg = gen_rtx (REG, mode, regno); +#ifdef STACK_REGS + if (GET_CODE (set_dest) != REG + || (STACK_REG_P (set_dest) == STACK_REG_P (copy_reg))) +#endif + simple_copy_f = 1; + } + + if (simple_copy_f) + { + MEM_HOLDER *mhp_org; + rtx mem; + + /* we can change this insn to a simple reg copy, instead + of a load or store */ + + mem = SET_SRC (pat); + if (copy_reg == NULL) + { + copy_reg = gen_rtx (REG, mode, regno); + } + + saved_code = INSN_CODE (insn); + SET_SRC (pat) = copy_reg; + +#ifdef REGISTER_CONSTRAINTS + if ((INSN_CODE (insn) = recog (PATTERN (insn), + insn, + 0)) != -1) + insn_extract (insn); + + if (INSN_CODE (insn) == -1 + || !constrain_operands (INSN_CODE (insn), 1)) + { + SET_SRC (pat) = mem; + INSN_CODE (insn) = saved_code; + } + else + { +#endif + + /* now we should eliminate the possibility of the risc + sequence loaded the memory int regno, to be later + recombined */ + + mhp_org = ®no_holds_mem[regno]; + mhp = ®no_holds_mem[old_regno]; + if (mhp_org -> insn_load) + { + /* we should reset the RISC flag on the insns + added for risc, so that they will not be + recombined later */ + + + if (mhp_org -> insn_dead) + { + t_insn = PREV_INSN (mhp_org->insn_dead); + while (t_insn && RTX_IS_RISC_P (t_insn)) + { + RTX_IS_RISC_P (t_insn) = 0; + t_insn = PREV_INSN (t_insn); + } + if (! t_insn) + fprintf (stderr, + "Not encountered insn_dead\n"); + remove_death (regno, mhp_org -> insn_dead); + } + } /* if (mhp_org -> insn_load) */ + + /* we should update old_regno entries in + regno_holds_mem array */ + + mhp -> mem = mhp_org -> mem; + mhp -> insn_load = insn; + + if (file) + fprintf (file, + "insn %d: mem source replaced with reg\n", + INSN_UID (insn)); + +#ifdef REGISTER_CONSTRAINTS + } /* else of if (INSN_CODE (insn) == -1 + || !constrain_operands (INSN_CODE (insn), 1)) + */ +#endif + } /* if (simple_copy_f) */ + + if (GET_CODE (pat) == SET + && GET_CODE (SET_DEST (pat)) == REG) + last_load_reg = REGNO (SET_DEST (pat)); + + } /* if (GET_CODE (insn) == INSN + && GET_CODE (pat) == SET + && GET_CODE (SET_DEST (pat)) == REG + && GET_CODE (SET_SRC (pat)) == MEM) */ + + /* mark all the original insns (those not created here). Since + we use here the same bit as RTX_IS_SPILL_P, we should do this + after checking for the spill reload register substitution. */ + RTX_IS_RISC_P (insn) = 0; + + end_of_block_f = (insn == basic_block_end[block]); + if (!INSN_UID (insn)) + fatal ("\nMemory simplify: Scanning illegal insn."); + + if (GET_CODE (insn) == INSN) + { + register rtx note; + + if (GET_CODE (pat) == SET) + { + rtx prev_insn, next_insn; + rtx insn_src = SET_SRC (pat); + rtx insn_dest = SET_DEST (pat); + int mem_opr_is_src = 0; + + /* indicates which of the two SET_SRC's arguments is a + memory reference. 0 - indicates the first one and 1 - + the second */ + + int mem_loc; + + switch (GET_CODE (insn_src)) + { + case CONST_INT: + if (flag_risc_const + && GET_CODE (insn_dest) == MEM + && !push_operand (insn_dest, + GET_MODE (insn_dest))) + { + mem_opr = insn_src; + mem_loc = 1; + mem_opr_is_src = 1; + /* this is a trick to make the code replacing + the memory operand in any other insn, valid + even here. + Note that insn_src now is actually the + insn's pattern, and not the SET_SRC of it. */ + insn_src = pat; + } + break; + case REG: + case SYMBOL_REF: + /* do nothing, this is a simple copy */ + break; + case MEM: + if (GET_CODE (insn_dest) == CC0) + /* this insn is not a simple load */ + { + mem_opr = insn_src; + mem_loc = 1; + + mem_opr_is_src = 1; + /* this is a trick to make the code replacing + the memory operand in any other insn, valid + even here. + Note that insn_src now is actually the + insn's pattern, and not the SET_SRC of it. */ + insn_src = pat; + } + break; + default: + if (GET_CODE (insn_src) == SIGN_EXTRACT + || GET_CODE (insn_src) == ZERO_EXTRACT) + { /* These cannot be handled properly */ + break; + } + fmt = GET_RTX_FORMAT (GET_CODE (insn_src)); + if (GET_CODE (XEXP (insn_src, 0)) == MEM) + { + mem_loc = 0; + mem_opr = XEXP (insn_src, 0); + } + else if (GET_RTX_LENGTH (GET_CODE (insn_src)) > 1 + && fmt[1] == 'e' + && GET_CODE (XEXP (insn_src, 1)) == MEM) + { + mem_loc = 1; + mem_opr = XEXP (insn_src, 1); + } + break; + } /* switch (GET_CODE(insn_src)) */ + + if (mem_opr) + /* we found a memory operand that we should replace */ + { + int skip_load_f = 0; /* should we skip mem load? */ + int regno_is_free = 0; /* was it allocated by find_free_reg */ + int memory_dest_changed + = GET_CODE (insn_dest) == MEM + && rtx_equal_p (insn_dest, mem_opr); + enum machine_mode mode = GET_MODE (mem_opr); + + if (GET_CODE (mem_opr) == CONST_INT) + mode = GET_MODE (insn_dest); + if ((regno = find_regno_holds_mem (mem_opr, mode)) + != FIRST_PSEUDO_REGISTER) + { + if (HARD_REGNO_NREGS (regno, mode) == 1 + && TEST_HARD_REG_BIT (free_regs, regno)) + skip_load_f = 1; + else + regno = FIRST_PSEUDO_REGISTER; + } + if (regno == FIRST_PSEUDO_REGISTER +#ifdef IS_RISC_MODE + && (IS_RISC_MODE (GET_MODE (mem_opr)) + || GET_CODE (mem_opr) == CONST_INT) +#endif + ) + { /* Look forward a few insns to see + if this mem_opr will be loaded + into a register and if it is then + try to use that register for riscifying. */ + t_insn = next_nonnote_insn (insn); + while (t_insn && regno == FIRST_PSEUDO_REGISTER) + { + if (GET_CODE (t_insn) == CODE_LABEL + || GET_CODE (t_insn) == CALL_INSN) + { + break; + } + if (GET_CODE (t_insn) == INSN) + { + register rtx dest; + + if (GET_CODE (PATTERN (t_insn)) != SET) + { + break; + } + dest = SET_DEST (PATTERN (t_insn)); + if (GET_CODE (dest) == REG + && rtx_equal_p (mem_opr, + SET_SRC (PATTERN (t_insn)))) + { + regno = REGNO (dest); + nregs = HARD_REGNO_NREGS (regno, mode); + if (HARD_REGNO_MODE_OK (regno, mode)) + { + for (i = 0; i < nregs; i++) + if (! TEST_HARD_REG_BIT (free_regs, + regno + i)) + { + regno = FIRST_PSEUDO_REGISTER; + break; + } + } + else + regno = FIRST_PSEUDO_REGISTER; + } + else if (GET_CODE (dest) == MEM + && ! push_operand (dest, + GET_MODE (dest))) + /* since there is a write to memory, no use + in trying to load something that might be + clobbered. */ + regno = FIRST_PSEUDO_REGISTER; + } + t_insn = next_nonnote_insn (t_insn); + } + + } + if (regno == FIRST_PSEUDO_REGISTER + && GET_CODE (insn_dest) == REG +#ifdef IS_RISC_MODE + && (IS_RISC_MODE (GET_MODE (mem_opr)) + || GET_CODE (mem_opr) == CONST_INT) +#endif + ) + { + regno = REGNO (insn_dest); + nregs = HARD_REGNO_NREGS (regno, mode); + + if (HARD_REGNO_MODE_OK (regno, mode)) + { + for (i = 0; i < nregs; i++) + if (! TEST_HARD_REG_BIT (free_regs, + regno + i)) + { + regno = FIRST_PSEUDO_REGISTER; + break; + } + } + else + regno = FIRST_PSEUDO_REGISTER; + } + + if (regno == FIRST_PSEUDO_REGISTER +#ifdef IS_RISC_MODE + && (IS_RISC_MODE (GET_MODE (mem_opr)) + || GET_CODE (mem_opr) == CONST_INT) +#endif + ) + { + prev_insn = prev_nonnote_insn (insn); + next_insn = next_nonnote_insn (insn); + + /* update set of not recommended hard registers + for find_free_reg () */ + /* NOTE that we can refer only to integer + registers, but now we do it more general. */ + + for (regno = 0; + regno < FIRST_PSEUDO_REGISTER; + regno++) + + if ((prev_insn + && GET_RTX_CLASS (GET_CODE (prev_insn)) + == 'i' + && (INSN_USES_REGNO (prev_insn, regno) + || INSN_SETS_REGNO (prev_insn, regno))) + || (next_insn + && GET_RTX_CLASS (GET_CODE (next_insn)) + == 'i' + && (INSN_USES_REGNO (next_insn, regno) + /* If the destination is MEM we + might write the new register + contents to the memory as the + last insn. This will force us to + also consider a write to the + allocated register in the next + insn. */ + + || (memory_dest_changed + && INSN_SETS_REGNO (next_insn, + regno))))) + SET_HARD_REG_BIT (not_recommended_regs,regno); + else + CLEAR_HARD_REG_BIT (not_recommended_regs, + regno); + + regno = find_free_reg (mode); + regno_is_free = 1; + } + + if (regno != FIRST_PSEUDO_REGISTER) + { + rtx new_insn, new_reg, link; + + /* before changing the insn, and adding others, we + check the changed insn will be legal. */ + + new_reg = gen_rtx (REG, mode, regno); + saved_code = INSN_CODE (insn); + if (mem_opr_is_src) + { + SET_SRC (pat) = new_reg; + } + else + { + init_undo_buf (); + subst_in_insn (insn, pat, mem_opr, new_reg, 0, 0); + } + +#ifdef REGISTER_CONSTRAINTS + /* now check if the insn's O.K. */ + + INSN_CODE (insn) = recog (pat, insn, 0); + + if (INSN_CODE (insn) != -1) + insn_extract (insn); + + if (INSN_CODE (insn) == -1 + || ! constrain_operands (INSN_CODE (insn), 1)) + { + if (mem_opr_is_src) + { + SET_SRC (pat) = mem_opr; + } + else + { + loop_undo_all (); + } + INSN_CODE (insn) = saved_code; + } + else /* the replacement is valid */ + { +#endif + if (! skip_load_f) + { + + if (mode != SImode && regno_is_free + && GET_CODE (mem_opr) == CONST_INT) + { + new_reg = gen_rtx (REG, SImode, regno); + } + /* load the memory into regno */ + new_insn + = make_insn_raw (gen_rtx (SET, + VOIDmode, + new_reg, + mem_opr)); + + RTX_IS_RISC_P (new_insn) = 1; + add_insn_after (new_insn, + PREV_INSN (insn)); + + /* record regno as the last register that + is used for loading */ + + last_load_reg = regno; + + + /* update new data in regno_holds_mem[] */ + +#if 0 + mhp = ®no_holds_mem[regno]; + mhp -> insn_load = new_insn; +#endif + update_regno_holds_mem(new_insn, + PATTERN(new_insn)); + + /* if insn was the first insn in this + block this should be updated */ + + if (basic_block_head[block] == insn) + basic_block_head[block] = new_insn; + + if (file) + { + fprintf (file, "insn %d was added ", + INSN_UID (new_insn)); + fprintf (file, "before insn %d\n", + INSN_UID (insn)); + } + + /* move the insn's LOG_LINKS to new_insn */ + LOG_LINKS (new_insn) = LOG_LINKS (insn); + LOG_LINKS (insn) = 0; + + /* move all relevant REG_DEAD notes to + new_insn */ + for (note = REG_NOTES (insn); + note; + note = XEXP (note, 1)) + { + if (REG_NOTE_KIND (note) == REG_DEAD) + { + register int regno + = REGNO (XEXP (note, 0)); + + if (GET_RTX_LENGTH ( + GET_CODE (insn_src)) < 2 + || GET_CODE (XEXP (insn_src, + 1 - mem_loc)) + != REG + || REGNO (XEXP (insn_src, + 1 - mem_loc)) + != regno) + { + + /* this note does not refer to + the register that will be + used from now on within + insn, thus we move it to + new_insn. */ + + remove_note (insn, note); + mhp = ®no_holds_mem[regno]; + REG_NOTES (new_insn) = + gen_rtx (EXPR_LIST, + REG_DEAD, + XEXP (note, 0), + REG_NOTES(new_insn)); + mhp -> insn_dead = new_insn; + + SET_HARD_REG_BIT + (free_regs, + REGNO (XEXP (note, 0))); + } + } /* if (REG_NOTE_KIND (note) == REG_DEAD) */ + } /* for (note = REG_NOTES (insn); + note; + note = XEXP (note, 1)) */ + } /* if (! skip_load_f) */ + else + /* we use an already loaded register */ + { + + /* since we use a load for a possibly + previously riscified insn, we should + unmark the insns created for that insn, + so that recombine will not try to + delete its load */ + mhp = ®no_holds_mem[regno]; + if (mhp -> insn_dead) + { + /* we should reset the RISC flag on + the insns added for risc, so that + they will not be recombined later + */ + + t_insn = PREV_INSN (mhp -> insn_dead); + while (t_insn && RTX_IS_RISC_P (t_insn)) + { + RTX_IS_RISC_P (t_insn) = 0; + t_insn = PREV_INSN (t_insn); + } + remove_death (regno, mhp->insn_dead); + } /* if (mhp -> insn_load) */ + + if (file) + { + fprintf (file, "insn %d: changed mem ", + INSN_UID (insn)); + fprintf (file, "operand with already " + "loaded register %d\n", + regno); + } + } + + /* in the case the memory operand was also the + insn's destination, we should add an insn + to store the result, now stored in + new_reg. */ + + if (memory_dest_changed) + { + /* Since memory destination was replaced by + a register, its contents is clobbered */ + +#if 0 + regno_holds_mem[regno].mem = 0; +#endif + bzero (®no_holds_mem[regno], + sizeof (MEM_HOLDER)); + update_entries (new_reg); + + new_insn = make_insn_raw (pat); + + RTX_IS_RISC_P (new_insn) = 1; + add_insn_after (new_insn, + PREV_INSN (insn)); + + if (skip_load_f + && basic_block_head[block] == insn) + basic_block_head[block] = new_insn; + + if (file + && ! skip_load_f) + { + fprintf (file, "insn %d was also ", + INSN_UID (new_insn)); + fprintf (file, "added before insn "); + fprintf (file, "%d\n", + INSN_UID (insn)); + } + else if (file) + { + fprintf (file, + "insn %d was added before " + "insn %d, load was saved\n", + INSN_UID (new_insn), + INSN_UID (insn)); + } + + + /* change insn to be just a store insn */ + PATTERN (insn) = gen_rtx (SET, + VOIDmode, + mem_opr, + new_reg); + + /* now we might find that a previous + store is redundant... */ + if ((i = remove_redundant_store (mem_opr, + block)) + && file) + { + fprintf (file, + "insn %d: caused deletion of " + "a redundant store: %d\n", + INSN_UID (insn), + i); + } + + /* now we actually changed the insn's + code, so we erase the current one and + we let next phases (probably sched2) to + update this code. */ + + INSN_CODE (insn) = -1; + + if (! skip_load_f) + { + /* add the last_new_insn to the new_insn's + dependency list */ + + link = rtx_alloc (INSN_LIST); + PUT_REG_NOTE_KIND (link, 0); + XEXP (link, 0) = PREV_INSN (new_insn); + XEXP (link, 1) = LOG_LINKS (new_insn); + LOG_LINKS (new_insn) = link; + } + } /* if (memory_dest_changed) */ + + /* add the new_insn to the insn's dependency + list */ + + if (! skip_load_f + || memory_dest_changed) + { + link = rtx_alloc (INSN_LIST); + PUT_REG_NOTE_KIND (link, 0); + XEXP (link, 0) = new_insn; + XEXP (link, 1) = LOG_LINKS (insn); + LOG_LINKS (insn) = link; + } + + /* Add a REG_DEAD note to the last insn to + indicate that the used register is no + longer needed. + This is not needed for this phase since we + do not remove this register from the free + register list (we just mark it to indicate + that next allocation of free register, will + not return it again, so that dependency + between adjacent insns will be as less as + possible). */ + + if (GET_CODE (insn_dest) != REG + || REGNO (insn_dest) != REGNO (new_reg)) + { + REG_NOTES (insn) + = gen_rtx (EXPR_LIST, + REG_DEAD, + new_reg, + REG_NOTES (insn)); + } +#ifdef REGISTER_CONSTRAINTS + } /* the replacement is valid */ +#endif + } /* if (regno != FIRST_PSEUDO_REGISTER) */ + else if (file) + { + fprintf (file, "insn %d: No suitable free hard", + INSN_UID (insn)); + fprintf (file, " register found for risc\n"); + } + } /* if (mem_opr) */ + } /* if (GET_CODE (pat) == SET) */ + } /* if (GET_CODE(insn) == INSN) */ + + if (GET_CODE (insn) == CODE_LABEL) + bzero (regno_holds_mem, sizeof regno_holds_mem); + + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') + { + + if (GET_CODE (insn) == CALL_INSN) + { + /* all call clobbered registers are now free */ + + for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) + if (call_used_regs[j]) + SET_HARD_REG_BIT (free_regs, j); + } + + update_free_regs (PATTERN (insn)); + + update_regno_holds_mem (insn, PATTERN (insn)); + + /* add each dead register to the free_regs set */ + /* mark each dead regno in the regno_holds_mem array */ + for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) + { + if ((REG_NOTE_KIND (note) == REG_DEAD + || REG_NOTE_KIND (note) == REG_UNUSED) + && GET_CODE (XEXP (note, 0)) == REG) + { + regno = REGNO (XEXP (note, 0)); + nregs = + HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))); + + for (i = 0; i < nregs; i++) + SET_HARD_REG_BIT (free_regs, regno + i); + regno_holds_mem[regno].insn_dead = insn; + } + } + if ((note = find_reg_note (insn, REG_WAS_0, 0))) + { + rtx set; + set = single_set (insn); + if (set == NULL + || GET_CODE (SET_DEST (set)) == REG) + { /* Since reg may have been reused. */ + remove_note (insn, note); + } + } + } /* if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') */ + } /* for (insn = basic_block_head[block]; */ + } /* for (block = 0; block < n_basic_blocks; block++) */ + + /* mark each insn with it's next nonnote insn so that recombine can work */ + { + + t_insn = f; + while (t_insn) + { + if (GET_CODE (t_insn) == INSN) + ORG_NEXT_INSN (t_insn) = next_nonnote_insn (t_insn); + t_insn = NEXT_INSN (t_insn); + } + } +} /* memory_simplify (file, f) */ + + +static void +dump_free_registers (file) + FILE *file; +{ + register int regno; + + fprintf (file, "Free registers now are: "); + for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) + if (TEST_HARD_REG_BIT (free_regs, regno)) + { + fprintf (file, " %d", regno); + } + fprintf (file, "\n"); +} + +/* Finds a free register that is able to contain a value of mode MODE. + * Returns the number of the hard register (or the first hard register, in + * case of multi-register value) found, if such exists, and mark it in the + * regs_ever_live array. Otherwise returns FIRST_PSEUDO_REGISTER. + */ + +int +find_free_reg (mode) + enum machine_mode mode; +{ + register int regno; + + /* record last_reg retunrned. Try next find form this reg on. */ + static int last_reg; + + int not_desired; /* is this the "not-desired" regset: i.e. are we going to + * take the register from those who are not "safe" within + * a function (their values is promised not to be altered). + */ + int second_half; /* is this the second half of the "round-robin" search */ + +#ifdef IS_RISC_MODE + if (!IS_RISC_MODE (mode)) + { + return (FIRST_PSEUDO_REGISTER); + } +#endif + /* we handle only DImode SImode, HImode and QImode */ + switch (mode) + { + case DImode: + case SImode: + case HImode: + case QImode: + + /* Try to find the register among those whos value is not "safe" + * first. + */ + for (not_desired = 0; not_desired < 2; not_desired++) + { + int last_reg_scanned = 0; + + /* implement a "round-robin" algorithm for register scanning. + fisrt look from the last_reg and on, and then from 0 to + last_reg. */ + + for (regno = (last_reg + 1) % FIRST_PSEUDO_REGISTER; + ! last_reg_scanned; + regno = (regno + 1) % FIRST_PSEUDO_REGISTER) + { + register int i, nregs = HARD_REGNO_NREGS (regno, mode); + register int found = 1; + + last_reg_scanned = last_reg == regno; + for (i = 0; i < nregs; i++) + { + if (! not_desired + && (! call_used_regs[regno + i] + || TEST_HARD_REG_BIT (not_recommended_regs, + regno + i))) + found = 0; + else if (! fixed_regs[regno + i] + && TEST_HARD_REG_BIT (free_regs, regno + i) + && HARD_REGNO_MODE_OK (regno + i, mode) +#ifdef ELIMINABLE_REGS + && (! frame_pointer_needed + || regno != FRAME_POINTER_REGNUM) +#endif + /* allow only registers that lived before this + phase to take part. This might reduce the number + of registers available, but otherwise some + problems may occur due to use of a register that + need to be pushed at the the function prologue, + thus corrupting the calculations of stack slots + previously performed at the reload phase. */ + && (call_used_regs[regno + i] + || regs_ever_live[regno + i]) + ) + continue; + else + found = 0; + } /* for (i = 0; i < nregs; i++) */ + if (found) + { + /* save regno for the next invokation */ + last_reg = regno + nregs - 1; + + return (regno); + } + } /* for (regno = (last_reg + 1) % FIRST_PSEUDO_REG; + regno != last_reg; + regno = (regno + 1) % FIRST_PSEUDO_REG) */ + } /* for (not_desired = 0; not_desired < 2; not_desired ++) */ + break; + } /* switch (mode) */ + return (FIRST_PSEUDO_REGISTER); +} + +/* Updates the free_regs regset according the contents of PAT */ + +void +update_free_regs (rtx pat) +{ + register int i, regno, nregs; + register j; + register char *fmt; + register RTX_CODE code = GET_CODE (pat); + + switch (code) + { + case SET: + case USE: + case CLOBBER: + if (GET_CODE (SET_DEST (pat)) == REG) + { + regno = REGNO (SET_DEST (pat)); + nregs = HARD_REGNO_NREGS (regno, + GET_MODE (SET_DEST (pat))); + + if (GET_CODE (pat) == SET + || GET_CODE (pat) == USE) + for (i = 0; i < nregs; i++) + CLEAR_HARD_REG_BIT (free_regs, regno + i); +#if 0 + else /* GET_CODE (pat) == CLOBBER */ + for (i = 0; i < nregs; i++) + SET_HARD_REG_BIT (free_regs, regno + i); +#endif + } + else if (GET_CODE (SET_DEST (pat)) == SUBREG + && GET_CODE (SUBREG_REG (SET_DEST (pat))) == REG) + { + regno = REGNO (SUBREG_REG (SET_DEST (pat))) + + SUBREG_WORD (SET_DEST (pat)); + nregs = HARD_REGNO_NREGS (regno, + GET_MODE (SET_DEST (pat))); + + if (GET_CODE (pat) == SET + || GET_CODE (pat) == USE) + for (i = 0; i < nregs; i++) + CLEAR_HARD_REG_BIT (free_regs, regno + i); + } + break; + case ADDR_VEC: + case CALL: + case HIGH: + case CONST_INT: + case CONST: + case CONST_DOUBLE: + case SYMBOL_REF: + case LABEL_REF: + case PC: + case CC0: + case REG: + /* do nothing */ + return; + } /* switch (GET_CODE (pat)) */ + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + if (fmt[i] == 'e') + { + if( XEXP (pat, i)) + update_free_regs (XEXP (pat, i)); + } + else if (fmt[i] == 'E' || fmt[i] == 'V') + { + for (j = 0; j < XVECLEN (pat, i); j++) + update_free_regs (XVECEXP (pat, i, j)); + } +} + +#if 0 +/* Returns a hard register regno, if the contents of entry regno in + last_reloads array equals to MEM, FIRST_PSEUDO_REGISTER otherwise. */ + +static int +find_last_reload (rtx mem) +{ + register int regno; + + if (GET_CODE (mem) != MEM) + abort (); + + for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) + if (rtx_equal_p (LAST_RELOAD (regno), mem)) + return (regno); + + return (FIRST_PSEUDO_REGISTER); +} +#endif + +/* Returns regno of a free register holding MEM, or FIRST_PSEUDO_REGISTER if + not exist such register. */ + +static int +find_regno_holds_mem (rtx mem, enum machine_mode mode) +{ + int i, is_const; + MEM_HOLDER *mhp; + + is_const = GET_CODE (mem) == CONST_INT; + + for (mhp = regno_holds_mem; + mhp < regno_holds_mem + FIRST_PSEUDO_REGISTER; + mhp++) + { + if (mhp->mem && GET_CODE (mhp->insn_load) == NOTE) + { /* was deleted */ + mhp->insn_load = NULL; + mhp->mem = NULL; + mhp->insn_dead = NULL; + } + if (mhp->insn_store && GET_CODE (mhp->insn_store) == NOTE) + { /* was deleted */ + mhp->insn_store = NULL; + } +#if 0 + if ((mhp->insn_load + && mhp->mem +#endif + if ((mhp->mem + && GET_CODE (mhp -> mem) == GET_CODE (mem) + && (is_const + ? rtx_equal_p ( (mhp -> mem), (mem)) + : rtx_equal_p (XEXP (mhp -> mem, 0), XEXP (mem, 0))) + && HARD_REGNO_MODE_OK (mhp - regno_holds_mem, mode) + && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (mhp -> insn_load)))) + >= GET_MODE_SIZE (mode)) + || (mhp -> mem + && mhp -> insn_store + && GET_MODE_SIZE (GET_MODE (SET_SRC (PATTERN (mhp -> insn_store)))) + >= GET_MODE_SIZE (mode) + && GET_CODE (SET_DEST ( PATTERN (mhp -> insn_store))) + == GET_CODE (mem) + && HARD_REGNO_MODE_OK (mhp - regno_holds_mem, mode) + && (is_const + ? rtx_equal_p (SET_DEST ( PATTERN (mhp -> insn_store)), + mem) + : rtx_equal_p (XEXP (SET_DEST (PATTERN (mhp -> insn_store)), + 0), + XEXP (mem, 0))))) + return (mhp - regno_holds_mem); + } + return FIRST_PSEUDO_REGISTER; +} /* find_regno_holds_mem (rtx mem) */ + + + +/* Updates the regno_holds_mem array as required from pat */ + +static void +update_regno_holds_mem (rtx insn, rtx pat) +{ + register int i, j, regno, nregs; + MEM_HOLDER *mhp; + rtx set_src, set_dest; + register char *fmt; + register RTX_CODE code = GET_CODE (pat); + + if (GET_CODE (insn) == JUMP_INSN) + { + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + regno_holds_mem[i].insn_store = 0; + return; + } + + switch (GET_CODE (pat)) + { + case SET: + set_src = SET_SRC (pat); + set_dest = SET_DEST (pat); + if (GET_CODE (set_dest) == REG) + { + regno = REGNO (set_dest); + nregs = HARD_REGNO_NREGS (regno, GET_MODE (set_dest)); + + mhp = ®no_holds_mem[regno]; + if (nregs == 1 + && (GET_CODE (set_src) == MEM + && !MEM_VOLATILE_P (set_src) + && GET_CODE (XEXP (set_src, 0)) != PRE_INC + && GET_CODE (XEXP (set_src, 0)) != PRE_DEC + && GET_CODE (XEXP (set_src, 0)) != POST_INC + && GET_CODE (XEXP (set_src, 0)) != POST_DEC) + || GET_CODE (set_src) == CONST_INT) + { + mhp -> mem = set_src; + mhp -> insn_load = insn; + mhp -> insn_store = mhp -> insn_dead = 0; + } + else + { + for (; mhp < ®no_holds_mem[regno] + nregs; mhp++) + { + bzero (mhp, sizeof (MEM_HOLDER)); + } + } + if (nregs == 1) + { + /* since we set a register, each mem using this reg is not valid + any more */ + + update_entries (set_dest); + } + else + { + /* memory holds more than one register. This is a simplification + Actually we should zero only those register entries which are + relevant for nregs... */ + bzero (regno_holds_mem, sizeof regno_holds_mem); + break; + } + update_regno_holds_mem (insn, set_src); + } + else if (GET_CODE (set_dest) == SUBREG) + { + if (GET_CODE (SUBREG_REG (set_dest)) == REG) + { + regno = REGNO (SUBREG_REG (set_dest)) + SUBREG_WORD (set_dest); + nregs + = HARD_REGNO_NREGS (regno, GET_MODE (SUBREG_REG (set_dest))); + + mhp = ®no_holds_mem[regno]; + for (; mhp < ®no_holds_mem[regno] + nregs; mhp++) + { + bzero (mhp, sizeof (MEM_HOLDER)); + } + if (nregs == 1) + { + update_entries (SUBREG_REG (set_dest)); + } + else + { + /* memory holds more than one register. This is a simplification. + Actually we should zero only those register entries which are + relevant for nregs... */ + bzero (regno_holds_mem, sizeof regno_holds_mem); + } + update_regno_holds_mem (insn, set_src); + return; + } + else /* subreg of mem */ + { + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + regno_holds_mem[i].mem = 0; + update_regno_holds_mem (insn, XEXP (XEXP (set_dest, 0), 0)); + update_regno_holds_mem (insn, set_src); + return; + } + } + else if (GET_CODE (set_dest) == MEM) + { + MEM_HOLDER save_mh; + int is_push = 0; + + mhp = 0; + + if ((GET_CODE (set_src) == REG + || GET_CODE (set_src) == CONST_INT) + && push_operand (set_dest, Pmode)) + { /* A push only ruins memory references based on stack_pointer */ + is_push = 1; + } + else if (GET_CODE (set_src) == REG + /* We might want to add the possibility of SUBREG, isn't it? */ + && !MEM_VOLATILE_P (set_dest) + && GET_CODE (XEXP (set_dest, 0)) != PRE_INC + && GET_CODE (XEXP (set_dest, 0)) != PRE_DEC + && GET_CODE (XEXP (set_dest, 0)) != POST_INC + && GET_CODE (XEXP (set_dest, 0)) != POST_DEC) + { + register int regno = REGNO (set_src); + register int nregs = HARD_REGNO_NREGS (regno, + GET_MODE (set_src)); + + if (nregs == 1) + { + mhp = ®no_holds_mem[regno]; + save_mh = *mhp; + } + } + else if (GET_CODE (set_src) != REG) + update_regno_holds_mem (insn, set_src); + + if (!is_push) + { + MEM_HOLDER *p = regno_holds_mem; + rtx store_pat; + + for (; p < regno_holds_mem + FIRST_PSEUDO_REGISTER; p++) + { + if (p -> mem) + { + if (GET_CODE (p -> mem) == MEM + && true_dependence (set_dest, p -> mem)) + { + p -> mem = 0; + } + } + if (p -> insn_store + && (store_pat = PATTERN (p -> insn_store)) + && GET_CODE (SET_DEST (store_pat)) == MEM + && true_dependence (set_dest, + SET_DEST (store_pat))) + { + /* insn_store is not valid any more */ + p -> insn_store = 0; + } + } + } + + if (mhp) + { + /* restore the relevant entry */ + *mhp = save_mh; + mhp -> insn_store = insn; + + /* if there was no load, we can consider this insn as if it is a + load */ + if (! mhp -> insn_load || GET_CODE (mhp -> insn_load) == NOTE) + { + mhp -> insn_load = insn; + mhp -> mem = set_dest; + } + } + update_regno_holds_mem (insn, XEXP (set_dest, 0)); + } + else + { + update_regno_holds_mem (insn, set_dest); + update_regno_holds_mem (insn, set_src); + } + return; + case CLOBBER: + set_dest = SET_DEST (pat); + if (GET_CODE (set_dest) == REG) + { + register int regno = REGNO (set_dest); + register int nregs = HARD_REGNO_NREGS (regno, + GET_MODE (set_dest)); + + if (nregs == 1) + { + bzero (®no_holds_mem[regno], sizeof (MEM_HOLDER)); + update_entries (set_dest); + } + else + /* memory holds more than one register. This is a simplification. + Actually we should zero only those register entries which are + relevant for nregs... */ + bzero (regno_holds_mem, sizeof regno_holds_mem); + } + else if (GET_CODE (set_dest) == SUBREG) + { + regno = REGNO (SUBREG_REG (set_dest)); + nregs = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (set_dest, 0))); + + mhp = ®no_holds_mem[regno]; + for (; mhp < ®no_holds_mem[regno] + nregs; mhp++) + { + bzero (mhp, sizeof (MEM_HOLDER)); + } + if (nregs == 1) + { + update_entries (XEXP (set_dest, 0)); + } + else + { + /* memory holds more than one register. This is a simplification. + Actually we should zero only those register entries which are + relevant for nregs... */ + bzero (regno_holds_mem, sizeof regno_holds_mem); + } + return; + } + else if (GET_CODE (set_dest) == MEM) + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + { + /* the mem field indicates that this regno is no more valid for + replacement in loads. Note that this regno might be valid for + redundant store, or even replace loads with memory to which + this reg was writing in the insn_store, and in such case we + would like to reset the risc flags on all insns, from insn_load + to insn_dead. This is why we don't reset here insn_load and + insn_dead. */ + if (regno_holds_mem[i].mem + && GET_CODE (regno_holds_mem[i].mem) == MEM + && true_dependence (set_dest, regno_holds_mem[i].mem)) + regno_holds_mem[i].mem = 0; + } + else + { + fprintf (stderr, + "unpredicted case caused reset of regno_holds_mem:\n"); + fprintf (stderr, "pattern:\n"); + debug_rtx (pat); + fprintf (stderr, "insn:\n"); + debug_rtx (insn); + bzero (regno_holds_mem, sizeof regno_holds_mem); + } + return; + case CALL: + /* since we cannot know what writes to memory in the function call, + we must not use the information in regno_holds_mem anymore */ + + bzero (regno_holds_mem, sizeof regno_holds_mem); + return; + case PRE_DEC: + case PRE_INC: + case POST_DEC: + case POST_INC: + if (GET_CODE (XEXP (pat, 0)) == REG) + { + bzero (®no_holds_mem[REGNO (XEXP (pat,0))], sizeof (MEM_HOLDER)); + update_entries (XEXP (pat, 0)); + } + else + { + update_regno_holds_mem (insn, XEXP (pat, 0)); + } + return; + case MEM: + /* there is a use of a memory in this insn, we cannot trust the + insn_store data anymore */ + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + { + regno_holds_mem[i].insn_store = 0; + if (regno_holds_mem[i].insn_load == NULL) + { + regno_holds_mem[i].insn_dead = 0; + regno_holds_mem[i].mem = NULL; + } + } + update_regno_holds_mem (insn, XEXP (pat, 0)); + return; + case USE: + update_regno_holds_mem (insn, SET_DEST (pat)); + return; + case HIGH: + case CONST_INT: + case CONST: + case CONST_DOUBLE: + case SYMBOL_REF: + case LABEL_REF: + case PC: + case CC0: + case REG: + /*case SUBREG:*/ + /* do nothing */ + return; + } /* switch (GET_CODE (pat)) */ + + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + if (fmt[i] == 'e') + { + if( XEXP (pat, i)) + update_regno_holds_mem (insn, XEXP (pat, i)); + } + else if (fmt[i] == 'E' || fmt[i] == 'V') + { + for (j = 0; j < XVECLEN (pat, i); j++) + update_regno_holds_mem (insn, XVECEXP (pat, i, j)); + } +} /* update_regno_holds_mem (rtx pat) */ + + + + +/* Invalidates entries of memory mentioning REG in their memories, and the + entry of the appropriate REG */ + +static void +update_entries (rtx reg) +{ + register MEM_HOLDER *mhp = regno_holds_mem; + register int regno = REGNO (reg); + + for (; mhp < regno_holds_mem + FIRST_PSEUDO_REGISTER; mhp++) + { + if (mhp->mem && reg_overlap_mentioned_p (reg, mhp->mem)) + { + if (mhp->insn_store && mhp->insn_store != mhp->insn_load) + { + mhp -> insn_load = mhp -> insn_store; + mhp -> mem = SET_DEST (PATTERN (mhp -> insn_load)); + mhp -> insn_dead = 0; + } + else + bzero (mhp, sizeof (MEM_HOLDER)); + } + if (mhp -> insn_store && GET_CODE (mhp -> insn_store) == INSN + /* insn_store can be deleted by redundant store elimination */ + && reg_overlap_mentioned_p (reg, + SET_DEST (PATTERN (mhp->insn_store)))) + { + if (mhp->insn_load == mhp->insn_store) + { + bzero (mhp, sizeof (MEM_HOLDER)); + } + else + { + mhp -> insn_store = 0; + } + } + } /* for (; mhp < regno_holds_mem + FIRST_PSEUDO_REGISTER; mhp++) */ +} /* update_entries (rtx reg) */ + + + +/* for each regno found to be non-free (is used or set) from (and including) + FIRST, to LAST, clears the appropriate bit in HARD_REG_SET pointed to by + FREE. */ + +void +find_free_regs_between (free, first, last) + HARD_REG_SET *free; + rtx first; + rtx last; + +{ + rtx insn, pat; + char *funcname = "find_free_regs_between"; + register int i; + + + if (! first) + abort (); + if (! last) + abort (); + + insn = first; + while (insn + && insn != last) + { + if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') + { + if (GET_CODE (insn) == CALL_INSN) + { + /* we should reset all regs clobbered by a call */ + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (call_used_regs[i]) + CLEAR_HARD_REG_BIT (*free, i); + } + else /* GET_RTX_CLASS (GET_CODE (insn)) != 'i' */ + { + pat = PATTERN (insn); + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (INSN_SETS_REGNO (insn, i) + || INSN_USES_REGNO (insn, i)) + CLEAR_HARD_REG_BIT (*free, i); + } + } /* if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') */ + insn = NEXT_INSN (insn); + } + if (insn != last) + fprintf (stderr, "%s (): didn't encounterd last!\n", funcname); + +} + +/* removes a previous store of MEM if found, and returns INSN_UID of the insn + deleted. Otherwise returns 0. */ +static int +remove_redundant_store (rtx mem, int block) +{ + rtx t_insn; + int regno; + + for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) + if ((t_insn = regno_holds_mem[regno].insn_store) + && GET_CODE (t_insn) == INSN + && rtx_equal_p (SET_DEST (PATTERN (t_insn)), mem)) + { + if (basic_block_head[block] == t_insn) + basic_block_head[block] = NEXT_INSN (t_insn); + PUT_CODE (t_insn, NOTE); + NOTE_LINE_NUMBER (t_insn) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (t_insn) = 0; + + /* if the insn we have just deleted, was preceded with one or two risc + additions (i.e. memory_simplify added insns before it), and they are + not used for anything else, remove them as well */ + if (RTX_IS_RISC_P (PREV_INSN (t_insn))) + { + PUT_CODE (PREV_INSN (t_insn), NOTE); + NOTE_LINE_NUMBER (PREV_INSN (t_insn)) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (PREV_INSN (t_insn)) = 0; + if (RTX_IS_RISC_P (PREV_INSN (PREV_INSN (t_insn)))) + { + PUT_CODE (PREV_INSN (PREV_INSN (t_insn)), NOTE); + NOTE_LINE_NUMBER (PREV_INSN (PREV_INSN (t_insn))) + = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (PREV_INSN (PREV_INSN (t_insn))) = 0; + } + } + + return INSN_UID (t_insn); + } + return 0; +} /* remove_redundant_store (rtx mem) */ + +/* intel2 - end */ +/* intel1 */ + +/* + Try to eliminate unnecessary reg to reg moves, and also + if the destination is a register try to use that register + as one of the sources. + + EXAMPLE: + +(insn 618 614 616 (set (reg:SI %eax) + (mem/s:SI (plus:SI (mult:SI (reg/v:SI %ebx) + (const_int 4)) + (reg:SI %esi)))) -1 (nil) + (nil)) + +(insn 616 618 59 (set (reg:SI %esi) + (mem:SI (plus:SI (reg:SI %esp) + (const_int 36)))) -1 (nil) + (nil)) + +(insn:HI 59 616 60 (set (reg:SI %eax) + (ior:SI (reg:SI %eax) + (mem/s:SI (plus:SI (mult:SI (reg/v:SI %ebx) + (const_int 4)) + (reg:SI %esi))))) 105 {iorsi3} (nil) + (nil)) + +(insn 60 59 620 (set (reg:SI %eax) + (not:SI (reg:SI %eax))) 130 {one_cmplsi2} (insn_list 59 (nil)) + (nil)) + +(insn 620 60 61 (set (reg/v:SI %ecx) + (reg:SI %eax)) -1 (nil) + (expr_list:REG_DEAD (reg:SI %eax) + (nil))) + +WILL BECOME: + +(insn 618 614 616 (set (reg:SI %ecx) + (mem/s:SI (plus:SI (mult:SI (reg/v:SI %ebx) + (const_int 4)) + (reg:SI %esi)))) -1 (nil) + (nil)) + +(insn 616 618 59 (set (reg:SI %esi) + (mem:SI (plus:SI (reg:SI %esp) + (const_int 36)))) -1 (nil) + (nil)) + +(insn:HI 59 616 60 (set (reg:SI %ecx) + (ior:SI (reg:SI %ecx) + (mem/s:SI (plus:SI (mult:SI (reg/v:SI %ebx) + (const_int 4)) + (reg:SI %esi))))) 105 {iorsi3} (nil) + (nil)) + +(insn 60 59 620 (set (reg:SI %ecx) + (not:SI (reg:SI %ecx))) 130 {one_cmplsi2} (insn_list 59 (nil)) + (nil)) + +(note 620 60 61 "" NOTE_INSN_DELETED) + + +The trigger for the optimization is: + +(insn 620 60 61 (set (reg/v:SI %ecx) + (reg:SI %eax)) -1 (nil) + (expr_list:REG_DEAD (reg:SI %eax) + (nil))) + +*/ +void +reg_to_reg_copy_opt (f, file) + rtx f; + FILE *file; +{ + rtx this_insn, regx, note, src; + int regno, success, length, i; + char * fmt; + + if (file) + { + fprintf (file, "\n\ndoing reg to reg copy opt\n"); + } + hard_reg_flow_analysis (f, NULL, 1); + this_insn = f; + while (this_insn) + { + if (GET_CODE (this_insn) == INSN + && GET_CODE (PATTERN (this_insn)) == SET + && GET_CODE (SET_DEST (PATTERN (this_insn))) == REG + && GET_CODE (SET_SRC (PATTERN (this_insn))) == REG + && REGNO (SET_SRC (PATTERN (this_insn))) + != REGNO (SET_DEST (PATTERN (this_insn))) + && GET_MODE (SET_SRC (PATTERN (this_insn))) + == GET_MODE (SET_DEST (PATTERN (this_insn))) + && find_regno_note (this_insn, REG_DEAD, + REGNO (SET_SRC (PATTERN (this_insn)))) + ) + { + success = try_backwards_replace (SET_DEST (PATTERN (this_insn)), + SET_SRC (PATTERN (this_insn)), + this_insn, 1, file); + if (!success) + { + success = try_forwards_replace (SET_DEST (PATTERN (this_insn)), + SET_SRC (PATTERN (this_insn)), + this_insn, file); + } + } + else if (GET_CODE (this_insn) == INSN + && GET_CODE (PATTERN (this_insn)) == SET + && GET_CODE (SET_DEST (PATTERN (this_insn))) == REG + && GET_CODE (SET_SRC (PATTERN (this_insn))) == SUBREG + && REGNO (SET_DEST (PATTERN (this_insn))) + != REGNO (SUBREG_REG (SET_SRC (PATTERN (this_insn)))) + && SUBREG_WORD (SET_SRC (PATTERN (this_insn))) == 0 + && GET_MODE (SET_SRC (PATTERN (this_insn))) + == GET_MODE (SET_DEST (PATTERN (this_insn))) + && (note = find_regno_note (this_insn, REG_DEAD, + REGNO (SUBREG_REG (SET_SRC (PATTERN (this_insn)))))) + && rtx_equal_p (XEXP (note, 0), + SUBREG_REG (SET_SRC (PATTERN (this_insn)))) + && HARD_REGNO_NREGS (REGNO (SET_DEST (PATTERN (this_insn))), + GET_MODE (SUBREG_REG (SET_SRC (PATTERN (this_insn))))) + == + HARD_REGNO_NREGS (REGNO (SET_DEST (PATTERN (this_insn))), + GET_MODE (SET_DEST (PATTERN (this_insn)))) + && HARD_REGNO_NREGS (REGNO (SET_DEST (PATTERN (this_insn))), + GET_MODE (SET_DEST (PATTERN (this_insn)))) + == 1 + && HARD_REGNO_MODE_OK (REGNO (SET_DEST (PATTERN (this_insn))) , + GET_MODE (SUBREG_REG (SET_SRC (PATTERN (this_insn))))) + ) + { + regx = gen_rtx (REG, + GET_MODE (SUBREG_REG (SET_SRC (PATTERN (this_insn)))), + REGNO (SET_DEST (PATTERN (this_insn)))); + success + = try_backwards_replace (regx, + SUBREG_REG (SET_SRC (PATTERN (this_insn))), + this_insn, 1, file); + if (!success) + { + success + = try_forwards_replace (SET_DEST (PATTERN (this_insn)), + SET_SRC (PATTERN (this_insn)), + this_insn, file); + } + } + else if (GET_CODE (this_insn) == INSN + && GET_CODE (PATTERN (this_insn)) == SET + && GET_CODE (SET_DEST (PATTERN (this_insn))) == REG + && GET_CODE (SET_SRC (PATTERN (this_insn))) != MEM + && GET_CODE (SET_SRC (PATTERN (this_insn))) != SUBREG + && !reg_overlap_mentioned_p (SET_DEST (PATTERN (this_insn)), + SET_SRC (PATTERN (this_insn))) + ) + { + src = SET_SRC (PATTERN (this_insn)); + fmt = GET_RTX_FORMAT (GET_CODE (src)); + length = GET_RTX_LENGTH (GET_CODE (src)); + for (i=0; i<length; i++) + { + if (fmt[i] == 'e' + && GET_CODE (XEXP (src, i)) == SUBREG) + { /* Makes matters too complex. */ + return; + } + } + for (i=0; i<length; i++) + { + if (fmt[i] == 'e' + && GET_CODE (XEXP (src, i)) == REG + && (note = find_regno_note (this_insn, REG_DEAD, + REGNO (XEXP (src, i)))) + && rtx_equal_p (XEXP (src, i), XEXP (note, 0)) + ) + { /* One of the sources dies in this insn - + see if the destination register can be used + to replace that register. This has a chance + of producing better code e.g. reg1 <- reg1 AND reg3 + produces more efficient code than + reg1 <- reg2 AND reg3. */ + rtx regx, regy; + regy = XEXP (src, i); + regx = SET_DEST (PATTERN (this_insn)); + if (reg_overlap_mentioned_p (regx, PATTERN (this_insn))) + { + break; + } + if (GET_MODE (regx) != GET_MODE (regy)) + { + if (HARD_REGNO_NREGS (REGNO (regx), GET_MODE (regy)) != 1 + || + !(HARD_REGNO_MODE_OK (REGNO (regx), GET_MODE (regy)))) + { + continue; + } + regx = gen_rtx (REG, GET_MODE (regy), REGNO (regx)); + } + if (try_backwards_replace (regx, regy, this_insn, 0, file)) + { + remove_note (this_insn, note); + break; /* Since now the dest reg is + mentioned in the src. */ + } + } + } + + } + this_insn = NEXT_INSN (this_insn); + } + if (file) + { + fprintf (file, "\n"); + } +} + +/* + insn is of the form + regx <- regy (regy dead) + or + regx <- SUBREG (regy) (regy dead) + or + regx <- OP (regy, ...) (regy dead) + + Search backwards for last previous setting of regy in which the + setting of regy can be replaced with regx. If it can then + do the replacement and then if delete_flag is set delete insn. +*/ + +static +int +try_backwards_replace (regx, regy, insn, delete_flag, file) + rtx regx, regy, insn; + FILE *file; +{ + rtx this_insn, set_insn, stop_insn; + int stop_replacement = 0; + int found = 0, insn_code_number, not_yet_recoged; + + + if (file) + { + fprintf (file, "\ninsn %d reg%d <- reg%d (reg%d dead) (try backwards)\n", + INSN_UID(insn), REGNO (regx), REGNO (regy), REGNO(regy)); + } + this_insn = prev_nonnote_insn (insn); + /* Find the first previous insn in the block that sets regy and in + which regy can be replaced with regx */ + while (!found && this_insn + && !(GET_CODE (this_insn) == CODE_LABEL + || GET_CODE (this_insn) == CALL_INSN + || GET_CODE (this_insn) == JUMP_INSN)) + { + if (GET_CODE (this_insn) == INSN) + { + if (GET_CODE (PATTERN (this_insn)) != SET) + { + return (0); + } + if (GET_CODE (SET_DEST (PATTERN (this_insn))) == REG) + { + if (REGNO (regx) == REGNO (SET_DEST (PATTERN (this_insn)))) + { + return (0); + } + else if (REGNO (regy) == REGNO (SET_DEST (PATTERN (this_insn)))) + { + if (GET_MODE (regy) + == GET_MODE (SET_DEST (PATTERN (this_insn)))) + { +#ifdef REGISTER_CONSTRAINTS + if (INSN_CODE (this_insn) == -1) + { + INSN_CODE (this_insn) + = recog (PATTERN (this_insn), this_insn, 0); + } +#endif + SET_DEST (PATTERN (this_insn)) = regx; +#ifdef REGISTER_CONSTRAINTS + + if ((insn_code_number + = recog (PATTERN (this_insn), this_insn, 0)) < 0 + || (INSN_CODE (this_insn) != -1 + && insn_code_number != INSN_CODE (this_insn))) + {/* Need to have the same code number since + constraints are sometimes more lax than + predicates */ + SET_DEST (PATTERN (this_insn)) = regy; + stop_replacement = 1; + } + else + { + INSN_CODE (this_insn) = insn_code_number; + insn_extract (this_insn); + if(!constrain_operands (INSN_CODE (this_insn), 1)) + { + /* restore the previous situation */ + SET_DEST (PATTERN (this_insn)) = regy; + /*INSN_CODE (this_insn) + = recog (PATTERN (this_insn), this_insn, 0);*/ + stop_replacement = 1; + } + } + +#endif + if (!stop_replacement) + { + found = 1; + set_insn = this_insn; + } + } + else + { + return (0); + } + } + } + else if (reg_overlap_mentioned_p (regx, SET_DEST (PATTERN (this_insn)))) + { + return (0); + } + if (!found + && reg_overlap_mentioned_p (regx, SET_SRC (PATTERN (this_insn)))) + { + return (0); + } + } + if (!found) + { + stop_replacement = 0; + this_insn = prev_nonnote_insn (this_insn); + } + } + if (found) + {/* We have found the insn that last sets regy and successfully + replaced regx as the dest of that insn. + In all insns between set_insn and insn replace regy with regx. */ + stop_replacement = 0; + this_insn = next_nonnote_insn (set_insn); + init_undo_buf (); + stop_insn = next_nonnote_insn (insn); + while (this_insn != stop_insn && !stop_replacement) + { +#ifdef REGISTER_CONSTRAINTS + if (INSN_CODE (this_insn) == -1) + { + INSN_CODE (this_insn) + = recog (PATTERN (this_insn), this_insn, 0); + } +#endif + subst_in_insn (this_insn, PATTERN (this_insn), regy, regx, 0, 0); + if (reg_set_p (regy, this_insn) + || reg_overlap_mentioned_p (regy, PATTERN (this_insn))) + { /* regy was used in some other mode - fail */ + stop_replacement = 1; + } +#ifdef REGISTER_CONSTRAINTS + if (stop_replacement + || + (insn_code_number + = recog (PATTERN (this_insn), this_insn, 0)) < 0 + || (INSN_CODE (this_insn) != -1 + && insn_code_number != INSN_CODE (this_insn))) + {/* Need to have the same code number since constraints + are sometimes more lax than predicates */ + stop_replacement = 1; + } + else + { + INSN_CODE (this_insn) = insn_code_number; + insn_extract (this_insn); + if(!constrain_operands (INSN_CODE (this_insn), 1)) + { + stop_replacement = 1; + } + } +#endif + this_insn = next_nonnote_insn ( this_insn); + } + + if (stop_replacement) + { /* A replacement was unsuccessful - undo all of the replacements */ + SET_DEST (PATTERN (set_insn)) = regy; + /*INSN_CODE (this_insn) + = recog (PATTERN (this_insn), this_insn, 0);*/ + this_insn = next_nonnote_insn (set_insn); + loop_undo_all (); + /*while (this_insn != insn) + { + INSN_CODE (this_insn) + = recog (PATTERN (this_insn), this_insn, 0); + this_insn = next_nonnote_insn (this_insn); + }*/ + return (0); + } + else + { + if (file) + { + fprintf (file, "replaced dest reg%d of insn %d with reg%d\n", + REGNO (regy), INSN_UID (set_insn), REGNO (regx)); + fprintf (file, " in insns %d through %d replaced reg%d with reg%d\n", + INSN_UID (next_nonnote_insn (set_insn)), + INSN_UID (insn), + REGNO (regy), REGNO (regx)); + } + if (delete_flag) + {/* Delete insn */ + PUT_CODE (insn, NOTE); + NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (insn) = 0; + if (file) + { + fprintf (file, " deleted insn %d\n", INSN_UID (insn)); + } + } + return (1); + } + } + return (0); +} + + +/* + insn is of the form + regx <- regy (regy dead) + or + regx <- SUBREG (regy) (regy dead) + + Search forwards for next insn in which the regx is dead. + Try to replace all uses of regx with regy in those insns + and if successful then delete insn. +*/ + +static +int +try_forwards_replace (regx, regy, insn, file) + rtx regx, regy, insn; + FILE *file; +{ + rtx this_insn, dead_insn, dead_note, stop_insn; + int stop_replacement = 0; + int found = 0, insn_code_number; + + + if (file) + { + if (GET_CODE (regy) == REG ) + fprintf (file, "\ninsn %d reg%d <- reg%d (reg%d dead) (try forwards)\n", + INSN_UID(insn), REGNO (regx), REGNO (regy), REGNO(regy)); + else + fprintf (file, "\ninsn %d reg%d <- reg%d (reg%d dead) (try forwards)\n", + INSN_UID(insn), REGNO (regx), + REGNO (SUBREG_REG (regy)), + REGNO (SUBREG_REG (regy))); + } + this_insn = next_nonnote_insn (insn); + /* Find the next insn in the block where regx dies */ + while (!found && this_insn + && !(GET_CODE (this_insn) == CODE_LABEL + || GET_CODE (this_insn) == CALL_INSN + || GET_CODE (this_insn) == JUMP_INSN)) + { + if (GET_CODE (this_insn) == INSN) + { + if (GET_CODE (PATTERN (insn)) == USE + && reg_overlap_mentioned_p (regx, SET_DEST (PATTERN (insn)))) + { + return (0); + } + if (reg_set_p (regy, this_insn)) + { + return (0); + } + else if ((dead_note + = find_regno_note (this_insn, REG_DEAD, REGNO (regx))) + && rtx_equal_p (XEXP (dead_note, 0), regx)) + { + found = 1; + dead_insn = this_insn; + } + } + if (!found) + { + this_insn = next_nonnote_insn (this_insn); + } + } + if (found) + {/* We have found the insn where regx dies. */ + stop_replacement = 0; + this_insn = next_nonnote_insn (insn); + init_undo_buf (); + stop_insn = next_nonnote_insn (dead_insn); + while (this_insn != stop_insn && !stop_replacement) + { +#ifdef REGISTER_CONSTRAINTS + if (INSN_CODE (this_insn) == -1) + { + INSN_CODE (this_insn) + = recog (PATTERN (this_insn), this_insn, 0); + } +#endif + subst_in_insn (this_insn, PATTERN (this_insn), regx, regy, 0, 0); + if (reg_set_p (regx, this_insn) + || reg_overlap_mentioned_p (regx, PATTERN (this_insn))) + { /* regx is used in some other mode - fail. */ + if (file) + { + fprintf (file, "fail insn %d reg %d still mentioned\n", + INSN_UID (this_insn), REGNO (regx)); + tdebug_rtx (this_insn, file); + } + stop_replacement = 1; + } +#ifdef REGISTER_CONSTRAINTS + if (stop_replacement + || + (insn_code_number + = recog (PATTERN (this_insn), this_insn, 0)) < 0 + || (INSN_CODE (this_insn) != -1 + && insn_code_number != INSN_CODE (this_insn))) + { /* Need to have the same code number since constraints + are sometimes more lax than predicates */ + if (file) + { + fprintf (file, "fail insn %d new_recog %d old_recog %d\n", + INSN_UID (this_insn), insn_code_number, INSN_CODE (this_insn)); + } + stop_replacement = 1; + } + else + { + INSN_CODE (this_insn) = insn_code_number; + insn_extract (this_insn); + if(!constrain_operands (INSN_CODE (this_insn), 1)) + { + stop_replacement = 1; + } + } +#endif + this_insn = next_nonnote_insn ( this_insn); + } + + if (stop_replacement) + { /* A replacement was unsuccessful - undo all of the replacements */ + this_insn = next_nonnote_insn (insn); + loop_undo_all (); + stop_insn = next_nonnote_insn (dead_insn); + /*while (this_insn != stop_insn) + { + INSN_CODE (this_insn) + = recog (PATTERN (this_insn), this_insn, 0); + this_insn = next_nonnote_insn (this_insn); + }*/ + return (0); + } + else + { /* Delete insn */ + PUT_CODE (insn, NOTE); + NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (insn) = 0; + XEXP (dead_note, 0) = regy; + if (file) + { + fprintf (file, " in insns %d through %d replaced reg%d with reg%d\n", + INSN_UID (next_nonnote_insn (insn)), + INSN_UID (dead_insn), + REGNO (regx), + GET_CODE (regy) == REG + ? REGNO (regy) + : REGNO (SUBREG_REG (regy))); + fprintf (file, " deleted insn %d\n", INSN_UID (insn)); + } + return (1); + } + } + return (0); } diff -r -u -H -N gcc-2.6.3/config/i386/i386.c gcc-i2.6.3/config/i386/i386.c --- gcc-2.6.3/config/i386/i386.c Sat Nov 5 13:57:47 1994 +++ gcc-i2.6.3/config/i386/i386.c Thu Feb 16 12:51:33 1995 @@ -1,6 +1,9 @@ /* Subroutines for insn-output.c for Intel X86. - Copyright (C) 1988, 1992, 1994 Free Software Foundation, Inc. + Copyright (C) 1988, 1992 Free Software Foundation, Inc. + Pentium cpu support and other enhancements by Tevi Devor Intel Corp. + (tevi@iil.intel.com). + This file is part of GNU CC. GNU CC is free software; you can redistribute it and/or modify @@ -33,6 +36,8 @@ #include "flags.h" #include "function.h" +/* intel1 Need the EXTRA_CONSTRAINT - changed s to */ +#if 0 #ifdef EXTRA_CONSTRAINT /* If EXTRA_CONSTRAINT is defined, then the 'S' constraint in REG_CLASS_FROM_LETTER will no longer work, and various @@ -41,6 +46,10 @@ /* The previous line used to be #error, but some compilers barf even if the conditional was untrue. */ #endif +#endif + +/* which cpu are we scheduling for intel1*/ +enum processor_type x86_cpu; #define AT_BP(mode) (gen_rtx (MEM, (mode), frame_pointer_rtx)) @@ -51,6 +60,9 @@ char *output_move_const_single (); char *output_fp_cc0_set (); +/* intel1 */ +static int opt_level=0; + char *hi_reg_name[] = HI_REGISTER_NAMES; char *qi_reg_name[] = QI_REGISTER_NAMES; char *qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES; @@ -74,151 +86,8 @@ /* Test and compare insns in i386.md store the information needed to generate branch and scc insns here. */ -struct rtx_def *i386_compare_op0 = NULL_RTX; -struct rtx_def *i386_compare_op1 = NULL_RTX; +struct rtx_def *i386_compare_op0, *i386_compare_op1; struct rtx_def *(*i386_compare_gen)(), *(*i386_compare_gen_eq)(); - -/* Register allocation order */ -char *i386_reg_alloc_order = (char *)0; -static char regs_allocated[FIRST_PSEUDO_REGISTER]; - - -/* Sometimes certain combinations of command options do not make - sense on a particular target machine. You can define a macro - `OVERRIDE_OPTIONS' to take account of this. This macro, if - defined, is executed once just after all the command options have - been parsed. - - Don't use this macro to turn on various extra optimizations for - `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ - -void -override_options () -{ - int ch, i, regno; - -#ifdef SUBTARGET_OVERRIDE_OPTIONS - SUBTARGET_OVERRIDE_OPTIONS; -#endif - - /* Validate registers in register allocation order */ - if (i386_reg_alloc_order) - { - for (i = 0; (ch = i386_reg_alloc_order[i]) != '\0'; i++) - { - switch (ch) - { - case 'a': regno = 0; break; - case 'd': regno = 1; break; - case 'c': regno = 2; break; - case 'b': regno = 3; break; - case 'S': regno = 4; break; - case 'D': regno = 5; break; - case 'B': regno = 6; break; - - default: fatal ("Register '%c' is unknown", ch); - } - - if (regs_allocated[regno]) - fatal ("Register '%c' was already specified in the allocation order", ch); - - regs_allocated[regno] = 1; - } - } -} - -/* A C statement (sans semicolon) to choose the order in which to - allocate hard registers for pseudo-registers local to a basic - block. - - Store the desired register order in the array `reg_alloc_order'. - Element 0 should be the register to allocate first; element 1, the - next register; and so on. - - The macro body should not assume anything about the contents of - `reg_alloc_order' before execution of the macro. - - On most machines, it is not necessary to define this macro. */ - -void -order_regs_for_local_alloc () -{ - int i, ch, order, regno; - - /* User specified the register allocation order */ - if (i386_reg_alloc_order) - { - for (i = order = 0; (ch = i386_reg_alloc_order[i]) != '\0'; i++) - { - switch (ch) - { - case 'a': regno = 0; break; - case 'd': regno = 1; break; - case 'c': regno = 2; break; - case 'b': regno = 3; break; - case 'S': regno = 4; break; - case 'D': regno = 5; break; - case 'B': regno = 6; break; - } - - reg_alloc_order[order++] = regno; - } - - for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) - { - if (!regs_allocated[i]) - reg_alloc_order[order++] = i; - } - } - - /* If users did not specify a register allocation order, favor eax - normally except if DImode variables are used, in which case - favor edx before eax, which seems to cause less spill register - not found messages. */ - else - { - rtx insn; - - for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) - reg_alloc_order[i] = i; - - if (optimize) - { - int use_dca = FALSE; - - for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) - { - if (GET_CODE (insn) == INSN) - { - rtx set = NULL_RTX; - rtx pattern = PATTERN (insn); - - if (GET_CODE (pattern) == SET) - set = pattern; - - else if ((GET_CODE (pattern) == PARALLEL - || GET_CODE (pattern) == SEQUENCE) - && GET_CODE (XVECEXP (pattern, 0, 0)) == SET) - set = XVECEXP (pattern, 0, 0); - - if (set && GET_MODE (SET_SRC (set)) == DImode) - { - use_dca = TRUE; - break; - } - } - } - - if (use_dca) - { - reg_alloc_order[0] = 1; /* edx */ - reg_alloc_order[1] = 2; /* ecx */ - reg_alloc_order[2] = 0; /* eax */ - } - } - } -} - /* Output an insn whose source is a 386 integer register. SRC is the rtx for the register, and TEMPLATE is the op-code template. SRC may @@ -378,7 +247,6 @@ abort (); } - /* Output an insn to add the constant N to the register X. */ static void @@ -387,25 +255,19 @@ rtx x; { rtx xops[2]; - xops[0] = x; - - if (n == -1) - output_asm_insn (AS1 (dec%L0,%0), xops); - else if (n == 1) - output_asm_insn (AS1 (inc%L0,%0), xops); - else if (n < 0) + xops[1] = x; + if (n < 0) { - xops[1] = GEN_INT (-n); - output_asm_insn (AS2 (sub%L0,%1,%0), xops); + xops[0] = GEN_INT (-n); + output_asm_insn (AS2 (sub%L0,%0,%1), xops); } else if (n > 0) { - xops[1] = GEN_INT (n); - output_asm_insn (AS2 (add%L0,%1,%0), xops); + xops[0] = GEN_INT (n); + output_asm_insn (AS2 (add%L0,%0,%1), xops); } } - /* Output assembler code to perform a doubleword move insn with operands OPERANDS. */ @@ -737,199 +599,6 @@ return ""; } - - -#define MAX_TMPS 2 /* max temporary registers used */ - -/* Output the appropriate code to move push memory on the stack */ - -char * -output_move_pushmem (operands, insn, length, tmp_start, n_operands) - rtx operands[]; - rtx insn; - int length; - int tmp_start; - int n_operands; -{ - - struct { - char *load; - char *push; - rtx xops[2]; - } tmp_info[MAX_TMPS]; - - rtx src = operands[1]; - int max_tmps = 0; - int offset = 0; - int stack_p = reg_overlap_mentioned_p (stack_pointer_rtx, src); - int stack_offset = 0; - int i, num_tmps; - rtx xops[1]; - - if (!offsettable_memref_p (src)) - fatal_insn ("Source is not offsettable", insn); - - if ((length & 3) != 0) - fatal_insn ("Pushing non-word aligned size", insn); - - /* Figure out which temporary registers we have available */ - for (i = tmp_start; i < n_operands; i++) - { - if (GET_CODE (operands[i]) == REG) - { - if (reg_overlap_mentioned_p (operands[i], src)) - continue; - - tmp_info[ max_tmps++ ].xops[1] = operands[i]; - if (max_tmps == MAX_TMPS) - break; - } - } - - if (max_tmps == 0) - for (offset = length - 4; offset >= 0; offset -= 4) - { - xops[0] = adj_offsettable_operand (src, offset + stack_offset); - output_asm_insn (AS1(push%L0,%0), xops); - if (stack_p) - stack_offset += 4; - } - - else - for (offset = length - 4; offset >= 0; ) - { - for (num_tmps = 0; num_tmps < max_tmps && offset >= 0; num_tmps++) - { - tmp_info[num_tmps].load = AS2(mov%L0,%0,%1); - tmp_info[num_tmps].push = AS1(push%L0,%1); - tmp_info[num_tmps].xops[0] = adj_offsettable_operand (src, offset + stack_offset); - offset -= 4; - } - - for (i = 0; i < num_tmps; i++) - output_asm_insn (tmp_info[i].load, tmp_info[i].xops); - - for (i = 0; i < num_tmps; i++) - output_asm_insn (tmp_info[i].push, tmp_info[i].xops); - - if (stack_p) - stack_offset += 4*num_tmps; - } - - return ""; -} - - - -/* Output the appropriate code to move data between two memory locations */ - -char * -output_move_memory (operands, insn, length, tmp_start, n_operands) - rtx operands[]; - rtx insn; - int length; - int tmp_start; - int n_operands; -{ - struct { - char *load; - char *store; - rtx xops[3]; - } tmp_info[MAX_TMPS]; - - rtx dest = operands[0]; - rtx src = operands[1]; - rtx qi_tmp = NULL_RTX; - int max_tmps = 0; - int offset = 0; - int i, num_tmps; - rtx xops[3]; - - if (GET_CODE (dest) == MEM - && GET_CODE (XEXP (dest, 0)) == PRE_INC - && XEXP (XEXP (dest, 0), 0) == stack_pointer_rtx) - return output_move_pushmem (operands, insn, length, tmp_start, n_operands); - - if (!offsettable_memref_p (src)) - fatal_insn ("Source is not offsettable", insn); - - if (!offsettable_memref_p (dest)) - fatal_insn ("Destination is not offsettable", insn); - - /* Figure out which temporary registers we have available */ - for (i = tmp_start; i < n_operands; i++) - { - if (GET_CODE (operands[i]) == REG) - { - if ((length & 1) != 0 && !qi_tmp && QI_REG_P (operands[i])) - qi_tmp = operands[i]; - - if (reg_overlap_mentioned_p (operands[i], dest)) - fatal_insn ("Temporary register overlaps the destination", insn); - - if (reg_overlap_mentioned_p (operands[i], src)) - fatal_insn ("Temporary register overlaps the source", insn); - - tmp_info[ max_tmps++ ].xops[2] = operands[i]; - if (max_tmps == MAX_TMPS) - break; - } - } - - if (max_tmps == 0) - fatal_insn ("No scratch registers were found to do memory->memory moves", insn); - - if ((length & 1) != 0) - { - if (!qi_tmp) - fatal_insn ("No byte register found when moving odd # of bytes.", insn); - } - - while (length > 1) - { - for (num_tmps = 0; num_tmps < max_tmps; num_tmps++) - { - if (length >= 4) - { - tmp_info[num_tmps].load = AS2(mov%L0,%1,%2); - tmp_info[num_tmps].store = AS2(mov%L0,%2,%0); - tmp_info[num_tmps].xops[0] = adj_offsettable_operand (dest, offset); - tmp_info[num_tmps].xops[1] = adj_offsettable_operand (src, offset); - offset += 4; - length -= 4; - } - else if (length >= 2) - { - tmp_info[num_tmps].load = AS2(mov%W0,%1,%2); - tmp_info[num_tmps].store = AS2(mov%W0,%2,%0); - tmp_info[num_tmps].xops[0] = adj_offsettable_operand (dest, offset); - tmp_info[num_tmps].xops[1] = adj_offsettable_operand (src, offset); - offset += 2; - length -= 2; - } - else - break; - } - - for (i = 0; i < num_tmps; i++) - output_asm_insn (tmp_info[i].load, tmp_info[i].xops); - - for (i = 0; i < num_tmps; i++) - output_asm_insn (tmp_info[i].store, tmp_info[i].xops); - } - - if (length == 1) - { - xops[0] = adj_offsettable_operand (dest, offset); - xops[1] = adj_offsettable_operand (src, offset); - xops[2] = qi_tmp; - output_asm_insn (AS2(mov%B0,%1,%2), xops); - output_asm_insn (AS2(mov%B0,%2,%0), xops); - } - - return ""; -} - int standard_80387_constant_p (x) @@ -1084,6 +753,111 @@ return 0; } +/* Return a legitimate reference for ORIG (an address) using the + register REG. If REG is 0, a new pseudo is generated. + + There are three types of references that must be handled: + + 1. Global data references must load the address from the GOT, via + the PIC reg. An insn is emitted to do this load, and the reg is + returned. + + 2. Static data references must compute the address as an offset + from the GOT, whose base is in the PIC reg. An insn is emitted to + compute the address into a reg, and the reg is returned. Static + data objects have SYMBOL_REF_FLAG set to differentiate them from + global data objects. + + 3. Constant pool addresses must be handled special. They are + considered legitimate addresses, but only if not used with regs. + When printed, the output routines know to print the reference with the + PIC reg, even though the PIC reg doesn't appear in the RTL. + + GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC + reg also appears in the address (except for constant pool references, + noted above). + + "switch" statements also require special handling when generating + PIC code. See comments by the `casesi' insn in i386.md for details. */ + +rtx +legitimize_pic_address (orig, reg) + rtx orig; + rtx reg; +{ + rtx addr = orig; + rtx new = orig; + + if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF) + { + if (GET_CODE (addr) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (addr)) + reg = new = orig; + else + { + if (reg == 0) + reg = gen_reg_rtx (Pmode); + + if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_FLAG (addr)) + new = gen_rtx (PLUS, Pmode, pic_offset_table_rtx, orig); + else + new = gen_rtx (MEM, Pmode, + gen_rtx (PLUS, Pmode, + pic_offset_table_rtx, orig)); + + emit_move_insn (reg, new); + } + current_function_uses_pic_offset_table = 1; + return reg; + } + else if (GET_CODE (addr) == CONST || GET_CODE (addr) == PLUS) + { + rtx base; + + if (GET_CODE (addr) == CONST) + { + addr = XEXP (addr, 0); + if (GET_CODE (addr) != PLUS) + abort (); + } + + if (XEXP (addr, 0) == pic_offset_table_rtx) + return orig; + + if (reg == 0) + reg = gen_reg_rtx (Pmode); + + base = legitimize_pic_address (XEXP (addr, 0), reg); + addr = legitimize_pic_address (XEXP (addr, 1), + base == reg ? NULL_RTX : reg); + + if (GET_CODE (addr) == CONST_INT) + return plus_constant (base, INTVAL (addr)); + + if (GET_CODE (addr) == PLUS && CONSTANT_P (XEXP (addr, 1))) + { + base = gen_rtx (PLUS, Pmode, base, XEXP (addr, 0)); + addr = XEXP (addr, 1); + } + return gen_rtx (PLUS, Pmode, base, addr); + } + return new; +} + +/* Emit insns to move operands[1] into operands[0]. */ + +void +emit_pic_move (operands, mode) + rtx *operands; + enum machine_mode mode; +{ + rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode); + + if (GET_CODE (operands[0]) == MEM && SYMBOLIC_CONST (operands[1])) + operands[1] = (rtx) force_reg (SImode, operands[1]); + else + operands[1] = legitimize_pic_address (operands[1], temp); +} + /* This function generates the assembly code for function entry. FILE is an stdio stream to output the code to. SIZE is an int: how many units of temporary storage to allocate. */ @@ -1177,7 +951,6 @@ return nregs == 0 || ! frame_pointer_needed; } - /* This function generates the assembly code for function exit. FILE is an stdio stream to output the code to. SIZE is an int: how many units of temporary storage to deallocate. */ @@ -1251,7 +1024,7 @@ { /* On i486, mov & pop is faster than "leave". */ - if (!TARGET_386) + if (TARGET_486) { xops[0] = frame_pointer_rtx; output_asm_insn (AS2 (mov%L2,%0,%2), xops); @@ -1290,1572 +1063,2060 @@ else output_asm_insn ("ret", xops); } - -/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression - that is a valid memory address for an instruction. - The MODE argument is the machine mode for the MEM expression - that wants to use this address. - - On x86, legitimate addresses are: - base movl (base),reg - displacement movl disp,reg - base + displacement movl disp(base),reg - index + base movl (base,index),reg - (index + base) + displacement movl disp(base,index),reg - index*scale movl (,index,scale),reg - index*scale + disp movl disp(,index,scale),reg - index*scale + base movl (base,index,scale),reg - (index*scale + base) + disp movl disp(base,index,scale),reg - - In each case, scale can be 1, 2, 4, 8. */ - -/* This is exactly the same as print_operand_addr, except that - it recognizes addresses instead of printing them. - - It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should - convert common non-canonical forms to canonical form so that they will - be recognized. */ - -#define ADDR_INVALID(msg,insn) \ -do { \ - if (TARGET_DEBUG_ADDR) \ - { \ - fprintf (stderr, msg); \ - debug_rtx (insn); \ - } \ -} while (0) +/* Print an integer constant expression in assembler syntax. Addition + and subtraction are the only arithmetic that may appear in these + expressions. FILE is the stdio stream to write to, X is the rtx, and + CODE is the operand print code from the output string. */ -int -legitimate_address_p (mode, addr, strict) - enum machine_mode mode; - register rtx addr; - int strict; +static void +output_pic_addr_const (file, x, code) + FILE *file; + rtx x; + int code; { - rtx base = NULL_RTX; - rtx indx = NULL_RTX; - rtx scale = NULL_RTX; - rtx disp = NULL_RTX; - - if (TARGET_DEBUG_ADDR) - { - fprintf (stderr, - "\n==========\nGO_IF_LEGITIMATE_ADDRESS, mode = %s, strict = %d\n", - GET_MODE_NAME (mode), strict); - - debug_rtx (addr); - } - - if (GET_CODE (addr) == REG || GET_CODE (addr) == SUBREG) - base = addr; /* base reg */ + char buf[256]; - else if (GET_CODE (addr) == PLUS) + switch (GET_CODE (x)) { - rtx op0 = XEXP (addr, 0); - rtx op1 = XEXP (addr, 1); - enum rtx_code code0 = GET_CODE (op0); - enum rtx_code code1 = GET_CODE (op1); + case PC: + if (flag_pic) + putc ('.', file); + else + abort (); + break; - if (code0 == REG || code0 == SUBREG) + case SYMBOL_REF: + case LABEL_REF: + if (GET_CODE (x) == SYMBOL_REF) + assemble_name (file, XSTR (x, 0)); + else { - if (code1 == REG || code1 == SUBREG) - { - indx = op0; /* index + base */ - base = op1; - } - - else - { - base = op0; /* base + displacement */ - disp = op1; - } + ASM_GENERATE_INTERNAL_LABEL (buf, "L", + CODE_LABEL_NUMBER (XEXP (x, 0))); + assemble_name (asm_out_file, buf); } - else if (code0 == MULT) - { - indx = XEXP (op0, 0); - scale = XEXP (op0, 1); + if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x)) + fprintf (file, "@GOTOFF(%%ebx)"); + else if (code == 'P') + fprintf (file, "@PLT"); + else if (GET_CODE (x) == LABEL_REF || ! SYMBOL_REF_FLAG (x)) + fprintf (file, "@GOT"); + else + fprintf (file, "@GOTOFF"); - if (code1 == REG || code1 == SUBREG) - base = op1; /* index*scale + base */ + break; - else - disp = op1; /* index*scale + disp */ - } + case CODE_LABEL: + ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x)); + assemble_name (asm_out_file, buf); + break; - else if (code0 == PLUS && GET_CODE (XEXP (op0, 0)) == MULT) - { - indx = XEXP (XEXP (op0, 0), 0); /* index*scale + base + disp */ - scale = XEXP (XEXP (op0, 0), 1); - base = XEXP (op0, 1); - disp = op1; - } + case CONST_INT: + fprintf (file, "%d", INTVAL (x)); + break; - else if (code0 == PLUS) - { - indx = XEXP (op0, 0); /* index + base + disp */ - base = XEXP (op0, 1); - disp = op1; - } + case CONST: + /* This used to output parentheses around the expression, + but that does not work on the 386 (either ATT or BSD assembler). */ + output_pic_addr_const (file, XEXP (x, 0), code); + break; - else + case CONST_DOUBLE: + if (GET_MODE (x) == VOIDmode) { - ADDR_INVALID ("PLUS subcode is not valid.\n", op0); - return FALSE; + /* We can use %d if the number is <32 bits and positive. */ + if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0) + fprintf (file, "0x%x%08x", + CONST_DOUBLE_HIGH (x), CONST_DOUBLE_LOW (x)); + else + fprintf (file, "%d", CONST_DOUBLE_LOW (x)); } - } - - else if (GET_CODE (addr) == MULT) - { - indx = XEXP (addr, 0); /* index*scale */ - scale = XEXP (addr, 1); - } - - else - disp = addr; /* displacement */ - - /* Allow arg pointer and stack pointer as index if there is not scaling */ - if (base && indx && !scale - && (indx == arg_pointer_rtx || indx == stack_pointer_rtx)) - { - rtx tmp = base; - base = indx; - indx = tmp; - } + else + /* We can't handle floating point constants; + PRINT_OPERAND must handle them. */ + output_operand_lossage ("floating constant misused"); + break; - /* Validate base register */ - /* Don't allow SUBREG's here, it can lead to spill failures when the base - is one word out of a two word structure, which is represented internally - as a DImode int. */ - if (base) - { - if (GET_CODE (base) != REG) + case PLUS: + /* Some assemblers need integer constants to appear last (eg masm). */ + if (GET_CODE (XEXP (x, 0)) == CONST_INT) { - ADDR_INVALID ("Base is not a register.\n", base); - return FALSE; + output_pic_addr_const (file, XEXP (x, 1), code); + if (INTVAL (XEXP (x, 0)) >= 0) + fprintf (file, "+"); + output_pic_addr_const (file, XEXP (x, 0), code); } - - if ((strict && !REG_OK_FOR_BASE_STRICT_P (base)) - || (!strict && !REG_OK_FOR_BASE_NONSTRICT_P (base))) + else { - ADDR_INVALID ("Base is not valid.\n", base); - return FALSE; + output_pic_addr_const (file, XEXP (x, 0), code); + if (INTVAL (XEXP (x, 1)) >= 0) + fprintf (file, "+"); + output_pic_addr_const (file, XEXP (x, 1), code); } - } + break; - /* Validate index register */ - /* Don't allow SUBREG's here, it can lead to spill failures when the index - is one word out of a two word structure, which is represented internally - as a DImode int. */ - if (indx) - { - if (GET_CODE (indx) != REG) - { - ADDR_INVALID ("Index is not a register.\n", indx); - return FALSE; - } + case MINUS: + output_pic_addr_const (file, XEXP (x, 0), code); + fprintf (file, "-"); + output_pic_addr_const (file, XEXP (x, 1), code); + break; - if ((strict && !REG_OK_FOR_INDEX_STRICT_P (indx)) - || (!strict && !REG_OK_FOR_INDEX_NONSTRICT_P (indx))) - { - ADDR_INVALID ("Index is not valid.\n", indx); - return FALSE; - } + default: + output_operand_lossage ("invalid expression as operand"); } - else if (scale) - abort (); /* scale w/o index illegal */ +} + +/* Meaning of CODE: + f -- float insn (print a CONST_DOUBLE as a float rather than in hex). + D,L,W,B,Q,S -- print the opcode suffix for specified size of operand. + R -- print the prefix for register names. + z -- print the opcode suffix for the size of the current operand. + * -- print a star (in certain assembler syntax) + w -- print the operand as if it's a "word" (HImode) even if it isn't. + c -- don't print special prefixes before constant operands. +*/ - /* Validate scale factor */ - if (scale) +void +print_operand (file, x, code) + FILE *file; + rtx x; + int code; +{ + if (code) { - HOST_WIDE_INT value; - - if (GET_CODE (scale) != CONST_INT) + switch (code) { - ADDR_INVALID ("Scale is not valid.\n", scale); - return FALSE; - } + case '*': + if (USE_STAR) + putc ('*', file); + return; - value = INTVAL (scale); - if (value != 1 && value != 2 && value != 4 && value != 8) - { - ADDR_INVALID ("Scale is not a good multiplier.\n", scale); - return FALSE; - } - } + case 'L': + PUT_OP_SIZE (code, 'l', file); + return; - /* Validate displacement */ - if (disp) - { - if (!CONSTANT_ADDRESS_P (disp)) - { - ADDR_INVALID ("Displacement is not valid.\n", disp); - return FALSE; - } + case 'W': + PUT_OP_SIZE (code, 'w', file); + return; - if (GET_CODE (disp) == CONST_DOUBLE) - { - ADDR_INVALID ("Displacement is a const_double.\n", disp); - return FALSE; - } + case 'B': + PUT_OP_SIZE (code, 'b', file); + return; - if (flag_pic && SYMBOLIC_CONST (disp) && base != pic_offset_table_rtx - && (indx != pic_offset_table_rtx || scale != NULL_RTX)) - { - ADDR_INVALID ("Displacement is an invalid pic reference.\n", disp); - return FALSE; - } + case 'Q': + PUT_OP_SIZE (code, 'l', file); + return; - if (HALF_PIC_P () && HALF_PIC_ADDRESS_P (disp) - && (base != NULL_RTX || indx != NULL_RTX)) - { - ADDR_INVALID ("Displacement is an invalid half-pic reference.\n", disp); - return FALSE; - } - } + case 'S': + PUT_OP_SIZE (code, 's', file); + return; - if (TARGET_DEBUG_ADDR) - fprintf (stderr, "Address is valid.\n"); + case 'T': + PUT_OP_SIZE (code, 't', file); + return; - /* Everything looks valid, return true */ - return TRUE; -} + case 'z': + /* 387 opcodes don't get size suffixes if the operands are + registers. */ - -/* Return a legitimate reference for ORIG (an address) using the - register REG. If REG is 0, a new pseudo is generated. + if (STACK_REG_P (x)) + return; - There are three types of references that must be handled: + /* this is the size of op from size of operand */ + switch (GET_MODE_SIZE (GET_MODE (x))) + { + case 1: + PUT_OP_SIZE ('B', 'b', file); + return; - 1. Global data references must load the address from the GOT, via - the PIC reg. An insn is emitted to do this load, and the reg is - returned. + case 2: + PUT_OP_SIZE ('W', 'w', file); + return; - 2. Static data references must compute the address as an offset - from the GOT, whose base is in the PIC reg. An insn is emitted to - compute the address into a reg, and the reg is returned. Static - data objects have SYMBOL_REF_FLAG set to differentiate them from - global data objects. + case 4: + if (GET_MODE (x) == SFmode) + { + PUT_OP_SIZE ('S', 's', file); + return; + } + else + PUT_OP_SIZE ('L', 'l', file); + return; - 3. Constant pool addresses must be handled special. They are - considered legitimate addresses, but only if not used with regs. - When printed, the output routines know to print the reference with the - PIC reg, even though the PIC reg doesn't appear in the RTL. + case 12: + PUT_OP_SIZE ('T', 't', file); + return; - GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC - reg also appears in the address (except for constant pool references, - noted above). + case 8: + if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT) + { +#ifdef GAS_MNEMONICS + PUT_OP_SIZE ('Q', 'q', file); + return; +#else + PUT_OP_SIZE ('Q', 'l', file); /* Fall through */ +#endif + } - "switch" statements also require special handling when generating - PIC code. See comments by the `casesi' insn in i386.md for details. */ + PUT_OP_SIZE ('Q', 'l', file); + return; + } -rtx -legitimize_pic_address (orig, reg) - rtx orig; - rtx reg; -{ - rtx addr = orig; - rtx new = orig; + case 'b': + case 'w': + case 'k': + case 'h': + case 'y': + case 'P': + break; - if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF) - { - if (GET_CODE (addr) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (addr)) - reg = new = orig; - else - { - if (reg == 0) - reg = gen_reg_rtx (Pmode); + default: + { + char str[50]; - if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_FLAG (addr)) - || GET_CODE (addr) == LABEL_REF) - new = gen_rtx (PLUS, Pmode, pic_offset_table_rtx, orig); - else - new = gen_rtx (MEM, Pmode, - gen_rtx (PLUS, Pmode, - pic_offset_table_rtx, orig)); - - emit_move_insn (reg, new); + sprintf (str, "invalid operand code `%c'", code); + output_operand_lossage (str); + } } - current_function_uses_pic_offset_table = 1; - return reg; } - else if (GET_CODE (addr) == CONST || GET_CODE (addr) == PLUS) + if (GET_CODE (x) == REG) { - rtx base; - - if (GET_CODE (addr) == CONST) + PRINT_REG (x, code, file); + } + else if (GET_CODE (x) == MEM) + { + PRINT_PTR (x, file); + if (CONSTANT_ADDRESS_P (XEXP (x, 0))) { - addr = XEXP (addr, 0); - if (GET_CODE (addr) != PLUS) - abort (); + if (flag_pic) + output_pic_addr_const (file, XEXP (x, 0), code); + else + output_addr_const (file, XEXP (x, 0)); } - - if (XEXP (addr, 0) == pic_offset_table_rtx) - return orig; - - if (reg == 0) - reg = gen_reg_rtx (Pmode); - - base = legitimize_pic_address (XEXP (addr, 0), reg); - addr = legitimize_pic_address (XEXP (addr, 1), - base == reg ? NULL_RTX : reg); - - if (GET_CODE (addr) == CONST_INT) - return plus_constant (base, INTVAL (addr)); - - if (GET_CODE (addr) == PLUS && CONSTANT_P (XEXP (addr, 1))) + else + output_address (XEXP (x, 0)); + } + else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) + { + REAL_VALUE_TYPE r; long l; + REAL_VALUE_FROM_CONST_DOUBLE (r, x); + REAL_VALUE_TO_TARGET_SINGLE (r, l); + PRINT_IMMED_PREFIX (file); + fprintf (file, "0x%x", l); + } + /* These float cases don't actually occur as immediate operands. */ + else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) + { + REAL_VALUE_TYPE r; char dstr[30]; + REAL_VALUE_FROM_CONST_DOUBLE (r, x); + REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr); + fprintf (file, "%s", dstr); + } + else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == XFmode) + { + REAL_VALUE_TYPE r; char dstr[30]; + REAL_VALUE_FROM_CONST_DOUBLE (r, x); + REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr); + fprintf (file, "%s", dstr); + } + else + { + if (code != 'P') { - base = gen_rtx (PLUS, Pmode, base, XEXP (addr, 0)); - addr = XEXP (addr, 1); + if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) + PRINT_IMMED_PREFIX (file); + else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF + || GET_CODE (x) == LABEL_REF) + PRINT_OFFSET_PREFIX (file); } - return gen_rtx (PLUS, Pmode, base, addr); + if (flag_pic) + output_pic_addr_const (file, x, code); + else + output_addr_const (file, x); } - return new; } - -/* Emit insns to move operands[1] into operands[0]. */ +/* Print a memory operand whose address is ADDR. */ void -emit_pic_move (operands, mode) - rtx *operands; - enum machine_mode mode; -{ - rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode); - - if (GET_CODE (operands[0]) == MEM && SYMBOLIC_CONST (operands[1])) - operands[1] = (rtx) force_reg (SImode, operands[1]); - else - operands[1] = legitimize_pic_address (operands[1], temp); -} - - -/* Try machine-dependent ways of modifying an illegitimate address - to be legitimate. If we find one, return the new, valid address. - This macro is used in only one place: `memory_address' in explow.c. - - OLDX is the address as it was before break_out_memory_refs was called. - In some cases it is useful to look at this to decide what needs to be done. - - MODE and WIN are passed so that this macro can use - GO_IF_LEGITIMATE_ADDRESS. - - It is always safe for this macro to do nothing. It exists to recognize - opportunities to optimize the output. - - For the 80386, we handle X+REG by loading X into a register R and - using R+REG. R will go in a general reg and indexing will be used. - However, if REG is a broken-out memory address or multiplication, - nothing needs to be done because REG can certainly go in a general reg. - - When -fpic is used, special handling is needed for symbolic references. - See comments by legitimize_pic_address in i386.c for details. */ - -rtx -legitimize_address (x, oldx, mode) - register rtx x; - register rtx oldx; - enum machine_mode mode; +print_operand_address (file, addr) + FILE *file; + register rtx addr; { - int changed = 0; - unsigned log; - - if (TARGET_DEBUG_ADDR) - { - fprintf (stderr, "\n==========\nLEGITIMIZE_ADDRESS, mode = %s\n", GET_MODE_NAME (mode)); - debug_rtx (x); - } - - if (flag_pic && SYMBOLIC_CONST (x)) - return legitimize_pic_address (x, 0); + register rtx reg1, reg2, breg, ireg; + rtx offset; - /* Canonicalize shifts by 0, 1, 2, 3 into multiply */ - if (GET_CODE (x) == ASHIFT - && GET_CODE (XEXP (x, 1)) == CONST_INT - && (log = (unsigned)exact_log2 (INTVAL (XEXP (x, 1)))) < 4) + switch (GET_CODE (addr)) { - changed = 1; - x = gen_rtx (MULT, Pmode, - force_reg (Pmode, XEXP (x, 0)), - GEN_INT (1 << log)); - } + case REG: + ADDR_BEG (file); + fprintf (file, "%se", RP); + fputs (hi_reg_name[REGNO (addr)], file); + ADDR_END (file); + break; - if (GET_CODE (x) == PLUS) - { - /* Canonicalize shifts by 0, 1, 2, 3 into multiply */ - if (GET_CODE (XEXP (x, 0)) == ASHIFT - && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT - && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) < 4) + case PLUS: + reg1 = 0; + reg2 = 0; + ireg = 0; + breg = 0; + offset = 0; + if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) { - changed = 1; - XEXP (x, 0) = gen_rtx (MULT, Pmode, - force_reg (Pmode, XEXP (XEXP (x, 0), 0)), - GEN_INT (1 << log)); + offset = XEXP (addr, 0); + addr = XEXP (addr, 1); } - - if (GET_CODE (XEXP (x, 1)) == ASHIFT - && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT - && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1)))) < 4) + else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) { - changed = 1; - XEXP (x, 1) = gen_rtx (MULT, Pmode, - force_reg (Pmode, XEXP (XEXP (x, 1), 0)), - GEN_INT (1 << log)); + offset = XEXP (addr, 1); + addr = XEXP (addr, 0); } - - /* Put multiply first if it isn't already */ - if (GET_CODE (XEXP (x, 1)) == MULT) + if (GET_CODE (addr) != PLUS) ; + else if (GET_CODE (XEXP (addr, 0)) == MULT) { - rtx tmp = XEXP (x, 0); - XEXP (x, 0) = XEXP (x, 1); - XEXP (x, 1) = tmp; - changed = 1; + reg1 = XEXP (addr, 0); + addr = XEXP (addr, 1); } - - /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const))) - into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be - created by virtual register instantiation, register elimination, and - similar optimizations. */ - if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS) + else if (GET_CODE (XEXP (addr, 1)) == MULT) + { + reg1 = XEXP (addr, 1); + addr = XEXP (addr, 0); + } + else if (GET_CODE (XEXP (addr, 0)) == REG) + { + reg1 = XEXP (addr, 0); + addr = XEXP (addr, 1); + } + else if (GET_CODE (XEXP (addr, 1)) == REG) + { + reg1 = XEXP (addr, 1); + addr = XEXP (addr, 0); + } + if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT) + { + if (reg1 == 0) reg1 = addr; + else reg2 = addr; + addr = 0; + } + if (offset != 0) + { + if (addr != 0) abort (); + addr = offset; + } + if ((reg1 && GET_CODE (reg1) == MULT) + || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) + { + breg = reg2; + ireg = reg1; + } + else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) { - changed = 1; - x = gen_rtx (PLUS, Pmode, - gen_rtx (PLUS, Pmode, XEXP (x, 0), XEXP (XEXP (x, 1), 0)), - XEXP (XEXP (x, 1), 1)); + breg = reg1; + ireg = reg2; } - /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const) - into (plus (plus (mult (reg) (const)) (reg)) (const)). */ - else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS - && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT - && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS - && CONSTANT_P (XEXP (x, 1))) + if (ireg != 0 || breg != 0) { - rtx constant, other; + int scale = 1; - if (GET_CODE (XEXP (x, 1)) == CONST_INT) - { - constant = XEXP (x, 1); - other = XEXP (XEXP (XEXP (x, 0), 1), 1); - } - else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT) + if (addr != 0) { - constant = XEXP (XEXP (XEXP (x, 0), 1), 1); - other = XEXP (x, 1); + if (GET_CODE (addr) == LABEL_REF) + output_asm_label (addr); + else + { + if (flag_pic) + output_pic_addr_const (file, addr, 0); + else + output_addr_const (file, addr); + } } - else - constant = 0; - if (constant) + if (ireg != 0 && GET_CODE (ireg) == MULT) { - changed = 1; - x = gen_rtx (PLUS, Pmode, - gen_rtx (PLUS, Pmode, XEXP (XEXP (x, 0), 0), - XEXP (XEXP (XEXP (x, 0), 1), 0)), - plus_constant (other, INTVAL (constant))); + scale = INTVAL (XEXP (ireg, 1)); + ireg = XEXP (ireg, 0); } - } - if (changed && legitimate_address_p (mode, x, FALSE)) - return x; - - if (GET_CODE (XEXP (x, 0)) == MULT) - { - changed = 1; - XEXP (x, 0) = force_operand (XEXP (x, 0), 0); - } + /* The stack pointer can only appear as a base register, + never an index register, so exchange the regs if it is wrong. */ - if (GET_CODE (XEXP (x, 1)) == MULT) - { - changed = 1; - XEXP (x, 1) = force_operand (XEXP (x, 1), 0); - } + if (scale == 1 && ireg && REGNO (ireg) == STACK_POINTER_REGNUM) + { + rtx tmp; - if (changed - && GET_CODE (XEXP (x, 1)) == REG - && GET_CODE (XEXP (x, 0)) == REG) - return x; + tmp = breg; + breg = ireg; + ireg = tmp; + } - if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1))) - { - changed = 1; - x = legitimize_pic_address (x, 0); + /* output breg+ireg*scale */ + PRINT_B_I_S (breg, ireg, scale, file); + break; } - if (changed && legitimate_address_p (mode, x, FALSE)) - return x; - - if (GET_CODE (XEXP (x, 0)) == REG) - { - register rtx temp = gen_reg_rtx (Pmode); - register rtx val = force_operand (XEXP (x, 1), temp); - if (val != temp) - emit_move_insn (temp, val); - - XEXP (x, 1) = temp; - return x; - } + case MULT: + { + int scale; + if (GET_CODE (XEXP (addr, 0)) == CONST_INT) + { + scale = INTVAL (XEXP (addr, 0)); + ireg = XEXP (addr, 1); + } + else + { + scale = INTVAL (XEXP (addr, 1)); + ireg = XEXP (addr, 0); + } + output_addr_const (file, const0_rtx); + PRINT_B_I_S ((rtx) 0, ireg, scale, file); + } + break; - else if (GET_CODE (XEXP (x, 1)) == REG) + default: + if (GET_CODE (addr) == CONST_INT + && INTVAL (addr) < 0x8000 + && INTVAL (addr) >= -0x8000) + fprintf (file, "%d", INTVAL (addr)); + else { - register rtx temp = gen_reg_rtx (Pmode); - register rtx val = force_operand (XEXP (x, 0), temp); - if (val != temp) - emit_move_insn (temp, val); - - XEXP (x, 0) = temp; - return x; + if (flag_pic) + output_pic_addr_const (file, addr, 0); + else + output_addr_const (file, addr); } } - - return x; } - -/* Print an integer constant expression in assembler syntax. Addition - and subtraction are the only arithmetic that may appear in these - expressions. FILE is the stdio stream to write to, X is the rtx, and - CODE is the operand print code from the output string. */ +/* Set the cc_status for the results of an insn whose pattern is EXP. + On the 80386, we assume that only test and compare insns, as well + as SI, HI, & DI mode ADD, SUB, NEG, AND, IOR, XOR, ASHIFT, LSHIFT, + ASHIFTRT, and LSHIFTRT instructions set the condition codes usefully. + Also, we assume that jumps, moves and sCOND don't affect the condition + codes. All else clobbers the condition codes, by assumption. -static void -output_pic_addr_const (file, x, code) - FILE *file; - rtx x; - int code; -{ - char buf[256]; + We assume that ALL integer add, minus, etc. instructions effect the + condition codes. This MUST be consistent with i386.md. - switch (GET_CODE (x)) - { - case PC: - if (flag_pic) - putc ('.', file); - else - abort (); - break; + We don't record any float test or compare - the redundant test & + compare check in final.c does not handle stack-like regs correctly. */ - case SYMBOL_REF: - case LABEL_REF: - if (GET_CODE (x) == SYMBOL_REF) - assemble_name (file, XSTR (x, 0)); - else +void +notice_update_cc (exp) + rtx exp; +{ + if (GET_CODE (exp) == SET) + { + /* Jumps do not alter the cc's. */ + if (SET_DEST (exp) == pc_rtx) + return; +#ifdef IS_STACK_MODE + /* intel1 + Moving into a memory of stack_mode may have been moved + in between the use and set of cc0 by loop_spl(). So + old value of cc.status must be retained */ + if(GET_CODE(SET_DEST(exp))==MEM + && IS_STACK_MODE(GET_MODE(SET_DEST(exp)))) + { + return; + } +#endif + /* Moving register or memory into a register: + it doesn't alter the cc's, but it might invalidate + the RTX's which we remember the cc's came from. + (Note that moving a constant 0 or 1 MAY set the cc's). */ + if (REG_P (SET_DEST (exp)) + && (REG_P (SET_SRC (exp)) || GET_CODE (SET_SRC (exp)) == MEM + || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<')) { - ASM_GENERATE_INTERNAL_LABEL (buf, "L", - CODE_LABEL_NUMBER (XEXP (x, 0))); - assemble_name (asm_out_file, buf); + if (cc_status.value1 + && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1)) + cc_status.value1 = 0; + if (cc_status.value2 + && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2)) + cc_status.value2 = 0; + return; } - - if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x)) - fprintf (file, "@GOTOFF(%%ebx)"); - else if (code == 'P') - fprintf (file, "@PLT"); - else if (GET_CODE (x) == LABEL_REF) - fprintf (file, "@GOTOFF"); - else if (! SYMBOL_REF_FLAG (x)) - fprintf (file, "@GOT"); - else - fprintf (file, "@GOTOFF"); - - break; - - case CODE_LABEL: - ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x)); - assemble_name (asm_out_file, buf); - break; - - case CONST_INT: - fprintf (file, "%d", INTVAL (x)); - break; - - case CONST: - /* This used to output parentheses around the expression, - but that does not work on the 386 (either ATT or BSD assembler). */ - output_pic_addr_const (file, XEXP (x, 0), code); - break; - - case CONST_DOUBLE: - if (GET_MODE (x) == VOIDmode) + /* Moving register into memory doesn't alter the cc's. + It may invalidate the RTX's which we remember the cc's came from. */ + if (GET_CODE (SET_DEST (exp)) == MEM + && (REG_P (SET_SRC (exp)) + || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<')) { - /* We can use %d if the number is <32 bits and positive. */ - if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0) - fprintf (file, "0x%x%08x", - CONST_DOUBLE_HIGH (x), CONST_DOUBLE_LOW (x)); - else - fprintf (file, "%d", CONST_DOUBLE_LOW (x)); + if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM) + cc_status.value1 = 0; + if (cc_status.value2 && GET_CODE (cc_status.value2) == MEM) + cc_status.value2 = 0; + return; } - else - /* We can't handle floating point constants; - PRINT_OPERAND must handle them. */ - output_operand_lossage ("floating constant misused"); - break; - - case PLUS: - /* Some assemblers need integer constants to appear last (eg masm). */ - if (GET_CODE (XEXP (x, 0)) == CONST_INT) + /* Function calls clobber the cc's. */ + else if (GET_CODE (SET_SRC (exp)) == CALL) { - output_pic_addr_const (file, XEXP (x, 1), code); - if (INTVAL (XEXP (x, 0)) >= 0) - fprintf (file, "+"); - output_pic_addr_const (file, XEXP (x, 0), code); + CC_STATUS_INIT; + return; } - else + /* Tests and compares set the cc's in predictable ways. */ + else if (SET_DEST (exp) == cc0_rtx) { - output_pic_addr_const (file, XEXP (x, 0), code); - if (INTVAL (XEXP (x, 1)) >= 0) - fprintf (file, "+"); - output_pic_addr_const (file, XEXP (x, 1), code); + CC_STATUS_INIT; + cc_status.value1 = SET_SRC (exp); + return; } - break; + /* Certain instructions effect the condition codes. */ + else if (GET_MODE (SET_SRC (exp)) == SImode + || GET_MODE (SET_SRC (exp)) == HImode + || GET_MODE (SET_SRC (exp)) == QImode) + switch (GET_CODE (SET_SRC (exp))) + { + case ASHIFTRT: case LSHIFTRT: + case ASHIFT: case LSHIFT: + /* Shifts on the 386 don't set the condition codes if the + shift count is zero. */ + if (GET_CODE (XEXP (SET_SRC (exp), 1)) != CONST_INT) + { + CC_STATUS_INIT; + break; + } + /* We assume that the CONST_INT is non-zero (this rtx would + have been deleted if it were zero. */ - case MINUS: - output_pic_addr_const (file, XEXP (x, 0), code); - fprintf (file, "-"); - output_pic_addr_const (file, XEXP (x, 1), code); - break; + case PLUS: case MINUS: case NEG: + case AND: case IOR: case XOR: + cc_status.flags = CC_NO_OVERFLOW; + cc_status.value1 = SET_SRC (exp); + cc_status.value2 = SET_DEST (exp); + break; - default: - output_operand_lossage ("invalid expression as operand"); + default: + CC_STATUS_INIT; + } + else + { + CC_STATUS_INIT; + } + } + else if (GET_CODE (exp) == PARALLEL + && GET_CODE (XVECEXP (exp, 0, 0)) == SET) + { + if (SET_DEST (XVECEXP (exp, 0, 0)) == pc_rtx) + return; + if (SET_DEST (XVECEXP (exp, 0, 0)) == cc0_rtx) + { + CC_STATUS_INIT; + if (stack_regs_mentioned_p (SET_SRC (XVECEXP (exp, 0, 0)))) + cc_status.flags |= CC_IN_80387; + else + cc_status.value1 = SET_SRC (XVECEXP (exp, 0, 0)); + return; + } + CC_STATUS_INIT; + } + else + { + CC_STATUS_INIT; } } -/* Meaning of CODE: - f -- float insn (print a CONST_DOUBLE as a float rather than in hex). - D,L,W,B,Q,S -- print the opcode suffix for specified size of operand. - R -- print the prefix for register names. - z -- print the opcode suffix for the size of the current operand. - * -- print a star (in certain assembler syntax) - w -- print the operand as if it's a "word" (HImode) even if it isn't. - c -- don't print special prefixes before constant operands. -*/ +/* Split one or more DImode RTL references into pairs of SImode + references. The RTL can be REG, offsettable MEM, integer constant, or + CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to + split and "num" is its length. lo_half and hi_half are output arrays + that parallel "operands". */ void -print_operand (file, x, code) - FILE *file; - rtx x; - int code; +split_di (operands, num, lo_half, hi_half) + rtx operands[]; + int num; + rtx lo_half[], hi_half[]; { - if (code) + while (num--) { - switch (code) + if (GET_CODE (operands[num]) == REG) { - case '*': - if (USE_STAR) - putc ('*', file); - return; + lo_half[num] = gen_rtx (REG, SImode, REGNO (operands[num])); + hi_half[num] = gen_rtx (REG, SImode, REGNO (operands[num]) + 1); + } + else if (CONSTANT_P (operands[num])) + { + split_double (operands[num], &lo_half[num], &hi_half[num]); + } + else if (offsettable_memref_p (operands[num])) + { + lo_half[num] = operands[num]; + hi_half[num] = adj_offsettable_operand (operands[num], 4); + } + else + abort(); + } +} + +/* Return 1 if this is a valid binary operation on a 387. + OP is the expression matched, and MODE is its mode. */ - case 'L': - PUT_OP_SIZE (code, 'l', file); - return; +int +binary_387_op (op, mode) + register rtx op; + enum machine_mode mode; +{ + if (mode != VOIDmode && mode != GET_MODE (op)) + return 0; - case 'W': - PUT_OP_SIZE (code, 'w', file); - return; + switch (GET_CODE (op)) + { + case PLUS: + case MINUS: + case MULT: + case DIV: + return GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT; - case 'B': - PUT_OP_SIZE (code, 'b', file); - return; + default: + return 0; + } +} - case 'Q': - PUT_OP_SIZE (code, 'l', file); - return; +/* Return 1 if this is a valid conversion operation on a 387. + OP is the expression matched, and MODE is its mode. */ - case 'S': - PUT_OP_SIZE (code, 's', file); - return; +int +convert_387_op (op, mode) + register rtx op; + enum machine_mode mode; +{ + if (mode != VOIDmode && mode != GET_MODE (op)) + return 0; - case 'T': - PUT_OP_SIZE (code, 't', file); - return; + switch (GET_CODE (op)) + { + case FLOAT: + return GET_MODE (XEXP (op, 0)) == SImode; - case 'z': - /* 387 opcodes don't get size suffixes if the operands are - registers. */ + case FLOAT_EXTEND: + return ((mode == DFmode && GET_MODE (XEXP (op, 0)) == SFmode) + || (mode == XFmode && GET_MODE (XEXP (op, 0)) == DFmode) + || (mode == XFmode && GET_MODE (XEXP (op, 0)) == SFmode)); - if (STACK_REG_P (x)) - return; + default: + return 0; + } +} - /* this is the size of op from size of operand */ - switch (GET_MODE_SIZE (GET_MODE (x))) - { - case 1: - PUT_OP_SIZE ('B', 'b', file); - return; +/* Return 1 if this is a valid shift or rotate operation on a 386. + OP is the expression matched, and MODE is its mode. */ - case 2: - PUT_OP_SIZE ('W', 'w', file); - return; +int +shift_op (op, mode) + register rtx op; + enum machine_mode mode; +{ + rtx operand = XEXP (op, 0); - case 4: - if (GET_MODE (x) == SFmode) - { - PUT_OP_SIZE ('S', 's', file); - return; - } - else - PUT_OP_SIZE ('L', 'l', file); - return; + if (mode != VOIDmode && mode != GET_MODE (op)) + return 0; - case 12: - PUT_OP_SIZE ('T', 't', file); - return; + if (GET_MODE (operand) != GET_MODE (op) + || GET_MODE_CLASS (GET_MODE (op)) != MODE_INT) + return 0; - case 8: - if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT) - { -#ifdef GAS_MNEMONICS - PUT_OP_SIZE ('Q', 'q', file); - return; -#else - PUT_OP_SIZE ('Q', 'l', file); /* Fall through */ -#endif - } + return (GET_CODE (op) == ASHIFT + || GET_CODE (op) == ASHIFTRT + || GET_CODE (op) == LSHIFTRT + || GET_CODE (op) == ROTATE + || GET_CODE (op) == ROTATERT); +} - PUT_OP_SIZE ('Q', 'l', file); - return; - } +/* Return 1 if OP is COMPARE rtx with mode VOIDmode. + MODE is not used. */ - case 'b': - case 'w': - case 'k': - case 'h': - case 'y': - case 'P': - break; +int +VOIDmode_compare_op (op, mode) + register rtx op; + enum machine_mode mode; +{ + return GET_CODE (op) == COMPARE && GET_MODE (op) == VOIDmode; +} + +/* Output code to perform a 387 binary operation in INSN, one of PLUS, + MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3] + is the expression of the binary operation. The output may either be + emitted here, or returned to the caller, like all output_* functions. - default: - { - char str[50]; + There is no guarantee that the operands are the same mode, as they + might be within FLOAT or FLOAT_EXTEND expressions. */ - sprintf (str, "invalid operand code `%c'", code); - output_operand_lossage (str); - } - } - } - if (GET_CODE (x) == REG) - { - PRINT_REG (x, code, file); - } - else if (GET_CODE (x) == MEM) +char * +output_387_binary_op (insn, operands) + rtx insn; + rtx *operands; +{ + rtx temp; + char *base_op; + static char buf[100]; + + switch (GET_CODE (operands[3])) { - PRINT_PTR (x, file); - if (CONSTANT_ADDRESS_P (XEXP (x, 0))) - { - if (flag_pic) - output_pic_addr_const (file, XEXP (x, 0), code); - else - output_addr_const (file, XEXP (x, 0)); - } + case PLUS: + if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT + || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT) + base_op = "fiadd"; else - output_address (XEXP (x, 0)); - } - else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) - { - REAL_VALUE_TYPE r; long l; - REAL_VALUE_FROM_CONST_DOUBLE (r, x); - REAL_VALUE_TO_TARGET_SINGLE (r, l); - PRINT_IMMED_PREFIX (file); - fprintf (file, "0x%x", l); - } - /* These float cases don't actually occur as immediate operands. */ - else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) - { - REAL_VALUE_TYPE r; char dstr[30]; - REAL_VALUE_FROM_CONST_DOUBLE (r, x); - REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr); - fprintf (file, "%s", dstr); - } - else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == XFmode) - { - REAL_VALUE_TYPE r; char dstr[30]; - REAL_VALUE_FROM_CONST_DOUBLE (r, x); - REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr); - fprintf (file, "%s", dstr); - } - else - { - if (code != 'P') - { - if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) - PRINT_IMMED_PREFIX (file); - else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF - || GET_CODE (x) == LABEL_REF) - PRINT_OFFSET_PREFIX (file); - } - if (flag_pic) - output_pic_addr_const (file, x, code); + base_op = "fadd"; + break; + + case MINUS: + if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT + || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT) + base_op = "fisub"; else - output_addr_const (file, x); - } -} - -/* Print a memory operand whose address is ADDR. */ + base_op = "fsub"; + break; -void -print_operand_address (file, addr) - FILE *file; - register rtx addr; -{ - register rtx reg1, reg2, breg, ireg; - rtx offset; + case MULT: + if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT + || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT) + base_op = "fimul"; + else + base_op = "fmul"; + break; - switch (GET_CODE (addr)) - { - case REG: - ADDR_BEG (file); - fprintf (file, "%se", RP); - fputs (hi_reg_name[REGNO (addr)], file); - ADDR_END (file); + case DIV: + if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT + || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT) + base_op = "fidiv"; + else + base_op = "fdiv"; break; + default: + abort (); + } + + strcpy (buf, base_op); + + switch (GET_CODE (operands[3])) + { + case MULT: case PLUS: - reg1 = 0; - reg2 = 0; - ireg = 0; - breg = 0; - offset = 0; - if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) + if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2])) { - offset = XEXP (addr, 0); - addr = XEXP (addr, 1); + temp = operands[2]; + operands[2] = operands[1]; + operands[1] = temp; } - else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) + + if (GET_CODE (operands[2]) == MEM) + return strcat (buf, AS1 (%z2,%2)); + + if (NON_STACK_REG_P (operands[1])) { - offset = XEXP (addr, 1); - addr = XEXP (addr, 0); + output_op_from_reg (operands[1], strcat (buf, AS1 (%z0,%1))); + RET; } - if (GET_CODE (addr) != PLUS) ; - else if (GET_CODE (XEXP (addr, 0)) == MULT) + else if (NON_STACK_REG_P (operands[2])) { - reg1 = XEXP (addr, 0); - addr = XEXP (addr, 1); + output_op_from_reg (operands[2], strcat (buf, AS1 (%z0,%1))); + RET; } - else if (GET_CODE (XEXP (addr, 1)) == MULT) - { - reg1 = XEXP (addr, 1); - addr = XEXP (addr, 0); - } - else if (GET_CODE (XEXP (addr, 0)) == REG) - { - reg1 = XEXP (addr, 0); - addr = XEXP (addr, 1); - } - else if (GET_CODE (XEXP (addr, 1)) == REG) - { - reg1 = XEXP (addr, 1); - addr = XEXP (addr, 0); - } - if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT) - { - if (reg1 == 0) reg1 = addr; - else reg2 = addr; - addr = 0; - } - if (offset != 0) + + if (find_regno_note (insn, REG_DEAD, REGNO (operands[2]))) + return strcat (buf, AS2 (p,%2,%0)); + + if (STACK_TOP_P (operands[0])) + return strcat (buf, AS2 (,%y2,%0)); + else + return strcat (buf, AS2 (,%2,%0)); + + case MINUS: + case DIV: + if (GET_CODE (operands[1]) == MEM) + return strcat (buf, AS1 (r%z1,%1)); + + if (GET_CODE (operands[2]) == MEM) + return strcat (buf, AS1 (%z2,%2)); + + if (NON_STACK_REG_P (operands[1])) { - if (addr != 0) abort (); - addr = offset; + output_op_from_reg (operands[1], strcat (buf, AS1 (r%z0,%1))); + RET; } - if ((reg1 && GET_CODE (reg1) == MULT) - || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) + else if (NON_STACK_REG_P (operands[2])) { - breg = reg2; - ireg = reg1; + output_op_from_reg (operands[2], strcat (buf, AS1 (%z0,%1))); + RET; } - else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) + + if (! STACK_REG_P (operands[1]) || ! STACK_REG_P (operands[2])) + abort (); + + if (find_regno_note (insn, REG_DEAD, REGNO (operands[2]))) + return strcat (buf, AS2 (rp,%2,%0)); + + if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) + return strcat (buf, AS2 (p,%1,%0)); + + if (STACK_TOP_P (operands[0])) { - breg = reg1; - ireg = reg2; + if (STACK_TOP_P (operands[1])) + return strcat (buf, AS2 (,%y2,%0)); + else + return strcat (buf, AS2 (r,%y1,%0)); } + else if (STACK_TOP_P (operands[1])) + return strcat (buf, AS2 (,%1,%0)); + else + return strcat (buf, AS2 (r,%2,%0)); - if (ireg != 0 || breg != 0) - { - int scale = 1; + default: + abort (); + } +} + +/* Output code for INSN to convert a float to a signed int. OPERANDS + are the insn operands. The output may be SFmode or DFmode and the + input operand may be SImode or DImode. As a special case, make sure + that the 387 stack top dies if the output mode is DImode, because the + hardware requires this. */ - if (addr != 0) - { - if (flag_pic) - output_pic_addr_const (file, addr, 0); +char * +output_fix_trunc (insn, operands) + rtx insn; + rtx *operands; +{ + int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; + rtx xops[2]; - else if (GET_CODE (addr) == LABEL_REF) - output_asm_label (addr); + if (! STACK_TOP_P (operands[1]) || + (GET_MODE (operands[0]) == DImode && ! stack_top_dies)) + abort (); - else - output_addr_const (file, addr); - } + xops[0] = GEN_INT (12); + xops[1] = operands[4]; - if (ireg != 0 && GET_CODE (ireg) == MULT) - { - scale = INTVAL (XEXP (ireg, 1)); - ireg = XEXP (ireg, 0); - } + output_asm_insn (AS1 (fnstc%W2,%2), operands); + output_asm_insn (AS2 (mov%L2,%2,%4), operands); + output_asm_insn (AS2 (mov%B1,%0,%h1), xops); + output_asm_insn (AS2 (mov%L4,%4,%3), operands); + output_asm_insn (AS1 (fldc%W3,%3), operands); - /* The stack pointer can only appear as a base register, - never an index register, so exchange the regs if it is wrong. */ + if (NON_STACK_REG_P (operands[0])) + output_to_reg (operands[0], stack_top_dies); + else if (GET_CODE (operands[0]) == MEM) + { + if (stack_top_dies) + output_asm_insn (AS1 (fistp%z0,%0), operands); + else + output_asm_insn (AS1 (fist%z0,%0), operands); + } + else + abort (); - if (scale == 1 && ireg && REGNO (ireg) == STACK_POINTER_REGNUM) - { - rtx tmp; + return AS1 (fldc%W2,%2); +} + +/* Output code for INSN to compare OPERANDS. The two operands might + not have the same mode: one might be within a FLOAT or FLOAT_EXTEND + expression. If the compare is in mode CCFPEQmode, use an opcode that + will not fault if a qNaN is present. */ - tmp = breg; - breg = ireg; - ireg = tmp; - } +char * +output_float_compare (insn, operands) + rtx insn; + rtx *operands; +{ + int stack_top_dies; + rtx body = XVECEXP (PATTERN (insn), 0, 0); + int unordered_compare = GET_MODE (SET_SRC (body)) == CCFPEQmode; - /* output breg+ireg*scale */ - PRINT_B_I_S (breg, ireg, scale, file); - break; - } + /* intel1 */ + rtx tmp; + if (! STACK_TOP_P (operands[0])) + { + tmp = operands[0]; + operands[0] = operands[1]; + operands[1] = tmp; + cc_status.flags |= CC_REVERSED; + } + + if (! STACK_TOP_P (operands[0])) + abort (); - case MULT: - { - int scale; - if (GET_CODE (XEXP (addr, 0)) == CONST_INT) - { - scale = INTVAL (XEXP (addr, 0)); - ireg = XEXP (addr, 1); - } - else - { - scale = INTVAL (XEXP (addr, 1)); - ireg = XEXP (addr, 0); - } - output_addr_const (file, const0_rtx); - PRINT_B_I_S ((rtx) 0, ireg, scale, file); - } - break; + stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; - default: - if (GET_CODE (addr) == CONST_INT - && INTVAL (addr) < 0x8000 - && INTVAL (addr) >= -0x8000) - fprintf (file, "%d", INTVAL (addr)); + if (STACK_REG_P (operands[1]) + && stack_top_dies + && find_regno_note (insn, REG_DEAD, REGNO (operands[1])) + && REGNO (operands[1]) != FIRST_STACK_REG) + { + /* If both the top of the 387 stack dies, and the other operand + is also a stack register that dies, then this must be a + `fcompp' float compare */ + + if (unordered_compare) + output_asm_insn ("fucompp", operands); else - { - if (flag_pic) - output_pic_addr_const (file, addr, 0); - else - output_addr_const (file, addr); - } + output_asm_insn ("fcompp", operands); + } + else + { + static char buf[100]; + + /* Decide if this is the integer or float compare opcode, or the + unordered float compare. */ + + if (unordered_compare) + strcpy (buf, "fucom"); + else if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_FLOAT) + strcpy (buf, "fcom"); + else + strcpy (buf, "ficom"); + + /* Modify the opcode if the 387 stack is to be popped. */ + + if (stack_top_dies) + strcat (buf, "p"); + + if (NON_STACK_REG_P (operands[1])) + output_op_from_reg (operands[1], strcat (buf, AS1 (%z0,%1))); + else + output_asm_insn (strcat (buf, AS1 (%z1,%y1)), operands); } + + /* Now retrieve the condition code. */ + + return output_fp_cc0_set (insn); } -/* Set the cc_status for the results of an insn whose pattern is EXP. - On the 80386, we assume that only test and compare insns, as well - as SI, HI, & DI mode ADD, SUB, NEG, AND, IOR, XOR, ASHIFT, - ASHIFTRT, and LSHIFTRT instructions set the condition codes usefully. - Also, we assume that jumps, moves and sCOND don't affect the condition - codes. All else clobbers the condition codes, by assumption. +/* Output opcodes to transfer the results of FP compare or test INSN + from the FPU to the CPU flags. If TARGET_IEEE_FP, ensure that if the + result of the compare or test is unordered, no comparison operator + succeeds except NE. Return an output template, if any. */ - We assume that ALL integer add, minus, etc. instructions effect the - condition codes. This MUST be consistent with i386.md. +char * +output_fp_cc0_set (insn) + rtx insn; +{ + rtx xops[3]; + rtx unordered_label; + rtx next; + enum rtx_code code; - We don't record any float test or compare - the redundant test & - compare check in final.c does not handle stack-like regs correctly. */ + xops[0] = gen_rtx (REG, HImode, 0); + output_asm_insn (AS1 (fnsts%W0,%0), xops); -void -notice_update_cc (exp) - rtx exp; -{ - if (GET_CODE (exp) == SET) + + if (! TARGET_IEEE_FP) { - /* Jumps do not alter the cc's. */ - if (SET_DEST (exp) == pc_rtx) - return; - /* Moving register or memory into a register: - it doesn't alter the cc's, but it might invalidate - the RTX's which we remember the cc's came from. - (Note that moving a constant 0 or 1 MAY set the cc's). */ - if (REG_P (SET_DEST (exp)) - && (REG_P (SET_SRC (exp)) || GET_CODE (SET_SRC (exp)) == MEM - || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<')) - { - if (cc_status.value1 - && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1)) - cc_status.value1 = 0; - if (cc_status.value2 - && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2)) - cc_status.value2 = 0; - return; - } - /* Moving register into memory doesn't alter the cc's. - It may invalidate the RTX's which we remember the cc's came from. */ - if (GET_CODE (SET_DEST (exp)) == MEM - && (REG_P (SET_SRC (exp)) - || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<')) - { - if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM) - cc_status.value1 = 0; - if (cc_status.value2 && GET_CODE (cc_status.value2) == MEM) - cc_status.value2 = 0; - return; - } - /* Function calls clobber the cc's. */ - else if (GET_CODE (SET_SRC (exp)) == CALL) - { - CC_STATUS_INIT; - return; - } - /* Tests and compares set the cc's in predictable ways. */ - else if (SET_DEST (exp) == cc0_rtx) - { - CC_STATUS_INIT; - cc_status.value1 = SET_SRC (exp); - return; - } - /* Certain instructions effect the condition codes. */ - else if (GET_MODE (SET_SRC (exp)) == SImode - || GET_MODE (SET_SRC (exp)) == HImode - || GET_MODE (SET_SRC (exp)) == QImode) - switch (GET_CODE (SET_SRC (exp))) - { - case ASHIFTRT: case LSHIFTRT: - case ASHIFT: - /* Shifts on the 386 don't set the condition codes if the - shift count is zero. */ - if (GET_CODE (XEXP (SET_SRC (exp), 1)) != CONST_INT) - { - CC_STATUS_INIT; - break; - } - /* We assume that the CONST_INT is non-zero (this rtx would - have been deleted if it were zero. */ + /* intel1 */ + if (!(cc_status.flags & CC_REVERSED)) + { + next = next_cc0_user (insn); + + if (GET_CODE (next) == JUMP_INSN + && GET_CODE (PATTERN (next)) == SET + && SET_DEST (PATTERN (next)) == pc_rtx + && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE) + { + code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0)); + } + else if (GET_CODE (PATTERN (next)) == SET) + { + code = GET_CODE (SET_SRC (PATTERN (next))); + } + else + { + return "sahf"; + } + if (code == GT || code == LT || code == EQ || code == NE + || code == LE || code == GE) + { /* We will test eax directly */ + cc_status.flags |= CC_TEST_AX; + RET; + } + } + return "sahf"; + } - case PLUS: case MINUS: case NEG: - case AND: case IOR: case XOR: - cc_status.flags = CC_NO_OVERFLOW; - cc_status.value1 = SET_SRC (exp); - cc_status.value2 = SET_DEST (exp); - break; + next = next_cc0_user (insn); + if (next == NULL_RTX) + abort (); - default: - CC_STATUS_INIT; - } - else - { - CC_STATUS_INIT; - } + if (GET_CODE (next) == JUMP_INSN + && GET_CODE (PATTERN (next)) == SET + && SET_DEST (PATTERN (next)) == pc_rtx + && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE) + { + code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0)); } - else if (GET_CODE (exp) == PARALLEL - && GET_CODE (XVECEXP (exp, 0, 0)) == SET) + else if (GET_CODE (PATTERN (next)) == SET) { - if (SET_DEST (XVECEXP (exp, 0, 0)) == pc_rtx) - return; - if (SET_DEST (XVECEXP (exp, 0, 0)) == cc0_rtx) - { - CC_STATUS_INIT; - if (stack_regs_mentioned_p (SET_SRC (XVECEXP (exp, 0, 0)))) - cc_status.flags |= CC_IN_80387; - else - cc_status.value1 = SET_SRC (XVECEXP (exp, 0, 0)); - return; - } - CC_STATUS_INIT; + code = GET_CODE (SET_SRC (PATTERN (next))); } else + abort (); + + xops[0] = gen_rtx (REG, QImode, 0); + + switch (code) { - CC_STATUS_INIT; + case GT: + xops[1] = GEN_INT (0x45); + output_asm_insn (AS2 (and%B0,%1,%h0), xops); + /* je label */ + break; + + case LT: + xops[1] = GEN_INT (0x45); + xops[2] = GEN_INT (0x01); + output_asm_insn (AS2 (and%B0,%1,%h0), xops); + output_asm_insn (AS2 (cmp%B0,%2,%h0), xops); + /* je label */ + break; + + case GE: + xops[1] = GEN_INT (0x05); + output_asm_insn (AS2 (and%B0,%1,%h0), xops); + /* je label */ + break; + + case LE: + xops[1] = GEN_INT (0x45); + xops[2] = GEN_INT (0x40); + output_asm_insn (AS2 (and%B0,%1,%h0), xops); + output_asm_insn (AS1 (dec%B0,%h0), xops); + output_asm_insn (AS2 (cmp%B0,%2,%h0), xops); + /* jb label */ + break; + + case EQ: + xops[1] = GEN_INT (0x45); + xops[2] = GEN_INT (0x40); + output_asm_insn (AS2 (and%B0,%1,%h0), xops); + output_asm_insn (AS2 (cmp%B0,%2,%h0), xops); + /* je label */ + break; + + case NE: + xops[1] = GEN_INT (0x44); + xops[2] = GEN_INT (0x40); + output_asm_insn (AS2 (and%B0,%1,%h0), xops); + output_asm_insn (AS2 (xor%B0,%2,%h0), xops); + /* jne label */ + break; + + case GTU: + case LTU: + case GEU: + case LEU: + default: + abort (); } + RET; +} + +#define MAX_386_STACK_LOCALS 2 + +static rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS]; + +/* Define the structure for the machine field in struct function. */ +struct machine_function +{ + rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS]; +}; + +/* Functions to save and restore i386_stack_locals. + These will be called, via pointer variables, + from push_function_context and pop_function_context. */ + +void +save_386_machine_status (p) + struct function *p; +{ + p->machine = (struct machine_function *) xmalloc (sizeof i386_stack_locals); + bcopy (i386_stack_locals, p->machine->i386_stack_locals, + sizeof i386_stack_locals); } - -/* Split one or more DImode RTL references into pairs of SImode - references. The RTL can be REG, offsettable MEM, integer constant, or - CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to - split and "num" is its length. lo_half and hi_half are output arrays - that parallel "operands". */ void -split_di (operands, num, lo_half, hi_half) - rtx operands[]; - int num; - rtx lo_half[], hi_half[]; +restore_386_machine_status (p) + struct function *p; { - while (num--) - { - if (GET_CODE (operands[num]) == REG) - { - lo_half[num] = gen_rtx (REG, SImode, REGNO (operands[num])); - hi_half[num] = gen_rtx (REG, SImode, REGNO (operands[num]) + 1); - } - else if (CONSTANT_P (operands[num])) - { - split_double (operands[num], &lo_half[num], &hi_half[num]); - } - else if (offsettable_memref_p (operands[num])) - { - lo_half[num] = operands[num]; - hi_half[num] = adj_offsettable_operand (operands[num], 4); - } - else - abort(); - } + bcopy (p->machine->i386_stack_locals, i386_stack_locals, + sizeof i386_stack_locals); + free (p->machine); } - -/* Return 1 if this is a valid binary operation on a 387. - OP is the expression matched, and MODE is its mode. */ -int -binary_387_op (op, mode) - register rtx op; - enum machine_mode mode; +/* Clear stack slot assignments remembered from previous functions. + This is called from INIT_EXPANDERS once before RTL is emitted for each + function. */ + +void +clear_386_stack_locals () { - if (mode != VOIDmode && mode != GET_MODE (op)) - return 0; + enum machine_mode mode; + int n; - switch (GET_CODE (op)) - { - case PLUS: - case MINUS: - case MULT: - case DIV: - return GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT; + for (mode = VOIDmode; (int) mode < (int) MAX_MACHINE_MODE; + mode = (enum machine_mode) ((int) mode + 1)) + for (n = 0; n < MAX_386_STACK_LOCALS; n++) + i386_stack_locals[(int) mode][n] = NULL_RTX; - default: - return 0; - } + /* Arrange to save and restore i386_stack_locals around nested functions. */ + save_machine_status = save_386_machine_status; + restore_machine_status = restore_386_machine_status; } - -/* Return 1 if this is a valid shift or rotate operation on a 386. - OP is the expression matched, and MODE is its mode. */ +/* Return a MEM corresponding to a stack slot with mode MODE. + Allocate a new slot if necessary. -int -shift_op (op, mode) - register rtx op; - enum machine_mode mode; + The RTL for a function can have several slots available: N is + which slot to use. */ + +rtx +assign_386_stack_local (mode, n) + enum machine_mode mode; + int n; { - rtx operand = XEXP (op, 0); + if (n < 0 || n >= MAX_386_STACK_LOCALS) + abort (); - if (mode != VOIDmode && mode != GET_MODE (op)) - return 0; + if (i386_stack_locals[(int) mode][n] == NULL_RTX) + { + i386_stack_locals[(int) mode][n] + = assign_stack_local (mode, GET_MODE_SIZE (mode), 0); + } + return i386_stack_locals[(int) mode][n]; +} - if (GET_MODE (operand) != GET_MODE (op) - || GET_MODE_CLASS (GET_MODE (op)) != MODE_INT) - return 0; - return (GET_CODE (op) == ASHIFT - || GET_CODE (op) == ASHIFTRT - || GET_CODE (op) == LSHIFTRT - || GET_CODE (op) == ROTATE - || GET_CODE (op) == ROTATERT); +/* all functions after here added by intel1 */ +/* intel1 */ +int is_mul(op,mode) + register rtx op; + enum machine_mode mode; +{ + return(GET_CODE(op)==MULT); } -/* Return 1 if OP is COMPARE rtx with mode VOIDmode. - MODE is not used. */ - -int -VOIDmode_compare_op (op, mode) +/* intel1 */ +int is_div(op,mode) register rtx op; enum machine_mode mode; { - return GET_CODE (op) == COMPARE && GET_MODE (op) == VOIDmode; + return(GET_CODE(op)==DIV); } - -/* Output code to perform a 387 binary operation in INSN, one of PLUS, - MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3] - is the expression of the binary operation. The output may either be - emitted here, or returned to the caller, like all output_* functions. - There is no guarantee that the operands are the same mode, as they - might be within FLOAT or FLOAT_EXTEND expressions. */ +/* Create a new copy of an rtx. + Recursively copies the operands of the rtx, + except for those few rtx codes that are sharable. + Doesn't share CONST */ -char * -output_387_binary_op (insn, operands) - rtx insn; - rtx *operands; +rtx +copy_all_rtx (orig) + register rtx orig; { - rtx temp; - char *base_op; - static char buf[100]; + register rtx copy; + register int i, j; + register RTX_CODE code; + register char *format_ptr; - switch (GET_CODE (operands[3])) + code = GET_CODE (orig); + + switch (code) { - case PLUS: - if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT - || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT) - base_op = "fiadd"; - else - base_op = "fadd"; - break; + case REG: + case QUEUED: + case CONST_INT: + case CONST_DOUBLE: + case SYMBOL_REF: + case CODE_LABEL: + case PC: + case CC0: + case SCRATCH: + /* SCRATCH must be shared because they represent distinct values. */ + return orig; - case MINUS: - if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT - || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT) - base_op = "fisub"; - else - base_op = "fsub"; +#if 0 + case CONST: + /* CONST can be shared if it contains a SYMBOL_REF. If it contains + a LABEL_REF, it isn't sharable. */ + if (GET_CODE (XEXP (orig, 0)) == PLUS + && GET_CODE (XEXP (XEXP (orig, 0), 0)) == SYMBOL_REF + && GET_CODE (XEXP (XEXP (orig, 0), 1)) == CONST_INT) + return orig; break; +#endif + /* A MEM with a constant address is not sharable. The problem is that + the constant address may need to be reloaded. If the mem is shared, + then reloading one copy of this mem will cause all copies to appear + to have been reloaded. */ + } + + copy = rtx_alloc (code); + PUT_MODE (copy, GET_MODE (orig)); + copy->in_struct = orig->in_struct; + copy->volatil = orig->volatil; + copy->unchanging = orig->unchanging; + copy->integrated = orig->integrated; + /* intel1 */ + copy->is_spill_rtx = orig->is_spill_rtx; + + format_ptr = GET_RTX_FORMAT (GET_CODE (copy)); + + for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++) + { + switch (*format_ptr++) + { + case 'e': + XEXP (copy, i) = XEXP (orig, i); + if (XEXP (orig, i) != NULL) + XEXP (copy, i) = copy_rtx (XEXP (orig, i)); + break; - case MULT: - if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT - || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT) - base_op = "fimul"; - else - base_op = "fmul"; - break; + case '0': + case 'u': + XEXP (copy, i) = XEXP (orig, i); + break; - case DIV: - if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT - || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT) - base_op = "fidiv"; - else - base_op = "fdiv"; - break; + case 'E': + case 'V': + XVEC (copy, i) = XVEC (orig, i); + if (XVEC (orig, i) != NULL) + { + XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i)); + for (j = 0; j < XVECLEN (copy, i); j++) + XVECEXP (copy, i, j) = copy_rtx (XVECEXP (orig, i, j)); + } + break; - default: - abort (); + case 'w': + XWINT (copy, i) = XWINT (orig, i); + break; + + case 'i': + XINT (copy, i) = XINT (orig, i); + break; + + case 's': + case 'S': + XSTR (copy, i) = XSTR (orig, i); + break; + + default: + abort (); + } + } + return copy; +} + + +/* try to rewrite a memory address to make it valid */ +void +rewrite_address (mem_rtx) + rtx mem_rtx; +{ + rtx index_rtx, base_rtx, offset_rtx, scale_rtx, ret_rtx; + int scale = 1; + int offset_adjust = 0; + int was_only_offset = 0; + rtx mem_addr = XEXP (mem_rtx, 0); + char *storage = (char *) oballoc (0); + int in_struct = 0; + int is_spill_rtx = 0; + + in_struct = MEM_IN_STRUCT_P (mem_rtx); + is_spill_rtx = RTX_IS_SPILL_P (mem_rtx); + + if (GET_CODE (mem_addr) == PLUS && + GET_CODE (XEXP (mem_addr, 1)) == PLUS && + GET_CODE (XEXP (XEXP (mem_addr, 1), 0)) == REG) + { /* this part is utilized by the combiner */ + ret_rtx = + gen_rtx (PLUS, GET_MODE (mem_addr), + gen_rtx (PLUS, GET_MODE (XEXP (mem_addr, 1)), + XEXP (mem_addr, 0), + XEXP (XEXP (mem_addr, 1), 0)), + XEXP (XEXP (mem_addr, 1), 1)); + if (memory_address_p (GET_MODE (mem_rtx), ret_rtx)) + { + XEXP (mem_rtx, 0) = ret_rtx; + RTX_IS_SPILL_P (ret_rtx) = is_spill_rtx; + return; + } + obfree (storage); + } + + /* this part is utilized by loop.c */ + /* If the address contains PLUS (reg,const) and this pattern is invalid + in this case - try to rewrite the address to make it valid intel1 + */ + storage = (char *) oballoc (0); + index_rtx = base_rtx = offset_rtx = NULL; + /* find the base index and offset elements of the memory address */ + if (GET_CODE (mem_addr) == PLUS) + { + if (GET_CODE (XEXP (mem_addr, 0)) == REG) + { + if (GET_CODE (XEXP (mem_addr, 1)) == REG) + { + base_rtx = XEXP (mem_addr, 1); + index_rtx = XEXP (mem_addr, 0); + } + else + { + base_rtx = XEXP (mem_addr, 0); + offset_rtx = XEXP (mem_addr, 1); + } + } + else if (GET_CODE (XEXP (mem_addr, 0)) == MULT) + { + index_rtx = XEXP (mem_addr, 0); + if (GET_CODE (XEXP (mem_addr, 1)) == REG) + { + base_rtx = XEXP (mem_addr, 1); + } + else + { + offset_rtx = XEXP (mem_addr, 1); + } + } + else if (GET_CODE (XEXP (mem_addr, 0)) == PLUS) + { + /* intel1 */ + if (GET_CODE (XEXP (XEXP (mem_addr, 0), 0)) == PLUS && + GET_CODE (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0)) == MULT && + GET_CODE (XEXP (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0), 0)) == REG && + GET_CODE (XEXP (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0), 1)) == CONST_INT && + GET_CODE (XEXP (XEXP (XEXP (mem_addr, 0), 0), 1)) == CONST_INT && + GET_CODE (XEXP (XEXP (mem_addr, 0), 1)) == REG && + GET_CODE (XEXP (mem_addr, 1)) == SYMBOL_REF) + { + index_rtx = XEXP (XEXP (XEXP (mem_addr, 0), 0), 0); + offset_rtx = XEXP (mem_addr, 1); + base_rtx = XEXP (XEXP (mem_addr, 0), 1); + offset_adjust = INTVAL (XEXP (XEXP (XEXP (mem_addr, 0), 0), 1)); + } + else + { + offset_rtx = XEXP (mem_addr, 1); + index_rtx = XEXP (XEXP (mem_addr, 0), 0); + base_rtx = XEXP (XEXP (mem_addr, 0), 1); + } + } + else if (GET_CODE (XEXP (mem_addr, 0)) == CONST_INT) + { + was_only_offset = 1; + index_rtx = NULL; + base_rtx = NULL; + offset_rtx = XEXP (mem_addr, 1); + offset_adjust = INTVAL (XEXP (mem_addr, 0)); + if (offset_adjust == 0) + { + XEXP (mem_rtx, 0) = offset_rtx; + RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx; + return; + } + } + else + { + obfree (storage); + return; + } + } + else if (GET_CODE (mem_addr) == MULT) + { + index_rtx = mem_addr; + } + else + { + obfree (storage); + return; + } + if (index_rtx && GET_CODE (index_rtx) == MULT) + { + if (GET_CODE (XEXP (index_rtx, 1)) != CONST_INT) + { + obfree (storage); + return; + } + scale_rtx = XEXP (index_rtx, 1); + scale = INTVAL (scale_rtx); + index_rtx = copy_all_rtx (XEXP (index_rtx, 0)); + } + /* now find which of the elements are invalid and try to fix them */ + if (index_rtx && GET_CODE (index_rtx) == CONST_INT && base_rtx == NULL) + { + offset_adjust = INTVAL (index_rtx) * scale; + if (offset_rtx && GET_CODE (offset_rtx) == CONST && + GET_CODE (XEXP (offset_rtx, 0)) == PLUS) + { + if (GET_CODE (XEXP (XEXP (offset_rtx, 0), 0)) == SYMBOL_REF && + GET_CODE (XEXP (XEXP (offset_rtx, 0), 1)) == CONST_INT) + { + offset_rtx = copy_all_rtx (offset_rtx); + XEXP (XEXP (offset_rtx, 0), 1) = + gen_rtx (CONST_INT, 0, INTVAL (XEXP (XEXP (offset_rtx, 0), 1)) + offset_adjust); + if (!CONSTANT_P (offset_rtx)) + { + obfree (storage); + return; + } + } + } + else if (offset_rtx && GET_CODE (offset_rtx) == SYMBOL_REF) + { + offset_rtx = + gen_rtx (CONST, GET_MODE (offset_rtx), + gen_rtx (PLUS, GET_MODE (offset_rtx), + offset_rtx, + gen_rtx (CONST_INT, 0, offset_adjust))); + if (!CONSTANT_P (offset_rtx)) + { + obfree (storage); + return; + } + } + else if (offset_rtx && GET_CODE (offset_rtx) == CONST_INT) + { + offset_rtx = gen_rtx (CONST_INT, 0, INTVAL (offset_rtx) + offset_adjust); + } + else if (!offset_rtx) + { + offset_rtx = gen_rtx (CONST_INT, 0, 0); + } + RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx; + XEXP (mem_rtx, 0) = offset_rtx; + return; } - - strcpy (buf, base_op); - - switch (GET_CODE (operands[3])) + if (base_rtx && GET_CODE (base_rtx) == PLUS && + GET_CODE (XEXP (base_rtx, 0)) == REG && + GET_CODE (XEXP (base_rtx, 1)) == CONST_INT) { - case MULT: - case PLUS: - if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2])) + offset_adjust += INTVAL (XEXP (base_rtx, 1)); + base_rtx = copy_all_rtx (XEXP (base_rtx, 0)); + } + else if (base_rtx && GET_CODE (base_rtx) == CONST_INT) + { + offset_adjust += INTVAL (base_rtx); + base_rtx = NULL; + } + if (index_rtx && GET_CODE (index_rtx) == PLUS && + GET_CODE (XEXP (index_rtx, 0)) == REG && + GET_CODE (XEXP (index_rtx, 1)) == CONST_INT) + { + offset_adjust += INTVAL (XEXP (index_rtx, 1)) * scale; + index_rtx = copy_all_rtx (XEXP (index_rtx, 0)); + } + if (index_rtx) + { + if (!LEGITIMATE_INDEX_P (index_rtx) + && !(index_rtx == stack_pointer_rtx && scale == 1 && base_rtx == NULL)) { - temp = operands[2]; - operands[2] = operands[1]; - operands[1] = temp; + obfree (storage); + return; } - - if (GET_CODE (operands[2]) == MEM) - return strcat (buf, AS1 (%z2,%2)); - - if (NON_STACK_REG_P (operands[1])) + } + if (base_rtx) + { + if (!LEGITIMATE_INDEX_P (base_rtx) && GET_CODE (base_rtx) != REG) { - output_op_from_reg (operands[1], strcat (buf, AS1 (%z0,%1))); - RET; + obfree (storage); + return; } - else if (NON_STACK_REG_P (operands[2])) + } + if (offset_adjust != 0) + { + if (offset_rtx) { - output_op_from_reg (operands[2], strcat (buf, AS1 (%z0,%1))); - RET; + if (GET_CODE (offset_rtx) == CONST && + GET_CODE (XEXP (offset_rtx, 0)) == PLUS) + { + if (GET_CODE (XEXP (XEXP (offset_rtx, 0), 0)) == SYMBOL_REF && + GET_CODE (XEXP (XEXP (offset_rtx, 0), 1)) == CONST_INT) + { + offset_rtx = copy_all_rtx (offset_rtx); + XEXP (XEXP (offset_rtx, 0), 1) = + gen_rtx (CONST_INT, 0, INTVAL (XEXP (XEXP (offset_rtx, 0), 1)) + offset_adjust); + if (!CONSTANT_P (offset_rtx)) + { + obfree (storage); + return; + } + } + } + else if (GET_CODE (offset_rtx) == SYMBOL_REF) + { + offset_rtx = + gen_rtx (CONST, GET_MODE (offset_rtx), + gen_rtx (PLUS, GET_MODE (offset_rtx), + offset_rtx, + gen_rtx (CONST_INT, 0, offset_adjust))); + if (!CONSTANT_P (offset_rtx)) + { + obfree (storage); + return; + } + } + else if (GET_CODE (offset_rtx) == CONST_INT) + { + offset_rtx = gen_rtx (CONST_INT, 0, INTVAL (offset_rtx) + offset_adjust); + } + else + { + obfree (storage); + return; + } } - - if (find_regno_note (insn, REG_DEAD, REGNO (operands[2]))) - return strcat (buf, AS2 (p,%2,%0)); - - if (STACK_TOP_P (operands[0])) - return strcat (buf, AS2C (%y2,%0)); else - return strcat (buf, AS2C (%2,%0)); - - case MINUS: - case DIV: - if (GET_CODE (operands[1]) == MEM) - return strcat (buf, AS1 (r%z1,%1)); - - if (GET_CODE (operands[2]) == MEM) - return strcat (buf, AS1 (%z2,%2)); - - if (NON_STACK_REG_P (operands[1])) { - output_op_from_reg (operands[1], strcat (buf, AS1 (r%z0,%1))); - RET; + offset_rtx = gen_rtx (CONST_INT, 0, offset_adjust); } - else if (NON_STACK_REG_P (operands[2])) + if (index_rtx) { - output_op_from_reg (operands[2], strcat (buf, AS1 (%z0,%1))); - RET; + if (base_rtx) + { + if (scale != 1) + { + if (GET_CODE (offset_rtx) == CONST_INT && + INTVAL (offset_rtx) == 0) + { + ret_rtx = gen_rtx (PLUS, GET_MODE (base_rtx), + gen_rtx (MULT, GET_MODE (index_rtx), index_rtx, + scale_rtx), + base_rtx); + } + else + { + ret_rtx = gen_rtx (PLUS, GET_MODE (offset_rtx), + gen_rtx (PLUS, GET_MODE (base_rtx), + gen_rtx (MULT, GET_MODE (index_rtx), index_rtx, + scale_rtx), + base_rtx), + offset_rtx); + } + } + else + { + if (GET_CODE (offset_rtx) == CONST_INT && + INTVAL (offset_rtx) == 0) + { + ret_rtx = gen_rtx (PLUS, GET_MODE (index_rtx), index_rtx, base_rtx); + } + else + { + ret_rtx = gen_rtx (PLUS, GET_MODE (offset_rtx), + gen_rtx (PLUS, GET_MODE (index_rtx), index_rtx, + base_rtx), + offset_rtx); + } + } + } + else + { + if (scale != 1) + { + if (GET_CODE (offset_rtx) == CONST_INT && + INTVAL (offset_rtx) == 0) + { + ret_rtx = gen_rtx (MULT, GET_MODE (index_rtx), index_rtx, scale_rtx); + } + else + { + ret_rtx = + gen_rtx (PLUS, GET_MODE (offset_rtx), + gen_rtx (MULT, GET_MODE (index_rtx), index_rtx, + scale_rtx), + offset_rtx); + } + } + else + { + if (GET_CODE (offset_rtx) == CONST_INT && + INTVAL (offset_rtx) == 0) + { + ret_rtx = index_rtx; + } + else + { + ret_rtx = gen_rtx (PLUS, GET_MODE (index_rtx), index_rtx, offset_rtx); + } + } + } } - - if (! STACK_REG_P (operands[1]) || ! STACK_REG_P (operands[2])) - abort (); - - if (find_regno_note (insn, REG_DEAD, REGNO (operands[2]))) - return strcat (buf, AS2 (rp,%2,%0)); - - if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) - return strcat (buf, AS2 (p,%1,%0)); - - if (STACK_TOP_P (operands[0])) + else { - if (STACK_TOP_P (operands[1])) - return strcat (buf, AS2C (%y2,%0)); + if (base_rtx) + { + if (GET_CODE (offset_rtx) == CONST_INT && + INTVAL (offset_rtx) == 0) + { + ret_rtx = base_rtx; + } + else + { + ret_rtx = gen_rtx (PLUS, GET_MODE (base_rtx), base_rtx, offset_rtx); + } + } + else if (was_only_offset) + { + ret_rtx = offset_rtx; + } else - return strcat (buf, AS2 (r,%y1,%0)); + { + obfree (storage); + return; + } } - else if (STACK_TOP_P (operands[1])) - return strcat (buf, AS2C (%1,%0)); - else - return strcat (buf, AS2 (r,%2,%0)); - - default: - abort (); + XEXP (mem_rtx, 0) = ret_rtx; + RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx; + return; } -} - -/* Output code for INSN to convert a float to a signed int. OPERANDS - are the insn operands. The output may be SFmode or DFmode and the - input operand may be SImode or DImode. As a special case, make sure - that the 387 stack top dies if the output mode is DImode, because the - hardware requires this. */ - -char * -output_fix_trunc (insn, operands) - rtx insn; - rtx *operands; -{ - int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; - rtx xops[2]; - - if (! STACK_TOP_P (operands[1]) || - (GET_MODE (operands[0]) == DImode && ! stack_top_dies)) - abort (); - - xops[0] = GEN_INT (12); - xops[1] = operands[4]; - - output_asm_insn (AS1 (fnstc%W2,%2), operands); - output_asm_insn (AS2 (mov%L2,%2,%4), operands); - output_asm_insn (AS2 (mov%B1,%0,%h1), xops); - output_asm_insn (AS2 (mov%L4,%4,%3), operands); - output_asm_insn (AS1 (fldc%W3,%3), operands); - - if (NON_STACK_REG_P (operands[0])) - output_to_reg (operands[0], stack_top_dies); - else if (GET_CODE (operands[0]) == MEM) + else { - if (stack_top_dies) - output_asm_insn (AS1 (fistp%z0,%0), operands); - else - output_asm_insn (AS1 (fist%z0,%0), operands); + obfree (storage); + return; } - else - abort (); - - return AS1 (fldc%W2,%2); } - -/* Output code for INSN to compare OPERANDS. The two operands might - not have the same mode: one might be within a FLOAT or FLOAT_EXTEND - expression. If the compare is in mode CCFPEQmode, use an opcode that - will not fault if a qNaN is present. */ -char * -output_float_compare (insn, operands) - rtx insn; - rtx *operands; +/* return 1 if the first insn to set cc before insn also sets the register + reg_rtx - otherwise return 0 +*/ +int +last_to_set_cc (reg_rtx, insn) + rtx reg_rtx, insn; { - int stack_top_dies; - rtx body = XVECEXP (PATTERN (insn), 0, 0); - int unordered_compare = GET_MODE (SET_SRC (body)) == CCFPEQmode; - - if (! STACK_TOP_P (operands[0])) - abort (); + rtx prev_insn = PREV_INSN (insn); - stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; - - if (STACK_REG_P (operands[1]) - && stack_top_dies - && find_regno_note (insn, REG_DEAD, REGNO (operands[1])) - && REGNO (operands[1]) != FIRST_STACK_REG) + while (prev_insn) { - /* If both the top of the 387 stack dies, and the other operand - is also a stack register that dies, then this must be a - `fcompp' float compare */ - - if (unordered_compare) - output_asm_insn ("fucompp", operands); + if (GET_CODE (prev_insn) == NOTE) + { + ; + } + else if (GET_CODE (prev_insn) == INSN) + { + if (GET_CODE (PATTERN (prev_insn)) != SET) + { + return (0); + } + if (rtx_equal_p (SET_DEST (PATTERN (prev_insn)), reg_rtx)) + { + if (sets_condition_code (SET_SRC (PATTERN (prev_insn)))) + { + return (1); + } + else + { + return (0); + } + } + else if (!doesnt_set_condition_code (SET_SRC (PATTERN (prev_insn)))) + { + return (0); + } + } else - output_asm_insn ("fcompp", operands); + { + return (0); + } + prev_insn = PREV_INSN (prev_insn); } - else - { - static char buf[100]; - - /* Decide if this is the integer or float compare opcode, or the - unordered float compare. */ - - if (unordered_compare) - strcpy (buf, "fucom"); - else if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_FLOAT) - strcpy (buf, "fcom"); - else - strcpy (buf, "ficom"); - - /* Modify the opcode if the 387 stack is to be popped. */ - - if (stack_top_dies) - strcat (buf, "p"); + return (0); +} - if (NON_STACK_REG_P (operands[1])) - output_op_from_reg (operands[1], strcat (buf, AS1 (%z0,%1))); - else - output_asm_insn (strcat (buf, AS1 (%z1,%y1)), operands); - } +int +doesnt_set_condition_code (pat) + rtx pat; +{ + switch (GET_CODE (pat)) + { + case MEM: + case REG: + return (1); - /* Now retrieve the condition code. */ + default: + return (0); - return output_fp_cc0_set (insn); + } } - -/* Output opcodes to transfer the results of FP compare or test INSN - from the FPU to the CPU flags. If TARGET_IEEE_FP, ensure that if the - result of the compare or test is unordered, no comparison operator - succeeds except NE. Return an output template, if any. */ -char * -output_fp_cc0_set (insn) - rtx insn; +int +sets_condition_code (pat) + rtx pat; { - rtx xops[3]; - rtx unordered_label; - rtx next; - enum rtx_code code; + switch (GET_CODE (pat)) + { + case PLUS: + case MINUS: + case AND: + case IOR: + case XOR: + case NOT: + case NEG: + case MULT: + case DIV: + case MOD: + case UDIV: + case UMOD: + return (1); - xops[0] = gen_rtx (REG, HImode, 0); - output_asm_insn (AS1 (fnsts%W0,%0), xops); + default: + return (0); - if (! TARGET_IEEE_FP) - return "sahf"; + } +} - next = next_cc0_user (insn); - if (next == NULL_RTX) - abort (); - if (GET_CODE (next) == JUMP_INSN - && GET_CODE (PATTERN (next)) == SET - && SET_DEST (PATTERN (next)) == pc_rtx - && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE) - { - code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0)); - } - else if (GET_CODE (PATTERN (next)) == SET) +/* intel1 */ +int +str_immediate_operand (op, mode) + register rtx op; + enum machine_mode mode; +{ + if (GET_CODE (op) == CONST_INT && INTVAL (op) <= 32 && INTVAL (op) >= 0) { - code = GET_CODE (SET_SRC (PATTERN (next))); + return (1); } - else - abort (); + return (0); +} - xops[0] = gen_rtx (REG, QImode, 0); +/* intel1 */ +void +override_options () +{ + register int i, start; + register int regno; + register enum machine_mode mode; +#if 0 + int blend = 0; +#endif - switch (code) + /* only one `-mcpu' allowed */ + if (TARGET_X && (TARGET_X != TARGET_386) && (TARGET_X != TARGET_486) && (TARGET_X != TARGET_PENTIUM)) + fatal ("multilple `-mcpu' definitions .\n"); + + /* if `-mcpu' use it, otherwise take default */ + target_flags |= USE_CPU; + + if (TARGET_PENTIUM) + x86_cpu = PROCESSOR_PENTIUM; + else if (TARGET_486) + x86_cpu = PROCESSOR_486; + else if (TARGET_386) + x86_cpu = PROCESSOR_386; + else /* no processor type ? */ + fatal ("no processor type.\n"); + +#if 0 /* what happens if we have few -mcpu's, I don't think it's needed */ + /* Identify the processor type */ + if (!(TARGET_PENTIUM) && !(TARGET_486) && !(TARGET_386)) + { + x86_cpu = PROCESSOR_PENTIUM; + target_flags |= (TARGET_486_SWITCH); + blend = 1; + } + + else { - case GT: - xops[1] = GEN_INT (0x45); - output_asm_insn (AS2 (and%B0,%1,%h0), xops); - /* je label */ - break; + x86_cpu = PROCESSOR_DEFAULT; + if (TARGET_PENTIUM) + { + x86_cpu = PROCESSOR_PENTIUM; + } + if (TARGET_486) + { + if (x86_cpu != PROCESSOR_DEFAULT) + { + error ("conflicting -mX86 : using blend"); + blend = 1; + x86_cpu = PROCESSOR_PENTIUM; + target_flags &= ~(TARGET_386_SWITCH); + target_flags &= ~(TARGET_PENTIUM_SWITCH); + } + else + { + x86_cpu = PROCESSOR_486; + } + } + if (TARGET_386) + { + if (x86_cpu != PROCESSOR_DEFAULT) + { + error ("conflicting -mX86 : using blend"); + blend = 1; + x86_cpu = PROCESSOR_486; + target_flags &= ~(TARGET_386_SWITCH); + target_flags &= ~(TARGET_PENTIUM_SWITCH); + target_flags |= (TARGET_486_SWITCH); + } + else + { + x86_cpu = PROCESSOR_386; + } + } - case LT: - xops[1] = GEN_INT (0x45); - xops[2] = GEN_INT (0x01); - output_asm_insn (AS2 (and%B0,%1,%h0), xops); - output_asm_insn (AS2 (cmp%B0,%2,%h0), xops); - /* je label */ - break; - case GE: - xops[1] = GEN_INT (0x05); - output_asm_insn (AS2 (and%B0,%1,%h0), xops); - /* je label */ - break; + } +#endif + if (opt_level >= 4) + { + if (TARGET_486) + { + if (opt_level == 4 + && !flag_no_interleave_stack_non_stack) + { + flag_interleave_stack_non_stack = 1; + flag_schedule_insns = 1; + } + } +#if 0 + if(TARGET_BLEND) + { + if (!flag_no_risc) + flag_risc = 1; + if (!flag_no_risc_const) + flag_risc_const = 1; + if (!flag_no_recombine) + flag_recombine = 1; + } +#endif + if (TARGET_PENTIUM) + { + if (!flag_no_risc) + flag_risc = 1; + if (!flag_no_risc_const) + flag_risc_const = 1; + /*if (!flag_no_recombine) + flag_recombine = 1;*/ + if (opt_level == 4 + && !flag_no_schedule_stack_reg_insns) + { + flag_schedule_stack_reg_insns = 1; + flag_schedule_insns = 1; + } + if (opt_level == 4 + && !flag_no_interleave_stack_non_stack) + { + flag_interleave_stack_non_stack = 1; + flag_schedule_insns = 1; + } + } + } +} - case LE: - xops[1] = GEN_INT (0x45); - xops[2] = GEN_INT (0x40); - output_asm_insn (AS2 (and%B0,%1,%h0), xops); - output_asm_insn (AS1 (dec%B0,%h0), xops); - output_asm_insn (AS2 (cmp%B0,%2,%h0), xops); - /* jb label */ - break; - case EQ: - xops[1] = GEN_INT (0x45); - xops[2] = GEN_INT (0x40); - output_asm_insn (AS2 (and%B0,%1,%h0), xops); - output_asm_insn (AS2 (cmp%B0,%2,%h0), xops); - /* je label */ - break; - case NE: - xops[1] = GEN_INT (0x44); - xops[2] = GEN_INT (0x40); - output_asm_insn (AS2 (and%B0,%1,%h0), xops); - output_asm_insn (AS2 (xor%B0,%2,%h0), xops); - /* jne label */ - break; - case GTU: - case LTU: - case GEU: - case LEU: - default: - abort (); +optimization_options (level) + int level; +{ + opt_level = level; + if (level > 0) + { + flag_opt_reg_use = 1; + flag_reduce_index_givs = 1; } - RET; + if (level >= 2) + { +#ifdef INSN_SCHEDULING + flag_schedule_insns = 0; + flag_schedule_insns_after_reload = 0; +#endif + } + if (level >= 3) + { + flag_inline_functions = 1; + flag_jump_back = 1; + flag_copy_prop = 1; + flag_compare_elim = 1; + flag_sftwr_pipe = 1; + flag_omit_frame_pointer = 1; + flag_reg_reg_copy_opt = 1; + flag_opt_reg_stack = 1; + flag_loop_after_global = 1; + flag_peep_spills = 1; + flag_replace_stack_mem = 1; + flag_opt_jumps_out = 1; + flag_replace_mem = 1; + flag_correct_cse_mistakes = 1; + flag_push_load_into_loop = 1; + flag_replace_reload_regs = 1; + flag_sign_extension_elim = 1; + flag_lift_stores = 1; + flag_runtime_lift_stores = 1; + } + if (level >= 4) + { +#ifdef INSN_SCHEDULING + flag_schedule_insns_after_reload = 1; + flag_swap_for_agi = 1; + if (TARGET_PENTIUM) + { + flag_risc = 1; + flag_risc_const = 1; + /*flag_recombine = 1;*/ + if (level == 4) + { + flag_schedule_stack_reg_insns = 1; + flag_schedule_insns = 1; + } + } +#endif + } + if (level >= 5) + { +#ifdef INSN_SCHEDULING + flag_schedule_insns = 1; +#endif + } + if (flag_no_risc) + flag_risc = 0; + if (flag_no_risc_const) + flag_risc_const = 0; + if (flag_no_recombine) + flag_recombine = 0; + if (flag_no_risc_mem_dest) + flag_risc_mem_dest = 0; } - -#define MAX_386_STACK_LOCALS 2 -static rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS]; +/* intel1 */ -/* Define the structure for the machine field in struct function. */ -struct machine_function +int +is_fp_insn (insn) + rtx insn; { - rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS]; -}; + if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET + && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode + || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode)) + { + return (1); + } + return (0); +} -/* Functions to save and restore i386_stack_locals. - These will be called, via pointer variables, - from push_function_context and pop_function_context. */ -void -save_386_machine_status (p) - struct function *p; +/* + Return 1 if the mode of the SET_DEST of insn is floating point + and it is not an fld or a move from memory to memory. + Otherwise return 0 +*/ +int +is_fp_dest (insn) + rtx insn; { - p->machine = (struct machine_function *) xmalloc (sizeof i386_stack_locals); - bcopy ((char *) i386_stack_locals, (char *) p->machine->i386_stack_locals, - sizeof i386_stack_locals); + if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET + && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode + || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode) + && GET_CODE (SET_DEST (PATTERN (insn))) == REG + && REGNO (SET_DEST (PATTERN (insn))) >= FIRST_FLOAT_REG + && GET_CODE (SET_SRC (insn)) != MEM + ) + { + return (1); + } + return (0); } -void -restore_386_machine_status (p) - struct function *p; +/* + Return 1 if the mode of the SET_DEST floating point and is memory + and the source is a register. +*/ +int +is_fp_store (insn) + rtx insn; { - bcopy ((char *) p->machine->i386_stack_locals, (char *) i386_stack_locals, - sizeof i386_stack_locals); - free (p->machine); + if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET + && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode + || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode) + && GET_CODE (SET_DEST (PATTERN (insn))) == MEM + && GET_CODE (SET_SRC (PATTERN (insn))) == REG + ) + { + return (1); + } + return (0); } -/* Clear stack slot assignments remembered from previous functions. - This is called from INIT_EXPANDERS once before RTL is emitted for each - function. */ -void -clear_386_stack_locals () +/* + Return 1 if dep_insn sets a register which insn uses as a base + or index to reference memory. + otherwise return 0 +*/ +int +agi_dependent (insn, dep_insn) + rtx insn, dep_insn; { - enum machine_mode mode; - int n; + if (GET_CODE (dep_insn) == INSN && GET_CODE (PATTERN (dep_insn)) == SET + && GET_CODE (SET_DEST (PATTERN (dep_insn))) == REG) + { + return (reg_mentioned_in_mem (SET_DEST (PATTERN (dep_insn)), insn)); + } + if (GET_CODE (dep_insn) == INSN && GET_CODE (PATTERN (dep_insn)) == SET + && GET_CODE (SET_DEST (PATTERN (dep_insn))) == MEM + && push_operand (SET_DEST (PATTERN (dep_insn)), + GET_MODE (SET_DEST (PATTERN (dep_insn)))) + ) + { + return (reg_mentioned_in_mem (stack_pointer_rtx, insn)); + } + + return (0); +} - for (mode = VOIDmode; (int) mode < (int) MAX_MACHINE_MODE; - mode = (enum machine_mode) ((int) mode + 1)) - for (n = 0; n < MAX_386_STACK_LOCALS; n++) - i386_stack_locals[(int) mode][n] = NULL_RTX; +/* + Return 1 if reg is used in rtl as a base or index for a memory ref + otherwise return 0. +*/ +int +reg_mentioned_in_mem (reg, rtl) + rtx reg, rtl; +{ + register char *fmt; + register int i; + register enum rtx_code code; - /* Arrange to save and restore i386_stack_locals around nested functions. */ - save_machine_status = save_386_machine_status; - restore_machine_status = restore_386_machine_status; -} + if (rtl == NULL) + return (0); -/* Return a MEM corresponding to a stack slot with mode MODE. - Allocate a new slot if necessary. + code = GET_CODE (rtl); - The RTL for a function can have several slots available: N is - which slot to use. */ + switch (code) + { + case HIGH: + case CONST_INT: + case CONST: + case CONST_DOUBLE: + case SYMBOL_REF: + case LABEL_REF: + case PC: + case CC0: + case SUBREG: + return (0); -rtx -assign_386_stack_local (mode, n) - enum machine_mode mode; - int n; -{ - if (n < 0 || n >= MAX_386_STACK_LOCALS) - abort (); - if (i386_stack_locals[(int) mode][n] == NULL_RTX) - i386_stack_locals[(int) mode][n] - = assign_stack_local (mode, GET_MODE_SIZE (mode), 0); + } - return i386_stack_locals[(int) mode][n]; + if (code == MEM && reg_mentioned_p (reg, rtl)) + { + return (1); + } + + fmt = GET_RTX_FORMAT (code); + + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'E') + { + register int j; + for (j = XVECLEN (rtl, i) - 1; j >= 0; j--) + if (reg_mentioned_in_mem (reg, XVECEXP (rtl, i, j))) + return 1; + } + else if (fmt[i] == 'e' + && reg_mentioned_in_mem (reg, XEXP (rtl, i))) + return 1; + } + return (0); } + diff -r -u -H -N gcc-2.6.3/config/i386/i386.c.old gcc-i2.6.3/config/i386/i386.c.old --- gcc-2.6.3/config/i386/i386.c.old Wed Dec 31 19:00:00 1969 +++ gcc-i2.6.3/config/i386/i386.c.old Thu Feb 16 12:42:13 1995 @@ -0,0 +1,3864 @@ +/* Subroutines for insn-output.c for Intel X86. + Copyright (C) 1988, 1992, 1994 Free Software Foundation, Inc. + + Pentium cpu support and other enhancements by Tevi Devor Intel Corp. + (tevi@iil.intel.com). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#include <stdio.h> +#include <setjmp.h> +#include "config.h" +#include "rtl.h" +#include "regs.h" + +/* HACK */ +#ifndef REG_ALLOC_ORDER +#define REG_ALLOC_ORDER +#endif + +#include "hard-reg-set.h" +#include "real.h" +#include "insn-config.h" +#include "conditions.h" +#include "insn-flags.h" +#include "output.h" +#include "insn-attr.h" +#include "tree.h" +#include "flags.h" +#include "function.h" + +/* intel1 Need the EXTRA_CONSTRAINT - changed s to */ +#if 0 +#ifdef EXTRA_CONSTRAINT +/* If EXTRA_CONSTRAINT is defined, then the 'S' + constraint in REG_CLASS_FROM_LETTER will no longer work, and various + asm statements that need 'S' for class SIREG will break. */ + error EXTRA_CONSTRAINT conflicts with S constraint letter +/* The previous line used to be #error, but some compilers barf + even if the conditional was untrue. */ +#endif +#endif + +/* which cpu are we scheduling for intel1*/ +enum processor_type x86_cpu; + +#define AT_BP(mode) (gen_rtx (MEM, (mode), frame_pointer_rtx)) + +extern FILE *asm_out_file; +extern char *strcat (); + +char *singlemove_string (); +char *output_move_const_single (); +char *output_fp_cc0_set (); + +/* intel1 */ +static int opt_level=0; + +char *hi_reg_name[] = HI_REGISTER_NAMES; +char *qi_reg_name[] = QI_REGISTER_NAMES; +char *qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES; + +/* Array of the smallest class containing reg number REGNO, indexed by + REGNO. Used by REGNO_REG_CLASS in i386.h. */ + +enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] = +{ + /* ax, dx, cx, bx */ + AREG, DREG, CREG, BREG, + /* si, di, bp, sp */ + SIREG, DIREG, INDEX_REGS, GENERAL_REGS, + /* FP registers */ + FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS, + FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, + /* arg pointer */ + INDEX_REGS +}; + +/* Test and compare insns in i386.md store the information needed to + generate branch and scc insns here. */ + +struct rtx_def *i386_compare_op0 = NULL_RTX; +struct rtx_def *i386_compare_op1 = NULL_RTX; +struct rtx_def *(*i386_compare_gen)(), *(*i386_compare_gen_eq)(); + +/* Register allocation order */ +char *i386_reg_alloc_order = (char *)0; +static char regs_allocated[FIRST_PSEUDO_REGISTER]; + + +/* Sometimes certain combinations of command options do not make + sense on a particular target machine. You can define a macro + `OVERRIDE_OPTIONS' to take account of this. This macro, if + defined, is executed once just after all the command options have + been parsed. + + Don't use this macro to turn on various extra optimizations for + `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ + +void +override_options () +{ + int ch, i, regno; + +#ifdef SUBTARGET_OVERRIDE_OPTIONS + SUBTARGET_OVERRIDE_OPTIONS; +#endif + + /* Validate registers in register allocation order */ + if (i386_reg_alloc_order) + { + for (i = 0; (ch = i386_reg_alloc_order[i]) != '\0'; i++) + { + switch (ch) + { + case 'a': regno = 0; break; + case 'd': regno = 1; break; + case 'c': regno = 2; break; + case 'b': regno = 3; break; + case 'S': regno = 4; break; + case 'D': regno = 5; break; + case 'B': regno = 6; break; + + default: fatal ("Register '%c' is unknown", ch); + } + + if (regs_allocated[regno]) + fatal ("Register '%c' was already specified in the allocation order", ch); + + regs_allocated[regno] = 1; + } + } +} + +/* A C statement (sans semicolon) to choose the order in which to + allocate hard registers for pseudo-registers local to a basic + block. + + Store the desired register order in the array `reg_alloc_order'. + Element 0 should be the register to allocate first; element 1, the + next register; and so on. + + The macro body should not assume anything about the contents of + `reg_alloc_order' before execution of the macro. + + On most machines, it is not necessary to define this macro. */ + +void +order_regs_for_local_alloc () +{ + int i, ch, order, regno; + + /* User specified the register allocation order */ + if (i386_reg_alloc_order) + { + for (i = order = 0; (ch = i386_reg_alloc_order[i]) != '\0'; i++) + { + switch (ch) + { + case 'a': regno = 0; break; + case 'd': regno = 1; break; + case 'c': regno = 2; break; + case 'b': regno = 3; break; + case 'S': regno = 4; break; + case 'D': regno = 5; break; + case 'B': regno = 6; break; + } + + reg_alloc_order[order++] = regno; + } + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + { + if (!regs_allocated[i]) + reg_alloc_order[order++] = i; + } + } + + /* If users did not specify a register allocation order, favor eax + normally except if DImode variables are used, in which case + favor edx before eax, which seems to cause less spill register + not found messages. */ + else + { + rtx insn; + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + reg_alloc_order[i] = i; + + if (optimize) + { + int use_dca = FALSE; + + for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) + { + if (GET_CODE (insn) == INSN) + { + rtx set = NULL_RTX; + rtx pattern = PATTERN (insn); + + if (GET_CODE (pattern) == SET) + set = pattern; + + else if ((GET_CODE (pattern) == PARALLEL + || GET_CODE (pattern) == SEQUENCE) + && GET_CODE (XVECEXP (pattern, 0, 0)) == SET) + set = XVECEXP (pattern, 0, 0); + + if (set && GET_MODE (SET_SRC (set)) == DImode) + { + use_dca = TRUE; + break; + } + } + } + + if (use_dca) + { + reg_alloc_order[0] = 1; /* edx */ + reg_alloc_order[1] = 2; /* ecx */ + reg_alloc_order[2] = 0; /* eax */ + } + } + } +} + + +/* Output an insn whose source is a 386 integer register. SRC is the + rtx for the register, and TEMPLATE is the op-code template. SRC may + be either SImode or DImode. + + The template will be output with operands[0] as SRC, and operands[1] + as a pointer to the top of the 386 stack. So a call from floatsidf2 + would look like this: + + output_op_from_reg (operands[1], AS1 (fild%z0,%1)); + + where %z0 corresponds to the caller's operands[1], and is used to + emit the proper size suffix. + + ??? Extend this to handle HImode - a 387 can load and store HImode + values directly. */ + +void +output_op_from_reg (src, template) + rtx src; + char *template; +{ + rtx xops[4]; + int size = GET_MODE_SIZE (GET_MODE (src)); + + xops[0] = src; + xops[1] = AT_SP (Pmode); + xops[2] = GEN_INT (size); + xops[3] = stack_pointer_rtx; + + if (size > UNITS_PER_WORD) + { + rtx high; + if (size > 2 * UNITS_PER_WORD) + { + high = gen_rtx (REG, SImode, REGNO (src) + 2); + output_asm_insn (AS1 (push%L0,%0), &high); + } + high = gen_rtx (REG, SImode, REGNO (src) + 1); + output_asm_insn (AS1 (push%L0,%0), &high); + } + output_asm_insn (AS1 (push%L0,%0), &src); + + output_asm_insn (template, xops); + + output_asm_insn (AS2 (add%L3,%2,%3), xops); +} + +/* Output an insn to pop an value from the 387 top-of-stack to 386 + register DEST. The 387 register stack is popped if DIES is true. If + the mode of DEST is an integer mode, a `fist' integer store is done, + otherwise a `fst' float store is done. */ + +void +output_to_reg (dest, dies) + rtx dest; + int dies; +{ + rtx xops[4]; + int size = GET_MODE_SIZE (GET_MODE (dest)); + + xops[0] = AT_SP (Pmode); + xops[1] = stack_pointer_rtx; + xops[2] = GEN_INT (size); + xops[3] = dest; + + output_asm_insn (AS2 (sub%L1,%2,%1), xops); + + if (GET_MODE_CLASS (GET_MODE (dest)) == MODE_INT) + { + if (dies) + output_asm_insn (AS1 (fistp%z3,%y0), xops); + else + output_asm_insn (AS1 (fist%z3,%y0), xops); + } + else if (GET_MODE_CLASS (GET_MODE (dest)) == MODE_FLOAT) + { + if (dies) + output_asm_insn (AS1 (fstp%z3,%y0), xops); + else + { + if (GET_MODE (dest) == XFmode) + { + output_asm_insn (AS1 (fstp%z3,%y0), xops); + output_asm_insn (AS1 (fld%z3,%y0), xops); + } + else + output_asm_insn (AS1 (fst%z3,%y0), xops); + } + } + else + abort (); + + output_asm_insn (AS1 (pop%L0,%0), &dest); + + if (size > UNITS_PER_WORD) + { + dest = gen_rtx (REG, SImode, REGNO (dest) + 1); + output_asm_insn (AS1 (pop%L0,%0), &dest); + if (size > 2 * UNITS_PER_WORD) + { + dest = gen_rtx (REG, SImode, REGNO (dest) + 1); + output_asm_insn (AS1 (pop%L0,%0), &dest); + } + } +} + +char * +singlemove_string (operands) + rtx *operands; +{ + rtx x; + if (GET_CODE (operands[0]) == MEM + && GET_CODE (x = XEXP (operands[0], 0)) == PRE_DEC) + { + if (XEXP (x, 0) != stack_pointer_rtx) + abort (); + return "push%L1 %1"; + } + else if (GET_CODE (operands[1]) == CONST_DOUBLE) + { + return output_move_const_single (operands); + } + else if (GET_CODE (operands[0]) == REG || GET_CODE (operands[1]) == REG) + return AS2 (mov%L0,%1,%0); + else if (CONSTANT_P (operands[1])) + return AS2 (mov%L0,%1,%0); + else + { + output_asm_insn ("push%L1 %1", operands); + return "pop%L0 %0"; + } +} + +/* Return a REG that occurs in ADDR with coefficient 1. + ADDR can be effectively incremented by incrementing REG. */ + +static rtx +find_addr_reg (addr) + rtx addr; +{ + while (GET_CODE (addr) == PLUS) + { + if (GET_CODE (XEXP (addr, 0)) == REG) + addr = XEXP (addr, 0); + else if (GET_CODE (XEXP (addr, 1)) == REG) + addr = XEXP (addr, 1); + else if (CONSTANT_P (XEXP (addr, 0))) + addr = XEXP (addr, 1); + else if (CONSTANT_P (XEXP (addr, 1))) + addr = XEXP (addr, 0); + else + abort (); + } + if (GET_CODE (addr) == REG) + return addr; + abort (); +} + + +/* Output an insn to add the constant N to the register X. */ + +static void +asm_add (n, x) + int n; + rtx x; +{ + rtx xops[2]; + xops[0] = x; + + if (n == -1) + output_asm_insn (AS1 (dec%L0,%0), xops); + else if (n == 1) + output_asm_insn (AS1 (inc%L0,%0), xops); + else if (n < 0) + { + xops[1] = GEN_INT (-n); + output_asm_insn (AS2 (sub%L0,%1,%0), xops); + } + else if (n > 0) + { + xops[1] = GEN_INT (n); + output_asm_insn (AS2 (add%L0,%1,%0), xops); + } +} + + +/* Output assembler code to perform a doubleword move insn + with operands OPERANDS. */ + +char * +output_move_double (operands) + rtx *operands; +{ + enum {REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1; + rtx latehalf[2]; + rtx middlehalf[2]; + rtx xops[2]; + rtx addreg0 = 0, addreg1 = 0; + int dest_overlapped_low = 0; + int size = GET_MODE_SIZE (GET_MODE (operands[1])); + + middlehalf[0] = 0; + middlehalf[1] = 0; + + /* First classify both operands. */ + + if (REG_P (operands[0])) + optype0 = REGOP; + else if (offsettable_memref_p (operands[0])) + optype0 = OFFSOP; + else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) + optype0 = POPOP; + else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) + optype0 = PUSHOP; + else if (GET_CODE (operands[0]) == MEM) + optype0 = MEMOP; + else + optype0 = RNDOP; + + if (REG_P (operands[1])) + optype1 = REGOP; + else if (CONSTANT_P (operands[1])) + optype1 = CNSTOP; + else if (offsettable_memref_p (operands[1])) + optype1 = OFFSOP; + else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC) + optype1 = POPOP; + else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) + optype1 = PUSHOP; + else if (GET_CODE (operands[1]) == MEM) + optype1 = MEMOP; + else + optype1 = RNDOP; + + /* Check for the cases that the operand constraints are not + supposed to allow to happen. Abort if we get one, + because generating code for these cases is painful. */ + + if (optype0 == RNDOP || optype1 == RNDOP) + abort (); + + /* If one operand is decrementing and one is incrementing + decrement the former register explicitly + and change that operand into ordinary indexing. */ + + if (optype0 == PUSHOP && optype1 == POPOP) + { + /* ??? Can this ever happen on i386? */ + operands[0] = XEXP (XEXP (operands[0], 0), 0); + asm_add (-size, operands[0]); + if (GET_MODE (operands[1]) == XFmode) + operands[0] = gen_rtx (MEM, XFmode, operands[0]); + else if (GET_MODE (operands[0]) == DFmode) + operands[0] = gen_rtx (MEM, DFmode, operands[0]); + else + operands[0] = gen_rtx (MEM, DImode, operands[0]); + optype0 = OFFSOP; + } + + if (optype0 == POPOP && optype1 == PUSHOP) + { + /* ??? Can this ever happen on i386? */ + operands[1] = XEXP (XEXP (operands[1], 0), 0); + asm_add (-size, operands[1]); + if (GET_MODE (operands[1]) == XFmode) + operands[1] = gen_rtx (MEM, XFmode, operands[1]); + else if (GET_MODE (operands[1]) == DFmode) + operands[1] = gen_rtx (MEM, DFmode, operands[1]); + else + operands[1] = gen_rtx (MEM, DImode, operands[1]); + optype1 = OFFSOP; + } + + /* If an operand is an unoffsettable memory ref, find a register + we can increment temporarily to make it refer to the second word. */ + + if (optype0 == MEMOP) + addreg0 = find_addr_reg (XEXP (operands[0], 0)); + + if (optype1 == MEMOP) + addreg1 = find_addr_reg (XEXP (operands[1], 0)); + + /* Ok, we can do one word at a time. + Normally we do the low-numbered word first, + but if either operand is autodecrementing then we + do the high-numbered word first. + + In either case, set up in LATEHALF the operands to use + for the high-numbered word and in some cases alter the + operands in OPERANDS to be suitable for the low-numbered word. */ + + if (size == 12) + { + if (optype0 == REGOP) + { + middlehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 2); + } + else if (optype0 == OFFSOP) + { + middlehalf[0] = adj_offsettable_operand (operands[0], 4); + latehalf[0] = adj_offsettable_operand (operands[0], 8); + } + else + { + middlehalf[0] = operands[0]; + latehalf[0] = operands[0]; + } + + if (optype1 == REGOP) + { + middlehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); + latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2); + } + else if (optype1 == OFFSOP) + { + middlehalf[1] = adj_offsettable_operand (operands[1], 4); + latehalf[1] = adj_offsettable_operand (operands[1], 8); + } + else if (optype1 == CNSTOP) + { + if (GET_CODE (operands[1]) == CONST_DOUBLE) + { + REAL_VALUE_TYPE r; long l[3]; + + REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); + REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l); + operands[1] = GEN_INT (l[0]); + middlehalf[1] = GEN_INT (l[1]); + latehalf[1] = GEN_INT (l[2]); + } + else if (CONSTANT_P (operands[1])) + /* No non-CONST_DOUBLE constant should ever appear here. */ + abort (); + } + else + { + middlehalf[1] = operands[1]; + latehalf[1] = operands[1]; + } + } + else /* size is not 12: */ + { + if (optype0 == REGOP) + latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + else if (optype0 == OFFSOP) + latehalf[0] = adj_offsettable_operand (operands[0], 4); + else + latehalf[0] = operands[0]; + + if (optype1 == REGOP) + latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); + else if (optype1 == OFFSOP) + latehalf[1] = adj_offsettable_operand (operands[1], 4); + else if (optype1 == CNSTOP) + { + if (GET_CODE (operands[1]) == CONST_DOUBLE) + split_double (operands[1], &operands[1], &latehalf[1]); + else if (CONSTANT_P (operands[1])) + { + /* ??? jrv: Can this really happen? A DImode constant + that isn't a CONST_DOUBLE? */ + if (GET_CODE (operands[1]) == CONST_INT + && INTVAL (operands[1]) < 0) + latehalf[1] = constm1_rtx; + else + latehalf[1] = const0_rtx; + } + } + else + latehalf[1] = operands[1]; + } + + /* If insn is effectively movd N (sp),-(sp) then we will do the + high word first. We should use the adjusted operand 1 + (which is N+4 (sp) or N+8 (sp)) + for the low word and middle word as well, + to compensate for the first decrement of sp. */ + if (optype0 == PUSHOP + && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM + && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1])) + middlehalf[1] = operands[1] = latehalf[1]; + + /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)), + if the upper part of reg N does not appear in the MEM, arrange to + emit the move late-half first. Otherwise, compute the MEM address + into the upper part of N and use that as a pointer to the memory + operand. */ + if (optype0 == REGOP + && (optype1 == OFFSOP || optype1 == MEMOP)) + { + if (reg_mentioned_p (operands[0], XEXP (operands[1], 0)) + && reg_mentioned_p (latehalf[0], XEXP (operands[1], 0))) + { + /* If both halves of dest are used in the src memory address, + compute the address into latehalf of dest. */ +compadr: + xops[0] = latehalf[0]; + xops[1] = XEXP (operands[1], 0); + output_asm_insn (AS2 (lea%L0,%a1,%0), xops); + if( GET_MODE (operands[1]) == XFmode ) + { +/* abort (); */ + operands[1] = gen_rtx (MEM, XFmode, latehalf[0]); + middlehalf[1] = adj_offsettable_operand (operands[1], size-8); + latehalf[1] = adj_offsettable_operand (operands[1], size-4); + } + else + { + operands[1] = gen_rtx (MEM, DImode, latehalf[0]); + latehalf[1] = adj_offsettable_operand (operands[1], size-4); + } + } + else if (size == 12 + && reg_mentioned_p (middlehalf[0], XEXP (operands[1], 0))) + { + /* Check for two regs used by both source and dest. */ + if (reg_mentioned_p (operands[0], XEXP (operands[1], 0)) + || reg_mentioned_p (latehalf[0], XEXP (operands[1], 0))) + goto compadr; + + /* JRV says this can't happen: */ + if (addreg0 || addreg1) + abort(); + + /* Only the middle reg conflicts; simply put it last. */ + output_asm_insn (singlemove_string (operands), operands); + output_asm_insn (singlemove_string (latehalf), latehalf); + output_asm_insn (singlemove_string (middlehalf), middlehalf); + return ""; + } + else if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))) + /* If the low half of dest is mentioned in the source memory + address, the arrange to emit the move late half first. */ + dest_overlapped_low = 1; + } + + /* If one or both operands autodecrementing, + do the two words, high-numbered first. */ + + /* Likewise, the first move would clobber the source of the second one, + do them in the other order. This happens only for registers; + such overlap can't happen in memory unless the user explicitly + sets it up, and that is an undefined circumstance. */ + +/* + if (optype0 == PUSHOP || optype1 == PUSHOP + || (optype0 == REGOP && optype1 == REGOP + && REGNO (operands[0]) == REGNO (latehalf[1])) + || dest_overlapped_low) +*/ + if (optype0 == PUSHOP || optype1 == PUSHOP + || (optype0 == REGOP && optype1 == REGOP + && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1])) + || REGNO (operands[0]) == REGNO (latehalf[1]))) + || dest_overlapped_low) + { + /* Make any unoffsettable addresses point at high-numbered word. */ + if (addreg0) + asm_add (size-4, addreg0); + if (addreg1) + asm_add (size-4, addreg1); + + /* Do that word. */ + output_asm_insn (singlemove_string (latehalf), latehalf); + + /* Undo the adds we just did. */ + if (addreg0) + asm_add (-4, addreg0); + if (addreg1) + asm_add (-4, addreg1); + + if (size == 12) + { + output_asm_insn (singlemove_string (middlehalf), middlehalf); + if (addreg0) + asm_add (-4, addreg0); + if (addreg1) + asm_add (-4, addreg1); + } + + /* Do low-numbered word. */ + return singlemove_string (operands); + } + + /* Normal case: do the two words, low-numbered first. */ + + output_asm_insn (singlemove_string (operands), operands); + + /* Do the middle one of the three words for long double */ + if (size == 12) + { + if (addreg0) + asm_add (4, addreg0); + if (addreg1) + asm_add (4, addreg1); + + output_asm_insn (singlemove_string (middlehalf), middlehalf); + } + + /* Make any unoffsettable addresses point at high-numbered word. */ + if (addreg0) + asm_add (4, addreg0); + if (addreg1) + asm_add (4, addreg1); + + /* Do that word. */ + output_asm_insn (singlemove_string (latehalf), latehalf); + + /* Undo the adds we just did. */ + if (addreg0) + asm_add (4-size, addreg0); + if (addreg1) + asm_add (4-size, addreg1); + + return ""; +} + + +#define MAX_TMPS 2 /* max temporary registers used */ + +/* Output the appropriate code to move push memory on the stack */ + +char * +output_move_pushmem (operands, insn, length, tmp_start, n_operands) + rtx operands[]; + rtx insn; + int length; + int tmp_start; + int n_operands; +{ + + struct { + char *load; + char *push; + rtx xops[2]; + } tmp_info[MAX_TMPS]; + + rtx src = operands[1]; + int max_tmps = 0; + int offset = 0; + int stack_p = reg_overlap_mentioned_p (stack_pointer_rtx, src); + int stack_offset = 0; + int i, num_tmps; + rtx xops[1]; + + if (!offsettable_memref_p (src)) + fatal_insn ("Source is not offsettable", insn); + + if ((length & 3) != 0) + fatal_insn ("Pushing non-word aligned size", insn); + + /* Figure out which temporary registers we have available */ + for (i = tmp_start; i < n_operands; i++) + { + if (GET_CODE (operands[i]) == REG) + { + if (reg_overlap_mentioned_p (operands[i], src)) + continue; + + tmp_info[ max_tmps++ ].xops[1] = operands[i]; + if (max_tmps == MAX_TMPS) + break; + } + } + + if (max_tmps == 0) + for (offset = length - 4; offset >= 0; offset -= 4) + { + xops[0] = adj_offsettable_operand (src, offset + stack_offset); + output_asm_insn (AS1(push%L0,%0), xops); + if (stack_p) + stack_offset += 4; + } + + else + for (offset = length - 4; offset >= 0; ) + { + for (num_tmps = 0; num_tmps < max_tmps && offset >= 0; num_tmps++) + { + tmp_info[num_tmps].load = AS2(mov%L0,%0,%1); + tmp_info[num_tmps].push = AS1(push%L0,%1); + tmp_info[num_tmps].xops[0] = adj_offsettable_operand (src, offset + stack_offset); + offset -= 4; + } + + for (i = 0; i < num_tmps; i++) + output_asm_insn (tmp_info[i].load, tmp_info[i].xops); + + for (i = 0; i < num_tmps; i++) + output_asm_insn (tmp_info[i].push, tmp_info[i].xops); + + if (stack_p) + stack_offset += 4*num_tmps; + } + + return ""; +} + + + +/* Output the appropriate code to move data between two memory locations */ + +char * +output_move_memory (operands, insn, length, tmp_start, n_operands) + rtx operands[]; + rtx insn; + int length; + int tmp_start; + int n_operands; +{ + struct { + char *load; + char *store; + rtx xops[3]; + } tmp_info[MAX_TMPS]; + + rtx dest = operands[0]; + rtx src = operands[1]; + rtx qi_tmp = NULL_RTX; + int max_tmps = 0; + int offset = 0; + int i, num_tmps; + rtx xops[3]; + + if (GET_CODE (dest) == MEM + && GET_CODE (XEXP (dest, 0)) == PRE_INC + && XEXP (XEXP (dest, 0), 0) == stack_pointer_rtx) + return output_move_pushmem (operands, insn, length, tmp_start, n_operands); + + if (!offsettable_memref_p (src)) + fatal_insn ("Source is not offsettable", insn); + + if (!offsettable_memref_p (dest)) + fatal_insn ("Destination is not offsettable", insn); + + /* Figure out which temporary registers we have available */ + for (i = tmp_start; i < n_operands; i++) + { + if (GET_CODE (operands[i]) == REG) + { + if ((length & 1) != 0 && !qi_tmp && QI_REG_P (operands[i])) + qi_tmp = operands[i]; + + if (reg_overlap_mentioned_p (operands[i], dest)) + fatal_insn ("Temporary register overlaps the destination", insn); + + if (reg_overlap_mentioned_p (operands[i], src)) + fatal_insn ("Temporary register overlaps the source", insn); + + tmp_info[ max_tmps++ ].xops[2] = operands[i]; + if (max_tmps == MAX_TMPS) + break; + } + } + + if (max_tmps == 0) + fatal_insn ("No scratch registers were found to do memory->memory moves", insn); + + if ((length & 1) != 0) + { + if (!qi_tmp) + fatal_insn ("No byte register found when moving odd # of bytes.", insn); + } + + while (length > 1) + { + for (num_tmps = 0; num_tmps < max_tmps; num_tmps++) + { + if (length >= 4) + { + tmp_info[num_tmps].load = AS2(mov%L0,%1,%2); + tmp_info[num_tmps].store = AS2(mov%L0,%2,%0); + tmp_info[num_tmps].xops[0] = adj_offsettable_operand (dest, offset); + tmp_info[num_tmps].xops[1] = adj_offsettable_operand (src, offset); + offset += 4; + length -= 4; + } + else if (length >= 2) + { + tmp_info[num_tmps].load = AS2(mov%W0,%1,%2); + tmp_info[num_tmps].store = AS2(mov%W0,%2,%0); + tmp_info[num_tmps].xops[0] = adj_offsettable_operand (dest, offset); + tmp_info[num_tmps].xops[1] = adj_offsettable_operand (src, offset); + offset += 2; + length -= 2; + } + else + break; + } + + for (i = 0; i < num_tmps; i++) + output_asm_insn (tmp_info[i].load, tmp_info[i].xops); + + for (i = 0; i < num_tmps; i++) + output_asm_insn (tmp_info[i].store, tmp_info[i].xops); + } + + if (length == 1) + { + xops[0] = adj_offsettable_operand (dest, offset); + xops[1] = adj_offsettable_operand (src, offset); + xops[2] = qi_tmp; + output_asm_insn (AS2(mov%B0,%1,%2), xops); + output_asm_insn (AS2(mov%B0,%2,%0), xops); + } + + return ""; +} + + +int +standard_80387_constant_p (x) + rtx x; +{ +#if ! defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC) + REAL_VALUE_TYPE d; + jmp_buf handler; + int is0, is1; + + if (setjmp (handler)) + return 0; + + set_float_handler (handler); + REAL_VALUE_FROM_CONST_DOUBLE (d, x); + is0 = REAL_VALUES_EQUAL (d, dconst0); + is1 = REAL_VALUES_EQUAL (d, dconst1); + set_float_handler (NULL_PTR); + + if (is0) + return 1; + + if (is1) + return 2; + + /* Note that on the 80387, other constants, such as pi, + are much slower to load as standard constants + than to load from doubles in memory! */ +#endif + + return 0; +} + +char * +output_move_const_single (operands) + rtx *operands; +{ + if (FP_REG_P (operands[0])) + { + int conval = standard_80387_constant_p (operands[1]); + + if (conval == 1) + return "fldz"; + + if (conval == 2) + return "fld1"; + } + if (GET_CODE (operands[1]) == CONST_DOUBLE) + { + REAL_VALUE_TYPE r; long l; + + if (GET_MODE (operands[1]) == XFmode) + abort (); + + REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); + REAL_VALUE_TO_TARGET_SINGLE (r, l); + operands[1] = GEN_INT (l); + } + return singlemove_string (operands); +} + +/* Returns 1 if OP is either a symbol reference or a sum of a symbol + reference and a constant. */ + +int +symbolic_operand (op, mode) + register rtx op; + enum machine_mode mode; +{ + switch (GET_CODE (op)) + { + case SYMBOL_REF: + case LABEL_REF: + return 1; + case CONST: + op = XEXP (op, 0); + return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF + || GET_CODE (XEXP (op, 0)) == LABEL_REF) + && GET_CODE (XEXP (op, 1)) == CONST_INT); + default: + return 0; + } +} + +/* Test for a valid operand for a call instruction. + Don't allow the arg pointer register or virtual regs + since they may change into reg + const, which the patterns + can't handle yet. */ + +int +call_insn_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (GET_CODE (op) == MEM + && ((CONSTANT_ADDRESS_P (XEXP (op, 0)) + /* This makes a difference for PIC. */ + && general_operand (XEXP (op, 0), Pmode)) + || (GET_CODE (XEXP (op, 0)) == REG + && XEXP (op, 0) != arg_pointer_rtx + && !(REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER + && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER)))) + return 1; + return 0; +} + +/* Like call_insn_operand but allow (mem (symbol_ref ...)) + even if pic. */ + +int +expander_call_insn_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (GET_CODE (op) == MEM + && (CONSTANT_ADDRESS_P (XEXP (op, 0)) + || (GET_CODE (XEXP (op, 0)) == REG + && XEXP (op, 0) != arg_pointer_rtx + && !(REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER + && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER)))) + return 1; + return 0; +} + +/* Returns 1 if OP contains a symbol reference */ + +int +symbolic_reference_mentioned_p (op) + rtx op; +{ + register char *fmt; + register int i; + + if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF) + return 1; + + fmt = GET_RTX_FORMAT (GET_CODE (op)); + for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--) + { + if (fmt[i] == 'E') + { + register int j; + + for (j = XVECLEN (op, i) - 1; j >= 0; j--) + if (symbolic_reference_mentioned_p (XVECEXP (op, i, j))) + return 1; + } + else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i))) + return 1; + } + + return 0; +} + +/* This function generates the assembly code for function entry. + FILE is an stdio stream to output the code to. + SIZE is an int: how many units of temporary storage to allocate. */ + +void +function_prologue (file, size) + FILE *file; + int size; +{ + register int regno; + int limit; + rtx xops[4]; + int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table + || current_function_uses_const_pool); + + xops[0] = stack_pointer_rtx; + xops[1] = frame_pointer_rtx; + xops[2] = GEN_INT (size); + if (frame_pointer_needed) + { + output_asm_insn ("push%L1 %1", xops); + output_asm_insn (AS2 (mov%L0,%0,%1), xops); + } + + if (size) + output_asm_insn (AS2 (sub%L0,%2,%0), xops); + + /* Note If use enter it is NOT reversed args. + This one is not reversed from intel!! + I think enter is slower. Also sdb doesn't like it. + But if you want it the code is: + { + xops[3] = const0_rtx; + output_asm_insn ("enter %2,%3", xops); + } + */ + limit = (frame_pointer_needed ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM); + for (regno = limit - 1; regno >= 0; regno--) + if ((regs_ever_live[regno] && ! call_used_regs[regno]) + || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) + { + xops[0] = gen_rtx (REG, SImode, regno); + output_asm_insn ("push%L0 %0", xops); + } + + if (pic_reg_used) + { + xops[0] = pic_offset_table_rtx; + xops[1] = (rtx) gen_label_rtx (); + + output_asm_insn (AS1 (call,%P1), xops); + ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (xops[1])); + output_asm_insn (AS1 (pop%L0,%0), xops); + output_asm_insn ("addl $_GLOBAL_OFFSET_TABLE_+[.-%P1],%0", xops); + } +} + +/* Return 1 if it is appropriate to emit `ret' instructions in the + body of a function. Do this only if the epilogue is simple, needing a + couple of insns. Prior to reloading, we can't tell how many registers + must be saved, so return 0 then. + + If NON_SAVING_SETJMP is defined and true, then it is not possible + for the epilogue to be simple, so return 0. This is a special case + since NON_SAVING_SETJMP will not cause regs_ever_live to change until + final, but jump_optimize may need to know sooner if a `return' is OK. */ + +int +simple_386_epilogue () +{ + int regno; + int nregs = 0; + int reglimit = (frame_pointer_needed + ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM); + int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table + || current_function_uses_const_pool); + +#ifdef NON_SAVING_SETJMP + if (NON_SAVING_SETJMP && current_function_calls_setjmp) + return 0; +#endif + + if (! reload_completed) + return 0; + + for (regno = reglimit - 1; regno >= 0; regno--) + if ((regs_ever_live[regno] && ! call_used_regs[regno]) + || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) + nregs++; + + return nregs == 0 || ! frame_pointer_needed; +} + + +/* This function generates the assembly code for function exit. + FILE is an stdio stream to output the code to. + SIZE is an int: how many units of temporary storage to deallocate. */ + +void +function_epilogue (file, size) + FILE *file; + int size; +{ + register int regno; + register int nregs, limit; + int offset; + rtx xops[3]; + int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table + || current_function_uses_const_pool); + + /* Compute the number of registers to pop */ + + limit = (frame_pointer_needed + ? FRAME_POINTER_REGNUM + : STACK_POINTER_REGNUM); + + nregs = 0; + + for (regno = limit - 1; regno >= 0; regno--) + if ((regs_ever_live[regno] && ! call_used_regs[regno]) + || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) + nregs++; + + /* sp is often unreliable so we must go off the frame pointer, + */ + + /* In reality, we may not care if sp is unreliable, because we can + restore the register relative to the frame pointer. In theory, + since each move is the same speed as a pop, and we don't need the + leal, this is faster. For now restore multiple registers the old + way. */ + + offset = -size - (nregs * UNITS_PER_WORD); + + xops[2] = stack_pointer_rtx; + + if (nregs > 1 || ! frame_pointer_needed) + { + if (frame_pointer_needed) + { + xops[0] = adj_offsettable_operand (AT_BP (Pmode), offset); + output_asm_insn (AS2 (lea%L2,%0,%2), xops); + } + + for (regno = 0; regno < limit; regno++) + if ((regs_ever_live[regno] && ! call_used_regs[regno]) + || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) + { + xops[0] = gen_rtx (REG, SImode, regno); + output_asm_insn ("pop%L0 %0", xops); + } + } + else + for (regno = 0; regno < limit; regno++) + if ((regs_ever_live[regno] && ! call_used_regs[regno]) + || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) + { + xops[0] = gen_rtx (REG, SImode, regno); + xops[1] = adj_offsettable_operand (AT_BP (Pmode), offset); + output_asm_insn (AS2 (mov%L0,%1,%0), xops); + offset += 4; + } + + if (frame_pointer_needed) + { + /* On i486, mov & pop is faster than "leave". */ + + if (!TARGET_386) + { + xops[0] = frame_pointer_rtx; + output_asm_insn (AS2 (mov%L2,%0,%2), xops); + output_asm_insn ("pop%L0 %0", xops); + } + else + output_asm_insn ("leave", xops); + } + else if (size) + { + /* If there is no frame pointer, we must still release the frame. */ + + xops[0] = GEN_INT (size); + output_asm_insn (AS2 (add%L2,%0,%2), xops); + } + + if (current_function_pops_args && current_function_args_size) + { + xops[1] = GEN_INT (current_function_pops_args); + + /* i386 can only pop 32K bytes (maybe 64K? Is it signed?). If + asked to pop more, pop return address, do explicit add, and jump + indirectly to the caller. */ + + if (current_function_pops_args >= 32768) + { + /* ??? Which register to use here? */ + xops[0] = gen_rtx (REG, SImode, 2); + output_asm_insn ("pop%L0 %0", xops); + output_asm_insn (AS2 (add%L2,%1,%2), xops); + output_asm_insn ("jmp %*%0", xops); + } + else + output_asm_insn ("ret %1", xops); + } + else + output_asm_insn ("ret", xops); +} + + +/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression + that is a valid memory address for an instruction. + The MODE argument is the machine mode for the MEM expression + that wants to use this address. + + On x86, legitimate addresses are: + base movl (base),reg + displacement movl disp,reg + base + displacement movl disp(base),reg + index + base movl (base,index),reg + (index + base) + displacement movl disp(base,index),reg + index*scale movl (,index,scale),reg + index*scale + disp movl disp(,index,scale),reg + index*scale + base movl (base,index,scale),reg + (index*scale + base) + disp movl disp(base,index,scale),reg + + In each case, scale can be 1, 2, 4, 8. */ + +/* This is exactly the same as print_operand_addr, except that + it recognizes addresses instead of printing them. + + It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should + convert common non-canonical forms to canonical form so that they will + be recognized. */ + +#define ADDR_INVALID(msg,insn) \ +do { \ + if (TARGET_DEBUG_ADDR) \ + { \ + fprintf (stderr, msg); \ + debug_rtx (insn); \ + } \ +} while (0) + +int +legitimate_address_p (mode, addr, strict) + enum machine_mode mode; + register rtx addr; + int strict; +{ + rtx base = NULL_RTX; + rtx indx = NULL_RTX; + rtx scale = NULL_RTX; + rtx disp = NULL_RTX; + + if (TARGET_DEBUG_ADDR) + { + fprintf (stderr, + "\n==========\nGO_IF_LEGITIMATE_ADDRESS, mode = %s, strict = %d\n", + GET_MODE_NAME (mode), strict); + + debug_rtx (addr); + } + + if (GET_CODE (addr) == REG || GET_CODE (addr) == SUBREG) + base = addr; /* base reg */ + + else if (GET_CODE (addr) == PLUS) + { + rtx op0 = XEXP (addr, 0); + rtx op1 = XEXP (addr, 1); + enum rtx_code code0 = GET_CODE (op0); + enum rtx_code code1 = GET_CODE (op1); + + if (code0 == REG || code0 == SUBREG) + { + if (code1 == REG || code1 == SUBREG) + { + indx = op0; /* index + base */ + base = op1; + } + + else + { + base = op0; /* base + displacement */ + disp = op1; + } + } + + else if (code0 == MULT) + { + indx = XEXP (op0, 0); + scale = XEXP (op0, 1); + + if (code1 == REG || code1 == SUBREG) + base = op1; /* index*scale + base */ + + else + disp = op1; /* index*scale + disp */ + } + + else if (code0 == PLUS && GET_CODE (XEXP (op0, 0)) == MULT) + { + indx = XEXP (XEXP (op0, 0), 0); /* index*scale + base + disp */ + scale = XEXP (XEXP (op0, 0), 1); + base = XEXP (op0, 1); + disp = op1; + } + + else if (code0 == PLUS) + { + indx = XEXP (op0, 0); /* index + base + disp */ + base = XEXP (op0, 1); + disp = op1; + } + + else + { + ADDR_INVALID ("PLUS subcode is not valid.\n", op0); + return FALSE; + } + } + + else if (GET_CODE (addr) == MULT) + { + indx = XEXP (addr, 0); /* index*scale */ + scale = XEXP (addr, 1); + } + + else + disp = addr; /* displacement */ + + /* Allow arg pointer and stack pointer as index if there is not scaling */ + if (base && indx && !scale + && (indx == arg_pointer_rtx || indx == stack_pointer_rtx)) + { + rtx tmp = base; + base = indx; + indx = tmp; + } + + /* Validate base register */ + /* Don't allow SUBREG's here, it can lead to spill failures when the base + is one word out of a two word structure, which is represented internally + as a DImode int. */ + if (base) + { + if (GET_CODE (base) != REG) + { + ADDR_INVALID ("Base is not a register.\n", base); + return FALSE; + } + + if ((strict && !REG_OK_FOR_BASE_STRICT_P (base)) + || (!strict && !REG_OK_FOR_BASE_NONSTRICT_P (base))) + { + ADDR_INVALID ("Base is not valid.\n", base); + return FALSE; + } + } + + /* Validate index register */ + /* Don't allow SUBREG's here, it can lead to spill failures when the index + is one word out of a two word structure, which is represented internally + as a DImode int. */ + if (indx) + { + if (GET_CODE (indx) != REG) + { + ADDR_INVALID ("Index is not a register.\n", indx); + return FALSE; + } + + if ((strict && !REG_OK_FOR_INDEX_STRICT_P (indx)) + || (!strict && !REG_OK_FOR_INDEX_NONSTRICT_P (indx))) + { + ADDR_INVALID ("Index is not valid.\n", indx); + return FALSE; + } + } + else if (scale) + abort (); /* scale w/o index illegal */ + + /* Validate scale factor */ + if (scale) + { + HOST_WIDE_INT value; + + if (GET_CODE (scale) != CONST_INT) + { + ADDR_INVALID ("Scale is not valid.\n", scale); + return FALSE; + } + + value = INTVAL (scale); + if (value != 1 && value != 2 && value != 4 && value != 8) + { + ADDR_INVALID ("Scale is not a good multiplier.\n", scale); + return FALSE; + } + } + + /* Validate displacement */ + if (disp) + { + if (!CONSTANT_ADDRESS_P (disp)) + { + ADDR_INVALID ("Displacement is not valid.\n", disp); + return FALSE; + } + + if (GET_CODE (disp) == CONST_DOUBLE) + { + ADDR_INVALID ("Displacement is a const_double.\n", disp); + return FALSE; + } + + if (flag_pic && SYMBOLIC_CONST (disp) && base != pic_offset_table_rtx + && (indx != pic_offset_table_rtx || scale != NULL_RTX)) + { + ADDR_INVALID ("Displacement is an invalid pic reference.\n", disp); + return FALSE; + } + + if (HALF_PIC_P () && HALF_PIC_ADDRESS_P (disp) + && (base != NULL_RTX || indx != NULL_RTX)) + { + ADDR_INVALID ("Displacement is an invalid half-pic reference.\n", disp); + return FALSE; + } + } + + if (TARGET_DEBUG_ADDR) + fprintf (stderr, "Address is valid.\n"); + + /* Everything looks valid, return true */ + return TRUE; +} + + +/* Return a legitimate reference for ORIG (an address) using the + register REG. If REG is 0, a new pseudo is generated. + + There are three types of references that must be handled: + + 1. Global data references must load the address from the GOT, via + the PIC reg. An insn is emitted to do this load, and the reg is + returned. + + 2. Static data references must compute the address as an offset + from the GOT, whose base is in the PIC reg. An insn is emitted to + compute the address into a reg, and the reg is returned. Static + data objects have SYMBOL_REF_FLAG set to differentiate them from + global data objects. + + 3. Constant pool addresses must be handled special. They are + considered legitimate addresses, but only if not used with regs. + When printed, the output routines know to print the reference with the + PIC reg, even though the PIC reg doesn't appear in the RTL. + + GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC + reg also appears in the address (except for constant pool references, + noted above). + + "switch" statements also require special handling when generating + PIC code. See comments by the `casesi' insn in i386.md for details. */ + +rtx +legitimize_pic_address (orig, reg) + rtx orig; + rtx reg; +{ + rtx addr = orig; + rtx new = orig; + + if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF) + { + if (GET_CODE (addr) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (addr)) + reg = new = orig; + else + { + if (reg == 0) + reg = gen_reg_rtx (Pmode); + + if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_FLAG (addr)) + || GET_CODE (addr) == LABEL_REF) + new = gen_rtx (PLUS, Pmode, pic_offset_table_rtx, orig); + else + new = gen_rtx (MEM, Pmode, + gen_rtx (PLUS, Pmode, + pic_offset_table_rtx, orig)); + + emit_move_insn (reg, new); + } + current_function_uses_pic_offset_table = 1; + return reg; + } + else if (GET_CODE (addr) == CONST || GET_CODE (addr) == PLUS) + { + rtx base; + + if (GET_CODE (addr) == CONST) + { + addr = XEXP (addr, 0); + if (GET_CODE (addr) != PLUS) + abort (); + } + + if (XEXP (addr, 0) == pic_offset_table_rtx) + return orig; + + if (reg == 0) + reg = gen_reg_rtx (Pmode); + + base = legitimize_pic_address (XEXP (addr, 0), reg); + addr = legitimize_pic_address (XEXP (addr, 1), + base == reg ? NULL_RTX : reg); + + if (GET_CODE (addr) == CONST_INT) + return plus_constant (base, INTVAL (addr)); + + if (GET_CODE (addr) == PLUS && CONSTANT_P (XEXP (addr, 1))) + { + base = gen_rtx (PLUS, Pmode, base, XEXP (addr, 0)); + addr = XEXP (addr, 1); + } + return gen_rtx (PLUS, Pmode, base, addr); + } + return new; +} + + +/* Emit insns to move operands[1] into operands[0]. */ + +void +emit_pic_move (operands, mode) + rtx *operands; + enum machine_mode mode; +{ + rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode); + + if (GET_CODE (operands[0]) == MEM && SYMBOLIC_CONST (operands[1])) + operands[1] = (rtx) force_reg (SImode, operands[1]); + else + operands[1] = legitimize_pic_address (operands[1], temp); +} + + +/* Try machine-dependent ways of modifying an illegitimate address + to be legitimate. If we find one, return the new, valid address. + This macro is used in only one place: `memory_address' in explow.c. + + OLDX is the address as it was before break_out_memory_refs was called. + In some cases it is useful to look at this to decide what needs to be done. + + MODE and WIN are passed so that this macro can use + GO_IF_LEGITIMATE_ADDRESS. + + It is always safe for this macro to do nothing. It exists to recognize + opportunities to optimize the output. + + For the 80386, we handle X+REG by loading X into a register R and + using R+REG. R will go in a general reg and indexing will be used. + However, if REG is a broken-out memory address or multiplication, + nothing needs to be done because REG can certainly go in a general reg. + + When -fpic is used, special handling is needed for symbolic references. + See comments by legitimize_pic_address in i386.c for details. */ + +rtx +legitimize_address (x, oldx, mode) + register rtx x; + register rtx oldx; + enum machine_mode mode; +{ + int changed = 0; + unsigned log; + + if (TARGET_DEBUG_ADDR) + { + fprintf (stderr, "\n==========\nLEGITIMIZE_ADDRESS, mode = %s\n", GET_MODE_NAME (mode)); + debug_rtx (x); + } + + if (flag_pic && SYMBOLIC_CONST (x)) + return legitimize_pic_address (x, 0); + + /* Canonicalize shifts by 0, 1, 2, 3 into multiply */ + if (GET_CODE (x) == ASHIFT + && GET_CODE (XEXP (x, 1)) == CONST_INT + && (log = (unsigned)exact_log2 (INTVAL (XEXP (x, 1)))) < 4) + { + changed = 1; + x = gen_rtx (MULT, Pmode, + force_reg (Pmode, XEXP (x, 0)), + GEN_INT (1 << log)); + } + + if (GET_CODE (x) == PLUS) + { + /* Canonicalize shifts by 0, 1, 2, 3 into multiply */ + if (GET_CODE (XEXP (x, 0)) == ASHIFT + && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT + && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) < 4) + { + changed = 1; + XEXP (x, 0) = gen_rtx (MULT, Pmode, + force_reg (Pmode, XEXP (XEXP (x, 0), 0)), + GEN_INT (1 << log)); + } + + if (GET_CODE (XEXP (x, 1)) == ASHIFT + && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT + && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1)))) < 4) + { + changed = 1; + XEXP (x, 1) = gen_rtx (MULT, Pmode, + force_reg (Pmode, XEXP (XEXP (x, 1), 0)), + GEN_INT (1 << log)); + } + + /* Put multiply first if it isn't already */ + if (GET_CODE (XEXP (x, 1)) == MULT) + { + rtx tmp = XEXP (x, 0); + XEXP (x, 0) = XEXP (x, 1); + XEXP (x, 1) = tmp; + changed = 1; + } + + /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const))) + into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be + created by virtual register instantiation, register elimination, and + similar optimizations. */ + if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS) + { + changed = 1; + x = gen_rtx (PLUS, Pmode, + gen_rtx (PLUS, Pmode, XEXP (x, 0), XEXP (XEXP (x, 1), 0)), + XEXP (XEXP (x, 1), 1)); + } + + /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const) + into (plus (plus (mult (reg) (const)) (reg)) (const)). */ + else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS + && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT + && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS + && CONSTANT_P (XEXP (x, 1))) + { + rtx constant, other; + + if (GET_CODE (XEXP (x, 1)) == CONST_INT) + { + constant = XEXP (x, 1); + other = XEXP (XEXP (XEXP (x, 0), 1), 1); + } + else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT) + { + constant = XEXP (XEXP (XEXP (x, 0), 1), 1); + other = XEXP (x, 1); + } + else + constant = 0; + + if (constant) + { + changed = 1; + x = gen_rtx (PLUS, Pmode, + gen_rtx (PLUS, Pmode, XEXP (XEXP (x, 0), 0), + XEXP (XEXP (XEXP (x, 0), 1), 0)), + plus_constant (other, INTVAL (constant))); + } + } + + if (changed && legitimate_address_p (mode, x, FALSE)) + return x; + + if (GET_CODE (XEXP (x, 0)) == MULT) + { + changed = 1; + XEXP (x, 0) = force_operand (XEXP (x, 0), 0); + } + + if (GET_CODE (XEXP (x, 1)) == MULT) + { + changed = 1; + XEXP (x, 1) = force_operand (XEXP (x, 1), 0); + } + + if (changed + && GET_CODE (XEXP (x, 1)) == REG + && GET_CODE (XEXP (x, 0)) == REG) + return x; + + if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1))) + { + changed = 1; + x = legitimize_pic_address (x, 0); + } + + if (changed && legitimate_address_p (mode, x, FALSE)) + return x; + + if (GET_CODE (XEXP (x, 0)) == REG) + { + register rtx temp = gen_reg_rtx (Pmode); + register rtx val = force_operand (XEXP (x, 1), temp); + if (val != temp) + emit_move_insn (temp, val); + + XEXP (x, 1) = temp; + return x; + } + + else if (GET_CODE (XEXP (x, 1)) == REG) + { + register rtx temp = gen_reg_rtx (Pmode); + register rtx val = force_operand (XEXP (x, 0), temp); + if (val != temp) + emit_move_insn (temp, val); + + XEXP (x, 0) = temp; + return x; + } + } + + return x; +} + + +/* Print an integer constant expression in assembler syntax. Addition + and subtraction are the only arithmetic that may appear in these + expressions. FILE is the stdio stream to write to, X is the rtx, and + CODE is the operand print code from the output string. */ + +static void +output_pic_addr_const (file, x, code) + FILE *file; + rtx x; + int code; +{ + char buf[256]; + + switch (GET_CODE (x)) + { + case PC: + if (flag_pic) + putc ('.', file); + else + abort (); + break; + + case SYMBOL_REF: + case LABEL_REF: + if (GET_CODE (x) == SYMBOL_REF) + assemble_name (file, XSTR (x, 0)); + else + { + ASM_GENERATE_INTERNAL_LABEL (buf, "L", + CODE_LABEL_NUMBER (XEXP (x, 0))); + assemble_name (asm_out_file, buf); + } + + if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x)) + fprintf (file, "@GOTOFF(%%ebx)"); + else if (code == 'P') + fprintf (file, "@PLT"); + else if (GET_CODE (x) == LABEL_REF) + fprintf (file, "@GOTOFF"); + else if (! SYMBOL_REF_FLAG (x)) + fprintf (file, "@GOT"); + else + fprintf (file, "@GOTOFF"); + + break; + + case CODE_LABEL: + ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x)); + assemble_name (asm_out_file, buf); + break; + + case CONST_INT: + fprintf (file, "%d", INTVAL (x)); + break; + + case CONST: + /* This used to output parentheses around the expression, + but that does not work on the 386 (either ATT or BSD assembler). */ + output_pic_addr_const (file, XEXP (x, 0), code); + break; + + case CONST_DOUBLE: + if (GET_MODE (x) == VOIDmode) + { + /* We can use %d if the number is <32 bits and positive. */ + if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0) + fprintf (file, "0x%x%08x", + CONST_DOUBLE_HIGH (x), CONST_DOUBLE_LOW (x)); + else + fprintf (file, "%d", CONST_DOUBLE_LOW (x)); + } + else + /* We can't handle floating point constants; + PRINT_OPERAND must handle them. */ + output_operand_lossage ("floating constant misused"); + break; + + case PLUS: + /* Some assemblers need integer constants to appear last (eg masm). */ + if (GET_CODE (XEXP (x, 0)) == CONST_INT) + { + output_pic_addr_const (file, XEXP (x, 1), code); + if (INTVAL (XEXP (x, 0)) >= 0) + fprintf (file, "+"); + output_pic_addr_const (file, XEXP (x, 0), code); + } + else + { + output_pic_addr_const (file, XEXP (x, 0), code); + if (INTVAL (XEXP (x, 1)) >= 0) + fprintf (file, "+"); + output_pic_addr_const (file, XEXP (x, 1), code); + } + break; + + case MINUS: + output_pic_addr_const (file, XEXP (x, 0), code); + fprintf (file, "-"); + output_pic_addr_const (file, XEXP (x, 1), code); + break; + + default: + output_operand_lossage ("invalid expression as operand"); + } +} + +/* Meaning of CODE: + f -- float insn (print a CONST_DOUBLE as a float rather than in hex). + D,L,W,B,Q,S -- print the opcode suffix for specified size of operand. + R -- print the prefix for register names. + z -- print the opcode suffix for the size of the current operand. + * -- print a star (in certain assembler syntax) + w -- print the operand as if it's a "word" (HImode) even if it isn't. + c -- don't print special prefixes before constant operands. +*/ + +void +print_operand (file, x, code) + FILE *file; + rtx x; + int code; +{ + if (code) + { + switch (code) + { + case '*': + if (USE_STAR) + putc ('*', file); + return; + + case 'L': + PUT_OP_SIZE (code, 'l', file); + return; + + case 'W': + PUT_OP_SIZE (code, 'w', file); + return; + + case 'B': + PUT_OP_SIZE (code, 'b', file); + return; + + case 'Q': + PUT_OP_SIZE (code, 'l', file); + return; + + case 'S': + PUT_OP_SIZE (code, 's', file); + return; + + case 'T': + PUT_OP_SIZE (code, 't', file); + return; + + case 'z': + /* 387 opcodes don't get size suffixes if the operands are + registers. */ + + if (STACK_REG_P (x)) + return; + + /* this is the size of op from size of operand */ + switch (GET_MODE_SIZE (GET_MODE (x))) + { + case 1: + PUT_OP_SIZE ('B', 'b', file); + return; + + case 2: + PUT_OP_SIZE ('W', 'w', file); + return; + + case 4: + if (GET_MODE (x) == SFmode) + { + PUT_OP_SIZE ('S', 's', file); + return; + } + else + PUT_OP_SIZE ('L', 'l', file); + return; + + case 12: + PUT_OP_SIZE ('T', 't', file); + return; + + case 8: + if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT) + { +#ifdef GAS_MNEMONICS + PUT_OP_SIZE ('Q', 'q', file); + return; +#else + PUT_OP_SIZE ('Q', 'l', file); /* Fall through */ +#endif + } + + PUT_OP_SIZE ('Q', 'l', file); + return; + } + + case 'b': + case 'w': + case 'k': + case 'h': + case 'y': + case 'P': + break; + + default: + { + char str[50]; + + sprintf (str, "invalid operand code `%c'", code); + output_operand_lossage (str); + } + } + } + if (GET_CODE (x) == REG) + { + PRINT_REG (x, code, file); + } + else if (GET_CODE (x) == MEM) + { + PRINT_PTR (x, file); + if (CONSTANT_ADDRESS_P (XEXP (x, 0))) + { + if (flag_pic) + output_pic_addr_const (file, XEXP (x, 0), code); + else + output_addr_const (file, XEXP (x, 0)); + } + else + output_address (XEXP (x, 0)); + } + else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) + { + REAL_VALUE_TYPE r; long l; + REAL_VALUE_FROM_CONST_DOUBLE (r, x); + REAL_VALUE_TO_TARGET_SINGLE (r, l); + PRINT_IMMED_PREFIX (file); + fprintf (file, "0x%x", l); + } + /* These float cases don't actually occur as immediate operands. */ + else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) + { + REAL_VALUE_TYPE r; char dstr[30]; + REAL_VALUE_FROM_CONST_DOUBLE (r, x); + REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr); + fprintf (file, "%s", dstr); + } + else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == XFmode) + { + REAL_VALUE_TYPE r; char dstr[30]; + REAL_VALUE_FROM_CONST_DOUBLE (r, x); + REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr); + fprintf (file, "%s", dstr); + } + else + { + if (code != 'P') + { + if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) + PRINT_IMMED_PREFIX (file); + else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF + || GET_CODE (x) == LABEL_REF) + PRINT_OFFSET_PREFIX (file); + } + if (flag_pic) + output_pic_addr_const (file, x, code); + else + output_addr_const (file, x); + } +} + +/* Print a memory operand whose address is ADDR. */ + +void +print_operand_address (file, addr) + FILE *file; + register rtx addr; +{ + register rtx reg1, reg2, breg, ireg; + rtx offset; + + switch (GET_CODE (addr)) + { + case REG: + ADDR_BEG (file); + fprintf (file, "%se", RP); + fputs (hi_reg_name[REGNO (addr)], file); + ADDR_END (file); + break; + + case PLUS: + reg1 = 0; + reg2 = 0; + ireg = 0; + breg = 0; + offset = 0; + if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) + { + offset = XEXP (addr, 0); + addr = XEXP (addr, 1); + } + else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) + { + offset = XEXP (addr, 1); + addr = XEXP (addr, 0); + } + if (GET_CODE (addr) != PLUS) ; + else if (GET_CODE (XEXP (addr, 0)) == MULT) + { + reg1 = XEXP (addr, 0); + addr = XEXP (addr, 1); + } + else if (GET_CODE (XEXP (addr, 1)) == MULT) + { + reg1 = XEXP (addr, 1); + addr = XEXP (addr, 0); + } + else if (GET_CODE (XEXP (addr, 0)) == REG) + { + reg1 = XEXP (addr, 0); + addr = XEXP (addr, 1); + } + else if (GET_CODE (XEXP (addr, 1)) == REG) + { + reg1 = XEXP (addr, 1); + addr = XEXP (addr, 0); + } + if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT) + { + if (reg1 == 0) reg1 = addr; + else reg2 = addr; + addr = 0; + } + if (offset != 0) + { + if (addr != 0) abort (); + addr = offset; + } + if ((reg1 && GET_CODE (reg1) == MULT) + || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) + { + breg = reg2; + ireg = reg1; + } + else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) + { + breg = reg1; + ireg = reg2; + } + + if (ireg != 0 || breg != 0) + { + int scale = 1; + + if (addr != 0) + { + if (flag_pic) + output_pic_addr_const (file, addr, 0); + + else if (GET_CODE (addr) == LABEL_REF) + output_asm_label (addr); + + else + output_addr_const (file, addr); + } + + if (ireg != 0 && GET_CODE (ireg) == MULT) + { + scale = INTVAL (XEXP (ireg, 1)); + ireg = XEXP (ireg, 0); + } + + /* The stack pointer can only appear as a base register, + never an index register, so exchange the regs if it is wrong. */ + + if (scale == 1 && ireg && REGNO (ireg) == STACK_POINTER_REGNUM) + { + rtx tmp; + + tmp = breg; + breg = ireg; + ireg = tmp; + } + + /* output breg+ireg*scale */ + PRINT_B_I_S (breg, ireg, scale, file); + break; + } + + case MULT: + { + int scale; + if (GET_CODE (XEXP (addr, 0)) == CONST_INT) + { + scale = INTVAL (XEXP (addr, 0)); + ireg = XEXP (addr, 1); + } + else + { + scale = INTVAL (XEXP (addr, 1)); + ireg = XEXP (addr, 0); + } + output_addr_const (file, const0_rtx); + PRINT_B_I_S ((rtx) 0, ireg, scale, file); + } + break; + + default: + if (GET_CODE (addr) == CONST_INT + && INTVAL (addr) < 0x8000 + && INTVAL (addr) >= -0x8000) + fprintf (file, "%d", INTVAL (addr)); + else + { + if (flag_pic) + output_pic_addr_const (file, addr, 0); + else + output_addr_const (file, addr); + } + } +} + +/* Set the cc_status for the results of an insn whose pattern is EXP. + On the 80386, we assume that only test and compare insns, as well + as SI, HI, & DI mode ADD, SUB, NEG, AND, IOR, XOR, ASHIFT, + ASHIFTRT, and LSHIFTRT instructions set the condition codes usefully. + Also, we assume that jumps, moves and sCOND don't affect the condition + codes. All else clobbers the condition codes, by assumption. + + We assume that ALL integer add, minus, etc. instructions effect the + condition codes. This MUST be consistent with i386.md. + + We don't record any float test or compare - the redundant test & + compare check in final.c does not handle stack-like regs correctly. */ + +void +notice_update_cc (exp) + rtx exp; +{ + if (GET_CODE (exp) == SET) + { + /* Jumps do not alter the cc's. */ + if (SET_DEST (exp) == pc_rtx) + return; +#ifdef IS_STACK_MODE + /* intel1 + Moving into a memory of stack_mode may have been moved + in between the use and set of cc0 by loop_spl(). So + old value of cc.status must be retained */ + if(GET_CODE(SET_DEST(exp))==MEM + && IS_STACK_MODE(GET_MODE(SET_DEST(exp)))) + { + return; + } +#endif + /* Moving register or memory into a register: + it doesn't alter the cc's, but it might invalidate + the RTX's which we remember the cc's came from. + (Note that moving a constant 0 or 1 MAY set the cc's). */ + if (REG_P (SET_DEST (exp)) + && (REG_P (SET_SRC (exp)) || GET_CODE (SET_SRC (exp)) == MEM + || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<')) + { + if (cc_status.value1 + && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1)) + cc_status.value1 = 0; + if (cc_status.value2 + && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2)) + cc_status.value2 = 0; + return; + } + /* Moving register into memory doesn't alter the cc's. + It may invalidate the RTX's which we remember the cc's came from. */ + if (GET_CODE (SET_DEST (exp)) == MEM + && (REG_P (SET_SRC (exp)) + || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<')) + { + if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM) + cc_status.value1 = 0; + if (cc_status.value2 && GET_CODE (cc_status.value2) == MEM) + cc_status.value2 = 0; + return; + } + /* Function calls clobber the cc's. */ + else if (GET_CODE (SET_SRC (exp)) == CALL) + { + CC_STATUS_INIT; + return; + } + /* Tests and compares set the cc's in predictable ways. */ + else if (SET_DEST (exp) == cc0_rtx) + { + CC_STATUS_INIT; + cc_status.value1 = SET_SRC (exp); + return; + } + /* Certain instructions effect the condition codes. */ + else if (GET_MODE (SET_SRC (exp)) == SImode + || GET_MODE (SET_SRC (exp)) == HImode + || GET_MODE (SET_SRC (exp)) == QImode) + switch (GET_CODE (SET_SRC (exp))) + { + case ASHIFTRT: case LSHIFTRT: + case ASHIFT: + /* Shifts on the 386 don't set the condition codes if the + shift count is zero. */ + if (GET_CODE (XEXP (SET_SRC (exp), 1)) != CONST_INT) + { + CC_STATUS_INIT; + break; + } + /* We assume that the CONST_INT is non-zero (this rtx would + have been deleted if it were zero. */ + + case PLUS: case MINUS: case NEG: + case AND: case IOR: case XOR: + cc_status.flags = CC_NO_OVERFLOW; + cc_status.value1 = SET_SRC (exp); + cc_status.value2 = SET_DEST (exp); + break; + + default: + CC_STATUS_INIT; + } + else + { + CC_STATUS_INIT; + } + } + else if (GET_CODE (exp) == PARALLEL + && GET_CODE (XVECEXP (exp, 0, 0)) == SET) + { + if (SET_DEST (XVECEXP (exp, 0, 0)) == pc_rtx) + return; + if (SET_DEST (XVECEXP (exp, 0, 0)) == cc0_rtx) + { + CC_STATUS_INIT; + if (stack_regs_mentioned_p (SET_SRC (XVECEXP (exp, 0, 0)))) + cc_status.flags |= CC_IN_80387; + else + cc_status.value1 = SET_SRC (XVECEXP (exp, 0, 0)); + return; + } + CC_STATUS_INIT; + } + else + { + CC_STATUS_INIT; + } +} + +/* Split one or more DImode RTL references into pairs of SImode + references. The RTL can be REG, offsettable MEM, integer constant, or + CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to + split and "num" is its length. lo_half and hi_half are output arrays + that parallel "operands". */ + +void +split_di (operands, num, lo_half, hi_half) + rtx operands[]; + int num; + rtx lo_half[], hi_half[]; +{ + while (num--) + { + if (GET_CODE (operands[num]) == REG) + { + lo_half[num] = gen_rtx (REG, SImode, REGNO (operands[num])); + hi_half[num] = gen_rtx (REG, SImode, REGNO (operands[num]) + 1); + } + else if (CONSTANT_P (operands[num])) + { + split_double (operands[num], &lo_half[num], &hi_half[num]); + } + else if (offsettable_memref_p (operands[num])) + { + lo_half[num] = operands[num]; + hi_half[num] = adj_offsettable_operand (operands[num], 4); + } + else + abort(); + } +} + +/* Return 1 if this is a valid binary operation on a 387. + OP is the expression matched, and MODE is its mode. */ + +int +binary_387_op (op, mode) + register rtx op; + enum machine_mode mode; +{ + if (mode != VOIDmode && mode != GET_MODE (op)) + return 0; + + switch (GET_CODE (op)) + { + case PLUS: + case MINUS: + case MULT: + case DIV: + return GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT; + + default: + return 0; + } +} + + +/* Return 1 if this is a valid shift or rotate operation on a 386. + OP is the expression matched, and MODE is its mode. */ + +int +shift_op (op, mode) + register rtx op; + enum machine_mode mode; +{ + rtx operand = XEXP (op, 0); + + if (mode != VOIDmode && mode != GET_MODE (op)) + return 0; + + if (GET_MODE (operand) != GET_MODE (op) + || GET_MODE_CLASS (GET_MODE (op)) != MODE_INT) + return 0; + + return (GET_CODE (op) == ASHIFT + || GET_CODE (op) == ASHIFTRT + || GET_CODE (op) == LSHIFTRT + || GET_CODE (op) == ROTATE + || GET_CODE (op) == ROTATERT); +} + +/* Return 1 if OP is COMPARE rtx with mode VOIDmode. + MODE is not used. */ + +int +VOIDmode_compare_op (op, mode) + register rtx op; + enum machine_mode mode; +{ + return GET_CODE (op) == COMPARE && GET_MODE (op) == VOIDmode; +} + +/* Output code to perform a 387 binary operation in INSN, one of PLUS, + MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3] + is the expression of the binary operation. The output may either be + emitted here, or returned to the caller, like all output_* functions. + + There is no guarantee that the operands are the same mode, as they + might be within FLOAT or FLOAT_EXTEND expressions. */ + +char * +output_387_binary_op (insn, operands) + rtx insn; + rtx *operands; +{ + rtx temp; + char *base_op; + static char buf[100]; + + switch (GET_CODE (operands[3])) + { + case PLUS: + if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT + || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT) + base_op = "fiadd"; + else + base_op = "fadd"; + break; + + case MINUS: + if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT + || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT) + base_op = "fisub"; + else + base_op = "fsub"; + break; + + case MULT: + if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT + || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT) + base_op = "fimul"; + else + base_op = "fmul"; + break; + + case DIV: + if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT + || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT) + base_op = "fidiv"; + else + base_op = "fdiv"; + break; + + default: + abort (); + } + + strcpy (buf, base_op); + + switch (GET_CODE (operands[3])) + { + case MULT: + case PLUS: + if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2])) + { + temp = operands[2]; + operands[2] = operands[1]; + operands[1] = temp; + } + + if (GET_CODE (operands[2]) == MEM) + return strcat (buf, AS1 (%z2,%2)); + + if (NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], strcat (buf, AS1 (%z0,%1))); + RET; + } + else if (NON_STACK_REG_P (operands[2])) + { + output_op_from_reg (operands[2], strcat (buf, AS1 (%z0,%1))); + RET; + } + + if (find_regno_note (insn, REG_DEAD, REGNO (operands[2]))) + return strcat (buf, AS2 (p,%2,%0)); + + if (STACK_TOP_P (operands[0])) + return strcat (buf, AS2C (%y2,%0)); + else + return strcat (buf, AS2C (%2,%0)); + + case MINUS: + case DIV: + if (GET_CODE (operands[1]) == MEM) + return strcat (buf, AS1 (r%z1,%1)); + + if (GET_CODE (operands[2]) == MEM) + return strcat (buf, AS1 (%z2,%2)); + + if (NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], strcat (buf, AS1 (r%z0,%1))); + RET; + } + else if (NON_STACK_REG_P (operands[2])) + { + output_op_from_reg (operands[2], strcat (buf, AS1 (%z0,%1))); + RET; + } + + if (! STACK_REG_P (operands[1]) || ! STACK_REG_P (operands[2])) + abort (); + + if (find_regno_note (insn, REG_DEAD, REGNO (operands[2]))) + return strcat (buf, AS2 (rp,%2,%0)); + + if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) + return strcat (buf, AS2 (p,%1,%0)); + + if (STACK_TOP_P (operands[0])) + { + if (STACK_TOP_P (operands[1])) + return strcat (buf, AS2C (%y2,%0)); + else + return strcat (buf, AS2 (r,%y1,%0)); + } + else if (STACK_TOP_P (operands[1])) + return strcat (buf, AS2C (%1,%0)); + else + return strcat (buf, AS2 (r,%2,%0)); + + default: + abort (); + } +} + +/* Output code for INSN to convert a float to a signed int. OPERANDS + are the insn operands. The output may be SFmode or DFmode and the + input operand may be SImode or DImode. As a special case, make sure + that the 387 stack top dies if the output mode is DImode, because the + hardware requires this. */ + +char * +output_fix_trunc (insn, operands) + rtx insn; + rtx *operands; +{ + int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; + rtx xops[2]; + + if (! STACK_TOP_P (operands[1]) || + (GET_MODE (operands[0]) == DImode && ! stack_top_dies)) + abort (); + + xops[0] = GEN_INT (12); + xops[1] = operands[4]; + + output_asm_insn (AS1 (fnstc%W2,%2), operands); + output_asm_insn (AS2 (mov%L2,%2,%4), operands); + output_asm_insn (AS2 (mov%B1,%0,%h1), xops); + output_asm_insn (AS2 (mov%L4,%4,%3), operands); + output_asm_insn (AS1 (fldc%W3,%3), operands); + + if (NON_STACK_REG_P (operands[0])) + output_to_reg (operands[0], stack_top_dies); + else if (GET_CODE (operands[0]) == MEM) + { + if (stack_top_dies) + output_asm_insn (AS1 (fistp%z0,%0), operands); + else + output_asm_insn (AS1 (fist%z0,%0), operands); + } + else + abort (); + + return AS1 (fldc%W2,%2); +} + +/* Output code for INSN to compare OPERANDS. The two operands might + not have the same mode: one might be within a FLOAT or FLOAT_EXTEND + expression. If the compare is in mode CCFPEQmode, use an opcode that + will not fault if a qNaN is present. */ + +char * +output_float_compare (insn, operands) + rtx insn; + rtx *operands; +{ + int stack_top_dies; + rtx body = XVECEXP (PATTERN (insn), 0, 0); + int unordered_compare = GET_MODE (SET_SRC (body)) == CCFPEQmode; + + /* intel1 */ + rtx tmp; + if (! STACK_TOP_P (operands[0])) + { + tmp = operands[0]; + operands[0] = operands[1]; + operands[1] = tmp; + cc_status.flags |= CC_REVERSED; + } + + if (! STACK_TOP_P (operands[0])) + abort (); + + stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; + + if (STACK_REG_P (operands[1]) + && stack_top_dies + && find_regno_note (insn, REG_DEAD, REGNO (operands[1])) + && REGNO (operands[1]) != FIRST_STACK_REG) + { + /* If both the top of the 387 stack dies, and the other operand + is also a stack register that dies, then this must be a + `fcompp' float compare */ + + if (unordered_compare) + output_asm_insn ("fucompp", operands); + else + output_asm_insn ("fcompp", operands); + } + else + { + static char buf[100]; + + /* Decide if this is the integer or float compare opcode, or the + unordered float compare. */ + + if (unordered_compare) + strcpy (buf, "fucom"); + else if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_FLOAT) + strcpy (buf, "fcom"); + else + strcpy (buf, "ficom"); + + /* Modify the opcode if the 387 stack is to be popped. */ + + if (stack_top_dies) + strcat (buf, "p"); + + if (NON_STACK_REG_P (operands[1])) + output_op_from_reg (operands[1], strcat (buf, AS1 (%z0,%1))); + else + output_asm_insn (strcat (buf, AS1 (%z1,%y1)), operands); + } + + /* Now retrieve the condition code. */ + + return output_fp_cc0_set (insn); +} + +/* Output opcodes to transfer the results of FP compare or test INSN + from the FPU to the CPU flags. If TARGET_IEEE_FP, ensure that if the + result of the compare or test is unordered, no comparison operator + succeeds except NE. Return an output template, if any. */ + +char * +output_fp_cc0_set (insn) + rtx insn; +{ + rtx xops[3]; + rtx unordered_label; + rtx next; + enum rtx_code code; + + xops[0] = gen_rtx (REG, HImode, 0); + output_asm_insn (AS1 (fnsts%W0,%0), xops); + + + if (! TARGET_IEEE_FP) + { + /* intel1 */ + if (!(cc_status.flags & CC_REVERSED)) + { + next = next_cc0_user (insn); + + if (GET_CODE (next) == JUMP_INSN + && GET_CODE (PATTERN (next)) == SET + && SET_DEST (PATTERN (next)) == pc_rtx + && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE) + { + code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0)); + } + else if (GET_CODE (PATTERN (next)) == SET) + { + code = GET_CODE (SET_SRC (PATTERN (next))); + } + else + { + return "sahf"; + } + if (code == GT || code == LT || code == EQ || code == NE + || code == LE || code == GE) + { /* We will test eax directly */ + cc_status.flags |= CC_TEST_AX; + RET; + } + } + return "sahf"; + } + + next = next_cc0_user (insn); + if (next == NULL_RTX) + abort (); + + if (GET_CODE (next) == JUMP_INSN + && GET_CODE (PATTERN (next)) == SET + && SET_DEST (PATTERN (next)) == pc_rtx + && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE) + { + code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0)); + } + else if (GET_CODE (PATTERN (next)) == SET) + { + code = GET_CODE (SET_SRC (PATTERN (next))); + } + else + abort (); + + xops[0] = gen_rtx (REG, QImode, 0); + + switch (code) + { + case GT: + xops[1] = GEN_INT (0x45); + output_asm_insn (AS2 (and%B0,%1,%h0), xops); + /* je label */ + break; + + case LT: + xops[1] = GEN_INT (0x45); + xops[2] = GEN_INT (0x01); + output_asm_insn (AS2 (and%B0,%1,%h0), xops); + output_asm_insn (AS2 (cmp%B0,%2,%h0), xops); + /* je label */ + break; + + case GE: + xops[1] = GEN_INT (0x05); + output_asm_insn (AS2 (and%B0,%1,%h0), xops); + /* je label */ + break; + + case LE: + xops[1] = GEN_INT (0x45); + xops[2] = GEN_INT (0x40); + output_asm_insn (AS2 (and%B0,%1,%h0), xops); + output_asm_insn (AS1 (dec%B0,%h0), xops); + output_asm_insn (AS2 (cmp%B0,%2,%h0), xops); + /* jb label */ + break; + + case EQ: + xops[1] = GEN_INT (0x45); + xops[2] = GEN_INT (0x40); + output_asm_insn (AS2 (and%B0,%1,%h0), xops); + output_asm_insn (AS2 (cmp%B0,%2,%h0), xops); + /* je label */ + break; + + case NE: + xops[1] = GEN_INT (0x44); + xops[2] = GEN_INT (0x40); + output_asm_insn (AS2 (and%B0,%1,%h0), xops); + output_asm_insn (AS2 (xor%B0,%2,%h0), xops); + /* jne label */ + break; + + case GTU: + case LTU: + case GEU: + case LEU: + default: + abort (); + } + RET; +} + +#define MAX_386_STACK_LOCALS 2 + +static rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS]; + +/* Define the structure for the machine field in struct function. */ +struct machine_function +{ + rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS]; +}; + +/* Functions to save and restore i386_stack_locals. + These will be called, via pointer variables, + from push_function_context and pop_function_context. */ + +void +save_386_machine_status (p) + struct function *p; +{ + p->machine = (struct machine_function *) xmalloc (sizeof i386_stack_locals); + bcopy ((char *) i386_stack_locals, (char *) p->machine->i386_stack_locals, + sizeof i386_stack_locals); +} + +void +restore_386_machine_status (p) + struct function *p; +{ + bcopy ((char *) p->machine->i386_stack_locals, (char *) i386_stack_locals, + sizeof i386_stack_locals); + free (p->machine); +} + +/* Clear stack slot assignments remembered from previous functions. + This is called from INIT_EXPANDERS once before RTL is emitted for each + function. */ + +void +clear_386_stack_locals () +{ + enum machine_mode mode; + int n; + + for (mode = VOIDmode; (int) mode < (int) MAX_MACHINE_MODE; + mode = (enum machine_mode) ((int) mode + 1)) + for (n = 0; n < MAX_386_STACK_LOCALS; n++) + i386_stack_locals[(int) mode][n] = NULL_RTX; + + /* Arrange to save and restore i386_stack_locals around nested functions. */ + save_machine_status = save_386_machine_status; + restore_machine_status = restore_386_machine_status; +} + +/* Return a MEM corresponding to a stack slot with mode MODE. + Allocate a new slot if necessary. + + The RTL for a function can have several slots available: N is + which slot to use. */ + +rtx +assign_386_stack_local (mode, n) + enum machine_mode mode; + int n; +{ + if (n < 0 || n >= MAX_386_STACK_LOCALS) + abort (); + + if (i386_stack_locals[(int) mode][n] == NULL_RTX) + { + i386_stack_locals[(int) mode][n] + = assign_stack_local (mode, GET_MODE_SIZE (mode), 0); + } + return i386_stack_locals[(int) mode][n]; +} + + +/* all functions after here added by intel1 */ +/* intel1 */ +int is_mul(op,mode) + register rtx op; + enum machine_mode mode; +{ + return(GET_CODE(op)==MULT); +} + +/* intel1 */ +int is_div(op,mode) + register rtx op; + enum machine_mode mode; +{ + return(GET_CODE(op)==DIV); +} + +/* Create a new copy of an rtx. + Recursively copies the operands of the rtx, + except for those few rtx codes that are sharable. + Doesn't share CONST */ + +rtx +copy_all_rtx (orig) + register rtx orig; +{ + register rtx copy; + register int i, j; + register RTX_CODE code; + register char *format_ptr; + + code = GET_CODE (orig); + + switch (code) + { + case REG: + case QUEUED: + case CONST_INT: + case CONST_DOUBLE: + case SYMBOL_REF: + case CODE_LABEL: + case PC: + case CC0: + case SCRATCH: + /* SCRATCH must be shared because they represent distinct values. */ + return orig; + +#if 0 + case CONST: + /* CONST can be shared if it contains a SYMBOL_REF. If it contains + a LABEL_REF, it isn't sharable. */ + if (GET_CODE (XEXP (orig, 0)) == PLUS + && GET_CODE (XEXP (XEXP (orig, 0), 0)) == SYMBOL_REF + && GET_CODE (XEXP (XEXP (orig, 0), 1)) == CONST_INT) + return orig; + break; +#endif + /* A MEM with a constant address is not sharable. The problem is that + the constant address may need to be reloaded. If the mem is shared, + then reloading one copy of this mem will cause all copies to appear + to have been reloaded. */ + } + + copy = rtx_alloc (code); + PUT_MODE (copy, GET_MODE (orig)); + copy->in_struct = orig->in_struct; + copy->volatil = orig->volatil; + copy->unchanging = orig->unchanging; + copy->integrated = orig->integrated; + /* intel1 */ + copy->is_spill_rtx = orig->is_spill_rtx; + + format_ptr = GET_RTX_FORMAT (GET_CODE (copy)); + + for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++) + { + switch (*format_ptr++) + { + case 'e': + XEXP (copy, i) = XEXP (orig, i); + if (XEXP (orig, i) != NULL) + XEXP (copy, i) = copy_rtx (XEXP (orig, i)); + break; + + case '0': + case 'u': + XEXP (copy, i) = XEXP (orig, i); + break; + + case 'E': + case 'V': + XVEC (copy, i) = XVEC (orig, i); + if (XVEC (orig, i) != NULL) + { + XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i)); + for (j = 0; j < XVECLEN (copy, i); j++) + XVECEXP (copy, i, j) = copy_rtx (XVECEXP (orig, i, j)); + } + break; + + case 'w': + XWINT (copy, i) = XWINT (orig, i); + break; + + case 'i': + XINT (copy, i) = XINT (orig, i); + break; + + case 's': + case 'S': + XSTR (copy, i) = XSTR (orig, i); + break; + + default: + abort (); + } + } + return copy; +} + + +/* try to rewrite a memory address to make it valid */ +void +rewrite_address (mem_rtx) + rtx mem_rtx; +{ + rtx index_rtx, base_rtx, offset_rtx, scale_rtx, ret_rtx; + int scale = 1; + int offset_adjust = 0; + int was_only_offset = 0; + rtx mem_addr = XEXP (mem_rtx, 0); + char *storage = (char *) oballoc (0); + int in_struct = 0; + int is_spill_rtx = 0; + + in_struct = MEM_IN_STRUCT_P (mem_rtx); + is_spill_rtx = RTX_IS_SPILL_P (mem_rtx); + + if (GET_CODE (mem_addr) == PLUS && + GET_CODE (XEXP (mem_addr, 1)) == PLUS && + GET_CODE (XEXP (XEXP (mem_addr, 1), 0)) == REG) + { /* this part is utilized by the combiner */ + ret_rtx = + gen_rtx (PLUS, GET_MODE (mem_addr), + gen_rtx (PLUS, GET_MODE (XEXP (mem_addr, 1)), + XEXP (mem_addr, 0), + XEXP (XEXP (mem_addr, 1), 0)), + XEXP (XEXP (mem_addr, 1), 1)); + if (memory_address_p (GET_MODE (mem_rtx), ret_rtx)) + { + XEXP (mem_rtx, 0) = ret_rtx; + RTX_IS_SPILL_P (ret_rtx) = is_spill_rtx; + return; + } + obfree (storage); + } + + /* this part is utilized by loop.c */ + /* If the address contains PLUS (reg,const) and this pattern is invalid + in this case - try to rewrite the address to make it valid intel1 + */ + storage = (char *) oballoc (0); + index_rtx = base_rtx = offset_rtx = NULL; + /* find the base index and offset elements of the memory address */ + if (GET_CODE (mem_addr) == PLUS) + { + if (GET_CODE (XEXP (mem_addr, 0)) == REG) + { + if (GET_CODE (XEXP (mem_addr, 1)) == REG) + { + base_rtx = XEXP (mem_addr, 1); + index_rtx = XEXP (mem_addr, 0); + } + else + { + base_rtx = XEXP (mem_addr, 0); + offset_rtx = XEXP (mem_addr, 1); + } + } + else if (GET_CODE (XEXP (mem_addr, 0)) == MULT) + { + index_rtx = XEXP (mem_addr, 0); + if (GET_CODE (XEXP (mem_addr, 1)) == REG) + { + base_rtx = XEXP (mem_addr, 1); + } + else + { + offset_rtx = XEXP (mem_addr, 1); + } + } + else if (GET_CODE (XEXP (mem_addr, 0)) == PLUS) + { + /* intel1 */ + if (GET_CODE (XEXP (XEXP (mem_addr, 0), 0)) == PLUS && + GET_CODE (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0)) == MULT && + GET_CODE (XEXP (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0), 0)) == REG && + GET_CODE (XEXP (XEXP (XEXP (XEXP (mem_addr, 0), 0), 0), 1)) == CONST_INT && + GET_CODE (XEXP (XEXP (XEXP (mem_addr, 0), 0), 1)) == CONST_INT && + GET_CODE (XEXP (XEXP (mem_addr, 0), 1)) == REG && + GET_CODE (XEXP (mem_addr, 1)) == SYMBOL_REF) + { + index_rtx = XEXP (XEXP (XEXP (mem_addr, 0), 0), 0); + offset_rtx = XEXP (mem_addr, 1); + base_rtx = XEXP (XEXP (mem_addr, 0), 1); + offset_adjust = INTVAL (XEXP (XEXP (XEXP (mem_addr, 0), 0), 1)); + } + else + { + offset_rtx = XEXP (mem_addr, 1); + index_rtx = XEXP (XEXP (mem_addr, 0), 0); + base_rtx = XEXP (XEXP (mem_addr, 0), 1); + } + } + else if (GET_CODE (XEXP (mem_addr, 0)) == CONST_INT) + { + was_only_offset = 1; + index_rtx = NULL; + base_rtx = NULL; + offset_rtx = XEXP (mem_addr, 1); + offset_adjust = INTVAL (XEXP (mem_addr, 0)); + if (offset_adjust == 0) + { + XEXP (mem_rtx, 0) = offset_rtx; + RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx; + return; + } + } + else + { + obfree (storage); + return; + } + } + else if (GET_CODE (mem_addr) == MULT) + { + index_rtx = mem_addr; + } + else + { + obfree (storage); + return; + } + if (index_rtx && GET_CODE (index_rtx) == MULT) + { + if (GET_CODE (XEXP (index_rtx, 1)) != CONST_INT) + { + obfree (storage); + return; + } + scale_rtx = XEXP (index_rtx, 1); + scale = INTVAL (scale_rtx); + index_rtx = copy_all_rtx (XEXP (index_rtx, 0)); + } + /* now find which of the elements are invalid and try to fix them */ + if (index_rtx && GET_CODE (index_rtx) == CONST_INT && base_rtx == NULL) + { + offset_adjust = INTVAL (index_rtx) * scale; + if (offset_rtx && GET_CODE (offset_rtx) == CONST && + GET_CODE (XEXP (offset_rtx, 0)) == PLUS) + { + if (GET_CODE (XEXP (XEXP (offset_rtx, 0), 0)) == SYMBOL_REF && + GET_CODE (XEXP (XEXP (offset_rtx, 0), 1)) == CONST_INT) + { + offset_rtx = copy_all_rtx (offset_rtx); + XEXP (XEXP (offset_rtx, 0), 1) = + gen_rtx (CONST_INT, 0, INTVAL (XEXP (XEXP (offset_rtx, 0), 1)) + offset_adjust); + if (!CONSTANT_P (offset_rtx)) + { + obfree (storage); + return; + } + } + } + else if (offset_rtx && GET_CODE (offset_rtx) == SYMBOL_REF) + { + offset_rtx = + gen_rtx (CONST, GET_MODE (offset_rtx), + gen_rtx (PLUS, GET_MODE (offset_rtx), + offset_rtx, + gen_rtx (CONST_INT, 0, offset_adjust))); + if (!CONSTANT_P (offset_rtx)) + { + obfree (storage); + return; + } + } + else if (offset_rtx && GET_CODE (offset_rtx) == CONST_INT) + { + offset_rtx = gen_rtx (CONST_INT, 0, INTVAL (offset_rtx) + offset_adjust); + } + else if (!offset_rtx) + { + offset_rtx = gen_rtx (CONST_INT, 0, 0); + } + RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx; + XEXP (mem_rtx, 0) = offset_rtx; + return; + } + if (base_rtx && GET_CODE (base_rtx) == PLUS && + GET_CODE (XEXP (base_rtx, 0)) == REG && + GET_CODE (XEXP (base_rtx, 1)) == CONST_INT) + { + offset_adjust += INTVAL (XEXP (base_rtx, 1)); + base_rtx = copy_all_rtx (XEXP (base_rtx, 0)); + } + else if (base_rtx && GET_CODE (base_rtx) == CONST_INT) + { + offset_adjust += INTVAL (base_rtx); + base_rtx = NULL; + } + if (index_rtx && GET_CODE (index_rtx) == PLUS && + GET_CODE (XEXP (index_rtx, 0)) == REG && + GET_CODE (XEXP (index_rtx, 1)) == CONST_INT) + { + offset_adjust += INTVAL (XEXP (index_rtx, 1)) * scale; + index_rtx = copy_all_rtx (XEXP (index_rtx, 0)); + } + if (index_rtx) + { + if (!LEGITIMATE_INDEX_P (index_rtx) + && !(index_rtx == stack_pointer_rtx && scale == 1 && base_rtx == NULL)) + { + obfree (storage); + return; + } + } + if (base_rtx) + { + if (!LEGITIMATE_INDEX_P (base_rtx) && GET_CODE (base_rtx) != REG) + { + obfree (storage); + return; + } + } + if (offset_adjust != 0) + { + if (offset_rtx) + { + if (GET_CODE (offset_rtx) == CONST && + GET_CODE (XEXP (offset_rtx, 0)) == PLUS) + { + if (GET_CODE (XEXP (XEXP (offset_rtx, 0), 0)) == SYMBOL_REF && + GET_CODE (XEXP (XEXP (offset_rtx, 0), 1)) == CONST_INT) + { + offset_rtx = copy_all_rtx (offset_rtx); + XEXP (XEXP (offset_rtx, 0), 1) = + gen_rtx (CONST_INT, 0, INTVAL (XEXP (XEXP (offset_rtx, 0), 1)) + offset_adjust); + if (!CONSTANT_P (offset_rtx)) + { + obfree (storage); + return; + } + } + } + else if (GET_CODE (offset_rtx) == SYMBOL_REF) + { + offset_rtx = + gen_rtx (CONST, GET_MODE (offset_rtx), + gen_rtx (PLUS, GET_MODE (offset_rtx), + offset_rtx, + gen_rtx (CONST_INT, 0, offset_adjust))); + if (!CONSTANT_P (offset_rtx)) + { + obfree (storage); + return; + } + } + else if (GET_CODE (offset_rtx) == CONST_INT) + { + offset_rtx = gen_rtx (CONST_INT, 0, INTVAL (offset_rtx) + offset_adjust); + } + else + { + obfree (storage); + return; + } + } + else + { + offset_rtx = gen_rtx (CONST_INT, 0, offset_adjust); + } + if (index_rtx) + { + if (base_rtx) + { + if (scale != 1) + { + if (GET_CODE (offset_rtx) == CONST_INT && + INTVAL (offset_rtx) == 0) + { + ret_rtx = gen_rtx (PLUS, GET_MODE (base_rtx), + gen_rtx (MULT, GET_MODE (index_rtx), index_rtx, + scale_rtx), + base_rtx); + } + else + { + ret_rtx = gen_rtx (PLUS, GET_MODE (offset_rtx), + gen_rtx (PLUS, GET_MODE (base_rtx), + gen_rtx (MULT, GET_MODE (index_rtx), index_rtx, + scale_rtx), + base_rtx), + offset_rtx); + } + } + else + { + if (GET_CODE (offset_rtx) == CONST_INT && + INTVAL (offset_rtx) == 0) + { + ret_rtx = gen_rtx (PLUS, GET_MODE (index_rtx), index_rtx, base_rtx); + } + else + { + ret_rtx = gen_rtx (PLUS, GET_MODE (offset_rtx), + gen_rtx (PLUS, GET_MODE (index_rtx), index_rtx, + base_rtx), + offset_rtx); + } + } + } + else + { + if (scale != 1) + { + if (GET_CODE (offset_rtx) == CONST_INT && + INTVAL (offset_rtx) == 0) + { + ret_rtx = gen_rtx (MULT, GET_MODE (index_rtx), index_rtx, scale_rtx); + } + else + { + ret_rtx = + gen_rtx (PLUS, GET_MODE (offset_rtx), + gen_rtx (MULT, GET_MODE (index_rtx), index_rtx, + scale_rtx), + offset_rtx); + } + } + else + { + if (GET_CODE (offset_rtx) == CONST_INT && + INTVAL (offset_rtx) == 0) + { + ret_rtx = index_rtx; + } + else + { + ret_rtx = gen_rtx (PLUS, GET_MODE (index_rtx), index_rtx, offset_rtx); + } + } + } + } + else + { + if (base_rtx) + { + if (GET_CODE (offset_rtx) == CONST_INT && + INTVAL (offset_rtx) == 0) + { + ret_rtx = base_rtx; + } + else + { + ret_rtx = gen_rtx (PLUS, GET_MODE (base_rtx), base_rtx, offset_rtx); + } + } + else if (was_only_offset) + { + ret_rtx = offset_rtx; + } + else + { + obfree (storage); + return; + } + } + XEXP (mem_rtx, 0) = ret_rtx; + RTX_IS_SPILL_P (XEXP (mem_rtx, 0)) = is_spill_rtx; + return; + } + else + { + obfree (storage); + return; + } +} + +/* return 1 if the first insn to set cc before insn also sets the register + reg_rtx - otherwise return 0 +*/ +int +last_to_set_cc (reg_rtx, insn) + rtx reg_rtx, insn; +{ + rtx prev_insn = PREV_INSN (insn); + + while (prev_insn) + { + if (GET_CODE (prev_insn) == NOTE) + { + ; + } + else if (GET_CODE (prev_insn) == INSN) + { + if (GET_CODE (PATTERN (prev_insn)) != SET) + { + return (0); + } + if (rtx_equal_p (SET_DEST (PATTERN (prev_insn)), reg_rtx)) + { + if (sets_condition_code (SET_SRC (PATTERN (prev_insn)))) + { + return (1); + } + else + { + return (0); + } + } + else if (!doesnt_set_condition_code (SET_SRC (PATTERN (prev_insn)))) + { + return (0); + } + } + else + { + return (0); + } + prev_insn = PREV_INSN (prev_insn); + } + return (0); +} + +int +doesnt_set_condition_code (pat) + rtx pat; +{ + switch (GET_CODE (pat)) + { + case MEM: + case REG: + return (1); + + default: + return (0); + + } +} + +int +sets_condition_code (pat) + rtx pat; +{ + switch (GET_CODE (pat)) + { + case PLUS: + case MINUS: + case AND: + case IOR: + case XOR: + case NOT: + case NEG: + case MULT: + case DIV: + case MOD: + case UDIV: + case UMOD: + return (1); + + default: + return (0); + + } +} + + +/* intel1 */ +int +str_immediate_operand (op, mode) + register rtx op; + enum machine_mode mode; +{ + if (GET_CODE (op) == CONST_INT && INTVAL (op) <= 32 && INTVAL (op) >= 0) + { + return (1); + } + return (0); +} + +/* intel1 */ +void +override_options () +{ + register int i, start; + register int regno; + register enum machine_mode mode; +#if 0 + int blend = 0; +#endif + + /* only one `-mcpu' allowed */ + if (TARGET_X && (TARGET_X != TARGET_386) && (TARGET_X != TARGET_486) && (TARGET_X != TARGET_PENTIUM)) + fatal ("multilple `-mcpu' definitions .\n"); + + /* if `-mcpu' use it, otherwise take default */ + target_flags |= USE_CPU; + + if (TARGET_PENTIUM) + x86_cpu = PROCESSOR_PENTIUM; + else if (TARGET_486) + x86_cpu = PROCESSOR_486; + else if (TARGET_386) + x86_cpu = PROCESSOR_386; + else /* no processor type ? */ + fatal ("no processor type.\n"); + +#if 0 /* what happens if we have few -mcpu's, I don't think it's needed */ + /* Identify the processor type */ + if (!(TARGET_PENTIUM) && !(TARGET_486) && !(TARGET_386)) + { + x86_cpu = PROCESSOR_PENTIUM; + target_flags |= (TARGET_486_SWITCH); + blend = 1; + } + + else + { + x86_cpu = PROCESSOR_DEFAULT; + if (TARGET_PENTIUM) + { + x86_cpu = PROCESSOR_PENTIUM; + } + if (TARGET_486) + { + if (x86_cpu != PROCESSOR_DEFAULT) + { + error ("conflicting -mX86 : using blend"); + blend = 1; + x86_cpu = PROCESSOR_PENTIUM; + target_flags &= ~(TARGET_386_SWITCH); + target_flags &= ~(TARGET_PENTIUM_SWITCH); + } + else + { + x86_cpu = PROCESSOR_486; + } + } + if (TARGET_386) + { + if (x86_cpu != PROCESSOR_DEFAULT) + { + error ("conflicting -mX86 : using blend"); + blend = 1; + x86_cpu = PROCESSOR_486; + target_flags &= ~(TARGET_386_SWITCH); + target_flags &= ~(TARGET_PENTIUM_SWITCH); + target_flags |= (TARGET_486_SWITCH); + } + else + { + x86_cpu = PROCESSOR_386; + } + } + + + } +#endif + if (opt_level >= 4) + { + if (TARGET_486) + { + if (opt_level == 4 + && !flag_no_interleave_stack_non_stack) + { + flag_interleave_stack_non_stack = 1; + flag_schedule_insns = 1; + } + } +#if 0 + if(TARGET_BLEND) + { + if (!flag_no_risc) + flag_risc = 1; + if (!flag_no_risc_const) + flag_risc_const = 1; + if (!flag_no_recombine) + flag_recombine = 1; + } +#endif + if (TARGET_PENTIUM) + { + if (!flag_no_risc) + flag_risc = 1; + if (!flag_no_risc_const) + flag_risc_const = 1; + /*if (!flag_no_recombine) + flag_recombine = 1;*/ + if (opt_level == 4 + && !flag_no_schedule_stack_reg_insns) + { + flag_schedule_stack_reg_insns = 1; + flag_schedule_insns = 1; + } + if (opt_level == 4 + && !flag_no_interleave_stack_non_stack) + { + flag_interleave_stack_non_stack = 1; + flag_schedule_insns = 1; + } + } + } +} + + + + +optimization_options (level) + int level; +{ + opt_level = level; + if (level > 0) + { + flag_opt_reg_use = 1; + flag_reduce_index_givs = 1; + } + if (level >= 2) + { +#ifdef INSN_SCHEDULING + flag_schedule_insns = 0; + flag_schedule_insns_after_reload = 0; +#endif + } + if (level >= 3) + { + flag_inline_functions = 1; + flag_jump_back = 1; + flag_copy_prop = 1; + flag_compare_elim = 1; + flag_sftwr_pipe = 1; + flag_omit_frame_pointer = 1; + flag_reg_reg_copy_opt = 1; + flag_opt_reg_stack = 1; + flag_loop_after_global = 1; + flag_peep_spills = 1; + flag_replace_stack_mem = 1; + flag_opt_jumps_out = 1; + flag_replace_mem = 1; + flag_correct_cse_mistakes = 1; + flag_push_load_into_loop = 1; + flag_replace_reload_regs = 1; + flag_sign_extension_elim = 1; + flag_lift_stores = 1; + flag_runtime_lift_stores = 1; + } + if (level >= 4) + { +#ifdef INSN_SCHEDULING + flag_schedule_insns_after_reload = 1; + flag_swap_for_agi = 1; + if (TARGET_PENTIUM) + { + flag_risc = 1; + flag_risc_const = 1; + /*flag_recombine = 1;*/ + if (level == 4) + { + flag_schedule_stack_reg_insns = 1; + flag_schedule_insns = 1; + } + } +#endif + } + if (level >= 5) + { +#ifdef INSN_SCHEDULING + flag_schedule_insns = 1; +#endif + } + if (flag_no_risc) + flag_risc = 0; + if (flag_no_risc_const) + flag_risc_const = 0; + if (flag_no_recombine) + flag_recombine = 0; + if (flag_no_risc_mem_dest) + flag_risc_mem_dest = 0; +} + +/* intel1 */ + +int +is_fp_insn (insn) + rtx insn; +{ + if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET + && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode + || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode)) + { + return (1); + } + return (0); +} + + +/* + Return 1 if the mode of the SET_DEST of insn is floating point + and it is not an fld or a move from memory to memory. + Otherwise return 0 +*/ +int +is_fp_dest (insn) + rtx insn; +{ + if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET + && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode + || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode) + && GET_CODE (SET_DEST (PATTERN (insn))) == REG + && REGNO (SET_DEST (PATTERN (insn))) >= FIRST_FLOAT_REG + && GET_CODE (SET_SRC (insn)) != MEM + ) + { + return (1); + } + return (0); +} + +/* + Return 1 if the mode of the SET_DEST floating point and is memory + and the source is a register. +*/ +int +is_fp_store (insn) + rtx insn; +{ + if (GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SET + && (GET_MODE (SET_DEST (PATTERN (insn))) == DFmode + || GET_MODE (SET_DEST (PATTERN (insn))) == SFmode) + && GET_CODE (SET_DEST (PATTERN (insn))) == MEM + && GET_CODE (SET_SRC (PATTERN (insn))) == REG + ) + { + return (1); + } + return (0); +} + + +/* + Return 1 if dep_insn sets a register which insn uses as a base + or index to reference memory. + otherwise return 0 +*/ +int +agi_dependent (insn, dep_insn) + rtx insn, dep_insn; +{ + if (GET_CODE (dep_insn) == INSN && GET_CODE (PATTERN (dep_insn)) == SET + && GET_CODE (SET_DEST (PATTERN (dep_insn))) == REG) + { + return (reg_mentioned_in_mem (SET_DEST (PATTERN (dep_insn)), insn)); + } + if (GET_CODE (dep_insn) == INSN && GET_CODE (PATTERN (dep_insn)) == SET + && GET_CODE (SET_DEST (PATTERN (dep_insn))) == MEM + && push_operand (SET_DEST (PATTERN (dep_insn)), + GET_MODE (SET_DEST (PATTERN (dep_insn)))) + ) + { + return (reg_mentioned_in_mem (stack_pointer_rtx, insn)); + } + + return (0); +} + +/* + Return 1 if reg is used in rtl as a base or index for a memory ref + otherwise return 0. +*/ +int +reg_mentioned_in_mem (reg, rtl) + rtx reg, rtl; +{ + register char *fmt; + register int i; + register enum rtx_code code; + + if (rtl == NULL) + return (0); + + code = GET_CODE (rtl); + + switch (code) + { + case HIGH: + case CONST_INT: + case CONST: + case CONST_DOUBLE: + case SYMBOL_REF: + case LABEL_REF: + case PC: + case CC0: + case SUBREG: + return (0); + + + } + + if (code == MEM && reg_mentioned_p (reg, rtl)) + { + return (1); + } + + fmt = GET_RTX_FORMAT (code); + + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + { + if (fmt[i] == 'E') + { + register int j; + for (j = XVECLEN (rtl, i) - 1; j >= 0; j--) + if (reg_mentioned_in_mem (reg, XVECEXP (rtl, i, j))) + return 1; + } + else if (fmt[i] == 'e' + && reg_mentioned_in_mem (reg, XEXP (rtl, i))) + return 1; + } + return (0); +} + diff -r -u -H -N gcc-2.6.3/config/i386/i386.h gcc-i2.6.3/config/i386/i386.h --- gcc-2.6.3/config/i386/i386.h Wed Oct 19 16:52:09 1994 +++ gcc-i2.6.3/config/i386/i386.h Wed Feb 15 23:07:40 1995 @@ -1,5 +1,8 @@ -/* Definitions of target machine for GNU compiler for Intel X86 (386, 486, pentium) - Copyright (C) 1988, 1992, 1994 Free Software Foundation, Inc. +/* Definitions of target machine for GNU compiler for Intel X86. + Copyright (C) 1988, 1992 Free Software Foundation, Inc. + + Pentium cpu support and other enhancements by Tevi Devor Intel Corp. + (tevi@iil.intel.com). This file is part of GNU CC. @@ -54,6 +57,50 @@ /* Run-time compilation parameters selecting different hardware subsets. */ extern int target_flags; +/* Which processor to schedule for. intel1 */ + +enum processor_type { + PROCESSOR_DEFAULT, + PROCESSOR_386, + PROCESSOR_486, + PROCESSOR_PENTIUM +}; +extern enum processor_type x86_cpu; /* which cpu are we scheduling for */ + +/* intel1 */ +#define REDUCE_INDEX (TARGET_486 || TARGET_PENTIUM) +#define SAVE_ON_REGS 1 +#define MAX_DEST_ADDR_GIVS 5 +#define PREFER_JUMP_NOT_TAKEN 1 +#define PREFER_CONST_IN_REG 1 +#define IGNORE_NON_DATA_DEP 1 +#define STORE_NOT_SET_CC0 1 +#define NO_CROSS_JUMP_ON_LOOP_ENTRY 1 +#define AGI 1 +/* #define SPILL1 */ +#define EXPENSIVE_OPS(x) \ + ( GET_CODE(x)==MULT ? \ + ((GET_CODE (XEXP (x, 1)) == CONST_INT && \ + exact_log2 (INTVAL (XEXP (x, 1))) >= 0) ? 0 : 1) : \ + (GET_CODE(x)==DIV || GET_CODE(x)==UDIV || \ + GET_CODE(x)==MOD || GET_CODE(x)==UMOD )) + +#define NO_STACK_REG_REORDER (!TARGET_PENTIUM) + +#define STACK_REG_REORDER \ + ((TARGET_PENTIUM) && reload_completed == 0 && flag_schedule_stack_reg_insns) + +#define STACK_NON_STACK_INTERLEAVE \ + (reload_completed == 0 && flag_interleave_stack_non_stack) + +#define IS_RISC_MODE(mode) (((mode) == QImode || (mode) == SImode)) + +/* Number of extra pseudo registers we allocate for so that reg-stack + can replace fld's and fstps with movs +*/ +#define SPARE_REGS 5 +#define OVERRIDE_OPTIONS override_options() + /* Macros used in the machine description to test the flags. */ @@ -62,142 +109,106 @@ #define TARGET_CPU_DEFAULT 0 #endif -/* Masks for the -m switches */ -#define MASK_80387 000000000001 /* Hardware floating point */ -#define MASK_486 000000000002 /* 80486 specific */ -#define MASK_NOTUSED 000000000004 /* bit not currently used */ -#define MASK_RTD 000000000010 /* Use ret that pops args */ -#define MASK_REGPARM 000000000020 /* Pass args in eax, edx */ -#define MASK_SVR3_SHLIB 000000000040 /* Uninit locals into bss */ -#define MASK_IEEE_FP 000000000100 /* IEEE fp comparisons */ -#define MASK_FLOAT_RETURNS 000000000200 /* Return float in st(0) */ -#define MASK_NO_FANCY_MATH_387 000000000400 /* Disable sin, cos, sqrt */ - - /* Temporary codegen switches */ -#define MASK_DEBUG_ADDR 000001000000 /* Debug GO_IF_LEGITIMATE_ADDRESS */ -#define MASK_NO_WIDE_MULTIPLY 000002000000 /* Disable 32x32->64 multiplies */ -#define MASK_NO_MOVE 000004000000 /* Don't generate mem->mem */ - -/* Use the floating point instructions */ -#define TARGET_80387 (target_flags & MASK_80387) - +/* Compile 80387 insns for floating point (not library calls). */ +#define TARGET_80387 (target_flags & 1) /* Compile using ret insn that pops args. This will not work unless you use prototypes at least for all functions that can take varying numbers of args. */ -#define TARGET_RTD (target_flags & MASK_RTD) - +#define TARGET_RTD (target_flags & 8) /* Compile passing first two args in regs 0 and 1. This exists only to test compiler features that will be needed for RISC chips. It is not usable and is not intended to be usable on this cpu. */ -#define TARGET_REGPARM (target_flags & MASK_RTD) +#define TARGET_REGPARM (target_flags & 020) /* Put uninitialized locals into bss, not data. Meaningful only on svr3. */ -#define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB) +#define TARGET_SVR3_SHLIB (target_flags & 040) /* Use IEEE floating point comparisons. These handle correctly the cases where the result of a comparison is unordered. Normally SIGFPE is generated in such cases, in which case this isn't needed. */ -#define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP) +#define TARGET_IEEE_FP (target_flags & 0100) /* Functions that return a floating point value may return that value in the 387 FPU or in 386 integer registers. If set, this flag causes the 387 to be used, which is compatible with most calling conventions. */ -#define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS) - -/* Disable generation of FP sin, cos and sqrt operations for 387. - This is because FreeBSD lacks these in the math-emulator-code */ -#define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387) - -/* Temporary switches for tuning code generation */ - -/* Disable 32x32->64 bit multiplies that are used for long long multiplies - and division by constants, but sometimes cause reload problems. */ -#define TARGET_NO_WIDE_MULTIPLY (target_flags & MASK_NO_WIDE_MULTIPLY) -#define TARGET_WIDE_MULTIPLY (!TARGET_NO_WIDE_MULTIPLY) - -/* Debug GO_IF_LEGITIMATE_ADDRESS */ -#define TARGET_DEBUG_ADDR (target_flags & MASK_DEBUG_ADDR) - -/* Hack macros for tuning code generation */ -#define TARGET_MOVE ((target_flags & MASK_NO_MOVE) == 0) /* Don't generate memory->memory */ - -/* Specific hardware switches */ -#define TARGET_486 (target_flags & MASK_486) /* 80486DX, 80486SX, 80486DX[24] */ -#define TARGET_386 (!TARGET_486) /* 80386 */ - -#define TARGET_SWITCHES \ -{ { "80387", MASK_80387 }, \ - { "no-80387", -MASK_80387 }, \ - { "hard-float", MASK_80387 }, \ - { "soft-float", -MASK_80387 }, \ - { "no-soft-float", MASK_80387 }, \ - { "386", -MASK_486 }, \ - { "no-386", MASK_486 }, \ - { "486", MASK_486 }, \ - { "no-486", -MASK_486 }, \ - { "rtd", MASK_RTD }, \ - { "no-rtd", -MASK_RTD }, \ - { "regparm", MASK_REGPARM }, \ - { "no-regparm", -MASK_REGPARM }, \ - { "svr3-shlib", MASK_SVR3_SHLIB }, \ - { "no-svr3-shlib", -MASK_SVR3_SHLIB }, \ - { "ieee-fp", MASK_IEEE_FP }, \ - { "no-ieee-fp", -MASK_IEEE_FP }, \ - { "fp-ret-in-387", MASK_FLOAT_RETURNS }, \ - { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS }, \ - { "no-fancy-math-387", MASK_NO_FANCY_MATH_387 }, \ - { "fancy-math-387", -MASK_NO_FANCY_MATH_387 }, \ - { "no-wide-multiply", MASK_NO_WIDE_MULTIPLY }, \ - { "wide-multiply", -MASK_NO_WIDE_MULTIPLY }, \ - { "debug-addr", MASK_DEBUG_ADDR }, \ - { "no-debug-addr", -MASK_DEBUG_ADDR }, \ - { "move", -MASK_NO_MOVE }, \ - { "no-move", MASK_NO_MOVE }, \ - SUBTARGET_SWITCHES \ - { "", TARGET_DEFAULT | TARGET_CPU_DEFAULT}} - -/* This macro is similar to `TARGET_SWITCHES' but defines names of - command options that have values. Its definition is an - initializer with a subgrouping for each command option. - - Each subgrouping contains a string constant, that defines the - fixed part of the option name, and the address of a variable. The - variable, type `char *', is set to the variable part of the given - option if the fixed part matches. The actual option name is made - by appending `-m' to the specified name. */ -#define TARGET_OPTIONS \ -{ { "reg-alloc=", &i386_reg_alloc_order }, \ - SUBTARGET_OPTIONS } - -/* Sometimes certain combinations of command options do not make - sense on a particular target machine. You can define a macro - `OVERRIDE_OPTIONS' to take account of this. This macro, if - defined, is executed once just after all the command options have - been parsed. +#define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & 0200) - Don't use this macro to turn on various extra optimizations for - `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ +/* Macro to define tables used to set the flags. + This is a list in braces of pairs in braces, + each pair being { "NAME", VALUE } + where VALUE is the bits to set or minus the bits to clear. + An empty string NAME is used to identify the default VALUE. */ + +/* intel1 */ +#define TARGET_486_SWITCH 2 +#define TARGET_486 (target_flags & TARGET_486_SWITCH) +/* Compile code for a Pentium. intel1 */ +#define TARGET_PENTIUM_SWITCH 4 +#define TARGET_PENTIUM (target_flags & TARGET_PENTIUM_SWITCH) +/* Compile code for an i386. intel1 */ +#define TARGET_386_SWITCH 0400 +#define TARGET_386 (target_flags & TARGET_386_SWITCH) +/* Compile code for a Blend. intel1 */ +#define TARGET_BLEND_SWITCH 02000 +#define TARGET_BLEND (target_flags & TARGET_BLEND_SWITCH) + +#define TARGET_X ((TARGET_386) | (TARGET_486) | (TARGET_PENTIUM)) +#define USE_CPU ((TARGET_X) ? (TARGET_X) : TARGET_CPU_DEFAULT) + +#define TARGET_SWITCHES \ + { { "80387", 1}, \ + { "no-80387", -1}, \ + { "soft-float", -1}, \ + { "no-soft-float", 1}, \ + { "486", 2}, \ + { "no-486", -2}, \ + { "386", 0400}, \ + { "pentium", 4}, \ + { "blend", 02000}, \ + { "rtd", 8}, \ + { "no-rtd", -8}, \ + { "regparm", 020}, \ + { "no-regparm", -020}, \ + { "svr3-shlib", 040}, \ + { "no-svr3-shlib", -040}, \ + { "ieee-fp", 0100}, \ + { "no-ieee-fp", -0100}, \ + { "fp-ret-in-387", 0200}, \ + { "no-fp-ret-in-387", -0200}, \ + SUBTARGET_SWITCHES \ + { "", TARGET_DEFAULT }} -#define OVERRIDE_OPTIONS override_options () - -/* These are meant to be redefined in the host dependent files */ +/* This is meant to be redefined in the host dependent files */ #define SUBTARGET_SWITCHES -#define SUBTARGET_OPTIONS +/* intel1 */ + +#define SUB_TARGET_STRING \ +(TARGET_PENTIUM ? "Pentium" : (TARGET_386 ? "Intel386" : "Intel486")) + +#define SUB_TARGET_VERSION fprintf (stderr, " [%s cpu] ", SUB_TARGET_STRING) + + +/* Define this to change the optimizations performed by default. */ + +#define OPTIMIZATION_OPTIONS(LEVEL) \ +optimization_options(LEVEL) + /* target machine storage layout */ /* Define for XFmode extended real floating point support. This will automatically cause REAL_ARITHMETIC to be defined. */ #define LONG_DOUBLE_TYPE_SIZE 96 - + /* Define if you don't want extended real, but do want to use the software floating point emulator for REAL_ARITHMETIC and decimal <-> binary conversion. */ /* #define REAL_ARITHMETIC */ + /* Define this if most significant byte of a word is the lowest numbered. */ /* That is true on the 80386. */ @@ -250,6 +261,9 @@ quantities, but these can be aligned on any 32-bit boundary. */ #define BIGGEST_ALIGNMENT 32 +/* intel1 - align DFmode constants and nonaggregates */ +#define ALIGN_DFmode (!TARGET_386) + /* Set this non-zero if move instructions will actually fail to work when given unaligned data. */ #define STRICT_ALIGNMENT 0 @@ -275,6 +289,8 @@ for details. */ #define STACK_REGS +/* intel1 */ +#define IS_STACK_MODE(mode) (mode==DFmode || mode==SFmode) /* Number of actual hardware registers. The hardware registers are assigned numbers for the compiler @@ -312,44 +328,6 @@ /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg*/ \ { 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 } -/* Order in which to allocate registers. Each register must be - listed once, even those in FIXED_REGISTERS. List frame pointer - late and fixed registers last. Note that, in general, we prefer - registers listed in CALL_USED_REGISTERS, keeping the others - available for storage of persistent values. - - Three different versions of REG_ALLOC_ORDER have been tried: - - If the order is edx, ecx, eax, ... it produces a slightly faster compiler, - but slower code on simple functions returning values in eax. - - If the order is eax, ecx, edx, ... it causes reload to abort when compiling - perl 4.036 due to not being able to create a DImode register (to hold a 2 - word union). - - If the order is eax, edx, ecx, ... it produces better code for simple - functions, and a slightly slower compiler. Users complained about the code - generated by allocating edx first, so restore the 'natural' order of things. */ - -#define REG_ALLOC_ORDER \ -/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg*/ \ -{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 } - -/* A C statement (sans semicolon) to choose the order in which to - allocate hard registers for pseudo-registers local to a basic - block. - - Store the desired register order in the array `reg_alloc_order'. - Element 0 should be the register to allocate first; element 1, the - next register; and so on. - - The macro body should not assume anything about the contents of - `reg_alloc_order' before execution of the macro. - - On most machines, it is not necessary to define this macro. */ - -#define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () - /* Macro to conditionally modify fixed_regs/call_used_regs. */ #define CONDITIONAL_REGISTER_USAGE \ { \ @@ -391,6 +369,9 @@ /* The casts to int placate a compiler on a microvax, for cross-compiler testing. */ +/* intel1 - added case of (REGNO)==16 (gbug12)*/ +/* : (REGNO) == 16 ? 1 \ */ + #define HARD_REGNO_MODE_OK(REGNO, MODE) \ ((REGNO) < 2 ? 1 \ : (REGNO) < 4 ? 1 \ @@ -462,27 +443,6 @@ /* Place in which caller passes the structure value address. 0 means push the value on the stack like an argument. */ #define STRUCT_VALUE 0 - -/* A C expression which can inhibit the returning of certain function - values in registers, based on the type of value. A nonzero value - says to return the function value in memory, just as large - structures are always returned. Here TYPE will be a C expression - of type `tree', representing the data type of the value. - - Note that values of mode `BLKmode' must be explicitly handled by - this macro. Also, the option `-fpcc-struct-return' takes effect - regardless of this macro. On most systems, it is possible to - leave the macro undefined; this causes a default definition to be - used, whose value is the constant 1 for `BLKmode' values, and 0 - otherwise. - - Do not use this macro to indicate that structures and unions - should always be returned in memory. You should instead use - `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */ - -#define RETURN_IN_MEMORY(TYPE) \ - ((TYPE_MODE (TYPE) == BLKmode) || int_size_in_bytes (TYPE) > 12) - /* Define the classes of registers for register constraints in the machine description. Also define ranges of constants. @@ -512,7 +472,6 @@ { NO_REGS, AREG, DREG, CREG, BREG, - AD_REGS, /* %eax/%edx for DImode */ Q_REGS, /* %eax %ebx %ecx %edx */ SIREG, DIREG, INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ @@ -531,7 +490,6 @@ #define REG_CLASS_NAMES \ { "NO_REGS", \ "AREG", "DREG", "CREG", "BREG", \ - "AD_REGS", \ "Q_REGS", \ "SIREG", "DIREG", \ "INDEX_REGS", \ @@ -547,10 +505,9 @@ #define REG_CLASS_CONTENTS \ { 0, \ 0x1, 0x2, 0x4, 0x8, /* AREG, DREG, CREG, BREG */ \ - 0x3, /* AD_REGS */ \ 0xf, /* Q_REGS */ \ 0x10, 0x20, /* SIREG, DIREG */ \ - 0x07f, /* INDEX_REGS */ \ + 0x1007f, /* INDEX_REGS */ \ 0x100ff, /* GENERAL_REGS */ \ 0x0100, 0x0200, /* FP_TOP_REG, FP_SECOND_REG */ \ 0xff00, /* FLOAT_REGS */ \ @@ -561,6 +518,7 @@ reg number REGNO. This could be a conditional expression or could index an array. */ +extern enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) /* When defined, the compiler allows registers explicitly used in the @@ -618,9 +576,8 @@ (C) == 'b' ? BREG : \ (C) == 'c' ? CREG : \ (C) == 'd' ? DREG : \ - (C) == 'A' ? AD_REGS : \ (C) == 'D' ? DIREG : \ - (C) == 'S' ? SIREG : NO_REGS) + (C) == 'S' ? SIREG : NO_REGS) /* intel1 changed to e from S */ /* The letters I, J, K, L and M in a register constraint string can be used to stand for particular ranges of immediate operands. @@ -632,6 +589,7 @@ J is for DImode shifts. K and L are for an `andsi' optimization. M is for shifts that can be executed by the "lea" opcode. + O is for block moves intel1 */ #define CONST_OK_FOR_LETTER_P(VALUE, C) \ @@ -640,6 +598,7 @@ (C) == 'K' ? (VALUE) == 0xff : \ (C) == 'L' ? (VALUE) == 0xffff : \ (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 : \ + (C) == 'O' ? (VALUE) >= 0 && (VALUE) <= 32 : \ 0) /* Similar, but for floating constants, and defining letters G and H. @@ -692,33 +651,91 @@ #define CLASS_MAX_NREGS(CLASS, MODE) \ (FLOAT_CLASS_P (CLASS) ? 1 : \ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) + + +/* A C statement (sans semicolon) to update the integer variable COST + based on the relationship between INSN that is dependent on + DEP_INSN through the dependence LINK. The default is to make no + adjustment to COST. */ +#define ADJUST_COST(insn,link,dep_insn,cost) \ + { \ + rtx next_inst; \ + if (GET_CODE (dep_insn) == CALL_INSN) \ + (cost) = 0; \ + if (GET_CODE (dep_insn) == INSN \ + && GET_CODE (PATTERN (dep_insn)) == SET \ + && GET_CODE (SET_DEST (PATTERN (dep_insn))) == REG \ + && GET_CODE (insn) == INSN \ + && GET_CODE (PATTERN (insn)) == SET \ + && !reg_overlap_mentioned_p (SET_DEST (PATTERN (dep_insn)), \ + SET_SRC (PATTERN (insn)))) \ + { \ + (cost) = 0; \ + } \ + if (GET_CODE (insn) == JUMP_INSN) \ + { \ + (cost) = 0; \ + } \ + if (TARGET_PENTIUM) \ + { \ + if (cost !=0 && is_fp_insn (insn) && is_fp_insn (dep_insn) \ + && !is_fp_dest (dep_insn)) \ + { \ + (cost) = 0; \ + } \ + if (agi_dependent (insn, dep_insn)) \ + { \ + (cost) = 3; \ + } \ + else if (GET_CODE (insn) == INSN \ + && GET_CODE (PATTERN (insn)) == SET \ + && SET_DEST (PATTERN (insn)) == cc0_rtx \ + && (next_inst = next_nonnote_insn (insn)) \ + && GET_CODE (next_inst) == JUMP_INSN) \ + { /* compare probably paired with jump */ \ + (cost) = 0; \ + } \ + } \ + else \ + if(!is_fp_dest (dep_insn)) \ + { \ + if(!agi_dependent (insn, dep_insn)) \ + (cost) = 0; \ + else if (TARGET_486) \ + (cost) = 2; \ + } \ + else \ + if(is_fp_store (insn) && is_fp_insn (dep_insn) \ + && NEXT_INSN (insn) && NEXT_INSN (NEXT_INSN (insn)) \ + && NEXT_INSN (NEXT_INSN (NEXT_INSN (insn))) \ + && (GET_CODE (NEXT_INSN (insn)) == INSN) \ + && (GET_CODE (NEXT_INSN (NEXT_INSN (insn))) == JUMP_INSN) \ + && (GET_CODE (NEXT_INSN (NEXT_INSN (NEXT_INSN (insn)))) \ + == NOTE) \ + && NOTE_LINE_NUMBER (NEXT_INSN (NEXT_INSN (NEXT_INSN (insn)))) \ + == NOTE_INSN_LOOP_END) \ + { \ + (cost) = 3; \ + } \ + } -/* A C expression whose value is nonzero if pseudos that have been - assigned to registers of class CLASS would likely be spilled - because registers of CLASS are needed for spill registers. - - The default value of this macro returns 1 if CLASS has exactly one - register and zero otherwise. On most machines, this default - should be used. Only define this macro to some other expression - if pseudo allocated by `local-alloc.c' end up in memory because - their hard registers were needed for spill regisers. If this - macro returns nonzero for those classes, those pseudos will only - be allocated by `global.c', which knows how to reallocate the - pseudo to another register. If there would not be another - register available for reallocation, you should not change the - definition of this macro since the only effect of such a - definition would be to slow down register allocation. */ - -#define CLASS_LIKELY_SPILLED_P(CLASS) \ - (((CLASS) == AREG) \ - || ((CLASS) == DREG) \ - || ((CLASS) == CREG) \ - || ((CLASS) == BREG) \ - || ((CLASS) == AD_REGS) \ - || ((CLASS) == SIREG) \ - || ((CLASS) == DIREG)) - +#define ADJUST_BLOCKAGE(last_insn,insn,blockage) \ + { \ + if(is_fp_store (last_insn) && is_fp_insn (insn) \ + && NEXT_INSN (last_insn) && NEXT_INSN (NEXT_INSN (last_insn)) \ + && NEXT_INSN (NEXT_INSN (NEXT_INSN (last_insn))) \ + && (GET_CODE (NEXT_INSN (last_insn)) == INSN) \ + && (GET_CODE (NEXT_INSN (NEXT_INSN (last_insn))) == JUMP_INSN) \ + && (GET_CODE (NEXT_INSN (NEXT_INSN (NEXT_INSN (last_insn)))) \ + == NOTE) \ + && NOTE_LINE_NUMBER (NEXT_INSN (NEXT_INSN (NEXT_INSN (last_insn)))) \ + == NOTE_INSN_LOOP_END) \ + { \ + (blockage) = 3; \ + } \ + } + /* Stack layout; function entry, exit and calling. */ /* Define this if pushing a word on the stack @@ -889,102 +906,6 @@ } \ } -/* A C statement or compound statement to output to FILE some - assembler code to initialize basic-block profiling for the current - object module. This code should call the subroutine - `__bb_init_func' once per object module, passing it as its sole - argument the address of a block allocated in the object module. - - The name of the block is a local symbol made with this statement: - - ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0); - - Of course, since you are writing the definition of - `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you - can take a short cut in the definition of this macro and use the - name that you know will result. - - The first word of this block is a flag which will be nonzero if the - object module has already been initialized. So test this word - first, and do not call `__bb_init_func' if the flag is nonzero. */ - -#undef FUNCTION_BLOCK_PROFILER -#define FUNCTION_BLOCK_PROFILER(STREAM, LABELNO) \ -do \ - { \ - static int num_func = 0; \ - rtx xops[8]; \ - char block_table[80], false_label[80]; \ - \ - ASM_GENERATE_INTERNAL_LABEL (block_table, "LPBX", 0); \ - ASM_GENERATE_INTERNAL_LABEL (false_label, "LPBZ", num_func); \ - \ - xops[0] = const0_rtx; \ - xops[1] = gen_rtx (SYMBOL_REF, VOIDmode, block_table); \ - xops[2] = gen_rtx (MEM, Pmode, gen_rtx (SYMBOL_REF, VOIDmode, false_label)); \ - xops[3] = gen_rtx (MEM, Pmode, gen_rtx (SYMBOL_REF, VOIDmode, "__bb_init_func")); \ - xops[4] = gen_rtx (MEM, Pmode, xops[1]); \ - xops[5] = stack_pointer_rtx; \ - xops[6] = GEN_INT (4); \ - xops[7] = gen_rtx (REG, Pmode, 0); /* eax */ \ - \ - CONSTANT_POOL_ADDRESS_P (xops[1]) = TRUE; \ - CONSTANT_POOL_ADDRESS_P (xops[2]) = TRUE; \ - \ - output_asm_insn (AS2(cmp%L4,%0,%4), xops); \ - output_asm_insn (AS1(jne,%2), xops); \ - \ - if (!flag_pic) \ - output_asm_insn (AS1(push%L1,%1), xops); \ - else \ - { \ - output_asm_insn (AS2 (lea%L7,%a1,%7), xops); \ - output_asm_insn (AS1 (push%L7,%7), xops); \ - } \ - \ - output_asm_insn (AS1(call,%P3), xops); \ - output_asm_insn (AS2(add%L0,%6,%5), xops); \ - ASM_OUTPUT_INTERNAL_LABEL (STREAM, "LPBZ", num_func); \ - num_func++; \ - } \ -while (0) - - -/* A C statement or compound statement to increment the count - associated with the basic block number BLOCKNO. Basic blocks are - numbered separately from zero within each compilation. The count - associated with block number BLOCKNO is at index BLOCKNO in a - vector of words; the name of this array is a local symbol made - with this statement: - - ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 2); - - Of course, since you are writing the definition of - `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you - can take a short cut in the definition of this macro and use the - name that you know will result. */ - -#define BLOCK_PROFILER(STREAM, BLOCKNO) \ -do \ - { \ - rtx xops[1], cnt_rtx; \ - char counts[80]; \ - \ - ASM_GENERATE_INTERNAL_LABEL (counts, "LPBX", 2); \ - cnt_rtx = gen_rtx (SYMBOL_REF, VOIDmode, counts); \ - SYMBOL_REF_FLAG (cnt_rtx) = TRUE; \ - \ - if (BLOCKNO) \ - cnt_rtx = plus_constant (cnt_rtx, (BLOCKNO)*4); \ - \ - if (flag_pic) \ - cnt_rtx = gen_rtx (PLUS, Pmode, pic_offset_table_rtx, cnt_rtx); \ - \ - xops[0] = gen_rtx (MEM, SImode, cnt_rtx); \ - output_asm_insn (AS1(inc%L0,%0), xops); \ - } \ -while (0) - /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, the stack pointer does not matter. The value is tested only in functions that have frame pointers. @@ -1148,35 +1069,36 @@ After reload, it makes no difference, since pseudo regs have been eliminated by then. */ +#ifndef REG_OK_STRICT + +/* Nonzero if X is a hard reg that can be used as an index or if + it is a pseudo reg. */ -/* Non strict versions, pseudos are ok */ -#define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ - (REGNO (X) < STACK_POINTER_REGNUM \ +#define REG_OK_FOR_INDEX_P(X) \ + (REGNO (X) < STACK_POINTER_REGNUM \ || REGNO (X) >= FIRST_PSEUDO_REGISTER) -#define REG_OK_FOR_BASE_NONSTRICT_P(X) \ - (REGNO (X) <= STACK_POINTER_REGNUM \ - || REGNO (X) == ARG_POINTER_REGNUM \ - || REGNO (X) >= FIRST_PSEUDO_REGISTER) +/* Nonzero if X is a hard reg that can be used as a base reg + of if it is a pseudo reg. */ + /* ?wfs */ + +#define REG_OK_FOR_BASE_P(X) \ + (REGNO (X) <= STACK_POINTER_REGNUM \ + || REGNO (X) == ARG_POINTER_REGNUM \ + || REGNO(X) >= FIRST_PSEUDO_REGISTER) -#define REG_OK_FOR_STRREG_NONSTRICT_P(X) \ +#define REG_OK_FOR_STRREG_P(X) \ (REGNO (X) == 4 || REGNO (X) == 5 || REGNO (X) >= FIRST_PSEUDO_REGISTER) -/* Strict versions, hard registers only */ -#define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) -#define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) -#define REG_OK_FOR_STRREG_STRICT_P(X) \ - (REGNO_OK_FOR_DIREG_P (REGNO (X)) || REGNO_OK_FOR_SIREG_P (REGNO (X))) +#else -#ifndef REG_OK_STRICT -#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P(X) -#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P(X) -#define REG_OK_FOR_STRREG_P(X) REG_OK_FOR_STRREG_NONSTRICT_P(X) +/* Nonzero if X is a hard reg that can be used as an index. */ +#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) +/* Nonzero if X is a hard reg that can be used as a base reg. */ +#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) +#define REG_OK_FOR_STRREG_P(X) \ + (REGNO_OK_FOR_DIREG_P (REGNO (X)) || REGNO_OK_FOR_SIREG_P (REGNO (X))) -#else -#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P(X) -#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P(X) -#define REG_OK_FOR_STRREG_P(X) REG_OK_FOR_STRREG_STRICT_P(X) #endif /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression @@ -1202,22 +1124,62 @@ #define LEGITIMATE_CONSTANT_P(X) 1 -#ifdef REG_OK_STRICT -#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ -{ \ - if (legitimate_address_p (MODE, X, 1)) \ - goto ADDR; \ -} +#define GO_IF_INDEXABLE_BASE(X, ADDR) \ + if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) goto ADDR -#else -#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ +#define LEGITIMATE_INDEX_REG_P(X) \ + (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) + +/* Return 1 if X is an index or an index times a scale. */ + +#define LEGITIMATE_INDEX_P(X) \ + (LEGITIMATE_INDEX_REG_P (X) \ + || (GET_CODE (X) == MULT \ + && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \ + && GET_CODE (XEXP (X, 1)) == CONST_INT \ + && (INTVAL (XEXP (X, 1)) == 2 \ + || INTVAL (XEXP (X, 1)) == 4 \ + || INTVAL (XEXP (X, 1)) == 8))) + +/* Go to ADDR if X is an index term, a base reg, or a sum of those. */ + +#define GO_IF_INDEXING(X, ADDR) \ +{ if (LEGITIMATE_INDEX_P (X)) goto ADDR; \ + GO_IF_INDEXABLE_BASE (X, ADDR); \ + if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \ + { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \ + if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \ + { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } } + +/* We used to allow this, but it isn't ever used. + || ((GET_CODE (X) == POST_DEC || GET_CODE (X) == POST_INC) \ + && REG_P (XEXP (X, 0)) \ + && REG_OK_FOR_STRREG_P (XEXP (X, 0))) \ +*/ + +#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ { \ - if (legitimate_address_p (MODE, X, 0)) \ + if (CONSTANT_ADDRESS_P (X) \ + && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \ goto ADDR; \ + GO_IF_INDEXING (X, ADDR); \ + if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \ + { \ + rtx x0 = XEXP (X, 0); \ + if (! flag_pic || ! SYMBOLIC_CONST (XEXP (X, 1))) \ + { GO_IF_INDEXING (x0, ADDR); } \ + else if (x0 == pic_offset_table_rtx) \ + goto ADDR; \ + else if (GET_CODE (x0) == PLUS) \ + { \ + if (XEXP (x0, 0) == pic_offset_table_rtx) \ + { GO_IF_INDEXABLE_BASE (XEXP (x0, 1), ADDR); } \ + if (XEXP (x0, 1) == pic_offset_table_rtx) \ + { GO_IF_INDEXABLE_BASE (XEXP (x0, 0), ADDR); } \ + } \ + } \ } -#endif - /* Try machine-dependent ways of modifying an illegitimate address to be legitimate. If we find one, return the new, valid address. This macro is used in only one place: `memory_address' in explow.c. @@ -1239,13 +1201,41 @@ When -fpic is used, special handling is needed for symbolic references. See comments by legitimize_pic_address in i386.c for details. */ -#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ -{ \ - rtx orig_x = (X); \ - (X) = legitimize_address (X, OLDX, MODE); \ - if (memory_address_p (MODE, X)) \ - goto WIN; \ -} +#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ +{ extern rtx legitimize_pic_address (); \ + int ch = (X) != (OLDX); \ + if (flag_pic && SYMBOLIC_CONST (X)) \ + { \ + (X) = legitimize_pic_address (X, 0); \ + if (memory_address_p (MODE, X)) \ + goto WIN; \ + } \ + if (GET_CODE (X) == PLUS) \ + { if (GET_CODE (XEXP (X, 0)) == MULT) \ + ch = 1, XEXP (X, 0) = force_operand (XEXP (X, 0), 0); \ + if (GET_CODE (XEXP (X, 1)) == MULT) \ + ch = 1, XEXP (X, 1) = force_operand (XEXP (X, 1), 0); \ + if (ch && GET_CODE (XEXP (X, 1)) == REG \ + && GET_CODE (XEXP (X, 0)) == REG) \ + goto WIN; \ + if (flag_pic && SYMBOLIC_CONST (XEXP (X, 1))) \ + ch = 1, (X) = legitimize_pic_address (X, 0); \ + if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \ + if (GET_CODE (XEXP (X, 0)) == REG) \ + { register rtx temp = gen_reg_rtx (Pmode); \ + register rtx val = force_operand (XEXP (X, 1), temp); \ + if (val != temp) emit_move_insn (temp, val); \ + XEXP (X, 1) = temp; \ + goto WIN; } \ + else if (GET_CODE (XEXP (X, 1)) == REG) \ + { register rtx temp = gen_reg_rtx (Pmode); \ + register rtx val = force_operand (XEXP (X, 0), temp); \ + if (val != temp) emit_move_insn (temp, val); \ + XEXP (X, 0) = temp; \ + goto WIN; }}} + +/* intel1 */ +#define REWRITE_ADDRESS(x) rewrite_address(x) /* Nonzero if the constant value X is a legitimate general operand when generating PIC code. It is given that flag_pic is on and @@ -1348,6 +1338,10 @@ /* Nonzero if access to memory by bytes is slow and undesirable. */ #define SLOW_BYTE_ACCESS 0 +/* intel1 */ +/* Nonzero if access to memory by shorts is slow and undesirable. */ +#define SLOW_SHORT_ACCESS 1 + /* Define if shifts truncate the shift count which implies one can omit a sign-extension or zero-extension of a shift count. */ @@ -1469,6 +1463,7 @@ stored from the compare operation. Note that we can't use "rtx" here since it hasn't been defined! */ +extern struct rtx_def *i386_compare_op0, *i386_compare_op1; extern struct rtx_def *(*i386_compare_gen)(), *(*i386_compare_gen_eq)(); /* Tell final.c how to eliminate redundant test instructions. */ @@ -1476,6 +1471,10 @@ /* Here we define machine-dependent flags and fields in cc_status (see `conditions.h'). */ +/* intel1 Set if the cc value is was actually from the 80387 and + we are testing eax directly (i.e. no sahf) */ +#define CC_TEST_AX 020000 + /* Set if the cc value is actually in the 80387, so a floating point conditional branch must be output. */ #define CC_IN_80387 04000 @@ -1773,12 +1772,12 @@ { fputs ("argp", FILE); break; } \ if (STACK_TOP_P (X)) \ { fputs ("st(0)", FILE); break; } \ - if (FP_REG_P (X)) \ - { fputs (hi_name[REGNO(X)], FILE); break; } \ switch (GET_MODE_SIZE (GET_MODE (X))) \ { \ - default: \ - fputs ("e", FILE); \ + case 12: \ + case 8: \ + case 4: \ + if (! FP_REG_P (X)) fputs ("e", FILE); \ case 2: \ fputs (hi_name[REGNO (X)], FILE); \ break; \ @@ -1813,60 +1812,6 @@ #define RET return "" #define AT_SP(mode) (gen_rtx (MEM, (mode), stack_pointer_rtx)) - -/* Functions in i386.c */ -extern void override_options (); -extern void order_regs_for_local_alloc (); -extern void output_op_from_reg (); -extern void output_to_reg (); -extern char *singlemove_string (); -extern char *output_move_double (); -extern char *output_move_memory (); -extern char *output_move_pushmem (); -extern int standard_80387_constant_p (); -extern char *output_move_const_single (); -extern int symbolic_operand (); -extern int call_insn_operand (); -extern int expander_call_insn_operand (); -extern int symbolic_reference_mentioned_p (); -extern void emit_pic_move (); -extern void function_prologue (); -extern int simple_386_epilogue (); -extern void function_epilogue (); -extern int legitimate_address_p (); -extern struct rtx_def *legitimize_pic_address (); -extern struct rtx_def *legitimize_address (); -extern void print_operand (); -extern void print_operand_address (); -extern void notice_update_cc (); -extern void split_di (); -extern int binary_387_op (); -extern int shift_op (); -extern int VOIDmode_compare_op (); -extern char *output_387_binary_op (); -extern char *output_fix_trunc (); -extern char *output_float_compare (); -extern char *output_fp_cc0_set (); -extern void save_386_machine_status (); -extern void restore_386_machine_status (); -extern void clear_386_stack_locals (); -extern struct rtx_def *assign_386_stack_local (); - -/* Variables in i386.c */ -extern char *i386_reg_alloc_order; /* register allocation order */ -extern char *hi_reg_name[]; /* names for 16 bit regs */ -extern char *qi_reg_name[]; /* names for 8 bit regs (low) */ -extern char *qi_high_reg_name[]; /* names for 8 bit regs (high) */ -extern enum reg_class regclass_map[]; /* smalled class containing REGNO */ -extern struct rtx_def *i386_compare_op0; /* operand 0 for comparisons */ -extern struct rtx_def *i386_compare_op1; /* operand 1 for comparisons */ - -/* External variables used */ -extern int optimize; /* optimization level */ -extern int obey_regdecls; /* TRUE if stupid register allocation */ - -/* External functions used */ -extern struct rtx_def *force_operand (); /* Local variables: diff -r -u -H -N gcc-2.6.3/config/i386/i386.md gcc-i2.6.3/config/i386/i386.md --- gcc-2.6.3/config/i386/i386.md Mon Oct 31 16:16:33 1994 +++ gcc-i2.6.3/config/i386/i386.md Wed Feb 15 23:08:02 1995 @@ -1,7 +1,10 @@ ;; GCC machine description for Intel X86. -;; Copyright (C) 1988, 1994 Free Software Foundation, Inc. +;; Copyright (C) 1988 Free Software Foundation, Inc. ;; Mostly by William Schelter. +;; Pentium cpu support and other enhancements by Tevi Devor Intel Corp. +;; (tevi@iil.intel.com). + ;; This file is part of GNU CC. ;; GNU CC is free software; you can redistribute it and/or modify @@ -70,6 +73,36 @@ ;; actually generating RTL. The bCOND or sCOND (emitted immediately ;; after the tstM or cmp) will actually emit the tstM or cmpM. +;intel1 +(define_attr "type" "fld,integer,fpop,fpdiv" + (const_string "integer")) + +;; Functional units intel1 +(define_function_unit "fp" 1 0 + (and (eq_attr "type" "fpop") + (ne (symbol_ref "x86_cpu") (symbol_ref "PROCESSOR_PENTIUM"))) + 5 5) + +(define_function_unit "fp" 1 0 + (and (eq_attr "type" "fpop") + (eq (symbol_ref "x86_cpu") (symbol_ref "PROCESSOR_PENTIUM"))) + 3 0) + +(define_function_unit "fp" 1 0 + (eq_attr "type" "fpdiv") + 10 10) + +(define_function_unit "fp" 1 0 + (eq_attr "type" "fld") + 1 0) + +(define_function_unit "integer" 1 0 + (and (eq_attr "type" "integer") + (ne (symbol_ref "x86_cpu") (symbol_ref "PROCESSOR_386"))) + 2 0) + + + (define_insn "tstsi_1" [(set (cc0) (match_operand:SI 0 "nonimmediate_operand" "rm"))] @@ -142,104 +175,105 @@ DONE; }") -(define_insn "tstsf_cc" - [(set (cc0) - (match_operand:SF 0 "register_operand" "f")) - (clobber (match_scratch:HI 1 "=a"))] - "TARGET_80387 && ! TARGET_IEEE_FP" - "* -{ - if (! STACK_TOP_P (operands[0])) - abort (); - - output_asm_insn (\"ftst\", operands); - - if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) - output_asm_insn (AS1 (fstp,%y0), operands); - - return output_fp_cc0_set (insn); -}") - -;; Don't generate tstsf if generating IEEE code, since the `ftst' opcode -;; isn't IEEE compliant. - -(define_expand "tstsf" - [(parallel [(set (cc0) - (match_operand:SF 0 "register_operand" "")) - (clobber (match_scratch:HI 1 ""))])] - "TARGET_80387 && ! TARGET_IEEE_FP" - " -{ - i386_compare_gen = gen_tstsf_cc; - i386_compare_op0 = operands[0]; - DONE; -}") - -(define_insn "tstdf_cc" - [(set (cc0) - (match_operand:DF 0 "register_operand" "f")) - (clobber (match_scratch:HI 1 "=a"))] - "TARGET_80387 && ! TARGET_IEEE_FP" - "* -{ - if (! STACK_TOP_P (operands[0])) - abort (); - - output_asm_insn (\"ftst\", operands); - - if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) - output_asm_insn (AS1 (fstp,%y0), operands); - - return output_fp_cc0_set (insn); -}") - -;; Don't generate tstdf if generating IEEE code, since the `ftst' opcode -;; isn't IEEE compliant. - -(define_expand "tstdf" - [(parallel [(set (cc0) - (match_operand:DF 0 "register_operand" "")) - (clobber (match_scratch:HI 1 ""))])] - "TARGET_80387 && ! TARGET_IEEE_FP" - " -{ - i386_compare_gen = gen_tstdf_cc; - i386_compare_op0 = operands[0]; - DONE; -}") - -(define_insn "tstxf_cc" - [(set (cc0) - (match_operand:XF 0 "register_operand" "f")) - (clobber (match_scratch:HI 1 "=a"))] - "TARGET_80387 && ! TARGET_IEEE_FP" - "* -{ - if (! STACK_TOP_P (operands[0])) - abort (); - - output_asm_insn (\"ftst\", operands); - - if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) - output_asm_insn (AS1 (fstp,%y0), operands); - - return output_fp_cc0_set (insn); -}") - -;; Don't generate tstdf if generating IEEE code, since the `ftst' opcode -;; isn't IEEE compliant. - -(define_expand "tstxf" - [(parallel [(set (cc0) - (match_operand:XF 0 "register_operand" "")) - (clobber (match_scratch:HI 1 ""))])] - "TARGET_80387 && ! TARGET_IEEE_FP" - " -{ - i386_compare_gen = gen_tstxf_cc; - i386_compare_op0 = operands[0]; - DONE; -}") +;; intel1 +;;(define_insn "tstsf_cc" +;; [(set (cc0) +;; (match_operand:SF 0 "register_operand" "f")) +;; (clobber (match_scratch:HI 1 "=a"))] +;; "TARGET_80387 && ! TARGET_IEEE_FP" +;; "* +;;{ +;; if (! STACK_TOP_P (operands[0])) +;; abort (); +;; +;; output_asm_insn (\"ftst\", operands); +;; +;; if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) +;; output_asm_insn (AS1 (fstp,%y0), operands); +;; +;; return (char *) output_fp_cc0_set (insn); +;;}") +;; +;;;; Don't generate tstsf if generating IEEE code, since the `ftst' opcode +;;;; isn't IEEE compliant. +;; +;;(define_expand "tstsf" +;; [(parallel [(set (cc0) +;; (match_operand:SF 0 "register_operand" "")) +;; (clobber (match_scratch:HI 1 ""))])] +;; "TARGET_80387 && ! TARGET_IEEE_FP" +;; " +;;{ +;; i386_compare_gen = gen_tstsf_cc; +;; i386_compare_op0 = operands[0]; +;; DONE; +;;}") +;; +;;(define_insn "tstdf_cc" +;; [(set (cc0) +;; (match_operand:DF 0 "register_operand" "f")) +;; (clobber (match_scratch:HI 1 "=a"))] +;; "TARGET_80387 && ! TARGET_IEEE_FP" +;; "* +;;{ +;; if (! STACK_TOP_P (operands[0])) +;; abort (); +;; +;; output_asm_insn (\"ftst\", operands); +;; +;; if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) +;; output_asm_insn (AS1 (fstp,%y0), operands); +;; +;; return (char *) output_fp_cc0_set (insn); +;;}") +;; +;;;; Don't generate tstdf if generating IEEE code, since the `ftst' opcode +;;;; isn't IEEE compliant. +;; +;;(define_expand "tstdf" +;; [(parallel [(set (cc0) +;; (match_operand:DF 0 "register_operand" "")) +;; (clobber (match_scratch:HI 1 ""))])] +;; "TARGET_80387 && ! TARGET_IEEE_FP" +;; " +;;{ +;; i386_compare_gen = gen_tstdf_cc; +;; i386_compare_op0 = operands[0]; +;; DONE; +;;}") + +;;(define_insn "tstxf_cc" +;; [(set (cc0) +;; (match_operand:XF 0 "register_operand" "f")) +;; (clobber (match_scratch:HI 1 "=a"))] +;; "TARGET_80387 && ! TARGET_IEEE_FP" +;; "* +;;{ +;; if (! STACK_TOP_P (operands[0])) +;; abort (); +;; +;; output_asm_insn (\"ftst\", operands); +;; +;; if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) +;; output_asm_insn (AS1 (fstp,%y0), operands); +;; +;; return (char *) output_fp_cc0_set (insn); +;;}") +;; +;;;; Don't generate tstdf if generating IEEE code, since the `ftst' opcode +;;;; isn't IEEE compliant. +;; +;;(define_expand "tstxf" +;; [(parallel [(set (cc0) +;; (match_operand:XF 0 "register_operand" "")) +;; (clobber (match_scratch:HI 1 ""))])] +;; "TARGET_80387 && ! TARGET_IEEE_FP" +;; " +;;{ +;; i386_compare_gen = gen_tstxf_cc; +;; i386_compare_op0 = operands[0]; +;; DONE; +;;}") ;;- compare instructions. See comments above tstM patterns about ;; expansion of these insns. @@ -341,55 +375,56 @@ ;; SFmode, there is the normal insn, and an insn where the second operand ;; is converted to the desired mode. +;;intel1 operand 1 and 2 changed from nonimmediate_operand to general_operand (define_insn "" [(set (cc0) (match_operator 2 "VOIDmode_compare_op" - [(match_operand:XF 0 "nonimmediate_operand" "f") - (match_operand:XF 1 "nonimmediate_operand" "f")])) + [(match_operand:XF 0 "general_operand" "f") + (match_operand:XF 1 "general_operand" "f")])) (clobber (match_scratch:HI 3 "=a"))] "TARGET_80387 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" - "* return output_float_compare (insn, operands);") + "* return (char *) output_float_compare (insn, operands);") (define_insn "" [(set (cc0) (match_operator 2 "VOIDmode_compare_op" [(match_operand:XF 0 "register_operand" "f") (float:XF - (match_operand:SI 1 "nonimmediate_operand" "rm"))])) + (match_operand:SI 1 "general_operand" "rm"))])) (clobber (match_scratch:HI 3 "=a"))] "TARGET_80387" - "* return output_float_compare (insn, operands);") + "* return (char *) output_float_compare (insn, operands);") (define_insn "" [(set (cc0) (match_operator 2 "VOIDmode_compare_op" [(float:XF - (match_operand:SI 0 "nonimmediate_operand" "rm")) + (match_operand:SI 0 "general_operand" "rm")) (match_operand:XF 1 "register_operand" "f")])) (clobber (match_scratch:HI 3 "=a"))] "TARGET_80387" - "* return output_float_compare (insn, operands);") + "* return (char *) output_float_compare (insn, operands);") (define_insn "" [(set (cc0) (match_operator 2 "VOIDmode_compare_op" [(match_operand:XF 0 "register_operand" "f") (float_extend:XF - (match_operand:DF 1 "nonimmediate_operand" "fm"))])) + (match_operand:DF 1 "general_operand" "fm"))])) (clobber (match_scratch:HI 3 "=a"))] "TARGET_80387" - "* return output_float_compare (insn, operands);") + "* return (char *) output_float_compare (insn, operands);") (define_insn "" [(set (cc0) (match_operator 2 "VOIDmode_compare_op" [(match_operand:XF 0 "register_operand" "f") (float_extend:XF - (match_operand:SF 1 "nonimmediate_operand" "fm"))])) + (match_operand:SF 1 "general_operand" "fm"))])) (clobber (match_scratch:HI 3 "=a"))] "TARGET_80387" - "* return output_float_compare (insn, operands);") + "* return (char *) output_float_compare (insn, operands);") (define_insn "" [(set (cc0) @@ -397,17 +432,17 @@ (match_operand:XF 1 "register_operand" "f"))) (clobber (match_scratch:HI 2 "=a"))] "TARGET_80387" - "* return output_float_compare (insn, operands);") + "* return (char *) output_float_compare (insn, operands);") (define_insn "" [(set (cc0) (match_operator 2 "VOIDmode_compare_op" - [(match_operand:DF 0 "nonimmediate_operand" "f,fm") - (match_operand:DF 1 "nonimmediate_operand" "fm,f")])) + [(match_operand:DF 0 "general_operand" "f,fm") + (match_operand:DF 1 "general_operand" "fm,f")])) (clobber (match_scratch:HI 3 "=a,a"))] "TARGET_80387 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" - "* return output_float_compare (insn, operands);") + "* return (char *) output_float_compare (insn, operands);") (define_insn "" [(set (cc0) @@ -417,7 +452,7 @@ (match_operand:SI 1 "nonimmediate_operand" "rm"))])) (clobber (match_scratch:HI 3 "=a"))] "TARGET_80387" - "* return output_float_compare (insn, operands);") + "* return (char *) output_float_compare (insn, operands);") (define_insn "" [(set (cc0) @@ -427,7 +462,7 @@ (match_operand:DF 1 "register_operand" "f")])) (clobber (match_scratch:HI 3 "=a"))] "TARGET_80387" - "* return output_float_compare (insn, operands);") + "* return (char *) output_float_compare (insn, operands);") (define_insn "" [(set (cc0) @@ -437,7 +472,7 @@ (match_operand:SF 1 "nonimmediate_operand" "fm"))])) (clobber (match_scratch:HI 3 "=a"))] "TARGET_80387" - "* return output_float_compare (insn, operands);") + "* return (char *) output_float_compare (insn, operands);") (define_insn "" [(set (cc0) @@ -447,7 +482,18 @@ (match_operand:DF 1 "register_operand" "f")])) (clobber (match_scratch:HI 3 "=a"))] "TARGET_80387" - "* return output_float_compare (insn, operands);") + "* return (char *) output_float_compare (insn, operands);") + +;;intel1 +(define_insn "" + [(set (cc0) + (match_operator 2 "VOIDmode_compare_op" + [(float_extend:DF + (match_operand:SF 0 "register_operand" "f")) + (match_operand:DF 1 "general_operand" "fm")])) + (clobber (match_scratch:HI 3 "=a"))] + "TARGET_80387" + "* return (char *) output_float_compare (insn, operands);") (define_insn "" [(set (cc0) @@ -455,7 +501,7 @@ (match_operand:DF 1 "register_operand" "f"))) (clobber (match_scratch:HI 2 "=a"))] "TARGET_80387" - "* return output_float_compare (insn, operands);") + "* return (char *) output_float_compare (insn, operands);") ;; These two insns will never be generated by combine due to the mode of ;; the COMPARE. @@ -466,7 +512,7 @@ ; (match_operand:SF 1 "register_operand" "f")))) ; (clobber (match_scratch:HI 2 "=a"))] ; "TARGET_80387" -; "* return output_float_compare (insn, operands);") +; "* return (char *) output_float_compare (insn, operands);") ; ;(define_insn "" ; [(set (cc0) @@ -475,17 +521,18 @@ ; (match_operand:DF 1 "register_operand" "f"))) ; (clobber (match_scratch:HI 2 "=a"))] ; "TARGET_80387" -; "* return output_float_compare (insn, operands);") +; "* return (char *) output_float_compare (insn, operands);") +;;intel1 operand 1 changed from nonimmediate_operand to general_operand (define_insn "cmpsf_cc_1" [(set (cc0) (match_operator 2 "VOIDmode_compare_op" [(match_operand:SF 0 "nonimmediate_operand" "f,fm") - (match_operand:SF 1 "nonimmediate_operand" "fm,f")])) + (match_operand:SF 1 "general_operand" "fm,f")])) (clobber (match_scratch:HI 3 "=a,a"))] "TARGET_80387 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" - "* return output_float_compare (insn, operands);") + "* return (char *) output_float_compare (insn, operands);") (define_insn "" [(set (cc0) @@ -495,7 +542,7 @@ (match_operand:SI 1 "nonimmediate_operand" "rm"))])) (clobber (match_scratch:HI 3 "=a"))] "TARGET_80387" - "* return output_float_compare (insn, operands);") + "* return (char *) output_float_compare (insn, operands);") (define_insn "" [(set (cc0) @@ -505,7 +552,7 @@ (match_operand:SF 1 "register_operand" "f")])) (clobber (match_scratch:HI 3 "=a"))] "TARGET_80387" - "* return output_float_compare (insn, operands);") + "* return (char *) output_float_compare (insn, operands);") (define_insn "" [(set (cc0) @@ -513,12 +560,12 @@ (match_operand:SF 1 "register_operand" "f"))) (clobber (match_scratch:HI 2 "=a"))] "TARGET_80387" - "* return output_float_compare (insn, operands);") + "* return (char *) output_float_compare (insn, operands);") (define_expand "cmpxf" [(set (cc0) - (compare (match_operand:XF 0 "register_operand" "") - (match_operand:XF 1 "nonimmediate_operand" "")))] + (compare (match_operand:XF 0 "register_operand" "") + (match_operand:XF 1 "nonimmediate_operand" "")))] "TARGET_80387" " { @@ -529,10 +576,11 @@ DONE; }") +;;intel1 operand 1 changed from nonimmediate_operand to general_operand (define_expand "cmpdf" [(set (cc0) (compare (match_operand:DF 0 "register_operand" "") - (match_operand:DF 1 "nonimmediate_operand" "")))] + (match_operand:DF 1 "general_operand" "")))] "TARGET_80387" " { @@ -543,10 +591,11 @@ DONE; }") +;;intel1 operand 1 changed from nonimmediate_operand to general_operand (define_expand "cmpsf" [(set (cc0) (compare (match_operand:SF 0 "register_operand" "") - (match_operand:SF 1 "nonimmediate_operand" "")))] + (match_operand:SF 1 "general_operand" "")))] "TARGET_80387" " { @@ -559,17 +608,17 @@ (define_expand "cmpxf_cc" [(parallel [(set (cc0) - (compare (match_operand:XF 0 "register_operand" "") - (match_operand:XF 1 "register_operand" ""))) - (clobber (match_scratch:HI 2 ""))])] + (compare (match_operand:XF 0 "register_operand" "") + (match_operand:XF 1 "register_operand" ""))) + (clobber (match_scratch:HI 2 ""))])] "TARGET_80387" "") (define_expand "cmpxf_ccfpeq" [(parallel [(set (cc0) - (compare:CCFPEQ (match_operand:XF 0 "register_operand" "") - (match_operand:XF 1 "register_operand" ""))) - (clobber (match_scratch:HI 2 ""))])] + (compare:CCFPEQ (match_operand:XF 0 "register_operand" "") + (match_operand:XF 1 "register_operand" ""))) + (clobber (match_scratch:HI 2 ""))])] "TARGET_80387" " { @@ -740,7 +789,7 @@ (define_insn "" [(set (match_operand:SI 0 "push_operand" "=<") (match_operand:SI 1 "general_operand" "g"))] - "TARGET_386" + "! TARGET_486" "push%L0 %1") ;; On a 486, it is faster to move MEM to a REG and then push, rather than @@ -748,14 +797,8 @@ (define_insn "" [(set (match_operand:SI 0 "push_operand" "=<") - (match_operand:SI 1 "nonmemory_operand" "ri"))] - "!TARGET_386 && TARGET_MOVE" - "push%L0 %1") - -(define_insn "" - [(set (match_operand:SI 0 "push_operand" "=<") (match_operand:SI 1 "general_operand" "ri"))] - "!TARGET_386 && !TARGET_MOVE" + "TARGET_486" "push%L0 %1") ;; General case of fullword move. @@ -773,15 +816,6 @@ if (flag_pic && SYMBOLIC_CONST (operands[1])) emit_pic_move (operands, SImode); - - /* Don't generate memory->memory moves, go through a register */ - else if (TARGET_MOVE - && (reload_in_progress | reload_completed) == 0 - && GET_CODE (operands[0]) == MEM - && GET_CODE (operands[1]) == MEM) - { - operands[1] = force_reg (SImode, operands[1]); - } }") ;; On i486, incl reg is faster than movl $1,reg. @@ -789,7 +823,7 @@ (define_insn "" [(set (match_operand:SI 0 "general_operand" "=g,r") (match_operand:SI 1 "general_operand" "ri,m"))] - "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)" + "" "* { rtx link; @@ -808,52 +842,21 @@ /* Fastest way to change a 0 to a 1. */ return AS1 (inc%L0,%0); - if (flag_pic && SYMBOLIC_CONST (operands[1])) - return AS2 (lea%L0,%a1,%0); - return AS2 (mov%L0,%1,%0); }") (define_insn "" [(set (match_operand:HI 0 "push_operand" "=<") (match_operand:HI 1 "general_operand" "g"))] - "TARGET_386" - "push%W0 %1") - -(define_insn "" - [(set (match_operand:HI 0 "push_operand" "=<") - (match_operand:HI 1 "nonmemory_operand" "ri"))] - "!TARGET_386 && TARGET_MOVE" - "push%W0 %1") - -(define_insn "" - [(set (match_operand:HI 0 "push_operand" "=<") - (match_operand:HI 1 "general_operand" "ri"))] - "!TARGET_386 && !TARGET_MOVE" + "" "push%W0 %1") ;; On i486, an incl and movl are both faster than incw and movw. -(define_expand "movhi" - [(set (match_operand:HI 0 "general_operand" "") - (match_operand:HI 1 "general_operand" ""))] - "" - " -{ - /* Don't generate memory->memory moves, go through a register */ - if (TARGET_MOVE - && (reload_in_progress | reload_completed) == 0 - && GET_CODE (operands[0]) == MEM - && GET_CODE (operands[1]) == MEM) - { - operands[1] = force_reg (HImode, operands[1]); - } -}") - -(define_insn "" +(define_insn "movhi" [(set (match_operand:HI 0 "general_operand" "=g,r") (match_operand:HI 1 "general_operand" "ri,m"))] - "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)" + "" "* { rtx link; @@ -883,26 +886,10 @@ return AS2 (mov%W0,%1,%0); }") -(define_expand "movstricthi" - [(set (strict_low_part (match_operand:HI 0 "general_operand" "")) - (match_operand:HI 1 "general_operand" ""))] - "" - " -{ - /* Don't generate memory->memory moves, go through a register */ - if (TARGET_MOVE - && (reload_in_progress | reload_completed) == 0 - && GET_CODE (operands[0]) == MEM - && GET_CODE (operands[1]) == MEM) - { - operands[1] = force_reg (HImode, operands[1]); - } -}") - -(define_insn "" +(define_insn "movstricthi" [(set (strict_low_part (match_operand:HI 0 "general_operand" "+g,r")) (match_operand:HI 1 "general_operand" "ri,m"))] - "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)" + "" "* { rtx link; @@ -930,24 +917,8 @@ ;; the amount pushed up to a halfword. (define_insn "" [(set (match_operand:QI 0 "push_operand" "=<") - (match_operand:QI 1 "immediate_operand" "n"))] + (match_operand:QI 1 "general_operand" "q"))] "" - "* return AS1 (push%W0,%1);") - -(define_insn "" - [(set (match_operand:QI 0 "push_operand" "=<") - (match_operand:QI 1 "nonimmediate_operand" "q"))] - "!TARGET_MOVE" - "* -{ - operands[1] = gen_rtx (REG, HImode, REGNO (operands[1])); - return AS1 (push%W0,%1); -}") - -(define_insn "" - [(set (match_operand:QI 0 "push_operand" "=<") - (match_operand:QI 1 "register_operand" "q"))] - "TARGET_MOVE" "* { operands[1] = gen_rtx (REG, HImode, REGNO (operands[1])); @@ -959,26 +930,10 @@ ;; ??? Do a recognizer for zero_extract that looks just like this, but reads ;; or writes %ah, %bh, %ch, %dh. -(define_expand "movqi" - [(set (match_operand:QI 0 "general_operand" "") - (match_operand:QI 1 "general_operand" ""))] - "" - " -{ - /* Don't generate memory->memory moves, go through a register */ - if (TARGET_MOVE - && (reload_in_progress | reload_completed) == 0 - && GET_CODE (operands[0]) == MEM - && GET_CODE (operands[1]) == MEM) - { - operands[1] = force_reg (QImode, operands[1]); - } -}") - -(define_insn "" +(define_insn "movqi" [(set (match_operand:QI 0 "general_operand" "=q,*r,qm") (match_operand:QI 1 "general_operand" "*g,q,qn"))] - "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)" + "" "* { rtx link; @@ -1013,26 +968,10 @@ ;; If operands[1] is a constant, then an andl/orl sequence would be ;; faster. -(define_expand "movstrictqi" - [(set (strict_low_part (match_operand:QI 0 "general_operand" "")) - (match_operand:QI 1 "general_operand" ""))] - "" - " -{ - /* Don't generate memory->memory moves, go through a register */ - if (TARGET_MOVE - && (reload_in_progress | reload_completed) == 0 - && GET_CODE (operands[0]) == MEM - && GET_CODE (operands[1]) == MEM) - { - operands[1] = force_reg (QImode, operands[1]); - } -}") - -(define_insn "" +(define_insn "movstrictqi" [(set (strict_low_part (match_operand:QI 0 "general_operand" "+qm,q")) (match_operand:QI 1 "general_operand" "*qn,m"))] - "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)" + "" "* { rtx link; @@ -1061,43 +1000,10 @@ return AS2 (mov%B0,%1,%0); }") -(define_expand "movsf" - [(set (match_operand:SF 0 "general_operand" "") - (match_operand:SF 1 "general_operand" ""))] - "" - " -{ - /* Special case memory->memory moves and pushes */ - if (TARGET_MOVE - && (reload_in_progress | reload_completed) == 0 - && GET_CODE (operands[0]) == MEM - && (GET_CODE (operands[1]) == MEM || push_operand (operands[0], SFmode))) - { - rtx (*genfunc) PROTO((rtx, rtx)) = (push_operand (operands[0], SFmode)) - ? gen_movsf_push - : gen_movsf_mem; - - emit_insn ((*genfunc) (operands[0], operands[1])); - DONE; - } - - /* If we are loading a floating point constant that isn't 0 or 1 into a register, - indicate we need the pic register loaded. This could be optimized into stores - of constants if the target eventually moves to memory, but better safe than - sorry. */ - if (flag_pic - && GET_CODE (operands[0]) != MEM - && GET_CODE (operands[1]) == CONST_DOUBLE - && !standard_80387_constant_p (operands[1])) - { - current_function_uses_pic_offset_table = 1; - } -}") - -(define_insn "movsf_push_nomove" +(define_insn "" [(set (match_operand:SF 0 "push_operand" "=<,<") (match_operand:SF 1 "general_operand" "gF,f"))] - "!TARGET_MOVE" + "" "* { if (STACK_REG_P (operands[1])) @@ -1122,61 +1028,24 @@ return AS1 (push%L1,%1); }") -(define_insn "movsf_push" - [(set (match_operand:SF 0 "push_operand" "=<,<,<,<") - (match_operand:SF 1 "general_operand" "rF,f,m,m")) - (clobber (match_scratch:SI 2 "=X,X,r,X"))] - "" - "* -{ - if (STACK_REG_P (operands[1])) - { - rtx xops[3]; - - if (! STACK_TOP_P (operands[1])) - abort (); - - xops[0] = AT_SP (SFmode); - xops[1] = GEN_INT (4); - xops[2] = stack_pointer_rtx; - - output_asm_insn (AS2 (sub%L2,%1,%2), xops); - - if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) - output_asm_insn (AS1 (fstp%S0,%0), xops); - else - output_asm_insn (AS1 (fst%S0,%0), xops); - RET; - } - - else if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != REG) - return AS1 (push%L1,%1); - - else - { - output_asm_insn (AS2 (mov%L2,%1,%2), operands); - return AS1 (push%L2,%2); - } -}") +;; Allow MEM-MEM moves before reload. The reload class for such a +;; move will be ALL_REGS. PREFERRED_RELOAD_CLASS will narrow this to +;; GENERAL_REGS. For the purposes of regclass, prefer FLOAT_REGS. -;; Special memory<->memory pattern that combine will recreate from the -;; moves to pseudos. -(define_insn "movsf_mem" - [(set (match_operand:SF 0 "memory_operand" "=m") - (match_operand:SF 1 "memory_operand" "m")) - (clobber (match_scratch:SI 2 "=&r"))] +;;intel1 +(define_insn "memmovsf" + [(set (match_operand:SF 0 "memory_operand" "=r,m") + (match_operand:SF 1 "memory_operand" "m,r"))] "" "* { - output_asm_insn (AS2 (mov%L2,%1,%2), operands); - return AS2 (mov%L0,%2,%0); + return (char *) singlemove_string (operands); }") -;; For the purposes of regclass, prefer FLOAT_REGS. -(define_insn "movsf_normal" +(define_insn "movsf" [(set (match_operand:SF 0 "general_operand" "=*rfm,*rf,f,!*rm") (match_operand:SF 1 "general_operand" "*rf,*rfm,fG,fF"))] - "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)" + "" "* { int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; @@ -1218,67 +1087,21 @@ /* Handle other kinds of reads to the 387 */ if (STACK_TOP_P (operands[0]) && GET_CODE (operands[1]) == CONST_DOUBLE) - return output_move_const_single (operands); + return (char *) output_move_const_single (operands); if (STACK_TOP_P (operands[0])) return AS1 (fld%z1,%y1); /* Handle all SFmode moves not involving the 387 */ - return singlemove_string (operands); -}") - -(define_insn "swapsf" - [(set (match_operand:SF 0 "register_operand" "f") - (match_operand:SF 1 "register_operand" "f")) - (set (match_dup 1) - (match_dup 0))] - "" - "* -{ - if (STACK_TOP_P (operands[0])) - return AS1 (fxch,%1); - else - return AS1 (fxch,%0); -}") - -(define_expand "movdf" - [(set (match_operand:DF 0 "general_operand" "") - (match_operand:DF 1 "general_operand" ""))] - "" - " -{ - /* Special case memory->memory moves and pushes */ - if (TARGET_MOVE - && (reload_in_progress | reload_completed) == 0 - && GET_CODE (operands[0]) == MEM - && (GET_CODE (operands[1]) == MEM || push_operand (operands[0], DFmode))) - { - rtx (*genfunc) PROTO((rtx, rtx)) = (push_operand (operands[0], DFmode)) - ? gen_movdf_push - : gen_movdf_mem; - - emit_insn ((*genfunc) (operands[0], operands[1])); - DONE; - } - - /* If we are loading a floating point constant that isn't 0 or 1 into a register, - indicate we need the pic register loaded. This could be optimized into stores - of constants if the target eventually moves to memory, but better safe than - sorry. */ - if (flag_pic - && GET_CODE (operands[0]) != MEM - && GET_CODE (operands[1]) == CONST_DOUBLE - && !standard_80387_constant_p (operands[1])) - { - current_function_uses_pic_offset_table = 1; - } -}") + return (char *) singlemove_string (operands); +}"[(set_attr "type" "fld")]) -(define_insn "movdf_push_nomove" +;;should change to handle the memory operands[1] without doing df push.. +(define_insn "" [(set (match_operand:DF 0 "push_operand" "=<,<") (match_operand:DF 1 "general_operand" "gF,f"))] - "!TARGET_MOVE" + "" "* { if (STACK_REG_P (operands[1])) @@ -1299,55 +1122,41 @@ RET; } else - return output_move_double (operands); + return (char *) output_move_double (operands); }") -(define_insn "movdf_push" - [(set (match_operand:DF 0 "push_operand" "=<,<,<,<,<") - (match_operand:DF 1 "general_operand" "rF,f,o,o,o")) - (clobber (match_scratch:SI 2 "=X,X,&r,&r,X")) - (clobber (match_scratch:SI 3 "=X,X,&r,X,X"))] +(define_insn "swapdf" + [(set (match_operand:DF 0 "register_operand" "f") + (match_operand:DF 1 "register_operand" "f")) + (set (match_dup 1) + (match_dup 0))] "" "* { - if (STACK_REG_P (operands[1])) - { - rtx xops[3]; - - xops[0] = AT_SP (SFmode); - xops[1] = GEN_INT (8); - xops[2] = stack_pointer_rtx; - - output_asm_insn (AS2 (sub%L2,%1,%2), xops); - - if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) - output_asm_insn (AS1 (fstp%Q0,%0), xops); - else - output_asm_insn (AS1 (fst%Q0,%0), xops); - - RET; - } - - else if (GET_CODE (operands[1]) != MEM) - return output_move_double (operands); - + if (STACK_TOP_P (operands[0])) + return AS1 (fxch,%1); else - return output_move_pushmem (operands, insn, GET_MODE_SIZE (DFmode), 2, 4); + return AS1 (fxch,%0); }") -(define_insn "movdf_mem" - [(set (match_operand:DF 0 "memory_operand" "=o,o") - (match_operand:DF 1 "memory_operand" "o,o")) - (clobber (match_scratch:SI 2 "=&r,&r")) - (clobber (match_scratch:SI 3 "=&r,X"))] +;; Allow MEM-MEM moves before reload. The reload class for such a +;; move will be ALL_REGS. PREFERRED_RELOAD_CLASS will narrow this to +;; GENERAL_REGS. For the purposes of regclass, prefer FLOAT_REGS. + +;;intel1 +(define_insn "memmovdf" + [(set (match_operand:DF 0 "memory_operand" "=r,m") + (match_operand:DF 1 "memory_operand" "m,r"))] "" - "* return output_move_memory (operands, insn, GET_MODE_SIZE (DFmode), 2, 4);") + "* +{ + return (char *) output_move_double (operands); +}") -;; For the purposes of regclass, prefer FLOAT_REGS. -(define_insn "movdf_normal" - [(set (match_operand:DF 0 "general_operand" "=f,fm,!*rf,!*rm") - (match_operand:DF 1 "general_operand" "fmG,f,*rfm,*rfF"))] - "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)" +(define_insn "movdf" + [(set (match_operand:DF 0 "general_operand" "=*rfm,*rf,f,!*rm") + (match_operand:DF 1 "general_operand" "*rf,*rfm,fG,fF"))] + "" "* { int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; @@ -1389,68 +1198,20 @@ /* Handle other kinds of reads to the 387 */ if (STACK_TOP_P (operands[0]) && GET_CODE (operands[1]) == CONST_DOUBLE) - return output_move_const_single (operands); + return (char *) output_move_const_single (operands); if (STACK_TOP_P (operands[0])) return AS1 (fld%z1,%y1); /* Handle all DFmode moves not involving the 387 */ - return output_move_double (operands); -}") + return (char *) output_move_double (operands); +}"[(set_attr "type" "fld")]) -(define_insn "swapdf" - [(set (match_operand:DF 0 "register_operand" "f") - (match_operand:DF 1 "register_operand" "f")) - (set (match_dup 1) - (match_dup 0))] - "" - "* -{ - if (STACK_TOP_P (operands[0])) - return AS1 (fxch,%1); - else - return AS1 (fxch,%0); -}") - -(define_expand "movxf" - [(set (match_operand:XF 0 "general_operand" "") - (match_operand:XF 1 "general_operand" ""))] - "" - " -{ - /* Special case memory->memory moves and pushes */ - if (TARGET_MOVE - && (reload_in_progress | reload_completed) == 0 - && GET_CODE (operands[0]) == MEM - && (GET_CODE (operands[1]) == MEM || push_operand (operands[0], XFmode))) - { - rtx (*genfunc) PROTO((rtx, rtx)) = (push_operand (operands[0], XFmode)) - ? gen_movxf_push - : gen_movxf_mem; - - emit_insn ((*genfunc) (operands[0], operands[1])); - DONE; - } - - /* If we are loading a floating point constant that isn't 0 or 1 into a register, - indicate we need the pic register loaded. This could be optimized into stores - of constants if the target eventually moves to memory, but better safe than - sorry. */ - if (flag_pic - && GET_CODE (operands[0]) != MEM - && GET_CODE (operands[1]) == CONST_DOUBLE - && !standard_80387_constant_p (operands[1])) - { - current_function_uses_pic_offset_table = 1; - } -}") - - -(define_insn "movxf_push_nomove" +(define_insn "" [(set (match_operand:XF 0 "push_operand" "=<,<") (match_operand:XF 1 "general_operand" "gF,f"))] - "!TARGET_MOVE" + "" "* { if (STACK_REG_P (operands[1])) @@ -1469,53 +1230,29 @@ RET; } else - return output_move_double (operands); + return (char *) output_move_double (operands); }") -(define_insn "movxf_push" - [(set (match_operand:XF 0 "push_operand" "=<,<,<,<,<") - (match_operand:XF 1 "general_operand" "rF,f,o,o,o")) - (clobber (match_scratch:SI 2 "=X,X,&r,&r,X")) - (clobber (match_scratch:SI 3 "=X,X,&r,X,X"))] +(define_insn "swapxf" + [(set (match_operand:XF 0 "register_operand" "f") + (match_operand:XF 1 "register_operand" "f")) + (set (match_dup 1) + (match_dup 0))] "" "* { - if (STACK_REG_P (operands[1])) - { - rtx xops[3]; - - xops[0] = AT_SP (SFmode); - xops[1] = GEN_INT (12); - xops[2] = stack_pointer_rtx; - - output_asm_insn (AS2 (sub%L2,%1,%2), xops); - output_asm_insn (AS1 (fstp%T0,%0), xops); - if (! find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) - output_asm_insn (AS1 (fld%T0,%0), xops); - - RET; - } - - else if (GET_CODE (operands[1]) != MEM - || GET_CODE (operands[2]) != REG) - return output_move_double (operands); - + if (STACK_TOP_P (operands[0])) + return AS1 (fxch,%1); else - return output_move_pushmem (operands, insn, GET_MODE_SIZE (XFmode), 2, 4); + return AS1 (fxch,%0); }") -(define_insn "movxf_mem" - [(set (match_operand:XF 0 "memory_operand" "=o,o") - (match_operand:XF 1 "memory_operand" "o,o")) - (clobber (match_scratch:SI 2 "=&r,&r")) - (clobber (match_scratch:SI 3 "=&r,X"))] - "" - "* return output_move_memory (operands, insn, GET_MODE_SIZE (XFmode), 2, 4);") - -(define_insn "movxf_normal" +(define_insn "movxf" [(set (match_operand:XF 0 "general_operand" "=f,fm,!*rf,!*rm") (match_operand:XF 1 "general_operand" "fmG,f,*rfm,*rfF"))] - "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)" +;; [(set (match_operand:XF 0 "general_operand" "=*rf,*rfm,f,!*rm") +;; (match_operand:XF 1 "general_operand" "*rfm,*rf,fG,fF"))] + "" "* { int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; @@ -1558,61 +1295,33 @@ /* Handle other kinds of reads to the 387 */ if (STACK_TOP_P (operands[0]) && GET_CODE (operands[1]) == CONST_DOUBLE) - return output_move_const_single (operands); + return (char *) output_move_const_single (operands); if (STACK_TOP_P (operands[0])) return AS1 (fld%z1,%y1); /* Handle all XFmode moves not involving the 387 */ - return output_move_double (operands); -}") - -(define_insn "swapxf" - [(set (match_operand:XF 0 "register_operand" "f") - (match_operand:XF 1 "register_operand" "f")) - (set (match_dup 1) - (match_dup 0))] - "" - "* -{ - if (STACK_TOP_P (operands[0])) - return AS1 (fxch,%1); - else - return AS1 (fxch,%0); + return (char *) output_move_double (operands); }") (define_insn "" - [(set (match_operand:DI 0 "push_operand" "=<,<,<,<") - (match_operand:DI 1 "general_operand" "riF,o,o,o")) - (clobber (match_scratch:SI 2 "=X,&r,&r,X")) - (clobber (match_scratch:SI 3 "=X,&r,X,X"))] + [(set (match_operand:DI 0 "push_operand" "=<") + (match_operand:DI 1 "general_operand" "roiF"))] "" "* { - if (GET_CODE (operands[1]) != MEM) - return output_move_double (operands); - - else - return output_move_pushmem (operands, insn, GET_MODE_SIZE (DImode), 2, 4); + return (char *) output_move_double (operands); }") (define_insn "movdi" - [(set (match_operand:DI 0 "general_operand" "=o,o,r,rm") - (match_operand:DI 1 "general_operand" "o,o,m,riF")) - (clobber (match_scratch:SI 2 "=&r,&r,X,X")) - (clobber (match_scratch:SI 3 "=&r,X,X,X"))] + [(set (match_operand:DI 0 "general_operand" "=r,rm") + (match_operand:DI 1 "general_operand" "m,riF"))] "" "* { - rtx low[2], high[2], xop[6]; - - if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) - return output_move_double (operands); - else - return output_move_memory (operands, insn, GET_MODE_SIZE (DImode), 2, 4); + return (char *) output_move_double (operands); }") - ;;- conversion instructions ;;- NONE @@ -1627,7 +1336,7 @@ "" "* { - if ((!TARGET_386 || REGNO (operands[0]) == 0) + if (((TARGET_486 || TARGET_PENTIUM) || REGNO (operands[0]) == 0) && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])) { rtx xops[2]; @@ -1637,6 +1346,25 @@ RET; } + if ((((TARGET_486 || TARGET_PENTIUM))) + && !reg_overlap_mentioned_p(operands[0],operands[1])) + { + rtx xops[2]; + output_asm_insn (AS2 (xor%L0,%0,%0),operands); + output_asm_insn (AS2 (mov%W0,%1,%w0),operands); + RET; + } + + if ((TARGET_486 || TARGET_PENTIUM)) + { + rtx xops[2]; + xops[0] = operands[0]; + xops[1] = gen_rtx (CONST_INT, VOIDmode, 0xffff); + output_asm_insn (AS2 (mov%W0,%1,%w0),operands); + output_asm_insn (AS2 (and%L0,%1,%k0), xops); + RET; + } + #ifdef INTEL_SYNTAX return AS2 (movzx,%1,%0); #else @@ -1651,7 +1379,7 @@ "" "* { - if ((!TARGET_386 || REGNO (operands[0]) == 0) + if (((TARGET_486 || TARGET_PENTIUM) || REGNO (operands[0]) == 0) && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])) { rtx xops[2]; @@ -1661,6 +1389,26 @@ RET; } + /* intel1 */ + if ((((TARGET_486 || TARGET_PENTIUM))) && + reg_fits_class_p (operands[0], Q_REGS, 0, SImode)) + { + rtx xops[2]; + if(!reg_overlap_mentioned_p(operands[0],operands[1])) + { + output_asm_insn (AS2 (xor%L0,%k0,%k0),operands); + output_asm_insn (AS2 (mov%B0,%1,%b0),operands); + } + else + { + xops[0] = operands[0]; + xops[1] = gen_rtx (CONST_INT, VOIDmode, 0xff); + output_asm_insn (AS2 (mov%B0,%1,%b0),operands); + output_asm_insn (AS2 (and%L0,%1,%k0), xops); + } + RET; + } + #ifdef INTEL_SYNTAX return AS2 (movzx,%1,%0); #else @@ -1675,7 +1423,7 @@ "" "* { - if ((!TARGET_386 || REGNO (operands[0]) == 0) + if (((TARGET_486 || TARGET_PENTIUM) || REGNO (operands[0]) == 0) && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])) { rtx xops[2]; @@ -1685,6 +1433,37 @@ RET; } + /* intel1 */ + if ((((TARGET_486 || TARGET_PENTIUM))) && + reg_fits_class_p (operands[0], Q_REGS, 0, SImode)) + { + rtx xops[2]; + if(!reg_overlap_mentioned_p(operands[0],operands[1])) + { + output_asm_insn (AS2 (xor%L0,%0,%0),operands); + output_asm_insn (AS2 (mov%B0,%1,%b0),operands); + } + else + { + xops[0] = operands[0]; + xops[1] = gen_rtx (CONST_INT, VOIDmode, 0xff); + output_asm_insn (AS2 (mov%B0,%1,%b0),operands); + output_asm_insn (AS2 (and%L0,%1,%k0), xops); + } + RET; + } + + if ((TARGET_486 || TARGET_PENTIUM) && GET_CODE (operands[1]) == REG) + { + rtx xops[2]; + xops[0] = operands[0]; + operands[1] = gen_rtx (REG, SImode, REGNO (operands[1])); + xops[1] = gen_rtx (CONST_INT, VOIDmode, 0xff); + output_asm_insn (AS2 (mov%L0,%1,%0),operands); + output_asm_insn (AS2 (and%L0,%1,%k0), xops); + RET; + } + #ifdef INTEL_SYNTAX return AS2 (movzx,%1,%0); #else @@ -2011,15 +1790,15 @@ (define_expand "fixuns_truncxfsi2" [(set (match_dup 4) - (match_operand:XF 1 "register_operand" "")) + (match_operand:XF 1 "register_operand" "")) (parallel [(set (match_dup 2) - (fix:DI (fix:XF (match_dup 4)))) - (clobber (match_dup 4)) - (clobber (match_dup 5)) - (clobber (match_dup 6)) - (clobber (match_scratch:SI 7 ""))]) + (fix:DI (fix:XF (match_dup 4)))) + (clobber (match_dup 4)) + (clobber (match_dup 5)) + (clobber (match_dup 6)) + (clobber (match_scratch:SI 7 ""))]) (set (match_operand:SI 0 "general_operand" "") - (match_dup 3))] + (match_dup 3))] "TARGET_80387" " { @@ -2076,13 +1855,13 @@ (define_expand "fix_truncxfdi2" [(set (match_dup 2) - (match_operand:XF 1 "register_operand" "")) + (match_operand:XF 1 "register_operand" "")) (parallel [(set (match_operand:DI 0 "general_operand" "") - (fix:DI (fix:XF (match_dup 2)))) - (clobber (match_dup 2)) - (clobber (match_dup 3)) - (clobber (match_dup 4)) - (clobber (match_scratch:SI 5 ""))])] + (fix:DI (fix:XF (match_dup 2)))) + (clobber (match_dup 2)) + (clobber (match_dup 3)) + (clobber (match_dup 4)) + (clobber (match_scratch:SI 5 ""))])] "TARGET_80387" " { @@ -2132,23 +1911,23 @@ (define_insn "" [(set (match_operand:DI 0 "general_operand" "=rm") - (fix:DI (fix:XF (match_operand:XF 1 "register_operand" "f")))) + (fix:DI (fix:XF (match_operand:XF 1 "register_operand" "f")))) (clobber (match_dup 1)) (clobber (match_operand:SI 2 "memory_operand" "m")) (clobber (match_operand:SI 3 "memory_operand" "m")) (clobber (match_scratch:SI 4 "=&q"))] "TARGET_80387" - "* return output_fix_trunc (insn, operands);") + "* return (char *) output_fix_trunc (insn, operands);") (define_insn "" - [(set (match_operand:DI 0 "general_operand" "=rm") - (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f")))) + [(set (match_operand:DI 0 "general_operand" "=rm") + (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f")))) (clobber (match_dup 1)) (clobber (match_operand:SI 2 "memory_operand" "m")) (clobber (match_operand:SI 3 "memory_operand" "m")) (clobber (match_scratch:SI 4 "=&q"))] "TARGET_80387" - "* return output_fix_trunc (insn, operands);") + "* return (char *) output_fix_trunc (insn, operands);") (define_insn "" [(set (match_operand:DI 0 "general_operand" "=rm") @@ -2158,17 +1937,17 @@ (clobber (match_operand:SI 3 "memory_operand" "m")) (clobber (match_scratch:SI 4 "=&q"))] "TARGET_80387" - "* return output_fix_trunc (insn, operands);") + "* return (char *) output_fix_trunc (insn, operands);") ;; Signed MODE_FLOAT conversion to SImode. (define_expand "fix_truncxfsi2" [(parallel [(set (match_operand:SI 0 "general_operand" "") - (fix:SI - (fix:XF (match_operand:XF 1 "register_operand" "")))) - (clobber (match_dup 2)) - (clobber (match_dup 3)) - (clobber (match_scratch:SI 4 ""))])] + (fix:SI + (fix:XF (match_operand:XF 1 "register_operand" "")))) + (clobber (match_dup 2)) + (clobber (match_dup 3)) + (clobber (match_scratch:SI 4 ""))])] "TARGET_80387" " { @@ -2206,21 +1985,21 @@ (define_insn "" [(set (match_operand:SI 0 "general_operand" "=rm") - (fix:SI (fix:XF (match_operand:XF 1 "register_operand" "f")))) + (fix:SI (fix:XF (match_operand:XF 1 "register_operand" "f")))) (clobber (match_operand:SI 2 "memory_operand" "m")) (clobber (match_operand:SI 3 "memory_operand" "m")) (clobber (match_scratch:SI 4 "=&q"))] "TARGET_80387" - "* return output_fix_trunc (insn, operands);") + "* return (char *) output_fix_trunc (insn, operands);") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=rm") - (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f")))) + (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f")))) (clobber (match_operand:SI 2 "memory_operand" "m")) (clobber (match_operand:SI 3 "memory_operand" "m")) (clobber (match_scratch:SI 4 "=&q"))] "TARGET_80387" - "* return output_fix_trunc (insn, operands);") + "* return (char *) output_fix_trunc (insn, operands);") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=rm") @@ -2229,7 +2008,7 @@ (clobber (match_operand:SI 3 "memory_operand" "m")) (clobber (match_scratch:SI 4 "=&q"))] "TARGET_80387" - "* return output_fix_trunc (insn, operands);") + "* return (char *) output_fix_trunc (insn, operands);") ;; Conversion between fixed point and floating point. ;; The actual pattern that matches these is at the end of this file. @@ -2262,13 +2041,13 @@ (define_expand "floatsixf2" [(set (match_operand:XF 0 "register_operand" "") - (float:XF (match_operand:SI 1 "nonimmediate_operand" "")))] + (float:XF (match_operand:SI 1 "nonimmediate_operand" "")))] "TARGET_80387" "") (define_expand "floatdixf2" [(set (match_operand:XF 0 "register_operand" "") - (float:XF (match_operand:DI 1 "nonimmediate_operand" "")))] + (float:XF (match_operand:DI 1 "nonimmediate_operand" "")))] "TARGET_80387" "") @@ -2276,7 +2055,7 @@ (define_insn "" [(set (match_operand:XF 0 "register_operand" "=f") - (float:XF (match_operand:DI 1 "general_operand" "rm")))] + (float:XF (match_operand:DI 1 "general_operand" "rm")))] "TARGET_80387" "* { @@ -2344,7 +2123,7 @@ (define_insn "" [(set (match_operand:XF 0 "register_operand" "=f,f") - (float:XF (match_operand:SI 1 "general_operand" "m,!*r")))] + (float:XF (match_operand:SI 1 "general_operand" "m,!*r")))] "TARGET_80387" "* { @@ -2379,83 +2158,34 @@ ;;- add instructions (define_insn "adddi3" - [(set (match_operand:DI 0 "general_operand" "=&r,ro,o,&r,ro,o,&r,o,o,o") - (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,o,riF,o,or,riF,riF,o") - (match_operand:DI 2 "general_operand" "o,riF,o,0,0,0,oriF,riF,o,o"))) - (clobber (match_scratch:SI 3 "=X,X,&r,X,X,&r,X,X,&r,&r"))] + [(set (match_operand:DI 0 "general_operand" "=&r,ro") + (plus:DI (match_operand:DI 1 "general_operand" "%0,0") + (match_operand:DI 2 "general_operand" "o,riF")))] "" "* { - rtx low[3], high[3], xops[7], temp; + rtx low[3], high[3]; CC_STATUS_INIT; - if (rtx_equal_p (operands[0], operands[2])) - { - temp = operands[1]; - operands[1] = operands[2]; - operands[2] = temp; - } - split_di (operands, 3, low, high); - if (!rtx_equal_p (operands[0], operands[1])) - { - xops[0] = high[0]; - xops[1] = low[0]; - xops[2] = high[1]; - xops[3] = low[1]; - - if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) - { - output_asm_insn (AS2 (mov%L1,%3,%1), xops); - output_asm_insn (AS2 (mov%L0,%2,%0), xops); - } - else - { - xops[4] = high[2]; - xops[5] = low[2]; - xops[6] = operands[3]; - output_asm_insn (AS2 (mov%L6,%3,%6), xops); - output_asm_insn (AS2 (add%L6,%5,%6), xops); - output_asm_insn (AS2 (mov%L1,%6,%1), xops); - output_asm_insn (AS2 (mov%L6,%2,%6), xops); - output_asm_insn (AS2 (adc%L6,%4,%6), xops); - output_asm_insn (AS2 (mov%L0,%6,%0), xops); - RET; - } - } - if (GET_CODE (operands[3]) == REG && GET_CODE (operands[2]) != REG) - { - xops[0] = high[0]; - xops[1] = low[0]; - xops[2] = high[2]; - xops[3] = low[2]; - xops[4] = operands[3]; - - output_asm_insn (AS2 (mov%L4,%3,%4), xops); - output_asm_insn (AS2 (add%L1,%4,%1), xops); - output_asm_insn (AS2 (mov%L4,%2,%4), xops); - output_asm_insn (AS2 (adc%L0,%4,%0), xops); - } - - else if (GET_CODE (low[2]) != CONST_INT || INTVAL (low[2]) != 0) + if (GET_CODE (low[2]) != CONST_INT || INTVAL (low[2]) != 0) { output_asm_insn (AS2 (add%L0,%2,%0), low); output_asm_insn (AS2 (adc%L0,%2,%0), high); } - else output_asm_insn (AS2 (add%L0,%2,%0), high); - RET; }") ;; On a 486, it is faster to do movl/addl than to do a single leal if ;; operands[1] and operands[2] are both registers. +; intel1 removed ? from first constraint (define_insn "addsi3" - [(set (match_operand:SI 0 "general_operand" "=?r,rm,r") + [(set (match_operand:SI 0 "general_operand" "=r,rm,r") (plus:SI (match_operand:SI 1 "general_operand" "%r,0,0") (match_operand:SI 2 "general_operand" "ri,ri,rm")))] "" @@ -2466,20 +2196,23 @@ if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2])) return AS2 (add%L0,%1,%0); - if (operands[2] == stack_pointer_rtx) - { - rtx temp; + if (! (TARGET_486 || TARGET_PENTIUM) || ! REG_P (operands[2])) + { + CC_STATUS_INIT; - temp = operands[1]; - operands[1] = operands[2]; - operands[2] = temp; - } + if (operands[2] == stack_pointer_rtx) + { + rtx temp; - if (operands[2] != stack_pointer_rtx) - { - CC_STATUS_INIT; - operands[1] = SET_SRC (PATTERN (insn)); - return AS2 (lea%L0,%a1,%0); + temp = operands[1]; + operands[1] = operands[2]; + operands[2] = temp; + } + if (operands[2] != stack_pointer_rtx) + { + operands[1] = SET_SRC (PATTERN (insn)); + return AS2 (lea%L0,%a1,%0); + } } output_asm_insn (AS2 (mov%L0,%1,%0), operands); @@ -2510,24 +2243,23 @@ && GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) & 0xff) == 0) { - int byteval = (INTVAL (operands[2]) >> 8) & 0xff; CC_STATUS_INIT; - if (byteval == 1) - return AS1 (inc%B0,%h0); - else if (byteval == 255) - return AS1 (dec%B0,%h0); + operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff); + + if (operands[2] == const1_rtx) + return AS1 (inc%B0,%h0); + + if (operands[2] == constm1_rtx) + return AS1 (dec%B0,%h0); - operands[2] = GEN_INT (byteval); return AS2 (add%B0,%2,%h0); } if (operands[2] == const1_rtx) return AS1 (inc%W0,%0); - if (operands[2] == constm1_rtx - || (GET_CODE (operands[2]) == CONST_INT - && INTVAL (operands[2]) == 65535)) + if (operands[2] == constm1_rtx) return AS1 (dec%W0,%0); return AS2 (add%W0,%2,%0); @@ -2543,9 +2275,7 @@ if (operands[2] == const1_rtx) return AS1 (inc%B0,%0); - if (operands[2] == constm1_rtx - || (GET_CODE (operands[2]) == CONST_INT - && INTVAL (operands[2]) == 255)) + if (operands[2] == constm1_rtx) return AS1 (dec%B0,%0); return AS2 (add%B0,%2,%0); @@ -2578,7 +2308,7 @@ ;; addsi3 is faster, so put this after. -(define_insn "movsi_lea" +(define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (match_operand:QI 1 "address_operand" "p"))] "" @@ -2608,8 +2338,8 @@ (define_expand "addxf3" [(set (match_operand:XF 0 "register_operand" "") - (plus:XF (match_operand:XF 1 "nonimmediate_operand" "") - (match_operand:XF 2 "nonimmediate_operand" "")))] + (plus:XF (match_operand:XF 1 "nonimmediate_operand" "") + (match_operand:XF 2 "nonimmediate_operand" "")))] "TARGET_80387" "") @@ -2630,66 +2360,23 @@ ;;- subtract instructions (define_insn "subdi3" - [(set (match_operand:DI 0 "general_operand" "=&r,ro,&r,o,o") - (minus:DI (match_operand:DI 1 "general_operand" "0,0,roiF,riF,o") - (match_operand:DI 2 "general_operand" "o,riF,roiF,riF,o"))) - (clobber (match_scratch:SI 3 "=X,X,X,X,&r"))] + [(set (match_operand:DI 0 "general_operand" "=&r,ro") + (minus:DI (match_operand:DI 1 "general_operand" "0,0") + (match_operand:DI 2 "general_operand" "o,riF")))] "" "* { - rtx low[3], high[3], xops[7]; + rtx low[3], high[3]; CC_STATUS_INIT; split_di (operands, 3, low, high); - if (!rtx_equal_p (operands[0], operands[1])) - { - xops[0] = high[0]; - xops[1] = low[0]; - xops[2] = high[1]; - xops[3] = low[1]; - - if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) - { - output_asm_insn (AS2 (mov%L1,%3,%1), xops); - output_asm_insn (AS2 (mov%L0,%2,%0), xops); - } - else - { - xops[4] = high[2]; - xops[5] = low[2]; - xops[6] = operands[3]; - output_asm_insn (AS2 (mov%L6,%3,%6), xops); - output_asm_insn (AS2 (sub%L6,%5,%6), xops); - output_asm_insn (AS2 (mov%L1,%6,%1), xops); - output_asm_insn (AS2 (mov%L6,%2,%6), xops); - output_asm_insn (AS2 (sbb%L6,%4,%6), xops); - output_asm_insn (AS2 (mov%L0,%6,%0), xops); - RET; - } - } - - if (GET_CODE (operands[3]) == REG) - { - xops[0] = high[0]; - xops[1] = low[0]; - xops[2] = high[2]; - xops[3] = low[2]; - xops[4] = operands[3]; - - output_asm_insn (AS2 (mov%L4,%3,%4), xops); - output_asm_insn (AS2 (sub%L1,%4,%1), xops); - output_asm_insn (AS2 (mov%L4,%2,%4), xops); - output_asm_insn (AS2 (sbb%L0,%4,%0), xops); - } - - else if (GET_CODE (low[2]) != CONST_INT || INTVAL (low[2]) != 0) + if (GET_CODE (low[2]) != CONST_INT || INTVAL (low[2]) != 0) { output_asm_insn (AS2 (sub%L0,%2,%0), low); output_asm_insn (AS2 (sbb%L0,%2,%0), high); } - else output_asm_insn (AS2 (sub%L0,%2,%0), high); @@ -2721,8 +2408,8 @@ (define_expand "subxf3" [(set (match_operand:XF 0 "register_operand" "") - (minus:XF (match_operand:XF 1 "nonimmediate_operand" "") - (match_operand:XF 2 "nonimmediate_operand" "")))] + (minus:XF (match_operand:XF 1 "nonimmediate_operand" "") + (match_operand:XF 2 "nonimmediate_operand" "")))] "TARGET_80387" "") @@ -2751,14 +2438,14 @@ (define_insn "" [(set (match_operand:HI 0 "general_operand" "=r") - (mult:HI (match_operand:HI 1 "general_operand" "%0") + (mult:SI (match_operand:HI 1 "general_operand" "%0") (match_operand:HI 2 "general_operand" "r")))] "GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x80" "* return AS2 (imul%W0,%2,%0);") (define_insn "mulhi3" [(set (match_operand:HI 0 "general_operand" "=r,r") - (mult:HI (match_operand:HI 1 "general_operand" "%0,rm") + (mult:SI (match_operand:HI 1 "general_operand" "%0,rm") (match_operand:HI 2 "general_operand" "g,i")))] "" "* @@ -2793,58 +2480,21 @@ return AS3 (imul%L0,%2,%1,%0); }") -(define_insn "umulqihi3" +(define_insn "" [(set (match_operand:HI 0 "general_operand" "=a") - (mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0")) - (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))] + (mult:SI (zero_extend:HI + (match_operand:QI 1 "nonimmediate_operand" "%0")) + (zero_extend:HI + (match_operand:QI 2 "nonimmediate_operand" "qm"))))] "" "mul%B0 %2") -(define_insn "mulqihi3" - [(set (match_operand:HI 0 "general_operand" "=a") - (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0")) - (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))] - "" - "imul%B0 %2") - -(define_insn "umulsidi3" - [(set (match_operand:DI 0 "register_operand" "=A") - (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0")) - (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))] - "TARGET_WIDE_MULTIPLY" - "mul%L0 %2") - -(define_insn "mulsidi3" - [(set (match_operand:DI 0 "register_operand" "=A") - (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%0")) - (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))] - "TARGET_WIDE_MULTIPLY" - "imul%L0 %2") - -(define_insn "umulsi3_highpart" - [(set (match_operand:SI 0 "register_operand" "=d") - (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%a")) - (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))) - (const_int 32)))) - (clobber (match_scratch:SI 3 "=a"))] - "TARGET_WIDE_MULTIPLY" - "mul%L0 %2") - -(define_insn "smulsi3_highpart" - [(set (match_operand:SI 0 "register_operand" "=d") - (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%a")) - (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))) - (const_int 32)))) - (clobber (match_scratch:SI 3 "=a"))] - "TARGET_WIDE_MULTIPLY" - "imul%L0 %2") - ;; The patterns that match these are at the end of this file. (define_expand "mulxf3" [(set (match_operand:XF 0 "register_operand" "") - (mult:XF (match_operand:XF 1 "nonimmediate_operand" "") - (match_operand:XF 2 "nonimmediate_operand" "")))] + (mult:XF (match_operand:XF 1 "nonimmediate_operand" "") + (match_operand:XF 2 "nonimmediate_operand" "")))] "TARGET_80387" "") @@ -2882,8 +2532,8 @@ (define_expand "divxf3" [(set (match_operand:XF 0 "register_operand" "") - (div:XF (match_operand:XF 1 "nonimmediate_operand" "") - (match_operand:XF 2 "nonimmediate_operand" "")))] + (div:XF (match_operand:XF 1 "nonimmediate_operand" "") + (match_operand:XF 2 "nonimmediate_operand" "")))] "TARGET_80387" "") @@ -2988,20 +2638,37 @@ ;; optional reloads to be generated if op 3 is a pseudo in a stack slot. ;; ??? What if we only change one byte of an offsettable memory reference? +;;(define_insn "andsi3" +;; [(set (match_operand:SI 0 "general_operand" "=r,r,rm,r") +;; (and:SI (match_operand:SI 1 "general_operand" "%rm,qm,0,0") +;; (match_operand:SI 2 "general_operand" "L,K,ri,rm")))] +;; "" +;; "* +;;{ +;intel1 (define_insn "andsi3" - [(set (match_operand:SI 0 "general_operand" "=r,r,rm,r") - (and:SI (match_operand:SI 1 "general_operand" "%rm,qm,0,0") - (match_operand:SI 2 "general_operand" "L,K,ri,rm")))] + [(set (match_operand:SI 0 "general_operand" "=rm,r,r") + (and:SI (match_operand:SI 1 "general_operand" "0,0,rm") + (match_operand:SI 2 "general_operand" "ri,rm,0")))] "" "* { + /* intel1 */ + if (!rtx_equal_p (operands[0], operands[1]) + && rtx_equal_p (operands[0], operands[2])) + { + rtx tmp; + tmp = operands[1]; + operands[1] = operands[2]; + operands[2] = tmp; + } if (GET_CODE (operands[2]) == CONST_INT && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) { if (INTVAL (operands[2]) == 0xffff && REG_P (operands[0]) && (! REG_P (operands[1]) || REGNO (operands[0]) != 0 || REGNO (operands[1]) != 0) - && (TARGET_386 || ! rtx_equal_p (operands[0], operands[1]))) + && (! (TARGET_486 || TARGET_PENTIUM) || ! rtx_equal_p (operands[0], operands[1]))) { /* ??? tege: Should forget CC_STATUS only if we clobber a remembered operand. Fix that later. */ @@ -3017,7 +2684,7 @@ && !(REG_P (operands[1]) && NON_QI_REG_P (operands[1])) && (! REG_P (operands[1]) || REGNO (operands[0]) != 0 || REGNO (operands[1]) != 0) - && (TARGET_386 || ! rtx_equal_p (operands[0], operands[1]))) + && (! (TARGET_486 || TARGET_PENTIUM) || ! rtx_equal_p (operands[0], operands[1]))) { /* ??? tege: Should forget CC_STATUS only if we clobber a remembered operand. Fix that later. */ @@ -3146,14 +2813,23 @@ ;;- Bit set (inclusive or) instructions +;intel1 added last constaints ;; ??? What if we only change one byte of an offsettable memory reference? (define_insn "iorsi3" - [(set (match_operand:SI 0 "general_operand" "=rm,r") - (ior:SI (match_operand:SI 1 "general_operand" "%0,0") - (match_operand:SI 2 "general_operand" "ri,rm")))] + [(set (match_operand:SI 0 "general_operand" "=rm,r,r") + (ior:SI (match_operand:SI 1 "general_operand" "%0,0,rm") + (match_operand:SI 2 "general_operand" "ri,rm,0")))] "" "* { + /* intel1 */ + if (!rtx_equal_p (operands[0], operands[1])) + { + rtx tmp; + tmp = operands[1]; + operands[1] = operands[2]; + operands[2] = tmp; + } if (GET_CODE (operands[2]) == CONST_INT && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) { @@ -3183,13 +2859,22 @@ return AS2 (or%L0,%2,%0); }") +;intel1 added last constraint (define_insn "iorhi3" - [(set (match_operand:HI 0 "general_operand" "=rm,r") - (ior:HI (match_operand:HI 1 "general_operand" "%0,0") - (match_operand:HI 2 "general_operand" "ri,rm")))] + [(set (match_operand:HI 0 "general_operand" "=rm,r,r") + (ior:HI (match_operand:HI 1 "general_operand" "%0,0,rm") + (match_operand:HI 2 "general_operand" "ri,rm,0")))] "" "* { + /* intel1 */ + if (!rtx_equal_p (operands[0], operands[1])) + { + rtx tmp; + tmp = operands[1]; + operands[1] = operands[2]; + operands[2] = tmp; + } if (GET_CODE (operands[2]) == CONST_INT && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) { @@ -3225,12 +2910,24 @@ return AS2 (or%W0,%2,%0); }") +;intel1 added last constraint (define_insn "iorqi3" - [(set (match_operand:QI 0 "general_operand" "=qm,q") - (ior:QI (match_operand:QI 1 "general_operand" "%0,0") - (match_operand:QI 2 "general_operand" "qn,qmn")))] + [(set (match_operand:QI 0 "general_operand" "=qm,q,q") + (ior:QI (match_operand:QI 1 "general_operand" "%0,0,qm") + (match_operand:QI 2 "general_operand" "qn,qmn,0")))] "" - "* return AS2 (or%B0,%2,%0);") + "* +{ + /* intel1 */ + if (!rtx_equal_p (operands[0], operands[1])) + { + rtx tmp; + tmp = operands[1]; + operands[1] = operands[2]; + operands[2] = tmp; + } + return AS2 (or%B0,%2,%0); +}") ;;- xor instructions @@ -3271,13 +2968,22 @@ return AS2 (xor%L0,%2,%0); }") +;intel1 added last constraint (define_insn "xorhi3" - [(set (match_operand:HI 0 "general_operand" "=rm,r") - (xor:HI (match_operand:HI 1 "general_operand" "%0,0") - (match_operand:HI 2 "general_operand" "ri,rm")))] + [(set (match_operand:HI 0 "general_operand" "=rm,r,r") + (xor:HI (match_operand:HI 1 "general_operand" "%0,0,rm") + (match_operand:HI 2 "general_operand" "ri,rm,0")))] "" "* { + /* intel1 */ + if (!rtx_equal_p (operands[0], operands[1])) + { + rtx tmp; + tmp = operands[1]; + operands[1] = operands[2]; + operands[2] = tmp; + } if (GET_CODE (operands[2]) == CONST_INT && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) { @@ -3313,12 +3019,24 @@ return AS2 (xor%W0,%2,%0); }") +;intel1 added last constraint (define_insn "xorqi3" - [(set (match_operand:QI 0 "general_operand" "=qm,q") - (xor:QI (match_operand:QI 1 "general_operand" "%0,0") - (match_operand:QI 2 "general_operand" "qn,qm")))] - "" - "* return AS2 (xor%B0,%2,%0);") + [(set (match_operand:QI 0 "general_operand" "=qm,q,q") + (xor:QI (match_operand:QI 1 "general_operand" "%0,0,qm") + (match_operand:QI 2 "general_operand" "qn,qm,0")))] + "" + "* + { + /* intel1 */ + if (!rtx_equal_p (operands[0], operands[1])) + { + rtx tmp; + tmp = operands[1]; + operands[1] = operands[2]; + operands[2] = tmp; + } + return AS2 (xor%B0,%2,%0); + }") ;;- negation instructions @@ -3380,13 +3098,13 @@ (define_insn "negxf2" [(set (match_operand:XF 0 "register_operand" "=f") - (neg:XF (match_operand:XF 1 "general_operand" "0")))] + (neg:XF (match_operand:XF 1 "general_operand" "0")))] "TARGET_80387" "fchs") (define_insn "" [(set (match_operand:XF 0 "register_operand" "=f") - (neg:XF (float_extend:XF (match_operand:DF 1 "general_operand" "0"))))] + (neg:XF (float_extend:XF (match_operand:DF 1 "general_operand" "0"))))] "TARGET_80387" "fchs") @@ -3396,120 +3114,108 @@ [(set (match_operand:SF 0 "register_operand" "=f") (abs:SF (match_operand:SF 1 "general_operand" "0")))] "TARGET_80387" - "fabs") + "fabs"[(set_attr "type" "fpop")]) (define_insn "absdf2" [(set (match_operand:DF 0 "register_operand" "=f") (abs:DF (match_operand:DF 1 "general_operand" "0")))] "TARGET_80387" - "fabs") + "fabs"[(set_attr "type" "fpop")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f") (abs:DF (float_extend:DF (match_operand:SF 1 "general_operand" "0"))))] "TARGET_80387" - "fabs") + "fabs"[(set_attr "type" "fpop")]) (define_insn "absxf2" [(set (match_operand:XF 0 "register_operand" "=f") - (abs:XF (match_operand:XF 1 "general_operand" "0")))] + (abs:XF (match_operand:XF 1 "general_operand" "0")))] "TARGET_80387" - "fabs") + "fabs"[(set_attr "type" "fpop")]) (define_insn "" [(set (match_operand:XF 0 "register_operand" "=f") - (abs:XF (float_extend:XF (match_operand:DF 1 "general_operand" "0"))))] + (abs:XF (float_extend:XF (match_operand:DF 1 "general_operand" "0"))))] "TARGET_80387" - "fabs") + "fabs"[(set_attr "type" "fpop")]) (define_insn "sqrtsf2" [(set (match_operand:SF 0 "register_operand" "=f") (sqrt:SF (match_operand:SF 1 "general_operand" "0")))] - "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 - && (TARGET_IEEE_FP || flag_fast_math) " - "fsqrt") + "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)" + "fsqrt"[(set_attr "type" "fpop")]) (define_insn "sqrtdf2" [(set (match_operand:DF 0 "register_operand" "=f") (sqrt:DF (match_operand:DF 1 "general_operand" "0")))] - "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 - && (TARGET_IEEE_FP || flag_fast_math) " - "fsqrt") + "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)" + "fsqrt"[(set_attr "type" "fpop")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f") (sqrt:DF (float_extend:DF (match_operand:SF 1 "general_operand" "0"))))] - "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 - && (TARGET_IEEE_FP || flag_fast_math) " - "fsqrt") + "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)" + "fsqrt"[(set_attr "type" "fpop")]) (define_insn "sqrtxf2" [(set (match_operand:XF 0 "register_operand" "=f") - (sqrt:XF (match_operand:XF 1 "general_operand" "0")))] - "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 - && (TARGET_IEEE_FP || flag_fast_math) " - "fsqrt") + (sqrt:XF (match_operand:XF 1 "general_operand" "0")))] + "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)" + "fsqrt"[(set_attr "type" "fpop")]) (define_insn "" [(set (match_operand:XF 0 "register_operand" "=f") - (sqrt:XF (float_extend:XF - (match_operand:DF 1 "general_operand" "0"))))] - "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 - && (TARGET_IEEE_FP || flag_fast_math) " - "fsqrt") + (sqrt:XF (float_extend:XF + (match_operand:DF 1 "general_operand" "0"))))] + "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)" + "fsqrt"[(set_attr "type" "fpop")]) (define_insn "" [(set (match_operand:XF 0 "register_operand" "=f") - (sqrt:XF (float_extend:XF - (match_operand:SF 1 "general_operand" "0"))))] - "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 - && (TARGET_IEEE_FP || flag_fast_math) " - "fsqrt") + (sqrt:XF (float_extend:XF + (match_operand:SF 1 "general_operand" "0"))))] + "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)" + "fsqrt"[(set_attr "type" "fpop")]) (define_insn "sindf2" [(set (match_operand:DF 0 "register_operand" "=f") (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 1))] - "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 - && (TARGET_IEEE_FP || flag_fast_math) " - "fsin") + "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)" + "fsin"[(set_attr "type" "fpop")]) (define_insn "sinsf2" [(set (match_operand:SF 0 "register_operand" "=f") (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 1))] - "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 - && (TARGET_IEEE_FP || flag_fast_math) " - "fsin") + "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)" + "fsin"[(set_attr "type" "fpop")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f") (unspec:DF [(float_extend:DF (match_operand:SF 1 "register_operand" "0"))] 1))] - "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 - && (TARGET_IEEE_FP || flag_fast_math) " - "fsin") + "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)" + "fsin"[(set_attr "type" "fpop")]) (define_insn "cosdf2" [(set (match_operand:DF 0 "register_operand" "=f") (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 2))] - "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 - && (TARGET_IEEE_FP || flag_fast_math) " - "fcos") + "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)" + "fcos"[(set_attr "type" "fpop")]) (define_insn "cossf2" [(set (match_operand:SF 0 "register_operand" "=f") (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 2))] - "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 - && (TARGET_IEEE_FP || flag_fast_math) " - "fcos") + "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)" + "fcos"[(set_attr "type" "fpop")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f") (unspec:DF [(float_extend:DF (match_operand:SF 1 "register_operand" "0"))] 2))] - "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 - && (TARGET_IEEE_FP || flag_fast_math) " - "fcos") + "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)" + "fcos"[(set_attr "type" "fpop")]) ;;- one complement instructions @@ -3660,7 +3366,7 @@ { if (REG_P (operands[0]) && REGNO (operands[0]) != REGNO (operands[1])) { - if (!TARGET_386 && INTVAL (operands[2]) == 1) + if ((TARGET_486 || TARGET_PENTIUM) && INTVAL (operands[2]) == 1) { output_asm_insn (AS2 (mov%L0,%1,%0), operands); return AS2 (add%L0,%1,%0); @@ -4161,7 +3867,7 @@ (const_int 1) (match_operand:SI 2 "general_operand" "r")) (match_operand:SI 3 "const_int_operand" "n"))] - "TARGET_386 && GET_CODE (operands[2]) != CONST_INT" + "! (TARGET_486 || TARGET_PENTIUM) && GET_CODE (operands[2]) != CONST_INT" "* { CC_STATUS_INIT; @@ -4179,7 +3885,7 @@ (xor:SI (ashift:SI (const_int 1) (match_operand:SI 1 "general_operand" "r")) (match_operand:SI 2 "general_operand" "0")))] - "TARGET_386 && GET_CODE (operands[1]) != CONST_INT" + "! (TARGET_486 || TARGET_PENTIUM) && GET_CODE (operands[1]) != CONST_INT" "* { CC_STATUS_INIT; @@ -4192,7 +3898,7 @@ (xor:SI (match_operand:SI 1 "general_operand" "0") (ashift:SI (const_int 1) (match_operand:SI 2 "general_operand" "r"))))] - "TARGET_386 && GET_CODE (operands[2]) != CONST_INT" + "! (TARGET_486 || TARGET_PENTIUM) && GET_CODE (operands[2]) != CONST_INT" "* { CC_STATUS_INIT; @@ -4537,6 +4243,15 @@ if (cc_prev_status.flags & CC_Z_IN_NOT_C) return \"jnc %l0\"; else + /* intel1 */ + if (cc_prev_status.flags & CC_TEST_AX) + { + operands[1] = gen_rtx (REG, SImode, 0); + operands[2] = GEN_INT (0x4000); + output_asm_insn (AS2 (testl,%2,%1), operands); + return AS1 (jne,%l0); + } + return \"je %l0\"; }") @@ -4569,6 +4284,15 @@ if (cc_prev_status.flags & CC_Z_IN_NOT_C) return \"jc %l0\"; else + /* intel1 */ + if (cc_prev_status.flags & CC_TEST_AX) + { + operands[1] = gen_rtx (REG, SImode, 0); + operands[2] = GEN_INT (0x4000); + output_asm_insn (AS2 (testl,%2,%1), operands); + return AS1 (je,%l0); + } + return \"jne %l0\"; }") @@ -4594,6 +4318,13 @@ if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) return AS1 (je,%l0); + if (cc_prev_status.flags & CC_TEST_AX) + { + operands[1] = gen_rtx (REG, SImode, 0); + operands[2] = GEN_INT (0x4100); + output_asm_insn (AS2 (testl,%2,%1), operands); + return AS1 (je,%l0); + } OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", NULL_PTR); }") @@ -4638,6 +4369,14 @@ if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) return AS1 (je,%l0); + /* intel1 */ + if (cc_prev_status.flags & CC_TEST_AX) + { + operands[1] = gen_rtx (REG, SImode, 0); + operands[2] = GEN_INT (0x100); + output_asm_insn (AS2 (testl,%2,%1), operands); + return AS1 (jne,%l0); + } OUTPUT_JUMP (\"jl %l0\", \"jb %l0\", \"js %l0\"); }") @@ -4681,7 +4420,14 @@ { if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) return AS1 (je,%l0); - + /* intel1 */ + if (cc_prev_status.flags & CC_TEST_AX) + { + operands[1] = gen_rtx (REG, SImode, 0); + operands[2] = GEN_INT (0x100); + output_asm_insn (AS2 (testl,%2,%1), operands); + return AS1 (je,%l0); + } OUTPUT_JUMP (\"jge %l0\", \"jae %l0\", \"jns %l0\"); }") @@ -4725,6 +4471,14 @@ { if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) return AS1 (jb,%l0); + /* intel1 */ + if (cc_prev_status.flags & CC_TEST_AX) + { + operands[1] = gen_rtx (REG, SImode, 0); + operands[2] = GEN_INT (0x4100); + output_asm_insn (AS2 (testl,%2,%1), operands); + return AS1 (jne,%l0); + } OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", NULL_PTR); }") @@ -4762,6 +4516,14 @@ if (cc_prev_status.flags & CC_Z_IN_NOT_C) return \"jc %l0\"; else + /* intel1 */ + if (cc_prev_status.flags & CC_TEST_AX) + { + operands[1] = gen_rtx (REG, SImode, 0); + operands[2] = GEN_INT (0x4000); + output_asm_insn (AS2 (testl,%2,%1), operands); + return AS1 (je,%l0); + } return \"jne %l0\"; }") @@ -4777,6 +4539,14 @@ if (cc_prev_status.flags & CC_Z_IN_NOT_C) return \"jnc %l0\"; else + /* intel1 */ + if (cc_prev_status.flags & CC_TEST_AX) + { + operands[1] = gen_rtx (REG, SImode, 0); + operands[2] = GEN_INT (0x4000); + output_asm_insn (AS2 (testl,%2,%1), operands); + return AS1 (jne,%l0); + } return \"je %l0\"; }") @@ -4791,7 +4561,14 @@ { if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) return AS1 (jne,%l0); - + /* intel1 */ + if (cc_prev_status.flags & CC_TEST_AX) + { + operands[1] = gen_rtx (REG, SImode, 0); + operands[2] = GEN_INT (0x4100); + output_asm_insn (AS2 (testl,%2,%1), operands); + return AS1 (jne,%l0); + } OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", NULL_PTR); }") @@ -4815,6 +4592,14 @@ { if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) return AS1 (jne,%l0); + /* intel1 */ + if (cc_prev_status.flags & CC_TEST_AX) + { + operands[1] = gen_rtx (REG, SImode, 0); + operands[2] = GEN_INT (0x100); + output_asm_insn (AS2 (testl,%2,%1), operands); + return AS1 (je,%l0); + } OUTPUT_JUMP (\"jge %l0\", \"jae %l0\", \"jns %l0\"); }") @@ -4839,7 +4624,14 @@ { if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) return AS1 (jne,%l0); - + /* intel1 */ + if (cc_prev_status.flags & CC_TEST_AX) + { + operands[1] = gen_rtx (REG, SImode, 0); + operands[2] = GEN_INT (0x100); + output_asm_insn (AS2 (testl,%2,%1), operands); + return AS1 (jne,%l0); + } OUTPUT_JUMP (\"jl %l0\", \"jb %l0\", \"js %l0\"); }") @@ -4864,6 +4656,14 @@ if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) return AS1 (jae,%l0); + /* intel1 */ + if (cc_prev_status.flags & CC_TEST_AX) + { + operands[1] = gen_rtx (REG, SImode, 0); + operands[2] = GEN_INT (0x4100); + output_asm_insn (AS2 (testl,%2,%1), operands); + return AS1 (je,%l0); + } OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", NULL_PTR); }") @@ -5210,42 +5010,126 @@ "!HALF_PIC_P ()" "call %P1") -;; Call subroutine returning any type. - (define_expand "untyped_call" - [(parallel [(call (match_operand 0 "" "") + [(parallel [(call (match_operand:QI 0 "indirect_operand" "") (const_int 0)) - (match_operand 1 "" "") + (match_operand:BLK 1 "memory_operand" "") (match_operand 2 "" "")])] "" " { - int i; + rtx addr; + + if (flag_pic) + current_function_uses_pic_offset_table = 1; + + /* With half-pic, force the address into a register. */ + addr = XEXP (operands[0], 0); + if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr)) + XEXP (operands[0], 0) = force_reg (Pmode, addr); - emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); + operands[1] = change_address (operands[1], DImode, XEXP (operands[1], 0)); + if (! expander_call_insn_operand (operands[1], QImode)) + operands[1] + = change_address (operands[1], VOIDmode, + copy_to_mode_reg (Pmode, XEXP (operands[1], 0))); +}") + +(define_insn "" + [(call (match_operand:QI 0 "call_insn_operand" "m") + (const_int 0)) + (match_operand:DI 1 "memory_operand" "o") + (match_operand 2 "" "")] + "" + "* +{ + rtx addr = operands[1]; - for (i = 0; i < XVECLEN (operands[2], 0); i++) + if (GET_CODE (operands[0]) == MEM + && ! CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) { - rtx set = XVECEXP (operands[2], 0, i); - emit_move_insn (SET_DEST (set), SET_SRC (set)); + operands[0] = XEXP (operands[0], 0); + output_asm_insn (AS1 (call,%*%0), operands); } + else + output_asm_insn (AS1 (call,%P0), operands); - /* The optimizer does not know that the call sets the function value - registers we stored in the result block. We avoid problems by - claiming that all hard registers are used and clobbered at this - point. */ - emit_insn (gen_blockage ()); + operands[2] = gen_rtx (REG, SImode, 0); + output_asm_insn (AS2 (mov%L2,%2,%1), operands); - DONE; + operands[2] = gen_rtx (REG, SImode, 1); + operands[1] = adj_offsettable_operand (addr, 4); + output_asm_insn (AS2 (mov%L2,%2,%1), operands); + + operands[1] = adj_offsettable_operand (addr, 8); + return AS1 (fnsave,%1); }") -;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and -;; all of memory. This blocks insns from being moved across this point. +(define_insn "" + [(call (mem:QI (match_operand:SI 0 "symbolic_operand" "")) + (const_int 0)) + (match_operand:DI 1 "memory_operand" "o") + (match_operand 2 "" "")] + "!HALF_PIC_P ()" + "* +{ + rtx addr = operands[1]; + + output_asm_insn (AS1 (call,%P0), operands); -(define_insn "blockage" - [(unspec_volatile [(const_int 0)] 0)] + operands[2] = gen_rtx (REG, SImode, 0); + output_asm_insn (AS2 (mov%L2,%2,%1), operands); + + operands[2] = gen_rtx (REG, SImode, 1); + operands[1] = adj_offsettable_operand (addr, 4); + output_asm_insn (AS2 (mov%L2,%2,%1), operands); + + operands[1] = adj_offsettable_operand (addr, 8); + return AS1 (fnsave,%1); +}") + +;; We use fnsave and frstor to save and restore the floating point result. +;; These are expensive instructions and require a large space to save the +;; FPU state. An more complicated alternative is to use fnstenv to store +;; the FPU environment and test whether the stack top is valid. Store the +;; result of the test, and if it is valid, pop and save the value. The +;; untyped_return would check the test and optionally push the saved value. + +(define_expand "untyped_return" + [(match_operand:BLK 0 "memory_operand" "") + (match_operand 1 "" "")] "" - "") + " +{ + rtx valreg1 = gen_rtx (REG, SImode, 0); + rtx valreg2 = gen_rtx (REG, SImode, 1); + rtx result = operands[0]; + + /* Restore the FPU state. */ + emit_insn (gen_update_return (change_address (result, SImode, + plus_constant (XEXP (result, 0), + 8)))); + + /* Reload the function value registers. */ + emit_move_insn (valreg1, change_address (result, SImode, XEXP (result, 0))); + emit_move_insn (valreg2, + change_address (result, SImode, + plus_constant (XEXP (result, 0), 4))); + + /* Put USE insns before the return. */ + emit_insn (gen_rtx (USE, VOIDmode, valreg1)); + emit_insn (gen_rtx (USE, VOIDmode, valreg2)); + + /* Construct the return. */ + expand_null_return (); + + DONE; +}") + +(define_insn "update_return" + [(unspec:SI [(match_operand:SI 0 "memory_operand" "m")] 0)] + "" + "frstor %0") ;; Insn emitted into the body of a function to return from a function. ;; This is only done if the function's epilogue is known to be simple. @@ -5294,7 +5178,7 @@ ;; It might seem that operands 0 & 1 could use predicate register_operand. ;; But strength reduction might offset the MEM expression. So we let ;; reload put the address into %edi & %esi. - +;; intel1 "e" used to be "S" (define_insn "" [(set (mem:BLK (match_operand:SI 0 "address_operand" "D")) (mem:BLK (match_operand:SI 1 "address_operand" "S"))) @@ -5370,6 +5254,7 @@ ;; possible to know that the length is non-zero, and to avoid the extra ;; code to handle zero-length compares. +;; intel1 "e" used to be "S" (define_insn "" [(set (match_operand:SI 0 "general_operand" "=&r") (compare:SI (mem:BLK (match_operand:SI 1 "address_operand" "S")) @@ -5406,6 +5291,7 @@ RET; }") +;; intel1 "e" used to be "S" (define_insn "" [(set (cc0) (compare:SI (mem:BLK (match_operand:SI 0 "address_operand" "S")) @@ -5457,19 +5343,19 @@ output_asm_insn (AS2 (bsf%L0,%1,%0), xops); #ifdef LOCAL_LABEL_PREFIX sprintf (buffer, \"jnz %sLFFSSI%d\", - LOCAL_LABEL_PREFIX, ffssi_label_number); + LOCAL_LABEL_PREFIX, ffssi_label_number); #else sprintf (buffer, \"jnz %sLFFSSI%d\", - \"\", ffssi_label_number); + \"\", ffssi_label_number); #endif output_asm_insn (buffer, xops); output_asm_insn (AS2 (mov%L0,%2,%0), xops); #ifdef LOCAL_LABEL_PREFIX sprintf (buffer, \"%sLFFSSI%d:\", - LOCAL_LABEL_PREFIX, ffssi_label_number); + LOCAL_LABEL_PREFIX, ffssi_label_number); #else sprintf (buffer, \"%sLFFSSI%d:\", - \"\", ffssi_label_number); + \"\", ffssi_label_number); #endif output_asm_insn (buffer, xops); @@ -5503,19 +5389,19 @@ output_asm_insn (AS2 (bsf%W0,%1,%0), xops); #ifdef LOCAL_LABEL_PREFIX sprintf (buffer, \"jnz %sLFFSHI%d\", - LOCAL_LABEL_PREFIX, ffshi_label_number); + LOCAL_LABEL_PREFIX, ffshi_label_number); #else sprintf (buffer, \"jnz %sLFFSHI%d\", - \"\", ffshi_label_number); + \"\", ffshi_label_number); #endif output_asm_insn (buffer, xops); output_asm_insn (AS2 (mov%W0,%2,%0), xops); #ifdef LOCAL_LABEL_PREFIX sprintf (buffer, \"%sLFFSHI%d:\", - LOCAL_LABEL_PREFIX, ffshi_label_number); + LOCAL_LABEL_PREFIX, ffshi_label_number); #else sprintf (buffer, \"%sLFFSHI%d:\", - \"\", ffshi_label_number); + \"\", ffshi_label_number); #endif output_asm_insn (buffer, xops); @@ -5530,14 +5416,23 @@ ;; the other operand a conversion. The conversion may be SFmode or ;; SImode if the target mode DFmode, but only SImode if the target mode ;; is SFmode. - +;; intel1 2 changed from nonimmediate operand to general operand (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f,f") (match_operator:DF 3 "binary_387_op" [(match_operand:DF 1 "nonimmediate_operand" "0,fm") - (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))] + (match_operand:DF 2 "general_operand" "fm,0")]))] "TARGET_80387" - "* return output_387_binary_op (insn, operands);") + "* return (char *) output_387_binary_op (insn, operands);" + [(set (attr "type") + (cond [(match_operand:DF 3 "is_mul" "") + (const_string "fpop") + (match_operand:DF 3 "is_div" "") + (const_string "fpdiv") + ] + (const_string "fpop") + ) + )]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f") @@ -5545,7 +5440,7 @@ [(float:DF (match_operand:SI 1 "general_operand" "rm")) (match_operand:DF 2 "general_operand" "0")]))] "TARGET_80387" - "* return output_387_binary_op (insn, operands);") + "* return (char *) output_387_binary_op (insn, operands);") (define_insn "" [(set (match_operand:XF 0 "register_operand" "=f,f") @@ -5553,7 +5448,7 @@ [(match_operand:XF 1 "nonimmediate_operand" "0,f") (match_operand:XF 2 "nonimmediate_operand" "f,0")]))] "TARGET_80387" - "* return output_387_binary_op (insn, operands);") + "* return (char *) output_387_binary_op (insn, operands);") (define_insn "" [(set (match_operand:XF 0 "register_operand" "=f") @@ -5561,7 +5456,7 @@ [(float:XF (match_operand:SI 1 "general_operand" "rm")) (match_operand:XF 2 "general_operand" "0")]))] "TARGET_80387" - "* return output_387_binary_op (insn, operands);") + "* return (char *) output_387_binary_op (insn, operands);") (define_insn "" [(set (match_operand:XF 0 "register_operand" "=f,f") @@ -5569,7 +5464,7 @@ [(float_extend:XF (match_operand:SF 1 "general_operand" "fm,0")) (match_operand:XF 2 "general_operand" "0,f")]))] "TARGET_80387" - "* return output_387_binary_op (insn, operands);") + "* return (char *) output_387_binary_op (insn, operands);") (define_insn "" [(set (match_operand:XF 0 "register_operand" "=f") @@ -5577,7 +5472,7 @@ [(match_operand:XF 1 "general_operand" "0") (float:XF (match_operand:SI 2 "general_operand" "rm"))]))] "TARGET_80387" - "* return output_387_binary_op (insn, operands);") + "* return (char *) output_387_binary_op (insn, operands);") (define_insn "" [(set (match_operand:XF 0 "register_operand" "=f,f") @@ -5585,8 +5480,18 @@ [(match_operand:XF 1 "general_operand" "0,f") (float_extend:XF (match_operand:SF 2 "general_operand" "fm,0"))]))] + "TARGET_80387" - "* return output_387_binary_op (insn, operands);") + "* return (char *) output_387_binary_op (insn, operands);" + [(set (attr "type") + (cond [(match_operand:DF 3 "is_mul" "") + (const_string "fpop") + (match_operand:DF 3 "is_div" "") + (const_string "fpdiv") + ] + (const_string "fpop") + ) + )]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f,f") @@ -5594,7 +5499,16 @@ [(float_extend:DF (match_operand:SF 1 "general_operand" "fm,0")) (match_operand:DF 2 "general_operand" "0,f")]))] "TARGET_80387" - "* return output_387_binary_op (insn, operands);") + "* return (char *) output_387_binary_op (insn, operands);" + [(set (attr "type") + (cond [(match_operand:DF 3 "is_mul" "") + (const_string "fpop") + (match_operand:DF 3 "is_div" "") + (const_string "fpdiv") + ] + (const_string "fpop") + ) + )]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f") @@ -5602,7 +5516,16 @@ [(match_operand:DF 1 "general_operand" "0") (float:DF (match_operand:SI 2 "general_operand" "rm"))]))] "TARGET_80387" - "* return output_387_binary_op (insn, operands);") + "* return (char *) output_387_binary_op (insn, operands);" + [(set (attr "type") + (cond [(match_operand:DF 3 "is_mul" "") + (const_string "fpop") + (match_operand:DF 3 "is_div" "") + (const_string "fpdiv") + ] + (const_string "fpop") + ) + )]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f,f") @@ -5611,15 +5534,34 @@ (float_extend:DF (match_operand:SF 2 "general_operand" "fm,0"))]))] "TARGET_80387" - "* return output_387_binary_op (insn, operands);") + "* return (char *) output_387_binary_op (insn, operands);" + [(set (attr "type") + (cond [(match_operand:DF 3 "is_mul" "") + (const_string "fpop") + (match_operand:DF 3 "is_div" "") + (const_string "fpdiv") + ] + (const_string "fpop") + ) + )]) +;; intel1 1 and 2 changed from nonimmediate operand to general operand (define_insn "" [(set (match_operand:SF 0 "register_operand" "=f,f") (match_operator:SF 3 "binary_387_op" - [(match_operand:SF 1 "nonimmediate_operand" "0,fm") - (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))] + [(match_operand:SF 1 "general_operand" "0,fm") + (match_operand:SF 2 "general_operand" "fm,0")]))] "TARGET_80387" - "* return output_387_binary_op (insn, operands);") + "* return (char *) output_387_binary_op (insn, operands);" + [(set (attr "type") + (cond [(match_operand:DF 3 "is_mul" "") + (const_string "fpop") + (match_operand:DF 3 "is_div" "") + (const_string "fpdiv") + ] + (const_string "fpop") + ) + )]) (define_insn "" [(set (match_operand:SF 0 "register_operand" "=f") @@ -5627,7 +5569,16 @@ [(float:SF (match_operand:SI 1 "general_operand" "rm")) (match_operand:SF 2 "general_operand" "0")]))] "TARGET_80387" - "* return output_387_binary_op (insn, operands);") + "* return (char *) output_387_binary_op (insn, operands);" + [(set (attr "type") + (cond [(match_operand:DF 3 "is_mul" "") + (const_string "fpop") + (match_operand:DF 3 "is_div" "") + (const_string "fpdiv") + ] + (const_string "fpop") + ) + )]) (define_insn "" [(set (match_operand:SF 0 "register_operand" "=f") @@ -5635,7 +5586,16 @@ [(match_operand:SF 1 "general_operand" "0") (float:SF (match_operand:SI 2 "general_operand" "rm"))]))] "TARGET_80387" - "* return output_387_binary_op (insn, operands);") + "* return (char *) output_387_binary_op (insn, operands);" + [(set (attr "type") + (cond [(match_operand:DF 3 "is_mul" "") + (const_string "fpop") + (match_operand:DF 3 "is_div" "") + (const_string "fpdiv") + ] + (const_string "fpop") + ) + )]) (define_expand "strlensi" [(parallel [(set (match_dup 4) @@ -5677,3 +5637,812 @@ output_asm_insn (AS2 (mov%L0,%1,%0), xops); return \"repnz\;scas%B2\"; }") + +;; intel1 peepholes +;; change fstp mem1 +;; fld mem1 +;; fop mem2 +;; to +;; fst mem1 +;; fop mem2 + +(define_peephole + [(set (match_operand:DF 0 "memory_operand" "g") + (reg:DF 8)) + (set (reg:DF 8) + (match_operand:DF 1 "memory_operand" "g")) + (set (reg:DF 8) + (mult:DF (reg:DF 8) + (match_dup 0))) + ] + "TARGET_80387" + "* + { + extern int flag_float_store; + if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) + { + if (flag_float_store) + { + output_asm_insn (AS1 (fstpl,%0),operands); + output_asm_insn (AS1 (fldl,%1),operands); + return AS1(fmull,%0); + } + output_asm_insn (AS1 (fstl,%0),operands); + return AS1(fmull,%1); + } + else + { + output_asm_insn (AS1 (fstl,%0),operands); + output_asm_insn (AS1 (fldl,%1),operands); + return AS1(fmull,%0); + } + }" +); + + + +(define_peephole + [(set (match_operand:DF 0 "memory_operand" "g") + (reg:DF 8)) + (set (reg:DF 8) + (match_operand:DF 1 "memory_operand" "g")) + (set (reg:DF 8) + (plus:DF (reg:DF 8) + (match_dup 0))) + ] + "TARGET_80387" + "* + { + extern int flag_float_store; + if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) + { + if (flag_float_store) + { + output_asm_insn (AS1 (fstpl,%0),operands); + output_asm_insn (AS1 (fldl,%1),operands); + return AS1(faddl,%0); + } + output_asm_insn (AS1 (fstl,%0),operands); + return AS1(faddl,%1); + } + else + { + output_asm_insn (AS1 (fstl,%0),operands); + output_asm_insn (AS1 (fldl,%1),operands); + return AS1(faddl,%0); + } + }" +); + + + +(define_peephole + [(set (match_operand:DF 0 "memory_operand" "g") + (reg:DF 8)) + (set (reg:DF 8) + (match_operand:DF 1 "memory_operand" "g")) + (set (reg:DF 8) + (minus:DF (reg:DF 8) + (match_dup 0))) + ] + "TARGET_80387" + "* + { + extern int flag_float_store; + if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) + { + if (flag_float_store) + { + output_asm_insn (AS1 (fstpl,%0),operands); + output_asm_insn (AS1 (fldl,%1),operands); + return AS1(fsubl,%0); + } + output_asm_insn (AS1 (fstl,%0),operands); + return AS1(fsubrl,%1); + } + else + { + output_asm_insn (AS1 (fstl,%0),operands); + output_asm_insn (AS1 (fldl,%1),operands); + return AS1(fsubl,%0); + } + }" +); + + + +(define_peephole + [(set (match_operand:DF 0 "memory_operand" "g") + (reg:DF 8)) + (set (reg:DF 8) + (match_operand:DF 1 "memory_operand" "g")) + (set (reg:DF 8) + (div:DF (reg:DF 8) + (match_dup 0))) + ] + "TARGET_80387" + "* + { + extern int flag_float_store; + if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) + { + if (flag_float_store) + { + output_asm_insn (AS1 (fstpl,%0),operands); + output_asm_insn (AS1 (fldl,%1),operands); + return AS1(fdivl,%0); + } + output_asm_insn (AS1 (fstl,%0),operands); + return AS1(fdivrl,%1); + } + else + { + output_asm_insn (AS1 (fstl,%0),operands); + output_asm_insn (AS1 (fldl,%1),operands); + return AS1(fdivl,%0); + } + }" +); + + +(define_peephole + [(set (match_operand:SF 0 "memory_operand" "g") + (reg:SF 8)) + (set (reg:SF 8) + (match_operand:SF 1 "memory_operand" "g")) + (set (reg:SF 8) + (mult:SF (reg:SF 8) + (match_dup 0))) + ] + "TARGET_80387" + "* + { + extern int flag_float_store; + if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) + { + if (flag_float_store) + { + output_asm_insn (AS1 (fstps,%0),operands); + output_asm_insn (AS1 (flds,%1),operands); + return AS1(fmuls,%0); + } + output_asm_insn (AS1 (fsts,%0),operands); + return AS1(fmuls,%1); + } + else + { + output_asm_insn (AS1 (fsts,%0),operands); + output_asm_insn (AS1 (flds,%1),operands); + return AS1(fmuls,%0); + } + }" +); + + + +(define_peephole + [(set (match_operand:SF 0 "memory_operand" "g") + (reg:SF 8)) + (set (reg:SF 8) + (match_operand:SF 1 "memory_operand" "g")) + (set (reg:SF 8) + (plus:SF (reg:SF 8) + (match_dup 0))) + ] + "TARGET_80387" + "* + { + extern int flag_float_store; + if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) + { + if (flag_float_store) + { + output_asm_insn (AS1 (fstps,%0),operands); + output_asm_insn (AS1 (flds,%1),operands); + return AS1(fadds,%0); + } + output_asm_insn (AS1 (fsts,%0),operands); + return AS1(fadds,%1); + } + else + { + output_asm_insn (AS1 (fsts,%0),operands); + output_asm_insn (AS1 (flds,%1),operands); + return AS1(fadds,%0); + } + }" +); + + + +(define_peephole + [(set (match_operand:SF 0 "memory_operand" "g") + (reg:SF 8)) + (set (reg:SF 8) + (match_operand:SF 1 "memory_operand" "g")) + (set (reg:SF 8) + (minus:SF (reg:SF 8) + (match_dup 0))) + ] + "TARGET_80387" + "* + { + extern int flag_float_store; + if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) + { + if (flag_float_store) + { + output_asm_insn (AS1 (fstps,%0),operands); + output_asm_insn (AS1 (flds,%1),operands); + return AS1(fsubs,%0); + } + output_asm_insn (AS1 (fsts,%0),operands); + return AS1(fsubrs,%1); + } + else + { + output_asm_insn (AS1 (fsts,%0),operands); + output_asm_insn (AS1 (flds,%1),operands); + return AS1(fsubs,%0); + } + }" +); + + + +(define_peephole + [(set (match_operand:SF 0 "memory_operand" "g") + (reg:SF 8)) + (set (reg:SF 8) + (match_operand:SF 1 "memory_operand" "g")) + (set (reg:SF 8) + (div:SF (reg:SF 8) + (match_dup 0))) + ] + "TARGET_80387" + "* + { + extern int flag_float_store; + if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) + { + if (flag_float_store) + { + output_asm_insn (AS1 (fstps,%0),operands); + output_asm_insn (AS1 (flds,%1),operands); + return AS1(fdivs,%0); + } + output_asm_insn (AS1 (fsts,%0),operands); + return AS1(fdivrs,%1); + } + else + { + output_asm_insn (AS1 (fsts,%0),operands); + output_asm_insn (AS1 (flds,%1),operands); + return AS1(fdivs,%0); + } + }" +); + + +;; change fstp mem1 +;; fld mem1 +;; to +;; fst mem1 + +(define_peephole + [(set (match_operand:DF 0 "memory_operand" "g") + (reg:DF 8)) + (set (reg:DF 8) + (match_dup 0))] + "TARGET_80387" + "* + { + extern int flag_float_store; + if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) + { + if(!MEM_VOLATILE_P (operands[0]) && !flag_float_store) + { + return AS1 (fstl,%0); + } + else + { + output_asm_insn (AS1 (fstpl,%0),operands); + return AS1 (fldl,%0); + } + } + else + { + output_asm_insn (AS1 (fstl,%0),operands); + return AS1 (fldl,%0); + } + }" +); + +(define_peephole + [(set (match_operand:SF 0 "memory_operand" "g") + (reg:SF 8)) + (set (reg:SF 8) + (match_dup 0))] + "TARGET_80387" + "* + { + extern int flag_float_store; + if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) + { + if(!MEM_VOLATILE_P (operands[0]) && !flag_float_store) + { + return AS1 (fsts,%0); + } + else + { + output_asm_insn (AS1 (fstps,%0),operands); + return AS1 (flds,%0); + } + } + else + { + output_asm_insn (AS1 (fsts,%0),operands); + return AS1 (flds,%0); + } + }" +); + +(define_peephole + [(set (match_operand:SF 0 "memory_operand" "g") + (reg:SF 8)) + (set (reg:DF 8) + (float_extend:DF (match_dup 0)))] + "TARGET_80387" + "* + { + extern int flag_float_store; + if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) && !flag_float_store) + { + return AS1 (fsts,%0); + } + else + { + output_asm_insn (AS1 (fsts,%0),operands); + return AS1 (flds,%0); + } + }" +); + +;; see if compare can be deleted +(define_peephole + [ + (set (cc0) + (compare (const_int 0) + (match_operand:SI 0 "general_operand" "g"))) + (set (pc) + (if_then_else (ne (cc0) + (const_int 0)) + (label_ref (match_operand 1 "" "")) + (pc))) + ] + "" + "* +{ + if(!last_to_set_cc(operands[0]),insn) + { + operands[2] = const0_rtx; + output_asm_insn (AS2 (cmp%L0,%2,%0),operands); + return \"jne %l1\"; + } + else + { + return \"jne %l1\"; + } +}"); + +(define_peephole + [ + (set (cc0) + (compare (match_operand:SI 0 "general_operand" "g") + (const_int 0))) + (set (pc) + (if_then_else (ne (cc0) + (const_int 0)) + (label_ref (match_operand 1 "" "")) + (pc))) + ] + "" + "* +{ + if(!last_to_set_cc(operands[0],insn)) + { + operands[2] = const0_rtx; + output_asm_insn (AS2 (cmp%L0,%2,%0),operands); + return \"jne %l1\"; + } + else + { + return \"jne %l1\"; + } +}"); + +;; optimization of sign_extend combined with and +(define_peephole + [ + (set (match_operand:HI 0 "register_operand" "") + (and:HI (match_dup 0) + (match_operand:HI 1 "immediate_operand" ""))) + (set (match_operand:SI 2 "register_operand" "") + (sign_extend:SI + (match_dup 0))) + ] + "" + "* +{ + int no_sign_extend = 0; + rtx note; + if ((INTVAL (operands[1]) & 0x8000) == 0) + { /* Don't need to do sign extend */ + no_sign_extend = 1; + } + CC_STATUS_INIT; + if (no_sign_extend) + { + if (REGNO (operands[0]) == REGNO (operands[2])) + { + operands [0] = gen_rtx (REG, SImode, REGNO (operands[0])); + output_asm_insn (AS2 (and%L0,%1,%0), operands); + } + else + { + output_asm_insn (AS2 (and%W0,%1,%w0), operands); + operands [0] = gen_rtx (REG, SImode, REGNO (operands[0])); + output_asm_insn (AS2 (mov%L0,%0,%2), operands); + operands [1] = gen_rtx (CONST_INT, 0, 0xffff); + output_asm_insn (AS2 (and%L0,%1,%2), operands); + } + RET; + } + /* Can we ignore the upper byte? */ + else if (QI_REG_P (operands[0]) + && (INTVAL (operands[1]) & 0xff00) == 0xff00) + { + if ((INTVAL (operands[1]) & 0xff) == 0) + { + operands[1] = const0_rtx; + output_asm_insn (AS2 (mov%B0,%1,%b0), operands); + } + else + { + operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff); + output_asm_insn (AS2 (and%B0,%1,%b0), operands); + } + } + else if (!no_sign_extend && QI_REG_P (operands[0]) + && (INTVAL (operands[1]) & 0xff) == 0xff) + { + if ((INTVAL (operands[1]) & 0xff00) == 0) + { + operands[1] = const0_rtx; + output_asm_insn (AS2 (mov%B0,%1,%h0), operands); + } + + operands[1] = GEN_INT ((INTVAL (operands[1]) >> 8) & 0xff); + output_asm_insn (AS2 (and%B0,%1,%b0), operands); + } + if (REGNO (operands[2]) == 0 && REGNO (operands[0]) == 0) +#ifdef INTEL_SYNTAX + return \"cwde\"; +#else + return \"cwtl\"; +#endif + +#ifdef INTEL_SYNTAX + return AS2 (movsx,%0,%2); +#else + return AS2 (movs%W0%L0,%0,%2); +#endif +}"); + +(define_peephole + [ + (set (match_operand:HI 0 "register_operand" "") + (match_operand:HI 1 "memory_operand" "")) + (set (match_dup 0) + (and:HI (match_dup 0) + (match_operand:HI 2 "immediate_operand" ""))) + (set (match_operand:SI 3 "register_operand" "") + (sign_extend:SI + (match_dup 0))) + ] + "" + "* +{ + int no_sign_extend = 0; + if ((INTVAL (operands[2]) & 0xff00) == 0 + && QI_REG_P (operands[0])) + { + output_asm_insn (AS2 (mov%B0,%b1,%b0), operands); + } + else + { + output_asm_insn (AS2 (mov%W0,%1,%0), operands); + } + if ((INTVAL (operands[2]) & 0x8000) == 0) + { /* Don't need to do sign extend */ + no_sign_extend = 1; + } + CC_STATUS_INIT; + if (no_sign_extend) + { + if (REGNO (operands[0]) == REGNO (operands[3])) + { + operands [0] = gen_rtx (REG, SImode, REGNO (operands[0])); + output_asm_insn (AS2 (and%L0,%2,%0), operands); + } + else + { + output_asm_insn (AS2 (and%W0,%2,%w0), operands); + operands [0] = gen_rtx (REG, SImode, REGNO (operands[0])); + output_asm_insn (AS2 (mov%L0,%0,%3), operands); + operands [2] = gen_rtx (CONST_INT, 0, 0xffff); + output_asm_insn (AS2 (and%L0,%2,%3), operands); + } + RET; + } + /* Can we ignore the upper byte? */ + else if (QI_REG_P (operands[0]) + && (INTVAL (operands[2]) & 0xff00) == 0xff00) + { + if ((INTVAL (operands[2]) & 0xff) == 0) + { + operands[2] = const0_rtx; + output_asm_insn (AS2 (mov%B0,%2,%b0), operands); + } + else + { + operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff); + output_asm_insn (AS2 (and%B0,%2,%b0), operands); + } + } + else if (!no_sign_extend && QI_REG_P (operands[0]) + && (INTVAL (operands[2]) & 0xff) == 0xff) + { + if ((INTVAL (operands[2]) & 0xff00) == 0) + { + operands[2] = const0_rtx; + output_asm_insn (AS2 (mov%B0,%2,%h0), operands); + } + + operands[1] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff); + output_asm_insn (AS2 (and%B0,%2,%b0), operands); + } + else + { + output_asm_insn (AS2 (and%W0,%2,%0), operands); + } + if (REGNO (operands[3]) == 0 && REGNO (operands[0]) == 0) +#ifdef INTEL_SYNTAX + return \"cwde\"; +#else + return \"cwtl\"; +#endif + +#ifdef INTEL_SYNTAX + return AS2 (movsx,%0,%3); +#else + return AS2 (movs%W0%L0,%0,%3); +#endif +}"); + +(define_peephole + [ + (set (match_operand:HI 0 "register_operand" "") + (sign_extend:HI + (match_operand:QI 1 "memory_operand" ""))) + (set (match_dup 0) + (and:HI (match_dup 0) + (match_operand:HI 2 "immediate_operand" ""))) + (set (match_operand:SI 3 "register_operand" "") + (sign_extend:SI + (match_dup 0))) + ] + "" + "* +{ + int no_sign_extend = 0; + if ((INTVAL (operands[2]) & 0xff00) == 0 + && QI_REG_P (operands[0])) + { + output_asm_insn (AS2 (mov%B0,%b1,%b0), operands); + } + else + { +#ifdef INTEL_SYNTAX + output_asm_insn( AS2 (movsx,%1,%0), operands); +#else + output_asm_insn( AS2 (movs%B0%W0,%1,%0), operands); +#endif + } + if ((INTVAL (operands[2]) & 0x8000) == 0) + { /* Don't need to do sign extend */ + no_sign_extend = 1; + } + CC_STATUS_INIT; + if (no_sign_extend) + { + if (REGNO (operands[0]) == REGNO (operands[3])) + { + operands [0] = gen_rtx (REG, SImode, REGNO (operands[0])); + output_asm_insn (AS2 (and%L0,%2,%0), operands); + } + else + { + output_asm_insn (AS2 (and%W0,%2,%w0), operands); + operands [0] = gen_rtx (REG, SImode, REGNO (operands[0])); + output_asm_insn (AS2 (mov%L0,%0,%3), operands); + operands [2] = gen_rtx (CONST_INT, 0, 0xffff); + output_asm_insn (AS2 (and%L0,%2,%3), operands); + } + RET; + } + /* Can we ignore the upper byte? */ + else if (QI_REG_P (operands[0]) + && (INTVAL (operands[2]) & 0xff00) == 0xff00) + { + if ((INTVAL (operands[2]) & 0xff) == 0) + { + operands[2] = const0_rtx; + output_asm_insn (AS2 (mov%B0,%2,%b0), operands); + } + else + { + operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff); + output_asm_insn (AS2 (and%B0,%2,%b0), operands); + } + } + else if (!no_sign_extend && QI_REG_P (operands[0]) + && (INTVAL (operands[2]) & 0xff) == 0xff) + { + if ((INTVAL (operands[2]) & 0xff00) == 0) + { + operands[2] = const0_rtx; + output_asm_insn (AS2 (mov%B0,%2,%h0), operands); + } + + operands[1] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff); + output_asm_insn (AS2 (and%B0,%2,%b0), operands); + } + else + { + output_asm_insn (AS2 (and%W0,%2,%0), operands); + } + if (REGNO (operands[3]) == 0 && REGNO (operands[0]) == 0) +#ifdef INTEL_SYNTAX + return \"cwde\"; +#else + return \"cwtl\"; +#endif + +#ifdef INTEL_SYNTAX + return AS2 (movsx,%0,%3); +#else + return AS2 (movs%W0%L0,%0,%3); +#endif +}"); + +(define_peephole + [ + (set (match_operand:HI 0 "register_operand" "") + (sign_extend:HI + (match_operand:QI 1 "memory_operand" ""))) + (set (match_dup 0) + (and:HI (match_dup 0) + (match_operand:HI 2 "immediate_operand" ""))) + ] + "" + "* +{ + if ((INTVAL (operands[2]) & 0xff00) == 0 + && QI_REG_P (operands[0])) + { + output_asm_insn (AS2 (mov%B0,%b1,%b0), operands); + } + else + { +#ifdef INTEL_SYNTAX + output_asm_insn( AS2 (movsx,%1,%0), operands); +#else + output_asm_insn( AS2 (movs%B0%W0,%1,%0), operands); +#endif + } + /* Can we ignore the upper byte? */ + if (QI_REG_P (operands[0]) + && (INTVAL (operands[2]) & 0xff00) == 0xff00) + { + if ((INTVAL (operands[2]) & 0xff) == 0) + { + operands[2] = const0_rtx; + output_asm_insn (AS2 (mov%B0,%2,%b0), operands); + } + else + { + operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff); + output_asm_insn (AS2 (and%B0,%2,%b0), operands); + } + } + else if (QI_REG_P (operands[0]) + && (INTVAL (operands[2]) & 0xff) == 0xff) + { + if ((INTVAL (operands[2]) & 0xff00) == 0) + { + operands[2] = const0_rtx; + output_asm_insn (AS2 (mov%B0,%2,%h0), operands); + } + + operands[1] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff); + output_asm_insn (AS2 (and%B0,%2,%b0), operands); + } + else + { + output_asm_insn (AS2 (and%W0,%2,%0), operands); + } + RET; +}"); + +(define_peephole + [ + (set (match_operand:SI 0 "register_operand" "") + (sign_extend:SI + (match_operand:QI 1 "memory_operand" ""))) + (set (match_dup 0) + (and:SI (match_dup 0) + (match_operand:SI 2 "immediate_operand" ""))) + ] + "" + "* +{ + if ((INTVAL (operands[2]) & 0xffffff00) == 0 + && QI_REG_P (operands[0])) + { + output_asm_insn (AS2 (mov%B0,%b1,%b0), operands); + } + else + { +#ifdef INTEL_SYNTAX + output_asm_insn( AS2 (movsx,%1,%0), operands); +#else + output_asm_insn( AS2 (movs%B0%L0,%1,%0), operands); +#endif + } + output_asm_insn (AS2 (and%L0,%2,%0), operands); + RET; +}"); + +(define_peephole + [ + (set (match_operand:SI 0 "register_operand" "") + (sign_extend:SI + (match_operand:HI 1 "memory_operand" ""))) + (set (match_dup 0) + (and:SI (match_dup 0) + (match_operand:SI 2 "immediate_operand" ""))) + ] + "" + "* +{ + if ((INTVAL (operands[2]) & 0xffffff00) == 0 + && QI_REG_P (operands[0])) + { + output_asm_insn (AS2 (mov%B0,%b1,%b0), operands); + } + else if ((INTVAL (operands[2]) & 0xffff0000) == 0) + { + output_asm_insn (AS2 (mov%W0,%h1,%h0), operands); + } + else + { +#ifdef INTEL_SYNTAX + output_asm_insn( AS2 (movsx,%1,%0), operands); +#else + output_asm_insn( AS2 (movs%B0%W0,%1,%0), operands); +#endif + } + output_asm_insn (AS2 (and%L0,%2,%0), operands); + RET; +}"); diff -r -u -H -N gcc-2.6.3/config/i386/osfrose.h gcc-i2.6.3/config/i386/osfrose.h --- gcc-2.6.3/config/i386/osfrose.h Wed Oct 26 17:14:11 1994 +++ gcc-i2.6.3/config/i386/osfrose.h Wed Feb 15 22:46:52 1995 @@ -468,6 +468,10 @@ defined, is executed once just after all the command options have been parsed. */ +#ifdef OVERRIDE_OPTIONS +#undef OVERRIDE_OPTIONS +#endif + #undef SUBTARGET_OVERRIDE_OPTIONS #define SUBTARGET_OVERRIDE_OPTIONS \ { \ diff -r -u -H -N gcc-2.6.3/config.sub gcc-i2.6.3/config.sub --- gcc-2.6.3/config.sub Wed Oct 26 14:23:05 1994 +++ gcc-i2.6.3/config.sub Wed Feb 15 23:11:03 1995 @@ -120,7 +120,7 @@ # Recognize the basic CPU types without company name. # Some are omitted here because they have special meanings below. tahoe | i[345]86 | i860 | m68k | m68000 | m88k | ns32k | arm | pyramid \ - | tron | a29k | 580 | i960 | h8300 | hppa1.0 | hppa1.1 \ + | pentium | tron | a29k | 580 | i960 | h8300 | hppa1.0 | hppa1.1 \ | alpha | we32k | ns16k | clipper | sparclite | i370 | sh \ | powerpc | sparc64 | 1750a | dsp16xx | mips64 | mipsel \ | pdp11 | mips64el | mips64orion | mips64orionel ) @@ -133,7 +133,7 @@ ;; # Recognize the basic CPU types with company name. vax-* | tahoe-* | i[345]86-* | i860-* | m68k-* | m68000-* | m88k-* \ - | sparc-* | ns32k-* | fx80-* | arm-* | c[123]* \ + | pentium-* | sparc-* | ns32k-* | fx80-* | arm-* | c[123]* \ | mips-* | pyramid-* | tron-* | a29k-* | romp-* | rs6000-* \ | none-* | 580-* | cray2-* | h8300-* | i960-* | xmp-* | ymp-* \ | hppa1.0-* | hppa1.1-* | alpha-* | we32k-* | cydra-* | ns16k-* \ @@ -300,18 +300,34 @@ basic_machine=`echo $1 | sed -e 's/86.*/86-unknown/'` os=-sysv32 ;; + pentiumv32) + basic_machine=`echo $1 | sed -e 's/pentium.*/pentium-unknown/'` + os=-sysv32 + ;; i[345]86v4*) basic_machine=`echo $1 | sed -e 's/86.*/86-unknown/'` os=-sysv4 ;; + pentiumv4*) + basic_machine=`echo $1 | sed -e 's/pentium.*/pentium-unknown/'` + os=-sysv4 + ;; i[345]86v) basic_machine=`echo $1 | sed -e 's/86.*/86-unknown/'` os=-sysv ;; + pentiumv) + basic_machine=`echo $1 | sed -e 's/pentium.*/pentium-unknown/'` + os=-sysv + ;; i[345]86sol2) basic_machine=`echo $1 | sed -e 's/86.*/86-unknown/'` os=-solaris2 ;; + pentiumsol2) + basic_machine=`echo $1 | sed -e 's/pentium.*/pentium-unknown/'` + os=-solaris2 + ;; iris | iris4d) basic_machine=mips-sgi case $os in diff -r -u -H -N gcc-2.6.3/configure gcc-i2.6.3/configure --- gcc-2.6.3/configure Wed Nov 23 17:26:27 1994 +++ gcc-i2.6.3/configure Wed Feb 15 23:56:29 1995 @@ -664,7 +664,7 @@ xm_file=i370/xm-mvs.h out_file=i370/mvs370.c ;; - i[345]86-ibm-aix*) # IBM PS/2 running AIX + pentium-ibm-aix* | i[345]86-ibm-aix*) # IBM PS/2 running AIX cpu_type=i386 if [ x$gas = xyes ] then @@ -685,7 +685,7 @@ tm_file=i386/sysv4.h tmake_file=t-svr4 ;; - i[345]86-next-*) + pentium-next-* | i[345]86-next-*) cpu_type=i386 tm_file=i386/next.h out_file=i386/next.c @@ -693,7 +693,7 @@ tmake_file=i386/t-next xmake_file=i386/x-next ;; - i[345]86-sequent-bsd*) # 80386 from Sequent + pentium-sequent-bsd* | i[345]86-sequent-bsd*) # 80386 from Sequent cpu_type=i386 use_collect2=yes if [ x$gas = xyes ] @@ -703,7 +703,7 @@ tm_file=i386/sequent.h fi ;; - i[345]86-sequent-ptx1*) + pentium-sequent-ptx1* | i[345]86-sequent-ptx1*) cpu_type=i386 xm_file=i386/xm-sysv3.h xmake_file=i386/x-sysv3 @@ -730,7 +730,7 @@ tm_file=i386/sun.h use_collect2=yes ;; - i[345]86-*-bsdi* | i[345]86-*-bsd386*) + pentium-*-bsd* | i[345]86-*-bsdi* | i[345]86-*-bsd386*) cpu_type=i386 tm_file=i386/bsd386.h # tmake_file=t-libc-ok @@ -742,21 +742,21 @@ # Next line turned off because both 386BSD and BSD/386 use GNU ld. # use_collect2=yes ;; - i[345]86-*-freebsd*) + pentium-*-freebsd* | i[345]86-*-freebsd*) cpu_type=i386 tm_file=i386/freebsd.h # On FreeBSD, the headers are already ok. fixincludes=Makefile.in xmake_file=i386/x-freebsd ;; - i[345]86-*-netbsd*) + pentium-*-netbsd* | i[345]86-*-netbsd*) cpu_type=i386 tm_file=i386/netbsd-i386.h # On NetBSD, the headers are already okay. fixincludes=Makefile.in xmake_file=x-netbsd ;; - i[345]86-*-gnu*) + pentium-*-gnu* | i[345]86-*-gnu*) cpu_type=i386 xm_file=i386/xm-gnu.h tm_file=i386/gnu.h @@ -790,7 +790,7 @@ install_headers_dir=install-headers-cpio broken_install=yes ;; - i[345]86-*-linux*) # Intel 80386's running Linux + pentium-*-linux* | i[345]86-*-linux*) # Intel 80386's running Linux cpu_type=i386 xm_file=i386/xm-linux.h xmake_file=i386/x-linux @@ -803,7 +803,7 @@ fixincludes=Makefile.in #On Linux, the headers are ok already. broken_install=yes ;; - i[345]86-*-lynxos*) + pentium-*-lynxos* | i[345]86-*-lynxos*) cpu_type=i386 if [ x$gas = xyes ] then @@ -814,13 +814,13 @@ xm_file=xm-lynx.h xmake_file=x-lynx ;; - i[345]86-*-mach*) + pentium-*-mach* | i[345]86-*-mach*) cpu_type=i386 tm_file=i386/mach.h # tmake_file=t-libc-ok use_collect2=yes ;; - i[345]86-*-osfrose*) # 386 using OSF/rose + pentium-*-osfrose* | i[345]86-*-osfrose*) # 386 using OSF/rose cpu_type=i386 if [ x$elf = xyes ] then @@ -876,7 +876,7 @@ fixincludes=fixinc.svr4 broken_install=yes ;; - i[345]86-*-sysv4*) # Intel 80386's running system V.4 + pentium-*-sysv4* | i[345]86-*-sysv4*) # Intel 80386's running system V.4 cpu_type=i386 xm_file=i386/xm-sysv4.h if [ x$stabs = xyes ] @@ -888,7 +888,7 @@ tmake_file=t-svr4 xmake_file=x-svr4 ;; - i[345]86-*-sysv*) # Intel 80386's running system V + pentium-*-sysv* | i[345]86-*-sysv*) # Intel 80386's running system V cpu_type=i386 xm_file=i386/xm-sysv3.h xmake_file=i386/x-sysv3 @@ -907,7 +907,7 @@ extra_parts="crtbegin.o crtend.o" fi ;; - i[345]86-*-winnt3*) + pentium-*-winnt3* | i[345]86-*-winnt3*) cpu_type=i386 tm_file=i386/winnt.h out_file=i386/i386.c @@ -1896,10 +1896,16 @@ esac # Distinguish i386 from i486/i586. - # ??? For the moment we treat i586 as an i486. + # ??? For the moment we treat i586 as an i486. (NOT!) # Also, do not run mips-tfile on MIPS if using gas. case $machine in - i[45]86-*-*) + pentium-*-*) + target_cpu_default=4 + ;; + i586-*-*) + target_cpu_default=4 + ;; + i486-*-*) target_cpu_default=2 ;; mips-*-*) diff -r -u -H -N gcc-2.6.3/cp/parse.c gcc-i2.6.3/cp/parse.c --- gcc-2.6.3/cp/parse.c Fri Oct 14 14:51:23 1994 +++ gcc-i2.6.3/cp/parse.c Tue Dec 20 16:53:24 1994 @@ -190,7 +190,7 @@ -#define YYFINAL 1356 +#define YYFINAL 1350 #define YYFLAG -32768 #define YYNTBASE 106 @@ -257,59 +257,59 @@ 630, 635, 640, 642, 646, 650, 654, 658, 662, 666, 670, 674, 678, 682, 686, 690, 694, 698, 702, 706, 710, 714, 718, 724, 728, 732, 734, 737, 741, 743, - 745, 747, 749, 751, 753, 755, 758, 761, 765, 767, - 769, 771, 775, 777, 779, 781, 783, 787, 791, 792, - 797, 798, 805, 808, 813, 816, 819, 821, 826, 828, - 836, 844, 852, 860, 865, 870, 873, 876, 878, 883, - 886, 889, 892, 898, 902, 908, 912, 917, 924, 926, - 929, 931, 934, 936, 938, 940, 943, 944, 947, 950, - 954, 958, 962, 966, 970, 973, 976, 978, 980, 982, - 985, 988, 991, 994, 996, 998, 1000, 1002, 1005, 1008, - 1012, 1016, 1021, 1023, 1026, 1029, 1031, 1033, 1036, 1039, - 1041, 1044, 1047, 1051, 1053, 1056, 1058, 1060, 1062, 1067, - 1072, 1077, 1082, 1084, 1086, 1088, 1090, 1094, 1096, 1100, - 1102, 1106, 1107, 1112, 1113, 1121, 1126, 1127, 1135, 1140, - 1141, 1149, 1154, 1155, 1163, 1168, 1169, 1171, 1173, 1176, - 1183, 1185, 1189, 1190, 1192, 1197, 1204, 1209, 1211, 1213, - 1215, 1217, 1219, 1223, 1225, 1228, 1232, 1237, 1239, 1241, - 1245, 1250, 1257, 1261, 1267, 1268, 1276, 1281, 1282, 1289, - 1293, 1296, 1299, 1304, 1306, 1307, 1309, 1310, 1312, 1314, - 1317, 1320, 1323, 1326, 1330, 1333, 1336, 1339, 1343, 1347, - 1349, 1352, 1353, 1354, 1358, 1362, 1365, 1367, 1369, 1370, - 1372, 1375, 1377, 1381, 1383, 1386, 1388, 1393, 1398, 1400, - 1402, 1405, 1408, 1410, 1411, 1413, 1418, 1422, 1424, 1427, - 1430, 1433, 1436, 1439, 1442, 1445, 1448, 1453, 1456, 1458, - 1464, 1468, 1469, 1471, 1475, 1476, 1478, 1482, 1484, 1486, - 1488, 1490, 1495, 1502, 1507, 1512, 1519, 1524, 1528, 1533, - 1540, 1545, 1550, 1557, 1562, 1566, 1568, 1572, 1574, 1578, - 1581, 1583, 1590, 1591, 1594, 1596, 1599, 1600, 1603, 1607, - 1611, 1614, 1617, 1621, 1623, 1625, 1627, 1630, 1636, 1642, - 1646, 1652, 1657, 1661, 1665, 1668, 1670, 1674, 1678, 1681, - 1684, 1688, 1690, 1694, 1698, 1701, 1704, 1708, 1710, 1716, - 1722, 1726, 1732, 1736, 1741, 1745, 1748, 1751, 1753, 1756, - 1761, 1766, 1769, 1771, 1773, 1775, 1778, 1781, 1784, 1786, - 1789, 1791, 1794, 1797, 1801, 1803, 1807, 1810, 1814, 1817, - 1820, 1824, 1826, 1830, 1835, 1839, 1842, 1845, 1847, 1851, - 1854, 1857, 1859, 1862, 1866, 1868, 1872, 1874, 1880, 1884, - 1889, 1893, 1898, 1901, 1904, 1908, 1911, 1913, 1915, 1918, - 1921, 1924, 1925, 1926, 1928, 1930, 1933, 1937, 1939, 1942, - 1946, 1952, 1959, 1965, 1966, 1967, 1974, 1976, 1979, 1981, - 1983, 1985, 1988, 1989, 1994, 1996, 1997, 1998, 2005, 2006, - 2007, 2015, 2016, 2017, 2018, 2029, 2030, 2031, 2032, 2043, - 2044, 2052, 2053, 2059, 2060, 2068, 2069, 2074, 2077, 2080, - 2083, 2087, 2094, 2103, 2114, 2127, 2132, 2136, 2139, 2142, - 2144, 2146, 2147, 2148, 2156, 2158, 2161, 2164, 2165, 2166, - 2172, 2174, 2176, 2180, 2184, 2187, 2190, 2193, 2197, 2202, - 2207, 2211, 2216, 2223, 2230, 2231, 2233, 2234, 2236, 2238, - 2239, 2241, 2243, 2247, 2252, 2254, 2258, 2259, 2261, 2263, - 2265, 2268, 2271, 2274, 2276, 2278, 2281, 2284, 2287, 2290, - 2292, 2296, 2299, 2302, 2307, 2310, 2313, 2316, 2319, 2322, - 2325, 2327, 2330, 2332, 2336, 2338, 2340, 2341, 2342, 2344, - 2345, 2350, 2352, 2354, 2358, 2359, 2363, 2367, 2371, 2373, - 2376, 2379, 2382, 2385, 2388, 2391, 2394, 2397, 2400, 2403, - 2406, 2409, 2412, 2415, 2418, 2421, 2424, 2427, 2430, 2433, - 2436, 2439, 2442, 2446, 2449, 2452, 2455, 2458, 2462, 2465, - 2468, 2473, 2478, 2482 + 745, 747, 749, 751, 753, 755, 758, 761, 763, 765, + 767, 769, 771, 773, 775, 779, 783, 784, 789, 790, + 797, 800, 805, 808, 811, 813, 818, 820, 828, 836, + 844, 852, 857, 862, 865, 868, 870, 875, 878, 881, + 884, 890, 894, 900, 904, 909, 916, 918, 921, 923, + 926, 928, 930, 932, 935, 936, 939, 942, 946, 950, + 954, 958, 962, 965, 968, 970, 972, 974, 977, 980, + 983, 986, 988, 990, 992, 994, 997, 1000, 1004, 1008, + 1013, 1015, 1018, 1021, 1023, 1025, 1028, 1031, 1033, 1036, + 1039, 1043, 1045, 1048, 1050, 1052, 1054, 1059, 1064, 1069, + 1074, 1076, 1078, 1080, 1082, 1086, 1088, 1092, 1094, 1098, + 1099, 1104, 1105, 1113, 1118, 1119, 1127, 1132, 1133, 1141, + 1146, 1147, 1155, 1160, 1161, 1163, 1165, 1168, 1175, 1177, + 1181, 1182, 1184, 1189, 1196, 1201, 1203, 1205, 1207, 1209, + 1211, 1215, 1217, 1220, 1224, 1229, 1231, 1233, 1237, 1242, + 1249, 1253, 1259, 1260, 1268, 1273, 1274, 1281, 1285, 1288, + 1291, 1296, 1298, 1299, 1301, 1302, 1304, 1306, 1309, 1312, + 1315, 1318, 1322, 1325, 1328, 1331, 1335, 1339, 1341, 1344, + 1345, 1346, 1350, 1354, 1357, 1359, 1361, 1362, 1364, 1367, + 1369, 1373, 1375, 1378, 1380, 1385, 1390, 1392, 1394, 1397, + 1400, 1402, 1403, 1405, 1410, 1414, 1416, 1419, 1422, 1425, + 1428, 1431, 1434, 1437, 1440, 1445, 1448, 1450, 1456, 1460, + 1461, 1463, 1467, 1468, 1470, 1474, 1476, 1478, 1480, 1482, + 1487, 1494, 1499, 1504, 1511, 1516, 1520, 1525, 1532, 1537, + 1542, 1549, 1554, 1558, 1560, 1564, 1566, 1570, 1573, 1575, + 1582, 1583, 1586, 1588, 1591, 1592, 1595, 1599, 1603, 1606, + 1609, 1613, 1615, 1617, 1619, 1622, 1628, 1634, 1638, 1644, + 1649, 1653, 1657, 1660, 1662, 1666, 1670, 1673, 1676, 1680, + 1682, 1686, 1690, 1693, 1696, 1700, 1702, 1708, 1714, 1718, + 1724, 1728, 1732, 1737, 1741, 1744, 1747, 1749, 1752, 1757, + 1762, 1765, 1767, 1769, 1771, 1774, 1777, 1780, 1782, 1785, + 1787, 1790, 1793, 1797, 1799, 1803, 1806, 1810, 1813, 1816, + 1820, 1822, 1826, 1831, 1835, 1838, 1841, 1843, 1847, 1850, + 1853, 1855, 1858, 1862, 1864, 1868, 1870, 1876, 1880, 1885, + 1889, 1894, 1897, 1900, 1904, 1907, 1909, 1911, 1914, 1917, + 1920, 1921, 1922, 1924, 1926, 1929, 1933, 1935, 1938, 1942, + 1948, 1955, 1961, 1962, 1963, 1970, 1972, 1975, 1977, 1979, + 1981, 1984, 1985, 1990, 1992, 1993, 1994, 2001, 2002, 2003, + 2011, 2012, 2013, 2014, 2025, 2026, 2027, 2028, 2039, 2040, + 2048, 2049, 2055, 2056, 2064, 2065, 2070, 2073, 2076, 2079, + 2083, 2090, 2099, 2110, 2123, 2128, 2132, 2135, 2138, 2140, + 2142, 2143, 2144, 2152, 2154, 2157, 2160, 2161, 2162, 2168, + 2170, 2172, 2176, 2180, 2183, 2186, 2189, 2193, 2198, 2203, + 2207, 2212, 2219, 2226, 2227, 2229, 2230, 2232, 2234, 2235, + 2237, 2239, 2243, 2248, 2250, 2254, 2255, 2257, 2259, 2261, + 2264, 2267, 2270, 2272, 2274, 2277, 2280, 2283, 2286, 2288, + 2292, 2295, 2298, 2303, 2306, 2309, 2312, 2315, 2318, 2321, + 2323, 2326, 2328, 2332, 2334, 2336, 2337, 2338, 2340, 2341, + 2346, 2348, 2350, 2354, 2355, 2359, 2363, 2367, 2369, 2372, + 2375, 2378, 2381, 2384, 2387, 2390, 2393, 2396, 2399, 2402, + 2405, 2408, 2411, 2414, 2417, 2420, 2423, 2426, 2429, 2432, + 2435, 2438, 2442, 2445, 2448, 2451, 2454, 2458, 2461, 2464, + 2469, 2474, 2478 }; static const short yyrhs[] = { -1, @@ -389,179 +389,178 @@ 0, 92, 0, 92, 169, 0, 83, 330, 139, 0, 337, 0, 3, 0, 53, 0, 170, 0, 4, 0, 170, 0, 263, 0, 75, 172, 0, 65, 172, 0, - 88, 172, 102, 0, 261, 0, 170, 0, 263, 0, - 88, 172, 102, 0, 170, 0, 8, 0, 179, 0, - 180, 0, 88, 153, 102, 0, 88, 1, 102, 0, - 0, 88, 175, 284, 102, 0, 0, 174, 88, 161, - 102, 176, 151, 0, 174, 44, 0, 174, 89, 153, - 105, 0, 174, 81, 0, 174, 82, 0, 40, 0, - 7, 88, 161, 102, 0, 265, 0, 47, 69, 186, - 70, 88, 153, 102, 0, 48, 69, 186, 70, 88, - 153, 102, 0, 49, 69, 186, 70, 88, 153, 102, - 0, 50, 69, 186, 70, 88, 153, 102, 0, 46, - 88, 153, 102, 0, 46, 88, 186, 102, 0, 272, - 3, 0, 272, 337, 0, 264, 0, 264, 88, 161, - 102, 0, 264, 44, 0, 182, 171, 0, 182, 262, - 0, 182, 171, 88, 161, 102, 0, 182, 171, 44, - 0, 182, 262, 88, 161, 102, 0, 182, 262, 44, - 0, 182, 83, 6, 44, 0, 182, 6, 51, 83, - 6, 44, 0, 38, 0, 272, 38, 0, 37, 0, - 272, 178, 0, 42, 0, 43, 0, 9, 0, 180, - 9, 0, 0, 174, 87, 0, 174, 86, 0, 193, - 184, 56, 0, 187, 184, 56, 0, 193, 195, 56, - 0, 187, 195, 56, 0, 190, 196, 56, 0, 187, - 56, 0, 190, 56, 0, 255, 0, 259, 0, 44, - 0, 185, 44, 0, 191, 275, 0, 252, 275, 0, - 193, 275, 0, 191, 0, 252, 0, 191, 0, 188, - 0, 190, 193, 0, 193, 189, 0, 190, 193, 189, - 0, 190, 193, 192, 0, 190, 193, 192, 189, 0, - 5, 0, 189, 194, 0, 189, 5, 0, 252, 0, - 5, 0, 190, 7, 0, 190, 5, 0, 193, 0, - 252, 193, 0, 193, 192, 0, 252, 193, 192, 0, - 194, 0, 192, 194, 0, 216, 0, 6, 0, 269, - 0, 27, 88, 153, 102, 0, 27, 88, 186, 102, - 0, 31, 88, 153, 102, 0, 31, 88, 186, 102, - 0, 6, 0, 7, 0, 216, 0, 199, 0, 195, - 55, 201, 0, 203, 0, 196, 55, 201, 0, 205, - 0, 197, 55, 201, 0, 0, 111, 88, 180, 102, - 0, 0, 184, 332, 198, 207, 58, 200, 214, 0, - 184, 332, 198, 207, 0, 0, 184, 332, 198, 207, - 58, 202, 214, 0, 184, 332, 198, 207, 0, 0, - 259, 332, 198, 207, 58, 204, 214, 0, 259, 332, - 198, 207, 0, 0, 259, 332, 198, 207, 58, 206, - 214, 0, 259, 332, 198, 207, 0, 0, 208, 0, - 209, 0, 208, 209, 0, 32, 88, 88, 210, 102, - 102, 0, 211, 0, 210, 55, 211, 0, 0, 212, - 0, 212, 88, 3, 102, 0, 212, 88, 3, 55, - 161, 102, 0, 212, 88, 161, 102, 0, 139, 0, - 5, 0, 6, 0, 7, 0, 139, 0, 213, 55, - 139, 0, 169, 0, 54, 103, 0, 54, 215, 103, - 0, 54, 215, 55, 103, 0, 1, 0, 214, 0, - 215, 55, 214, 0, 89, 169, 105, 214, 0, 215, - 55, 19, 169, 60, 214, 0, 139, 60, 214, 0, - 215, 55, 139, 60, 214, 0, 0, 12, 139, 54, - 217, 248, 220, 103, 0, 12, 139, 54, 103, 0, - 0, 12, 54, 218, 248, 220, 103, 0, 12, 54, - 103, 0, 12, 139, 0, 12, 270, 0, 229, 235, - 236, 103, 0, 229, 0, 0, 55, 0, 0, 55, - 0, 35, 0, 221, 5, 0, 221, 6, 0, 221, - 7, 0, 221, 35, 0, 221, 144, 56, 0, 221, - 139, 0, 221, 270, 0, 221, 143, 0, 221, 144, - 54, 0, 221, 144, 60, 0, 222, 0, 221, 141, - 0, 0, 0, 223, 225, 230, 0, 224, 226, 230, - 0, 221, 54, 0, 228, 0, 227, 0, 0, 60, - 0, 60, 231, 0, 232, 0, 231, 55, 232, 0, - 233, 0, 234, 233, 0, 269, 0, 31, 88, 153, - 102, 0, 31, 88, 186, 102, 0, 36, 0, 5, - 0, 234, 36, 0, 234, 5, 0, 54, 0, 0, - 237, 0, 236, 36, 60, 237, 0, 236, 36, 60, - 0, 238, 0, 237, 238, 0, 237, 56, 0, 239, - 56, 0, 239, 103, 0, 132, 60, 0, 132, 54, - 0, 187, 240, 0, 190, 241, 0, 259, 332, 198, - 207, 0, 60, 169, 0, 1, 0, 187, 88, 323, - 102, 251, 0, 187, 44, 251, 0, 0, 242, 0, - 240, 55, 243, 0, 0, 245, 0, 241, 55, 247, - 0, 244, 0, 245, 0, 246, 0, 247, 0, 255, + 261, 0, 170, 0, 263, 0, 170, 0, 8, 0, + 179, 0, 180, 0, 88, 153, 102, 0, 88, 1, + 102, 0, 0, 88, 175, 284, 102, 0, 0, 174, + 88, 161, 102, 176, 151, 0, 174, 44, 0, 174, + 89, 153, 105, 0, 174, 81, 0, 174, 82, 0, + 40, 0, 7, 88, 161, 102, 0, 265, 0, 47, + 69, 186, 70, 88, 153, 102, 0, 48, 69, 186, + 70, 88, 153, 102, 0, 49, 69, 186, 70, 88, + 153, 102, 0, 50, 69, 186, 70, 88, 153, 102, + 0, 46, 88, 153, 102, 0, 46, 88, 186, 102, + 0, 272, 3, 0, 272, 337, 0, 264, 0, 264, + 88, 161, 102, 0, 264, 44, 0, 182, 171, 0, + 182, 262, 0, 182, 171, 88, 161, 102, 0, 182, + 171, 44, 0, 182, 262, 88, 161, 102, 0, 182, + 262, 44, 0, 182, 83, 6, 44, 0, 182, 6, + 51, 83, 6, 44, 0, 38, 0, 272, 38, 0, + 37, 0, 272, 178, 0, 42, 0, 43, 0, 9, + 0, 180, 9, 0, 0, 174, 87, 0, 174, 86, + 0, 193, 184, 56, 0, 187, 184, 56, 0, 193, + 195, 56, 0, 187, 195, 56, 0, 190, 196, 56, + 0, 187, 56, 0, 190, 56, 0, 255, 0, 259, + 0, 44, 0, 185, 44, 0, 191, 275, 0, 252, + 275, 0, 193, 275, 0, 191, 0, 252, 0, 191, + 0, 188, 0, 190, 193, 0, 193, 189, 0, 190, + 193, 189, 0, 190, 193, 192, 0, 190, 193, 192, + 189, 0, 5, 0, 189, 194, 0, 189, 5, 0, + 252, 0, 5, 0, 190, 7, 0, 190, 5, 0, + 193, 0, 252, 193, 0, 193, 192, 0, 252, 193, + 192, 0, 194, 0, 192, 194, 0, 216, 0, 6, + 0, 269, 0, 27, 88, 153, 102, 0, 27, 88, + 186, 102, 0, 31, 88, 153, 102, 0, 31, 88, + 186, 102, 0, 6, 0, 7, 0, 216, 0, 199, + 0, 195, 55, 201, 0, 203, 0, 196, 55, 201, + 0, 205, 0, 197, 55, 201, 0, 0, 111, 88, + 180, 102, 0, 0, 184, 332, 198, 207, 58, 200, + 214, 0, 184, 332, 198, 207, 0, 0, 184, 332, + 198, 207, 58, 202, 214, 0, 184, 332, 198, 207, + 0, 0, 259, 332, 198, 207, 58, 204, 214, 0, + 259, 332, 198, 207, 0, 0, 259, 332, 198, 207, + 58, 206, 214, 0, 259, 332, 198, 207, 0, 0, + 208, 0, 209, 0, 208, 209, 0, 32, 88, 88, + 210, 102, 102, 0, 211, 0, 210, 55, 211, 0, + 0, 212, 0, 212, 88, 3, 102, 0, 212, 88, + 3, 55, 161, 102, 0, 212, 88, 161, 102, 0, + 139, 0, 5, 0, 6, 0, 7, 0, 139, 0, + 213, 55, 139, 0, 169, 0, 54, 103, 0, 54, + 215, 103, 0, 54, 215, 55, 103, 0, 1, 0, + 214, 0, 215, 55, 214, 0, 89, 169, 105, 214, + 0, 215, 55, 19, 169, 60, 214, 0, 139, 60, + 214, 0, 215, 55, 139, 60, 214, 0, 0, 12, + 139, 54, 217, 248, 220, 103, 0, 12, 139, 54, + 103, 0, 0, 12, 54, 218, 248, 220, 103, 0, + 12, 54, 103, 0, 12, 139, 0, 12, 270, 0, + 229, 235, 236, 103, 0, 229, 0, 0, 55, 0, + 0, 55, 0, 35, 0, 221, 5, 0, 221, 6, + 0, 221, 7, 0, 221, 35, 0, 221, 144, 56, + 0, 221, 139, 0, 221, 270, 0, 221, 143, 0, + 221, 144, 54, 0, 221, 144, 60, 0, 222, 0, + 221, 141, 0, 0, 0, 223, 225, 230, 0, 224, + 226, 230, 0, 221, 54, 0, 228, 0, 227, 0, + 0, 60, 0, 60, 231, 0, 232, 0, 231, 55, + 232, 0, 233, 0, 234, 233, 0, 269, 0, 31, + 88, 153, 102, 0, 31, 88, 186, 102, 0, 36, + 0, 5, 0, 234, 36, 0, 234, 5, 0, 54, + 0, 0, 237, 0, 236, 36, 60, 237, 0, 236, + 36, 60, 0, 238, 0, 237, 238, 0, 237, 56, + 0, 239, 56, 0, 239, 103, 0, 132, 60, 0, + 132, 54, 0, 187, 240, 0, 190, 241, 0, 259, + 332, 198, 207, 0, 60, 169, 0, 1, 0, 187, + 88, 323, 102, 251, 0, 187, 44, 251, 0, 0, + 242, 0, 240, 55, 243, 0, 0, 245, 0, 241, + 55, 247, 0, 244, 0, 245, 0, 246, 0, 247, + 0, 255, 332, 198, 207, 0, 255, 332, 198, 207, + 58, 214, 0, 4, 60, 169, 207, 0, 259, 332, + 198, 207, 0, 259, 332, 198, 207, 58, 214, 0, + 3, 60, 169, 207, 0, 60, 169, 207, 0, 255, 332, 198, 207, 0, 255, 332, 198, 207, 58, 214, 0, 4, 60, 169, 207, 0, 259, 332, 198, 207, 0, 259, 332, 198, 207, 58, 214, 0, 3, 60, - 169, 207, 0, 60, 169, 207, 0, 255, 332, 198, - 207, 0, 255, 332, 198, 207, 58, 214, 0, 4, - 60, 169, 207, 0, 259, 332, 198, 207, 0, 259, - 332, 198, 207, 58, 214, 0, 3, 60, 169, 207, - 0, 60, 169, 207, 0, 249, 0, 248, 55, 249, - 0, 139, 0, 139, 58, 169, 0, 312, 273, 0, - 312, 0, 88, 186, 102, 89, 153, 105, 0, 0, - 251, 7, 0, 7, 0, 252, 7, 0, 0, 254, - 153, 0, 75, 252, 255, 0, 65, 252, 255, 0, - 75, 255, 0, 65, 255, 0, 271, 251, 255, 0, - 258, 0, 266, 0, 257, 0, 267, 266, 0, 258, - 88, 161, 102, 251, 0, 258, 88, 323, 102, 251, - 0, 258, 44, 251, 0, 258, 88, 1, 102, 251, - 0, 258, 89, 253, 105, 0, 258, 89, 105, 0, - 88, 255, 102, 0, 267, 266, 0, 266, 0, 75, - 252, 259, 0, 65, 252, 259, 0, 75, 259, 0, - 65, 259, 0, 271, 251, 259, 0, 173, 0, 75, - 252, 259, 0, 65, 252, 259, 0, 75, 260, 0, - 65, 260, 0, 271, 251, 259, 0, 261, 0, 173, - 88, 161, 102, 251, 0, 173, 88, 323, 102, 251, - 0, 173, 44, 251, 0, 173, 88, 1, 102, 251, - 0, 88, 260, 102, 0, 173, 89, 253, 105, 0, - 173, 89, 105, 0, 267, 171, 0, 267, 170, 0, - 263, 0, 272, 263, 0, 193, 88, 161, 102, 0, - 193, 88, 172, 102, 0, 193, 185, 0, 4, 0, - 143, 0, 268, 0, 267, 268, 0, 4, 51, 0, - 143, 51, 0, 256, 0, 272, 256, 0, 257, 0, - 272, 256, 0, 267, 75, 0, 272, 267, 75, 0, - 51, 0, 75, 251, 273, 0, 75, 251, 0, 65, - 251, 273, 0, 65, 251, 0, 271, 251, 0, 271, - 251, 273, 0, 274, 0, 89, 153, 105, 0, 274, - 89, 253, 105, 0, 75, 252, 275, 0, 75, 275, - 0, 75, 252, 0, 75, 0, 65, 252, 275, 0, - 65, 275, 0, 65, 252, 0, 65, 0, 271, 251, - 0, 271, 251, 275, 0, 276, 0, 88, 275, 102, - 0, 85, 0, 276, 88, 323, 102, 251, 0, 276, - 44, 251, 0, 276, 89, 253, 105, 0, 276, 89, - 105, 0, 88, 324, 102, 251, 0, 166, 251, 0, - 185, 251, 0, 89, 253, 105, 0, 89, 105, 0, - 289, 0, 278, 0, 277, 289, 0, 277, 278, 0, - 1, 56, 0, 0, 0, 281, 0, 282, 0, 281, - 282, 0, 34, 213, 56, 0, 284, 0, 1, 284, - 0, 54, 279, 103, 0, 54, 279, 280, 277, 103, - 0, 54, 279, 280, 277, 1, 103, 0, 54, 279, - 280, 1, 103, 0, 0, 0, 13, 286, 279, 155, - 287, 288, 0, 284, 0, 279, 290, 0, 284, 0, - 290, 0, 183, 0, 153, 56, 0, 0, 285, 14, - 291, 288, 0, 285, 0, 0, 0, 15, 292, 279, - 155, 293, 159, 0, 0, 0, 16, 294, 288, 15, - 295, 154, 56, 0, 0, 0, 0, 315, 296, 279, - 156, 56, 297, 318, 102, 298, 159, 0, 0, 0, - 0, 316, 299, 279, 156, 56, 300, 318, 102, 301, - 159, 0, 0, 18, 279, 88, 157, 102, 302, 288, - 0, 0, 19, 169, 60, 303, 289, 0, 0, 19, - 169, 10, 169, 60, 304, 289, 0, 0, 20, 60, - 305, 289, 0, 21, 56, 0, 22, 56, 0, 23, - 56, 0, 23, 153, 56, 0, 111, 317, 88, 180, - 102, 56, 0, 111, 317, 88, 180, 60, 319, 102, - 56, 0, 111, 317, 88, 180, 60, 319, 60, 319, - 102, 56, 0, 111, 317, 88, 180, 60, 319, 60, - 319, 60, 322, 102, 56, 0, 24, 75, 153, 56, - 0, 24, 139, 56, 0, 314, 289, 0, 314, 103, - 0, 56, 0, 306, 0, 0, 0, 90, 54, 279, - 307, 309, 308, 310, 0, 103, 0, 277, 103, 0, - 1, 103, 0, 0, 0, 310, 91, 311, 313, 284, - 0, 191, 0, 252, 0, 88, 10, 102, 0, 88, - 329, 102, 0, 3, 60, 0, 53, 60, 0, 4, - 60, 0, 17, 88, 56, 0, 17, 88, 153, 56, - 0, 17, 88, 54, 103, 0, 17, 88, 183, 0, - 17, 88, 1, 56, 0, 17, 88, 54, 279, 277, - 103, 0, 17, 88, 54, 279, 1, 103, 0, 0, - 7, 0, 0, 153, 0, 1, 0, 0, 320, 0, - 321, 0, 320, 55, 321, 0, 9, 88, 153, 102, - 0, 9, 0, 322, 55, 9, 0, 0, 324, 0, - 186, 0, 325, 0, 326, 10, 0, 325, 10, 0, - 186, 10, 0, 10, 0, 93, 0, 325, 93, 0, - 186, 93, 0, 325, 60, 0, 186, 60, 0, 327, - 0, 329, 58, 214, 0, 326, 328, 0, 326, 331, - 0, 326, 331, 58, 214, 0, 325, 55, 0, 186, - 55, 0, 188, 184, 0, 191, 184, 0, 193, 184, - 0, 188, 275, 0, 188, 0, 190, 259, 0, 329, - 0, 329, 58, 214, 0, 327, 0, 186, 0, 0, - 0, 259, 0, 0, 92, 88, 334, 102, 0, 186, - 0, 333, 0, 334, 55, 333, 0, 0, 75, 251, - 335, 0, 65, 251, 335, 0, 271, 251, 335, 0, - 41, 0, 336, 75, 0, 336, 76, 0, 336, 77, - 0, 336, 73, 0, 336, 74, 0, 336, 65, 0, - 336, 63, 0, 336, 64, 0, 336, 83, 0, 336, - 55, 0, 336, 68, 0, 336, 69, 0, 336, 70, - 0, 336, 67, 0, 336, 57, 0, 336, 58, 0, - 336, 71, 0, 336, 72, 0, 336, 81, 0, 336, - 82, 0, 336, 62, 0, 336, 61, 0, 336, 104, - 0, 336, 59, 60, 0, 336, 66, 0, 336, 86, - 0, 336, 78, 0, 336, 44, 0, 336, 89, 105, - 0, 336, 38, 0, 336, 37, 0, 336, 38, 89, - 105, 0, 336, 37, 89, 105, 0, 336, 312, 335, - 0, 336, 1, 0 + 169, 207, 0, 60, 169, 207, 0, 249, 0, 248, + 55, 249, 0, 139, 0, 139, 58, 169, 0, 312, + 273, 0, 312, 0, 88, 186, 102, 89, 153, 105, + 0, 0, 251, 7, 0, 7, 0, 252, 7, 0, + 0, 254, 153, 0, 75, 252, 255, 0, 65, 252, + 255, 0, 75, 255, 0, 65, 255, 0, 271, 251, + 255, 0, 258, 0, 266, 0, 257, 0, 267, 266, + 0, 258, 88, 161, 102, 251, 0, 258, 88, 323, + 102, 251, 0, 258, 44, 251, 0, 258, 88, 1, + 102, 251, 0, 258, 89, 253, 105, 0, 258, 89, + 105, 0, 88, 255, 102, 0, 267, 266, 0, 266, + 0, 75, 252, 259, 0, 65, 252, 259, 0, 75, + 259, 0, 65, 259, 0, 271, 251, 259, 0, 173, + 0, 75, 252, 259, 0, 65, 252, 259, 0, 75, + 260, 0, 65, 260, 0, 271, 251, 259, 0, 261, + 0, 173, 88, 161, 102, 251, 0, 173, 88, 323, + 102, 251, 0, 173, 44, 251, 0, 173, 88, 1, + 102, 251, 0, 88, 172, 102, 0, 88, 260, 102, + 0, 173, 89, 253, 105, 0, 173, 89, 105, 0, + 267, 171, 0, 267, 170, 0, 263, 0, 272, 263, + 0, 193, 88, 161, 102, 0, 193, 88, 172, 102, + 0, 193, 185, 0, 4, 0, 143, 0, 268, 0, + 267, 268, 0, 4, 51, 0, 143, 51, 0, 256, + 0, 272, 256, 0, 257, 0, 272, 256, 0, 267, + 75, 0, 272, 267, 75, 0, 51, 0, 75, 251, + 273, 0, 75, 251, 0, 65, 251, 273, 0, 65, + 251, 0, 271, 251, 0, 271, 251, 273, 0, 274, + 0, 89, 153, 105, 0, 274, 89, 253, 105, 0, + 75, 252, 275, 0, 75, 275, 0, 75, 252, 0, + 75, 0, 65, 252, 275, 0, 65, 275, 0, 65, + 252, 0, 65, 0, 271, 251, 0, 271, 251, 275, + 0, 276, 0, 88, 275, 102, 0, 85, 0, 276, + 88, 323, 102, 251, 0, 276, 44, 251, 0, 276, + 89, 253, 105, 0, 276, 89, 105, 0, 88, 324, + 102, 251, 0, 166, 251, 0, 185, 251, 0, 89, + 253, 105, 0, 89, 105, 0, 289, 0, 278, 0, + 277, 289, 0, 277, 278, 0, 1, 56, 0, 0, + 0, 281, 0, 282, 0, 281, 282, 0, 34, 213, + 56, 0, 284, 0, 1, 284, 0, 54, 279, 103, + 0, 54, 279, 280, 277, 103, 0, 54, 279, 280, + 277, 1, 103, 0, 54, 279, 280, 1, 103, 0, + 0, 0, 13, 286, 279, 155, 287, 288, 0, 284, + 0, 279, 290, 0, 284, 0, 290, 0, 183, 0, + 153, 56, 0, 0, 285, 14, 291, 288, 0, 285, + 0, 0, 0, 15, 292, 279, 155, 293, 159, 0, + 0, 0, 16, 294, 288, 15, 295, 154, 56, 0, + 0, 0, 0, 315, 296, 279, 156, 56, 297, 318, + 102, 298, 159, 0, 0, 0, 0, 316, 299, 279, + 156, 56, 300, 318, 102, 301, 159, 0, 0, 18, + 279, 88, 157, 102, 302, 288, 0, 0, 19, 169, + 60, 303, 289, 0, 0, 19, 169, 10, 169, 60, + 304, 289, 0, 0, 20, 60, 305, 289, 0, 21, + 56, 0, 22, 56, 0, 23, 56, 0, 23, 153, + 56, 0, 111, 317, 88, 180, 102, 56, 0, 111, + 317, 88, 180, 60, 319, 102, 56, 0, 111, 317, + 88, 180, 60, 319, 60, 319, 102, 56, 0, 111, + 317, 88, 180, 60, 319, 60, 319, 60, 322, 102, + 56, 0, 24, 75, 153, 56, 0, 24, 139, 56, + 0, 314, 289, 0, 314, 103, 0, 56, 0, 306, + 0, 0, 0, 90, 54, 279, 307, 309, 308, 310, + 0, 103, 0, 277, 103, 0, 1, 103, 0, 0, + 0, 310, 91, 311, 313, 284, 0, 191, 0, 252, + 0, 88, 10, 102, 0, 88, 329, 102, 0, 3, + 60, 0, 53, 60, 0, 4, 60, 0, 17, 88, + 56, 0, 17, 88, 153, 56, 0, 17, 88, 54, + 103, 0, 17, 88, 183, 0, 17, 88, 1, 56, + 0, 17, 88, 54, 279, 277, 103, 0, 17, 88, + 54, 279, 1, 103, 0, 0, 7, 0, 0, 153, + 0, 1, 0, 0, 320, 0, 321, 0, 320, 55, + 321, 0, 9, 88, 153, 102, 0, 9, 0, 322, + 55, 9, 0, 0, 324, 0, 186, 0, 325, 0, + 326, 10, 0, 325, 10, 0, 186, 10, 0, 10, + 0, 93, 0, 325, 93, 0, 186, 93, 0, 325, + 60, 0, 186, 60, 0, 327, 0, 329, 58, 214, + 0, 326, 328, 0, 326, 331, 0, 326, 331, 58, + 214, 0, 325, 55, 0, 186, 55, 0, 188, 184, + 0, 191, 184, 0, 193, 184, 0, 188, 275, 0, + 188, 0, 190, 259, 0, 329, 0, 329, 58, 214, + 0, 327, 0, 186, 0, 0, 0, 259, 0, 0, + 92, 88, 334, 102, 0, 186, 0, 333, 0, 334, + 55, 333, 0, 0, 75, 251, 335, 0, 65, 251, + 335, 0, 271, 251, 335, 0, 41, 0, 336, 75, + 0, 336, 76, 0, 336, 77, 0, 336, 73, 0, + 336, 74, 0, 336, 65, 0, 336, 63, 0, 336, + 64, 0, 336, 83, 0, 336, 55, 0, 336, 68, + 0, 336, 69, 0, 336, 70, 0, 336, 67, 0, + 336, 57, 0, 336, 58, 0, 336, 71, 0, 336, + 72, 0, 336, 81, 0, 336, 82, 0, 336, 62, + 0, 336, 61, 0, 336, 104, 0, 336, 59, 60, + 0, 336, 66, 0, 336, 86, 0, 336, 78, 0, + 336, 44, 0, 336, 89, 105, 0, 336, 38, 0, + 336, 37, 0, 336, 38, 89, 105, 0, 336, 37, + 89, 105, 0, 336, 312, 335, 0, 336, 1, 0 }; #endif @@ -590,59 +589,59 @@ 1144, 1146, 1163, 1166, 1168, 1170, 1172, 1174, 1176, 1178, 1180, 1182, 1184, 1186, 1188, 1190, 1192, 1194, 1196, 1198, 1200, 1202, 1204, 1206, 1208, 1215, 1217, 1234, 1237, 1238, - 1239, 1242, 1244, 1247, 1249, 1250, 1252, 1254, 1258, 1260, - 1261, 1264, 1268, 1288, 1289, 1290, 1292, 1294, 1296, 1304, - 1325, 1330, 1337, 1344, 1346, 1355, 1360, 1383, 1427, 1428, - 1431, 1434, 1437, 1440, 1442, 1445, 1484, 1491, 1493, 1495, - 1497, 1499, 1501, 1516, 1531, 1542, 1554, 1561, 1610, 1612, - 1616, 1618, 1622, 1625, 1630, 1632, 1636, 1649, 1650, 1656, - 1667, 1675, 1681, 1686, 1688, 1693, 1700, 1702, 1706, 1710, - 1716, 1719, 1721, 1723, 1725, 1733, 1735, 1737, 1740, 1742, - 1744, 1746, 1751, 1757, 1759, 1770, 1773, 1775, 1778, 1793, - 1796, 1798, 1800, 1804, 1807, 1815, 1816, 1817, 1818, 1822, - 1826, 1840, 1858, 1859, 1860, 1863, 1865, 1868, 1870, 1873, - 1875, 1878, 1881, 1885, 1902, 1904, 1922, 1928, 1929, 1935, - 1943, 1945, 1954, 1962, 1964, 1975, 1978, 1982, 1985, 1989, - 1994, 1997, 2001, 2004, 2006, 2008, 2010, 2017, 2019, 2020, - 2021, 2025, 2028, 2032, 2034, 2037, 2040, 2043, 2049, 2052, - 2055, 2057, 2059, 2061, 2065, 2069, 2073, 2076, 2079, 2083, - 2086, 2088, 2092, 2143, 2158, 2160, 2163, 2165, 2169, 2170, - 2172, 2174, 2176, 2180, 2189, 2192, 2194, 2196, 2202, 2204, - 2207, 2212, 2215, 2218, 2227, 2238, 2243, 2243, 2245, 2248, - 2250, 2254, 2256, 2260, 2288, 2319, 2321, 2343, 2367, 2369, - 2373, 2399, 2408, 2470, 2473, 2480, 2491, 2500, 2504, 2517, - 2520, 2522, 2527, 2529, 2533, 2541, 2545, 2548, 2550, 2561, - 2566, 2574, 2577, 2578, 2589, 2592, 2593, 2604, 2606, 2609, - 2611, 2614, 2619, 2623, 2629, 2634, 2638, 2642, 2648, 2652, - 2655, 2660, 2664, 2667, 2670, 2679, 2681, 2685, 2688, 2693, - 2696, 2700, 2709, 2712, 2716, 2719, 2727, 2729, 2734, 2737, - 2739, 2741, 2743, 2747, 2750, 2764, 2767, 2772, 2775, 2777, - 2779, 2781, 2783, 2785, 2787, 2791, 2797, 2800, 2802, 2804, - 2806, 2810, 2813, 2816, 2818, 2820, 2822, 2826, 2829, 2832, - 2834, 2836, 2838, 2840, 2842, 2846, 2852, 2858, 2860, 2864, - 2867, 2869, 2873, 2875, 2878, 2880, 2886, 2889, 2903, 2905, - 2909, 2911, 2915, 2918, 2924, 2930, 2933, 2935, 2937, 2939, - 2943, 2947, 2951, 2954, 2959, 2962, 2964, 2966, 2968, 2970, - 2972, 2974, 2976, 2980, 2984, 2988, 2992, 2993, 2995, 2997, - 2999, 3001, 3003, 3005, 3007, 3009, 3017, 3019, 3020, 3021, - 3024, 3031, 3041, 3043, 3048, 3050, 3053, 3067, 3070, 3073, - 3077, 3081, 3085, 3091, 3094, 3098, 3100, 3103, 3109, 3112, - 3115, 3118, 3131, 3134, 3139, 3145, 3150, 3153, 3158, 3162, - 3165, 3171, 3176, 3179, 3184, 3193, 3197, 3200, 3206, 3216, - 3223, 3229, 3254, 3254, 3286, 3286, 3302, 3302, 3306, 3310, - 3313, 3318, 3325, 3334, 3343, 3352, 3355, 3361, 3363, 3367, - 3369, 3372, 3376, 3379, 3382, 3390, 3394, 3400, 3402, 3404, - 3408, 3410, 3413, 3426, 3431, 3439, 3441, 3445, 3448, 3450, - 3454, 3457, 3459, 3461, 3467, 3471, 3475, 3478, 3479, 3485, - 3487, 3490, 3492, 3496, 3501, 3504, 3514, 3521, 3522, 3529, - 3535, 3540, 3544, 3549, 3556, 3560, 3564, 3569, 3580, 3594, - 3597, 3599, 3601, 3603, 3607, 3609, 3617, 3634, 3636, 3638, - 3640, 3642, 3646, 3649, 3653, 3655, 3658, 3680, 3686, 3693, - 3696, 3700, 3705, 3707, 3714, 3717, 3719, 3721, 3727, 3731, + 1239, 1242, 1244, 1247, 1249, 1250, 1252, 1256, 1258, 1259, + 1264, 1284, 1285, 1286, 1288, 1290, 1292, 1300, 1321, 1326, + 1333, 1340, 1342, 1351, 1356, 1379, 1423, 1424, 1427, 1430, + 1433, 1436, 1438, 1441, 1480, 1487, 1489, 1491, 1493, 1495, + 1497, 1512, 1527, 1538, 1550, 1557, 1606, 1608, 1612, 1614, + 1618, 1621, 1626, 1628, 1632, 1645, 1646, 1652, 1663, 1671, + 1677, 1682, 1684, 1689, 1696, 1698, 1702, 1706, 1712, 1715, + 1717, 1719, 1721, 1729, 1731, 1733, 1736, 1738, 1740, 1742, + 1747, 1753, 1755, 1766, 1769, 1771, 1774, 1789, 1792, 1794, + 1796, 1800, 1803, 1811, 1812, 1813, 1814, 1818, 1822, 1836, + 1854, 1855, 1856, 1859, 1861, 1864, 1866, 1869, 1871, 1874, + 1877, 1881, 1898, 1900, 1918, 1924, 1925, 1931, 1939, 1941, + 1950, 1958, 1960, 1971, 1974, 1978, 1981, 1985, 1990, 1993, + 1997, 2000, 2002, 2004, 2006, 2013, 2015, 2016, 2017, 2021, + 2024, 2028, 2030, 2033, 2036, 2039, 2045, 2048, 2051, 2053, + 2055, 2057, 2061, 2065, 2069, 2072, 2075, 2079, 2082, 2084, + 2088, 2139, 2154, 2156, 2159, 2161, 2165, 2166, 2168, 2170, + 2172, 2176, 2185, 2188, 2190, 2192, 2198, 2200, 2203, 2208, + 2211, 2214, 2223, 2234, 2239, 2239, 2241, 2244, 2246, 2250, + 2252, 2256, 2284, 2315, 2317, 2339, 2363, 2365, 2369, 2395, + 2404, 2466, 2469, 2476, 2487, 2496, 2500, 2513, 2516, 2518, + 2523, 2525, 2529, 2537, 2541, 2544, 2546, 2557, 2562, 2570, + 2573, 2574, 2585, 2588, 2589, 2600, 2602, 2605, 2607, 2610, + 2615, 2619, 2625, 2630, 2634, 2638, 2644, 2648, 2651, 2656, + 2660, 2663, 2666, 2675, 2677, 2681, 2684, 2689, 2692, 2696, + 2705, 2708, 2712, 2715, 2723, 2725, 2730, 2733, 2735, 2737, + 2739, 2743, 2746, 2760, 2763, 2768, 2771, 2773, 2775, 2777, + 2779, 2781, 2783, 2787, 2793, 2796, 2798, 2800, 2802, 2806, + 2809, 2812, 2814, 2816, 2818, 2822, 2825, 2828, 2830, 2832, + 2834, 2836, 2838, 2840, 2844, 2850, 2856, 2858, 2862, 2865, + 2867, 2871, 2873, 2876, 2878, 2884, 2887, 2901, 2903, 2907, + 2909, 2913, 2916, 2922, 2928, 2931, 2933, 2935, 2937, 2941, + 2945, 2949, 2952, 2957, 2960, 2962, 2964, 2966, 2968, 2970, + 2972, 2974, 2978, 2982, 2986, 2990, 2991, 2993, 2995, 2997, + 2999, 3001, 3003, 3005, 3007, 3015, 3017, 3018, 3019, 3022, + 3029, 3039, 3041, 3046, 3048, 3051, 3065, 3068, 3071, 3075, + 3079, 3083, 3089, 3092, 3096, 3098, 3101, 3107, 3110, 3113, + 3116, 3129, 3132, 3137, 3143, 3148, 3151, 3156, 3160, 3163, + 3169, 3174, 3177, 3182, 3191, 3195, 3198, 3204, 3214, 3221, + 3227, 3252, 3252, 3284, 3284, 3300, 3300, 3304, 3308, 3311, + 3316, 3323, 3332, 3341, 3350, 3353, 3359, 3361, 3365, 3367, + 3370, 3374, 3377, 3380, 3388, 3392, 3398, 3400, 3402, 3406, + 3408, 3411, 3424, 3429, 3437, 3439, 3443, 3446, 3448, 3452, + 3455, 3457, 3459, 3465, 3469, 3473, 3476, 3477, 3483, 3485, + 3488, 3490, 3494, 3499, 3502, 3512, 3519, 3520, 3527, 3533, + 3538, 3542, 3547, 3554, 3558, 3562, 3567, 3578, 3592, 3595, + 3597, 3599, 3601, 3605, 3607, 3615, 3632, 3634, 3636, 3638, + 3640, 3644, 3647, 3651, 3653, 3656, 3678, 3684, 3691, 3694, + 3698, 3703, 3705, 3712, 3715, 3717, 3719, 3725, 3729, 3732, 3734, 3736, 3738, 3740, 3742, 3744, 3746, 3748, 3750, 3752, 3754, 3756, 3758, 3760, 3762, 3764, 3766, 3768, 3770, 3772, 3774, 3776, 3778, 3780, 3782, 3784, 3786, 3788, 3790, 3792, - 3794, 3796, 3799, 3801 + 3794, 3797, 3799 }; static const char * const yytname[] = { "$","error","$illegal.","IDENTIFIER", @@ -727,59 +726,59 @@ 168, 168, 169, 169, 169, 169, 169, 169, 169, 169, 169, 169, 169, 169, 169, 169, 169, 169, 169, 169, 169, 169, 169, 169, 169, 169, 169, 170, 170, 170, - 170, 171, 171, 172, 172, 172, 172, 172, 173, 173, - 173, 173, 174, 174, 174, 174, 174, 174, 175, 174, - 176, 174, 174, 174, 174, 174, 174, 174, 174, 174, + 170, 171, 171, 172, 172, 172, 172, 173, 173, 173, + 174, 174, 174, 174, 174, 174, 175, 174, 176, 174, 174, 174, 174, 174, 174, 174, 174, 174, 174, 174, - 174, 174, 174, 174, 174, 174, 174, 174, 177, 177, - 178, 178, 179, 179, 180, 180, 181, 182, 182, 183, - 183, 183, 183, 183, 183, 183, 184, 184, 185, 185, - 186, 186, 186, 186, 186, 187, 187, 188, 188, 188, - 188, 188, 189, 189, 189, 190, 190, 190, 190, 191, - 191, 191, 191, 192, 192, 193, 193, 193, 193, 193, - 193, 193, 194, 194, 194, 195, 195, 196, 196, 197, - 197, 198, 198, 200, 199, 199, 202, 201, 201, 204, - 203, 203, 206, 205, 205, 207, 207, 208, 208, 209, - 210, 210, 211, 211, 211, 211, 211, 212, 212, 212, - 212, 213, 213, 214, 214, 214, 214, 214, 215, 215, - 215, 215, 215, 215, 217, 216, 216, 218, 216, 216, - 216, 216, 216, 216, 219, 219, 220, 220, 221, 221, - 221, 221, 221, 222, 223, 223, 223, 223, 223, 223, - 224, 225, 226, 227, 227, 228, 229, 229, 230, 230, - 230, 231, 231, 232, 232, 233, 233, 233, 234, 234, - 234, 234, 235, 236, 236, 236, 236, 237, 237, 237, - 238, 238, 238, 238, 239, 239, 239, 239, 239, 239, - 239, 240, 240, 240, 241, 241, 241, 242, 242, 243, - 243, 244, 244, 244, 245, 245, 245, 245, 246, 246, - 246, 247, 247, 247, 247, 248, 248, 249, 249, 250, - 250, 250, 251, 251, 252, 252, 254, 253, 255, 255, - 255, 255, 255, 255, 256, 256, 257, 258, 258, 258, - 258, 258, 258, 258, 258, 258, 259, 259, 259, 259, - 259, 259, 260, 260, 260, 260, 260, 260, 261, 261, - 261, 261, 261, 261, 261, 262, 263, 264, 264, 265, - 265, 265, 266, 266, 267, 267, 268, 268, 269, 269, - 270, 270, 271, 271, 272, 273, 273, 273, 273, 273, - 273, 273, 274, 274, 275, 275, 275, 275, 275, 275, - 275, 275, 275, 275, 275, 276, 276, 276, 276, 276, - 276, 276, 276, 276, 276, 276, 277, 277, 277, 277, - 278, 279, 280, 280, 281, 281, 282, 283, 283, 284, - 284, 284, 284, 286, 287, 285, 288, 288, 289, 289, - 290, 290, 291, 290, 290, 292, 293, 290, 294, 295, - 290, 296, 297, 298, 290, 299, 300, 301, 290, 302, - 290, 303, 290, 304, 290, 305, 290, 290, 290, 290, + 174, 174, 174, 174, 174, 174, 174, 174, 174, 174, + 174, 174, 174, 174, 174, 174, 177, 177, 178, 178, + 179, 179, 180, 180, 181, 182, 182, 183, 183, 183, + 183, 183, 183, 183, 184, 184, 185, 185, 186, 186, + 186, 186, 186, 187, 187, 188, 188, 188, 188, 188, + 189, 189, 189, 190, 190, 190, 190, 191, 191, 191, + 191, 192, 192, 193, 193, 193, 193, 193, 193, 193, + 194, 194, 194, 195, 195, 196, 196, 197, 197, 198, + 198, 200, 199, 199, 202, 201, 201, 204, 203, 203, + 206, 205, 205, 207, 207, 208, 208, 209, 210, 210, + 211, 211, 211, 211, 211, 212, 212, 212, 212, 213, + 213, 214, 214, 214, 214, 214, 215, 215, 215, 215, + 215, 215, 217, 216, 216, 218, 216, 216, 216, 216, + 216, 216, 219, 219, 220, 220, 221, 221, 221, 221, + 221, 222, 223, 223, 223, 223, 223, 223, 224, 225, + 226, 227, 227, 228, 229, 229, 230, 230, 230, 231, + 231, 232, 232, 233, 233, 233, 234, 234, 234, 234, + 235, 236, 236, 236, 236, 237, 237, 237, 238, 238, + 238, 238, 239, 239, 239, 239, 239, 239, 239, 240, + 240, 240, 241, 241, 241, 242, 242, 243, 243, 244, + 244, 244, 245, 245, 245, 245, 246, 246, 246, 247, + 247, 247, 247, 248, 248, 249, 249, 250, 250, 250, + 251, 251, 252, 252, 254, 253, 255, 255, 255, 255, + 255, 255, 256, 256, 257, 258, 258, 258, 258, 258, + 258, 258, 258, 258, 259, 259, 259, 259, 259, 259, + 260, 260, 260, 260, 260, 260, 261, 261, 261, 261, + 261, 261, 261, 261, 262, 263, 264, 264, 265, 265, + 265, 266, 266, 267, 267, 268, 268, 269, 269, 270, + 270, 271, 271, 272, 273, 273, 273, 273, 273, 273, + 273, 274, 274, 275, 275, 275, 275, 275, 275, 275, + 275, 275, 275, 275, 276, 276, 276, 276, 276, 276, + 276, 276, 276, 276, 276, 277, 277, 277, 277, 278, + 279, 280, 280, 281, 281, 282, 283, 283, 284, 284, + 284, 284, 286, 287, 285, 288, 288, 289, 289, 290, + 290, 291, 290, 290, 292, 293, 290, 294, 295, 290, + 296, 297, 298, 290, 299, 300, 301, 290, 302, 290, + 303, 290, 304, 290, 305, 290, 290, 290, 290, 290, 290, 290, 290, 290, 290, 290, 290, 290, 290, 290, - 290, 307, 308, 306, 309, 309, 309, 310, 311, 310, - 312, 312, 313, 313, 314, 314, 314, 315, 315, 315, - 316, 316, 316, 316, 317, 317, 318, 318, 318, 319, - 319, 320, 320, 321, 322, 322, 323, 323, 323, 324, - 324, 324, 324, 324, 324, 324, 324, 324, 324, 325, - 325, 325, 325, 325, 326, 326, 327, 327, 327, 327, - 327, 327, 328, 328, 329, 329, 330, 331, 331, 332, - 332, 333, 334, 334, 335, 335, 335, 335, 336, 337, + 307, 308, 306, 309, 309, 309, 310, 311, 310, 312, + 312, 313, 313, 314, 314, 314, 315, 315, 315, 316, + 316, 316, 316, 317, 317, 318, 318, 318, 319, 319, + 320, 320, 321, 322, 322, 323, 323, 323, 324, 324, + 324, 324, 324, 324, 324, 324, 324, 324, 325, 325, + 325, 325, 325, 326, 326, 327, 327, 327, 327, 327, + 327, 328, 328, 329, 329, 330, 331, 331, 332, 332, + 333, 334, 334, 335, 335, 335, 335, 336, 337, 337, 337, 337, 337, 337, 337, 337, 337, 337, 337, 337, 337, 337, 337, 337, 337, 337, 337, 337, 337, 337, 337, 337, 337, 337, 337, 337, 337, 337, 337, 337, - 337, 337, 337, 337 + 337, 337, 337 }; static const short yyr2[] = { 0, @@ -805,2029 +804,2024 @@ 4, 4, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 5, 3, 3, 1, 2, 3, 1, 1, - 1, 1, 1, 1, 1, 2, 2, 3, 1, 1, - 1, 3, 1, 1, 1, 1, 3, 3, 0, 4, - 0, 6, 2, 4, 2, 2, 1, 4, 1, 7, - 7, 7, 7, 4, 4, 2, 2, 1, 4, 2, - 2, 2, 5, 3, 5, 3, 4, 6, 1, 2, - 1, 2, 1, 1, 1, 2, 0, 2, 2, 3, - 3, 3, 3, 3, 2, 2, 1, 1, 1, 2, - 2, 2, 2, 1, 1, 1, 1, 2, 2, 3, - 3, 4, 1, 2, 2, 1, 1, 2, 2, 1, - 2, 2, 3, 1, 2, 1, 1, 1, 4, 4, - 4, 4, 1, 1, 1, 1, 3, 1, 3, 1, - 3, 0, 4, 0, 7, 4, 0, 7, 4, 0, - 7, 4, 0, 7, 4, 0, 1, 1, 2, 6, - 1, 3, 0, 1, 4, 6, 4, 1, 1, 1, - 1, 1, 3, 1, 2, 3, 4, 1, 1, 3, - 4, 6, 3, 5, 0, 7, 4, 0, 6, 3, - 2, 2, 4, 1, 0, 1, 0, 1, 1, 2, - 2, 2, 2, 3, 2, 2, 2, 3, 3, 1, - 2, 0, 0, 3, 3, 2, 1, 1, 0, 1, - 2, 1, 3, 1, 2, 1, 4, 4, 1, 1, - 2, 2, 1, 0, 1, 4, 3, 1, 2, 2, - 2, 2, 2, 2, 2, 2, 4, 2, 1, 5, - 3, 0, 1, 3, 0, 1, 3, 1, 1, 1, - 1, 4, 6, 4, 4, 6, 4, 3, 4, 6, - 4, 4, 6, 4, 3, 1, 3, 1, 3, 2, - 1, 6, 0, 2, 1, 2, 0, 2, 3, 3, - 2, 2, 3, 1, 1, 1, 2, 5, 5, 3, - 5, 4, 3, 3, 2, 1, 3, 3, 2, 2, - 3, 1, 3, 3, 2, 2, 3, 1, 5, 5, - 3, 5, 3, 4, 3, 2, 2, 1, 2, 4, - 4, 2, 1, 1, 1, 2, 2, 2, 1, 2, - 1, 2, 2, 3, 1, 3, 2, 3, 2, 2, - 3, 1, 3, 4, 3, 2, 2, 1, 3, 2, - 2, 1, 2, 3, 1, 3, 1, 5, 3, 4, - 3, 4, 2, 2, 3, 2, 1, 1, 2, 2, - 2, 0, 0, 1, 1, 2, 3, 1, 2, 3, - 5, 6, 5, 0, 0, 6, 1, 2, 1, 1, - 1, 2, 0, 4, 1, 0, 0, 6, 0, 0, - 7, 0, 0, 0, 10, 0, 0, 0, 10, 0, - 7, 0, 5, 0, 7, 0, 4, 2, 2, 2, - 3, 6, 8, 10, 12, 4, 3, 2, 2, 1, - 1, 0, 0, 7, 1, 2, 2, 0, 0, 5, - 1, 1, 3, 3, 2, 2, 2, 3, 4, 4, - 3, 4, 6, 6, 0, 1, 0, 1, 1, 0, - 1, 1, 3, 4, 1, 3, 0, 1, 1, 1, - 2, 2, 2, 1, 1, 2, 2, 2, 2, 1, - 3, 2, 2, 4, 2, 2, 2, 2, 2, 2, - 1, 2, 1, 3, 1, 1, 0, 0, 1, 0, - 4, 1, 1, 3, 0, 3, 3, 3, 1, 2, + 1, 1, 1, 1, 1, 2, 2, 1, 1, 1, + 1, 1, 1, 1, 3, 3, 0, 4, 0, 6, + 2, 4, 2, 2, 1, 4, 1, 7, 7, 7, + 7, 4, 4, 2, 2, 1, 4, 2, 2, 2, + 5, 3, 5, 3, 4, 6, 1, 2, 1, 2, + 1, 1, 1, 2, 0, 2, 2, 3, 3, 3, + 3, 3, 2, 2, 1, 1, 1, 2, 2, 2, + 2, 1, 1, 1, 1, 2, 2, 3, 3, 4, + 1, 2, 2, 1, 1, 2, 2, 1, 2, 2, + 3, 1, 2, 1, 1, 1, 4, 4, 4, 4, + 1, 1, 1, 1, 3, 1, 3, 1, 3, 0, + 4, 0, 7, 4, 0, 7, 4, 0, 7, 4, + 0, 7, 4, 0, 1, 1, 2, 6, 1, 3, + 0, 1, 4, 6, 4, 1, 1, 1, 1, 1, + 3, 1, 2, 3, 4, 1, 1, 3, 4, 6, + 3, 5, 0, 7, 4, 0, 6, 3, 2, 2, + 4, 1, 0, 1, 0, 1, 1, 2, 2, 2, + 2, 3, 2, 2, 2, 3, 3, 1, 2, 0, + 0, 3, 3, 2, 1, 1, 0, 1, 2, 1, + 3, 1, 2, 1, 4, 4, 1, 1, 2, 2, + 1, 0, 1, 4, 3, 1, 2, 2, 2, 2, + 2, 2, 2, 2, 4, 2, 1, 5, 3, 0, + 1, 3, 0, 1, 3, 1, 1, 1, 1, 4, + 6, 4, 4, 6, 4, 3, 4, 6, 4, 4, + 6, 4, 3, 1, 3, 1, 3, 2, 1, 6, + 0, 2, 1, 2, 0, 2, 3, 3, 2, 2, + 3, 1, 1, 1, 2, 5, 5, 3, 5, 4, + 3, 3, 2, 1, 3, 3, 2, 2, 3, 1, + 3, 3, 2, 2, 3, 1, 5, 5, 3, 5, + 3, 3, 4, 3, 2, 2, 1, 2, 4, 4, + 2, 1, 1, 1, 2, 2, 2, 1, 2, 1, + 2, 2, 3, 1, 3, 2, 3, 2, 2, 3, + 1, 3, 4, 3, 2, 2, 1, 3, 2, 2, + 1, 2, 3, 1, 3, 1, 5, 3, 4, 3, + 4, 2, 2, 3, 2, 1, 1, 2, 2, 2, + 0, 0, 1, 1, 2, 3, 1, 2, 3, 5, + 6, 5, 0, 0, 6, 1, 2, 1, 1, 1, + 2, 0, 4, 1, 0, 0, 6, 0, 0, 7, + 0, 0, 0, 10, 0, 0, 0, 10, 0, 7, + 0, 5, 0, 7, 0, 4, 2, 2, 2, 3, + 6, 8, 10, 12, 4, 3, 2, 2, 1, 1, + 0, 0, 7, 1, 2, 2, 0, 0, 5, 1, + 1, 3, 3, 2, 2, 2, 3, 4, 4, 3, + 4, 6, 6, 0, 1, 0, 1, 1, 0, 1, + 1, 3, 4, 1, 3, 0, 1, 1, 1, 2, + 2, 2, 1, 1, 2, 2, 2, 2, 1, 3, + 2, 2, 4, 2, 2, 2, 2, 2, 2, 1, + 2, 1, 3, 1, 1, 0, 0, 1, 0, 4, + 1, 1, 3, 0, 3, 3, 3, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, - 2, 2, 3, 2, 2, 2, 2, 3, 2, 2, - 4, 4, 3, 2 + 2, 3, 2, 2, 2, 2, 3, 2, 2, 4, + 4, 3, 2 }; static const short yydefact[] = { 3, - 10, 10, 5, 0, 4, 0, 220, 523, 307, 317, - 475, 0, 8, 9, 0, 0, 389, 0, 709, 0, - 535, 221, 64, 0, 0, 697, 0, 76, 21, 0, - 11, 6, 0, 15, 14, 13, 12, 277, 0, 524, - 117, 230, 502, 0, 297, 0, 296, 310, 0, 330, - 316, 0, 400, 402, 403, 408, 407, 384, 306, 529, - 486, 0, 229, 231, 485, 0, 525, 318, 473, 0, - 0, 219, 62, 63, 527, 0, 0, 101, 102, 103, - 378, 381, 0, 531, 0, 382, 0, 0, 0, 32, - 0, 307, 0, 22, 0, 0, 400, 0, 0, 0, - 0, 500, 0, 0, 0, 499, 0, 0, 0, 0, - 230, 0, 0, 0, 229, 231, 473, 0, 3, 0, - 0, 0, 0, 402, 403, 700, 0, 88, 83, 277, - 0, 0, 60, 528, 124, 473, 0, 477, 61, 0, - 0, 0, 0, 0, 326, 287, 484, 288, 496, 0, - 473, 309, 308, 59, 298, 0, 328, 0, 303, 323, - 324, 299, 312, 314, 325, 0, 54, 390, 391, 392, - 393, 406, 107, 106, 108, 395, 401, 397, 117, 396, - 409, 409, 423, 0, 476, 311, 72, 0, 75, 533, - 517, 487, 526, 0, 530, 0, 744, 740, 739, 737, - 719, 724, 725, 0, 731, 730, 716, 717, 715, 734, - 723, 720, 721, 722, 726, 727, 713, 714, 710, 711, - 712, 736, 728, 729, 718, 735, 0, 732, 641, 310, - 642, 705, 475, 234, 275, 0, 0, 0, 0, 156, - 271, 269, 247, 273, 274, 0, 0, 0, 0, 0, - 0, 0, 129, 128, 0, 130, 131, 0, 0, 216, - 132, 0, 118, 0, 189, 0, 193, 186, 121, 233, - 155, 0, 0, 235, 236, 0, 120, 294, 310, 295, - 518, 258, 249, 0, 0, 0, 400, 380, 0, 375, - 532, 0, 133, 134, 0, 0, 0, 0, 31, 0, - 110, 409, 125, 109, 115, 0, 498, 0, 497, 102, - 103, 218, 227, 0, 506, 226, 0, 505, 0, 232, - 513, 0, 0, 18, 10, 0, 7, 7, 48, 47, - 700, 0, 34, 42, 38, 36, 43, 40, 332, 82, - 89, 86, 0, 0, 277, 0, 0, 0, 572, 65, - 578, 67, 113, 511, 0, 674, 675, 154, 0, 153, - 669, 691, 0, 294, 310, 295, 0, 668, 670, 698, - 680, 0, 515, 0, 0, 0, 482, 0, 481, 0, - 0, 0, 0, 473, 70, 58, 73, 0, 57, 473, - 0, 477, 495, 0, 300, 301, 0, 55, 71, 56, - 74, 305, 304, 315, 700, 331, 398, 394, 399, 410, - 404, 405, 439, 0, 0, 442, 445, 0, 0, 428, - 0, 700, 313, 0, 0, 346, 474, 501, 534, 0, - 0, 733, 738, 473, 473, 0, 473, 743, 0, 0, - 0, 163, 0, 0, 165, 0, 0, 0, 0, 0, - 0, 0, 0, 162, 159, 158, 160, 0, 0, 0, - 0, 217, 0, 116, 161, 0, 0, 187, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 10, 10, 5, 0, 4, 0, 220, 522, 305, 315, + 473, 0, 8, 9, 0, 0, 387, 0, 708, 0, + 534, 221, 64, 0, 0, 696, 0, 76, 21, 0, + 11, 6, 0, 15, 14, 13, 12, 275, 0, 523, + 117, 229, 500, 0, 295, 0, 294, 308, 0, 328, + 314, 0, 398, 400, 401, 406, 405, 382, 304, 528, + 484, 0, 228, 230, 483, 0, 524, 316, 471, 0, + 0, 219, 62, 63, 526, 0, 0, 101, 102, 103, + 376, 379, 0, 530, 0, 380, 0, 0, 0, 32, + 0, 305, 0, 22, 0, 0, 398, 0, 0, 0, + 0, 498, 0, 0, 0, 497, 0, 0, 0, 229, + 0, 0, 0, 228, 230, 471, 0, 3, 0, 0, + 0, 0, 400, 401, 699, 0, 88, 83, 275, 0, + 0, 60, 527, 124, 471, 0, 475, 61, 0, 0, + 0, 0, 0, 324, 285, 482, 286, 494, 0, 471, + 307, 306, 59, 296, 0, 326, 0, 301, 321, 322, + 297, 310, 312, 323, 0, 54, 388, 389, 390, 391, + 404, 107, 106, 108, 393, 399, 395, 117, 394, 407, + 407, 421, 0, 474, 309, 72, 0, 75, 532, 516, + 485, 525, 0, 529, 0, 743, 739, 738, 736, 718, + 723, 724, 0, 730, 729, 715, 716, 714, 733, 722, + 719, 720, 721, 725, 726, 712, 713, 709, 710, 711, + 735, 727, 728, 717, 734, 0, 731, 640, 308, 641, + 704, 473, 232, 273, 0, 0, 0, 0, 156, 269, + 267, 245, 271, 272, 0, 0, 0, 0, 0, 0, + 0, 129, 128, 0, 130, 131, 0, 0, 216, 132, + 0, 118, 0, 189, 0, 193, 186, 121, 231, 155, + 0, 0, 233, 234, 0, 120, 292, 308, 293, 517, + 256, 247, 0, 0, 0, 398, 378, 0, 373, 531, + 0, 133, 134, 0, 0, 0, 0, 31, 0, 110, + 407, 125, 109, 115, 0, 496, 0, 495, 102, 103, + 218, 227, 0, 504, 226, 0, 503, 511, 512, 0, + 0, 18, 10, 0, 7, 7, 48, 47, 699, 0, + 34, 42, 38, 36, 43, 40, 330, 82, 89, 86, + 0, 0, 275, 0, 0, 0, 571, 65, 577, 67, + 113, 509, 0, 673, 674, 154, 0, 153, 668, 690, + 0, 292, 308, 293, 0, 667, 669, 697, 679, 0, + 514, 0, 0, 0, 480, 0, 479, 0, 0, 0, + 471, 70, 58, 73, 0, 57, 471, 0, 475, 493, + 0, 298, 299, 0, 55, 71, 56, 74, 303, 302, + 313, 699, 329, 396, 392, 397, 408, 402, 403, 437, + 0, 0, 440, 443, 0, 0, 426, 0, 699, 311, + 0, 0, 344, 472, 499, 533, 0, 0, 732, 737, + 471, 471, 0, 471, 742, 0, 0, 0, 163, 0, + 0, 165, 0, 0, 0, 0, 0, 0, 0, 0, + 162, 159, 158, 160, 0, 0, 0, 0, 217, 0, + 116, 161, 0, 0, 187, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 243, 245, 246, 279, 278, 0, 0, 0, 0, 0, - 167, 471, 0, 175, 276, 223, 0, 697, 222, 261, - 262, 0, 289, 552, 548, 557, 0, 477, 473, 473, - 473, 291, 555, 0, 522, 293, 0, 292, 260, 0, - 256, 270, 272, 519, 0, 257, 112, 111, 468, 387, - 466, 377, 0, 319, 0, 0, 320, 321, 322, 33, - 0, 28, 24, 696, 310, 26, 695, 30, 693, 122, - 114, 504, 503, 232, 507, 0, 17, 20, 19, 332, - 53, 49, 51, 52, 50, 46, 0, 0, 0, 0, - 346, 104, 94, 105, 0, 87, 90, 0, 0, 0, - 368, 0, 364, 84, 0, 0, 66, 69, 579, 573, - 473, 473, 673, 686, 679, 677, 552, 548, 0, 687, - 473, 690, 692, 688, 0, 689, 473, 672, 685, 678, - 676, 671, 699, 682, 683, 0, 514, 478, 480, 479, - 0, 0, 494, 0, 346, 327, 490, 0, 0, 0, - 493, 0, 483, 302, 329, 346, 332, 420, 0, 419, - 411, 412, 414, 0, 416, 438, 434, 433, 220, 523, - 473, 0, 667, 700, 435, 443, 448, 449, 700, 700, - 436, 446, 700, 0, 383, 430, 429, 431, 432, 332, - 702, 310, 703, 0, 0, 0, 345, 347, 348, 742, - 741, 705, 705, 705, 0, 0, 0, 522, 0, 0, - 523, 0, 157, 0, 0, 0, 0, 0, 0, 238, - 237, 0, 184, 119, 220, 523, 221, 0, 0, 369, - 385, 0, 215, 214, 659, 658, 0, 212, 211, 209, - 210, 208, 207, 206, 203, 204, 205, 201, 202, 196, - 197, 198, 199, 200, 194, 195, 0, 0, 0, 0, - 0, 0, 169, 181, 0, 0, 168, 473, 473, 0, - 473, 470, 542, 0, 0, 0, 0, 264, 0, 266, - 0, 516, 551, 550, 547, 546, 696, 0, 0, 566, - 0, 0, 563, 290, 564, 553, 473, 667, 477, 552, - 548, 0, 0, 473, 233, 0, 518, 0, 0, 0, - 388, 0, 387, 152, 151, 150, 149, 0, 23, 0, - 395, 0, 0, 16, 346, 35, 39, 37, 41, 0, - 0, 92, 0, 96, 0, 100, 0, 98, 0, 365, - 0, 85, 68, 0, 580, 0, 574, 575, 512, 509, - 551, 547, 552, 548, 0, 485, 0, 473, 553, 552, - 548, 0, 233, 0, 518, 510, 0, 681, 336, 473, - 473, 473, 492, 342, 346, 0, 0, 422, 421, 415, - 0, 0, 441, 346, 0, 79, 0, 332, 332, 0, - 332, 0, 346, 0, 701, 0, 0, 343, 349, 707, - 706, 708, 248, 164, 0, 0, 0, 166, 190, 192, - 191, 254, 255, 0, 0, 0, 0, 240, 0, 0, - 0, 0, 185, 0, 241, 244, 179, 178, 171, 0, - 170, 183, 0, 0, 539, 537, 0, 540, 477, 176, - 0, 0, 267, 0, 0, 549, 545, 556, 473, 565, - 554, 559, 0, 561, 0, 0, 520, 521, 0, 259, - 469, 467, 379, 0, 25, 29, 694, 0, 0, 44, - 93, 91, 0, 0, 0, 0, 366, 362, 0, 0, - 220, 523, 584, 596, 599, 0, 572, 0, 0, 0, - 0, 0, 0, 221, 630, 0, 655, 0, 591, 0, - 0, 310, 0, 568, 589, 595, 567, 590, 631, 0, - 602, 606, 576, 551, 547, 487, 553, 521, 684, 334, - 491, 488, 489, 340, 339, 0, 0, 413, 346, 346, - 78, 458, 473, 220, 523, 0, 444, 450, 451, 700, - 700, 346, 346, 447, 0, 437, 704, 333, 353, 0, - 0, 0, 0, 0, 0, 373, 0, 0, 370, 188, - 213, 126, 0, 172, 173, 180, 182, 538, 536, 543, - 541, 0, 177, 0, 263, 265, 562, 473, 560, 228, - 376, 0, 45, 95, 99, 97, 367, 0, 577, 571, - 583, 645, 647, 572, 572, 572, 0, 0, 0, 616, - 618, 619, 620, 0, 0, 0, 646, 572, 656, 0, - 592, 285, 700, 0, 286, 0, 700, 0, 700, 0, - 0, 581, 570, 569, 593, 629, 628, 572, 572, 0, - 0, 337, 417, 418, 457, 454, 440, 0, 0, 346, - 332, 332, 452, 455, 359, 360, 361, 358, 0, 351, - 354, 344, 0, 0, 0, 0, 371, 0, 0, 126, - 242, 0, 174, 544, 268, 558, 123, 363, 0, 0, - 0, 587, 0, 0, 572, 648, 0, 651, 0, 0, - 612, 0, 621, 0, 627, 632, 0, 281, 332, 283, - 284, 332, 0, 0, 0, 280, 282, 582, 572, 0, - 0, 335, 341, 0, 77, 346, 346, 465, 346, 346, - 0, 0, 353, 0, 0, 250, 251, 252, 253, 0, - 374, 127, 472, 137, 0, 585, 597, 588, 600, 652, - 650, 0, 649, 144, 0, 310, 0, 0, 0, 617, - 626, 0, 0, 594, 141, 0, 140, 0, 338, 464, - 461, 459, 462, 453, 456, 352, 350, 220, 0, 372, - 0, 572, 0, 0, 0, 0, 610, 700, 614, 613, - 0, 635, 0, 633, 660, 0, 603, 607, 0, 0, - 0, 355, 357, 138, 586, 573, 598, 148, 135, 0, - 0, 654, 0, 653, 572, 332, 0, 637, 636, 638, - 0, 0, 661, 662, 622, 0, 0, 460, 463, 0, - 145, 0, 0, 601, 611, 346, 615, 634, 0, 660, - 0, 0, 0, 0, 356, 0, 0, 136, 0, 639, - 0, 0, 623, 663, 604, 608, 147, 146, 142, 0, - 664, 0, 0, 0, 0, 0, 0, 0, 665, 0, - 624, 605, 609, 143, 0, 0, 640, 0, 0, 643, - 644, 666, 625, 0, 0, 0 + 0, 0, 0, 0, 0, 0, 0, 241, 243, 244, + 277, 276, 0, 0, 0, 0, 0, 167, 469, 0, + 175, 274, 223, 0, 696, 222, 259, 260, 0, 287, + 551, 547, 556, 0, 475, 471, 471, 471, 289, 554, + 0, 521, 291, 0, 290, 258, 0, 254, 268, 270, + 518, 0, 255, 112, 111, 466, 385, 464, 375, 0, + 317, 0, 0, 318, 319, 320, 33, 0, 28, 24, + 695, 308, 26, 694, 30, 692, 122, 114, 502, 501, + 505, 0, 17, 20, 19, 330, 53, 49, 51, 52, + 50, 46, 0, 0, 0, 0, 344, 104, 94, 105, + 0, 87, 90, 0, 0, 0, 366, 0, 362, 84, + 0, 0, 66, 69, 578, 572, 471, 471, 672, 685, + 678, 676, 551, 547, 0, 686, 471, 689, 691, 687, + 0, 688, 471, 671, 684, 677, 675, 670, 698, 681, + 682, 0, 513, 476, 478, 477, 0, 0, 492, 0, + 344, 325, 488, 0, 0, 0, 491, 0, 481, 300, + 327, 344, 330, 418, 0, 417, 409, 410, 412, 0, + 414, 436, 432, 431, 220, 522, 471, 0, 666, 699, + 433, 441, 446, 447, 699, 699, 434, 444, 699, 0, + 381, 428, 427, 429, 430, 330, 701, 308, 702, 0, + 0, 0, 343, 345, 346, 741, 740, 704, 704, 704, + 0, 0, 0, 521, 0, 0, 522, 0, 157, 0, + 0, 0, 0, 0, 0, 236, 235, 0, 184, 119, + 220, 522, 221, 0, 0, 367, 383, 0, 215, 214, + 658, 657, 0, 212, 211, 209, 210, 208, 207, 206, + 203, 204, 205, 201, 202, 196, 197, 198, 199, 200, + 194, 195, 0, 0, 0, 0, 0, 0, 169, 181, + 0, 0, 168, 471, 471, 0, 471, 468, 541, 0, + 0, 0, 0, 262, 0, 264, 0, 515, 550, 549, + 546, 545, 695, 0, 0, 565, 0, 0, 562, 288, + 563, 552, 471, 666, 475, 551, 547, 0, 0, 471, + 231, 0, 517, 0, 0, 0, 386, 0, 385, 152, + 151, 150, 149, 0, 23, 0, 393, 0, 0, 16, + 344, 35, 39, 37, 41, 0, 0, 92, 0, 96, + 0, 100, 0, 98, 0, 363, 0, 85, 68, 0, + 579, 0, 573, 574, 510, 507, 550, 546, 551, 547, + 483, 0, 471, 552, 551, 547, 0, 231, 0, 517, + 508, 0, 680, 334, 471, 471, 471, 490, 340, 344, + 0, 0, 420, 419, 413, 0, 0, 439, 344, 0, + 79, 0, 330, 330, 0, 330, 0, 344, 0, 700, + 0, 0, 341, 347, 706, 705, 707, 246, 164, 0, + 0, 166, 190, 192, 191, 252, 253, 0, 0, 0, + 0, 238, 0, 0, 0, 0, 185, 0, 239, 242, + 179, 178, 171, 0, 170, 183, 0, 0, 538, 536, + 0, 539, 475, 176, 0, 0, 265, 0, 0, 548, + 544, 555, 471, 564, 553, 558, 0, 560, 0, 551, + 547, 519, 520, 0, 257, 467, 465, 377, 0, 25, + 29, 693, 0, 0, 44, 93, 91, 0, 0, 0, + 0, 364, 360, 0, 0, 220, 522, 583, 595, 598, + 0, 571, 0, 0, 0, 0, 0, 0, 221, 629, + 0, 654, 0, 590, 0, 0, 308, 0, 567, 588, + 594, 566, 589, 630, 0, 601, 605, 575, 550, 546, + 485, 552, 520, 683, 332, 489, 486, 487, 338, 337, + 0, 0, 411, 344, 344, 78, 456, 471, 220, 522, + 0, 442, 448, 449, 699, 699, 344, 344, 445, 0, + 435, 703, 331, 351, 0, 0, 0, 0, 0, 0, + 371, 0, 0, 368, 188, 213, 126, 0, 172, 173, + 180, 182, 537, 535, 542, 540, 0, 177, 0, 261, + 263, 561, 471, 559, 374, 0, 45, 95, 99, 97, + 365, 0, 576, 570, 582, 644, 646, 571, 571, 571, + 0, 0, 0, 615, 617, 618, 619, 0, 0, 0, + 645, 571, 655, 0, 591, 283, 699, 0, 284, 0, + 699, 0, 699, 0, 0, 580, 569, 568, 592, 628, + 627, 571, 571, 0, 0, 335, 415, 416, 455, 452, + 438, 0, 0, 344, 330, 330, 450, 453, 357, 358, + 359, 356, 0, 349, 352, 342, 0, 0, 0, 0, + 369, 0, 0, 126, 240, 0, 174, 543, 266, 557, + 123, 361, 0, 0, 0, 586, 0, 0, 571, 647, + 0, 650, 0, 0, 611, 0, 620, 0, 626, 631, + 0, 279, 330, 281, 282, 330, 0, 0, 0, 278, + 280, 581, 571, 0, 0, 333, 339, 0, 77, 344, + 344, 463, 344, 344, 0, 0, 351, 0, 0, 248, + 249, 250, 251, 0, 372, 127, 470, 137, 0, 584, + 596, 587, 599, 651, 649, 0, 648, 144, 0, 308, + 0, 0, 0, 616, 625, 0, 0, 593, 141, 0, + 140, 0, 336, 462, 459, 457, 460, 451, 454, 350, + 348, 220, 0, 370, 0, 571, 0, 0, 0, 0, + 609, 699, 613, 612, 0, 634, 0, 632, 659, 0, + 602, 606, 0, 0, 0, 353, 355, 138, 585, 572, + 597, 148, 135, 0, 0, 653, 0, 652, 571, 330, + 0, 636, 635, 637, 0, 0, 660, 661, 621, 0, + 0, 458, 461, 0, 145, 0, 0, 600, 610, 344, + 614, 633, 0, 659, 0, 0, 0, 0, 354, 0, + 0, 136, 0, 638, 0, 0, 622, 662, 603, 607, + 147, 146, 142, 0, 663, 0, 0, 0, 0, 0, + 0, 0, 664, 0, 623, 604, 608, 143, 0, 0, + 639, 0, 0, 642, 643, 665, 624, 0, 0, 0 }; -static const short yydefgoto[] = { 1354, - 1, 2, 120, 568, 987, 3, 4, 31, 32, 33, - 300, 551, 552, 553, 34, 91, 35, 577, 579, 578, - 580, 576, 36, 37, 38, 415, 129, 130, 131, 341, - 586, 587, 539, 588, 177, 39, 40, 41, 135, 262, - 263, 303, 813, 304, 1151, 264, 988, 1281, 1216, 1236, - 1237, 1336, 1277, 293, 793, 265, 448, 500, 757, 266, - 267, 268, 294, 270, 510, 313, 43, 271, 460, 1052, - 272, 273, 274, 275, 132, 276, 989, 405, 520, 777, - 990, 45, 162, 991, 47, 163, 443, 164, 144, 156, - 49, 635, 145, 1120, 406, 1194, 157, 1121, 50, 1040, - 687, 688, 689, 1139, 1140, 1141, 969, 720, 721, 51, - 543, 289, 912, 802, 52, 53, 54, 55, 181, 182, - 56, 57, 58, 411, 651, 652, 653, 654, 184, 418, - 419, 420, 421, 665, 671, 666, 1027, 667, 668, 1028, - 1029, 540, 541, 501, 783, 59, 374, 375, 146, 60, - 61, 147, 148, 114, 63, 511, 281, 282, 283, 65, - 284, 67, 68, 180, 69, 285, 762, 763, 778, 523, - 993, 994, 1161, 836, 837, 838, 350, 995, 996, 1084, - 1252, 1163, 997, 998, 1189, 1085, 1253, 1086, 1254, 1118, - 1296, 1334, 1119, 1297, 1335, 1285, 1229, 1287, 1172, 999, - 1232, 1290, 1264, 1308, 1330, 1227, 1338, 1000, 1001, 1002, - 1100, 727, 1292, 1293, 1294, 1340, 367, 779, 369, 370, - 371, 558, 372, 107, 625, 1179, 683, 684, 438, 71, +static const short yydefgoto[] = { 1348, + 1, 2, 119, 564, 982, 3, 4, 31, 32, 33, + 299, 548, 549, 550, 34, 91, 35, 573, 575, 574, + 576, 572, 36, 37, 38, 412, 128, 129, 130, 339, + 582, 583, 536, 584, 176, 39, 40, 41, 134, 261, + 262, 302, 809, 303, 1145, 263, 983, 1275, 1210, 1230, + 1231, 1330, 1271, 292, 789, 264, 445, 497, 753, 265, + 266, 267, 293, 269, 507, 312, 43, 270, 457, 1047, + 271, 272, 273, 274, 131, 275, 984, 402, 517, 773, + 985, 45, 161, 986, 47, 162, 440, 163, 143, 155, + 49, 631, 144, 1114, 403, 1188, 156, 1115, 50, 1035, + 683, 684, 685, 1133, 1134, 1135, 964, 716, 717, 51, + 540, 288, 906, 798, 52, 53, 54, 55, 180, 181, + 56, 57, 58, 408, 647, 648, 649, 650, 183, 415, + 416, 417, 418, 661, 667, 662, 1022, 663, 664, 1023, + 1024, 537, 538, 498, 779, 59, 372, 373, 145, 60, + 61, 146, 147, 113, 63, 508, 280, 281, 282, 65, + 283, 67, 68, 179, 69, 284, 758, 759, 770, 520, + 988, 989, 1155, 832, 833, 834, 348, 990, 991, 1078, + 1246, 1157, 992, 993, 1183, 1079, 1247, 1080, 1248, 1112, + 1290, 1328, 1113, 1291, 1329, 1279, 1223, 1281, 1166, 994, + 1226, 1284, 1258, 1302, 1324, 1221, 1332, 995, 996, 997, + 1094, 723, 1286, 1287, 1288, 1334, 365, 775, 367, 368, + 369, 555, 370, 107, 621, 1173, 679, 680, 435, 71, 72 }; -static const short yypact[] = { 64, - 80,-32768,-32768, 2131,-32768, 130,-32768, 283, 48,-32768, --32768, 556,-32768,-32768, 66, 87,-32768, 206,-32768, 2650, --32768, 210,-32768, 1299, 1299,-32768, 1901,-32768,-32768, 292, --32768, 333, 3137,-32768,-32768,-32768,-32768, 573, 353, 368, --32768,-32768, 166, 1701,-32768, 2829,-32768, 1033, 294,-32768, --32768, 540,-32768,-32768,-32768,-32768,-32768, 396, 1486,-32768, --32768, 591,-32768,-32768,-32768, 82,-32768,-32768,-32768, 214, - 6712,-32768,-32768,-32768,-32768, 8620, 2499,-32768, 283, 210, - 355, 414, 368,-32768, 214,-32768, 214, 8620, 8620,-32768, - 512,-32768, 210,-32768, 4042, 3298, 1, 214, 8446, 283, - 2225,-32768, 361, 267, 2225,-32768, 262, 2706, 2706, 1901, - 383, 435, 166, 453, 495, 498,-32768, 571, 446, 2532, - 224, 4042, 3192, 680, 723, 521, 617,-32768, 55, 16, - 143, 143,-32768,-32768, 546,-32768, 6059, 532,-32768, 3255, - 3255, 4407, 641, 569,-32768,-32768, 255,-32768,-32768, 82, --32768,-32768,-32768,-32768, 1033, 669,-32768, 998,-32768,-32768, --32768, 1070, 673,-32768,-32768, 4042,-32768,-32768,-32768,-32768, --32768,-32768,-32768,-32768,-32768,-32768,-32768, 368, 775,-32768, - 609, 609,-32768, 2064,-32768, 673,-32768, 604, 970,-32768, --32768,-32768,-32768, 3851,-32768, 50,-32768, 605, 633,-32768, --32768,-32768,-32768, 640,-32768,-32768,-32768,-32768,-32768,-32768, +static const short yypact[] = { 203, + 236,-32768,-32768, 1874,-32768, 85,-32768, 55, 300,-32768, +-32768, 590,-32768,-32768, -23, 252,-32768, 365,-32768, 1493, +-32768, 355,-32768, 963, 963,-32768, 2214,-32768,-32768, 349, +-32768, 429, 3939,-32768,-32768,-32768,-32768, 279, 435, 443, +-32768,-32768, 396, 1052,-32768, 9215,-32768, 704, 30,-32768, +-32768, 698,-32768,-32768,-32768,-32768,-32768, 488, 1610,-32768, +-32768, 410,-32768,-32768,-32768, 397,-32768,-32768,-32768, 89, + 6309,-32768,-32768,-32768,-32768, 8124, 2133,-32768, 55, 355, + 461, 515, 443,-32768, 89,-32768, 89, 8124, 8124,-32768, + 363,-32768, 355,-32768, 3239, 4205, 230, 89, 7950, 55, + 2347,-32768, 484, 103, 2347,-32768, 92, 2356, 2356, 479, + 501, 396, 514, 519, 540,-32768, 629, 555, 2912, 144, + 3239, 9396, 593, 706, 572, 666,-32768, 149, 306, 57, + 57,-32768,-32768, 575,-32768, 4662, 589,-32768, 3833, 3833, + 3542, 1266, 393,-32768,-32768, 408,-32768,-32768, 397,-32768, +-32768,-32768,-32768, 704, 536,-32768, 1285,-32768,-32768,-32768, + 907, 654,-32768,-32768, 3239,-32768,-32768,-32768,-32768,-32768, +-32768,-32768,-32768,-32768,-32768,-32768, 443, 719,-32768, 617, + 617,-32768, 2447,-32768, 654,-32768, 608, 875,-32768,-32768, +-32768,-32768, 4014,-32768, 56,-32768, 609, 647,-32768,-32768, +-32768,-32768, 683,-32768,-32768,-32768,-32768,-32768,-32768,-32768, -32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768, --32768,-32768,-32768,-32768,-32768,-32768, 601,-32768,-32768, 673, - 1486, 654, 627,-32768,-32768, 9561, 9644, 659, 664,-32768, --32768,-32768,-32768,-32768,-32768, 675, 689, 696, 698, 701, - 262, 9312,-32768,-32768, 9312,-32768,-32768, 9312, 6796, 3961, --32768, 422,-32768, 9312,-32768, 8707,-32768,-32768, 9780,-32768, - 845, 1829, 8790,-32768, 781, 434,-32768, 126, 1601, 4144, --32768, 160,-32768, 475, 813, 4042, 1,-32768, 262, 690, --32768, 721, 743, 9688, 726, 728, 734, 800,-32768, 2499, --32768, 609,-32768,-32768,-32768, 478,-32768, 125,-32768,-32768, --32768,-32768,-32768, 2225,-32768,-32768, 2225,-32768, 758,-32768, --32768, 3851, 47,-32768, 729, 2499,-32768,-32768,-32768,-32768, - 521, 708,-32768,-32768,-32768,-32768,-32768,-32768, 712,-32768, - 249,-32768, 6886, 8877,-32768, 143, 143, 803,-32768,-32768, --32768,-32768,-32768, 855, 765,-32768,-32768, 743, 767, 9688, - 296, 2466, 3192, 2466, 3043, 3464, 772,-32768, 100, 3351, - 807, 819,-32768, 776, 8877, 3862,-32768, 3862,-32768, 4280, - 4280, 4407, 785,-32768,-32768,-32768, 970, 4042,-32768,-32768, - 6161, 792,-32768, 4311, 1070, 1033, 4042,-32768,-32768,-32768, - 970,-32768,-32768,-32768, 521,-32768,-32768,-32768,-32768, 905, --32768,-32768,-32768, 8877, 447, 1155, 3724, 60, 1544,-32768, - 252, 521, 673, 2142, 802, 867,-32768,-32768,-32768, 796, - 798,-32768,-32768,-32768,-32768, 164,-32768,-32768, 8877, 627, - 6796,-32768, 229, 6796,-32768, 8877, 8964, 9312, 8620, 2142, - 2142, 2142, 2142,-32768,-32768,-32768,-32768, 805, 809, 803, - 810,-32768, 8620,-32768,-32768, 6623, 6796,-32768, 8877, 8877, - 6976, 8877, 8877, 8877, 8877, 8877, 8877, 8877, 8877, 8877, - 8877, 8877, 8877, 8877, 8877, 8877, 8877, 8877, 8877, 8877, --32768,-32768,-32768,-32768,-32768, 8877, 8877, 8877, 8620, 1393, - 564, 670, 7615,-32768,-32768, 283, 865, 912,-32768, 237, - 244, 615,-32768, 1080, 1080,-32768, 3796, 814, 837, 884, --32768,-32768, 490, 8090, 114,-32768, 188,-32768,-32768, 8877, --32768,-32768,-32768,-32768, 626,-32768,-32768,-32768, 877, 874, --32768,-32768, 262,-32768, 7438, 7528,-32768,-32768,-32768,-32768, - 606, 879,-32768,-32768, 3594, 540,-32768,-32768, 887,-32768, --32768,-32768,-32768, 844,-32768, 891,-32768,-32768,-32768, 712, --32768,-32768,-32768,-32768,-32768,-32768, 893, 896, 897, 903, - 867,-32768,-32768, 210, 8877, 906,-32768, 280, 420, 436, --32768, 6263, 9757,-32768, 849, 143,-32768,-32768,-32768, 24, --32768,-32768,-32768,-32768,-32768,-32768, 817, 817, 4802,-32768, --32768,-32768,-32768,-32768, 8181,-32768,-32768,-32768,-32768,-32768, --32768,-32768,-32768,-32768, 902, 6886,-32768,-32768,-32768,-32768, - 3862, 3862,-32768, 4311, 867,-32768, 855, 861, 863, 866, --32768, 872,-32768, 1070,-32768, 867, 712,-32768, 883,-32768, - 923,-32768,-32768, 939,-32768, 9757,-32768,-32768, 922, 18, --32768, 8877, 2818, 521, 930,-32768,-32768,-32768, 510, 611, - 934,-32768, 521, 937,-32768,-32768,-32768,-32768,-32768, 748, --32768, 3086,-32768, 281, 571, 916, 947, 867,-32768,-32768, --32768, 282, 282, 282, 904, 908, 9051, 884, 913, 915, - 192, 917,-32768, 918, 920, 938, 944, 948, 957,-32768, --32768, 932,-32768,-32768, 975, 421, 338, 8877, 976,-32768, - 987, 941, 9757, 9757,-32768,-32768, 988, 4588, 9818, 4862, - 4703, 4168, 4535, 3669, 1937, 1937, 1937, 1334, 1334, 1050, - 1050, 713, 713, 713,-32768,-32768, 955, 954, 959, 958, - 961, 2142, 564,-32768, 6886, 8877,-32768,-32768,-32768, 8877, --32768,-32768, 980, 9312, 967, 981, 1030,-32768, 8877,-32768, - 8877,-32768, 1350,-32768, 1350,-32768, 71, 977, 978,-32768, - 973, 2142, 855,-32768, 855, 1728,-32768, 1109, 983, 8272, - 8272, 5855, 979, 8707, 383, 984, 498, 813, 989, 8877, - 262, 982, 874,-32768, 9757,-32768, 9757, 2499,-32768, 2761, - 662, 6886, 396,-32768, 867,-32768,-32768,-32768,-32768, 708, - 994,-32768, 249,-32768, 8877,-32768, 8877,-32768, 8877,-32768, - 116,-32768,-32768, 262,-32768, 5585, 1049,-32768, 855, 855, - 1260, 1260, 1918, 1918, 4802,-32768, 82,-32768, 2412, 8359, - 8359, 5957, 240, 1005, 341, 855, 6886,-32768, 1031,-32768, --32768,-32768,-32768, 1051, 867, 8620, 905,-32768,-32768,-32768, - 8877, 8877, 152, 4929, 1006,-32768, 401, 712, 712, 3568, - 755, 2290, 867, 2142,-32768, 54, 1023,-32768,-32768,-32768, --32768,-32768,-32768,-32768, 9395, 9395, 7066,-32768,-32768,-32768, --32768,-32768,-32768, 1024, 1029, 1032, 1034,-32768, 4688, 6886, - 6353, 1020,-32768, 8877,-32768,-32768,-32768,-32768, 474, 1035, --32768,-32768, 1039, 44, 181, 181, 1027, 181,-32768,-32768, - 9312, 1128,-32768, 1044, 1046,-32768,-32768,-32768,-32768,-32768, --32768, 855, 1059,-32768, 1047, 1062,-32768,-32768, 452,-32768, - 9757,-32768,-32768, 1063,-32768,-32768,-32768, 2064, 708,-32768, --32768,-32768, 1068, 1071, 1073, 6443,-32768,-32768, 745, 289, - 1075, 575,-32768,-32768,-32768, 1065,-32768, 8877, 1116, 1121, - 1122, 8533, 67, 572,-32768, 1129, 1175, 1131,-32768, 2565, - 4428, 2918, 5022,-32768,-32768, 1170,-32768,-32768,-32768, 7718, --32768,-32768,-32768, 1260, 1260,-32768, 2412, 1408,-32768,-32768, - 855, 855, 855,-32768, 1132, 1089, 1093,-32768, 4929, 4929, --32768,-32768,-32768, 1138, 624, 8877,-32768,-32768,-32768, 521, - 521, 867, 867,-32768, 2406,-32768,-32768,-32768, 583, 6886, - 8877, 8877, 8877, 8877, 6886,-32768, 8877, 1140,-32768,-32768, - 9801, 546, 8877,-32768, 474,-32768,-32768,-32768,-32768,-32768, --32768, 1100,-32768, 1163,-32768,-32768, 855,-32768,-32768,-32768, --32768, 73,-32768,-32768,-32768,-32768,-32768, 262,-32768,-32768, --32768,-32768,-32768,-32768,-32768, 803, 6533, 1123, 4518,-32768, --32768,-32768,-32768, 1153, 8877, 1158,-32768,-32768,-32768, 1130, --32768,-32768, 191, 763,-32768, 788, 521, 9138, 427, 797, - 307,-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768, 6886, - 6886,-32768,-32768,-32768,-32768,-32768, 152, 8877, 8877, 4929, - 712, 712, 1159, 1161,-32768,-32768,-32768,-32768, 315,-32768, - 1133,-32768, 1120, 1126, 1127, 1137,-32768, 9711, 6886, 546, --32768, 1119,-32768,-32768,-32768, 855,-32768,-32768, 462, 462, - 8000,-32768, 1210, 1184, 1139,-32768, 1189,-32768, 8620, 8877, --32768, 7820,-32768, 1190,-32768,-32768, 571,-32768, 712,-32768, --32768, 712, 9478, 9478, 7156,-32768,-32768,-32768, 803, 7246, - 7246,-32768,-32768, 6886,-32768, 4929, 4929,-32768, 867, 867, - 6886, 6886, 583, 1146, 9225,-32768,-32768,-32768,-32768, 6886, --32768,-32768,-32768,-32768, 8620,-32768,-32768,-32768,-32768,-32768, --32768, 5675,-32768,-32768, 1148, 416, 4042, 9734, 7820,-32768, --32768, 5141, 51,-32768,-32768, 1198,-32768, 1199,-32768,-32768, --32768, 1174, 1200,-32768,-32768,-32768,-32768, 369, 1154,-32768, - 1160, 803, 7910, 527, 370, 5273,-32768, 521,-32768,-32768, - 379,-32768, 5377,-32768, 1248, 1204,-32768,-32768, 6886, 6886, - 8877,-32768,-32768,-32768,-32768, 25,-32768,-32768,-32768, 8877, - 1205,-32768, 1213,-32768, 803, 712, 7820,-32768,-32768,-32768, - 1178, 271, 1216,-32768,-32768, 7336, 7336,-32768,-32768, 1171, --32768, 5765, 1172,-32768,-32768, 867,-32768, 1181, 8877, 1248, - 1222, 1248, 1177, 1187,-32768, 397, 5481,-32768, 1233,-32768, - 1192, 365,-32768,-32768,-32768,-32768,-32768,-32768,-32768, 1208, --32768, 1271, 1236, 7910, 7910, 6886, 3413, 803,-32768, 410, --32768,-32768,-32768,-32768, 1195, 1197,-32768, 1296, 1251,-32768, --32768,-32768,-32768, 1308, 1309,-32768 +-32768,-32768,-32768,-32768,-32768, 601,-32768,-32768, 654, 1610, + 351, 657,-32768,-32768, 3117, 9065, 660, 662,-32768,-32768, +-32768,-32768,-32768,-32768, 665, 690, 692, 699, 703, 92, + 8816,-32768,-32768, 8816,-32768,-32768, 8816, 6393, 9148,-32768, + 29,-32768, 8816,-32768, 8211,-32768,-32768, 9444,-32768, 1334, + 2712, 8294,-32768, 767, 557,-32768, 160, 2819, 9439,-32768, + 266,-32768, 579, 809, 3239, 230,-32768, 92, 685,-32768, + 684, 738, 9497, 693, 697, 701, 808,-32768, 2133,-32768, + 617,-32768,-32768,-32768, 154,-32768, 139,-32768,-32768,-32768, +-32768,-32768, 2347,-32768,-32768, 2347,-32768,-32768,-32768, 4014, + 50,-32768, 711, 2133,-32768,-32768,-32768,-32768, 572, 766, +-32768,-32768,-32768,-32768,-32768,-32768, 656,-32768, 254,-32768, + 6483, 8381,-32768, 57, 57, 765,-32768,-32768,-32768,-32768, +-32768, 818, 730,-32768,-32768, 738, 735, 9497, 328, 1775, + 9396, 1775, 4904, 4548, 737,-32768, 72, 9289, 763, 787, +-32768, 746, 8381, 4250,-32768, 4250,-32768, 4314, 4314, 753, +-32768,-32768,-32768, 875, 3239,-32768,-32768, 5854, 752,-32768, + 4433, 907, 704, 3239,-32768,-32768,-32768, 875,-32768,-32768, +-32768, 572,-32768,-32768,-32768,-32768, 1191,-32768,-32768,-32768, + 8381, 156, 1389, 9306, 54, 2311,-32768, 167, 572, 654, + 2569, 771, 831,-32768,-32768,-32768, 773, 777,-32768,-32768, +-32768,-32768, 169,-32768,-32768, 8381, 657, 6393,-32768, 381, + 6393,-32768, 8381, 8468, 8816, 8124, 2569, 2569, 2569, 2569, +-32768,-32768,-32768,-32768, 782, 784, 765, 793,-32768, 8124, +-32768,-32768, 3487, 6393,-32768, 8381, 8381, 3006, 8381, 8381, + 8381, 8381, 8381, 8381, 8381, 8381, 8381, 8381, 8381, 8381, + 8381, 8381, 8381, 8381, 8381, 8381, 8381,-32768,-32768,-32768, +-32768,-32768, 8381, 8381, 8381, 8124, 3398, 497, 109, 7032, +-32768,-32768, 55, 848, 896,-32768, 387, 415, 592,-32768, + 388, 388,-32768, 3838, 798, 817, 864,-32768,-32768, 412, + 7507, 1099,-32768, 251,-32768,-32768, 8381,-32768,-32768,-32768, +-32768, 597,-32768,-32768,-32768, 851, 855,-32768,-32768, 92, +-32768, 6855, 6945,-32768,-32768,-32768,-32768, 419, 859,-32768, +-32768, 9200, 698,-32768,-32768, 862,-32768,-32768,-32768,-32768, +-32768, 865,-32768,-32768,-32768, 656,-32768,-32768,-32768,-32768, +-32768,-32768, 866, 868, 869, 870, 831,-32768,-32768, 355, + 8381, 877,-32768, 434, 438, 462,-32768, 5956, 9590,-32768, + 836, 57,-32768,-32768,-32768, 20,-32768,-32768,-32768,-32768, +-32768,-32768, 1506, 1506, 3333,-32768,-32768,-32768,-32768,-32768, + 7598,-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768, + 887, 6483,-32768,-32768,-32768,-32768, 4250, 4250,-32768, 4433, + 831,-32768, 818, 849, 856, 861,-32768, 863,-32768, 907, +-32768, 831, 656,-32768, 881,-32768, 899,-32768,-32768, 1243, +-32768, 9590,-32768,-32768, 912, 146,-32768, 8381, 2808, 572, + 921,-32768,-32768,-32768, 368, 407, 922,-32768, 572, 920, +-32768,-32768,-32768,-32768,-32768, 551,-32768, 4154,-32768, 187, + 629, 897, 926, 831,-32768,-32768,-32768, 505, 505, 505, + 885, 886, 8555, 864, 895, 900, 248, 901,-32768, 906, + 909, 919, 942, 943, 945,-32768,-32768, 918,-32768,-32768, + 962, 553, 136, 8381, 969,-32768, 968, 928, 9590, 9590, +-32768,-32768, 973, 9629, 4583, 9645, 9660, 5903, 6801, 3406, + 1324, 1324, 1324, 1664, 1664, 814, 814, 640, 640, 640, +-32768,-32768, 932, 934, 940, 935, 946, 2569, 497,-32768, + 6483, 8381,-32768,-32768,-32768, 8381,-32768,-32768, 955, 8816, + 944, 964, 1008,-32768, 8381,-32768, 8381,-32768, 890,-32768, + 890,-32768, 65, 951, 952,-32768, 953, 2569, 818,-32768, + 818, 2046,-32768, 1065, 957, 7689, 7689, 4811, 966, 8211, + 479, 972, 540, 809, 974, 8381, 92, 961, 855,-32768, + 9590,-32768, 9590, 2133,-32768, 664, 520, 6483, 488,-32768, + 831,-32768,-32768,-32768,-32768, 766, 978,-32768, 254,-32768, + 8381,-32768, 8381,-32768, 8381,-32768, 9,-32768,-32768, 92, +-32768, 5584, 1032,-32768, 818, 818, 2757, 2757, 3282, 3282, +-32768, 397,-32768, 3954, 7776, 7776, 5016, 174, 979, 244, + 818, 6483,-32768, 1030,-32768,-32768,-32768,-32768, 1037, 831, + 8124, 1191,-32768,-32768,-32768, 8381, 8381, 74, 9521, 995, +-32768, 2416, 656, 656, 3185, 603, 3228, 831, 2569,-32768, + 52, 1011,-32768,-32768,-32768,-32768,-32768,-32768,-32768, 8899, + 8899,-32768,-32768,-32768,-32768,-32768,-32768, 1013, 1014, 1019, + 1022,-32768, 9472, 6483, 6046, 1009,-32768, 8381,-32768,-32768, +-32768,-32768, 143, 1012,-32768,-32768, 1017, 75, 278, 278, + 1006, 278,-32768,-32768, 8816, 1107,-32768, 1018, 1020,-32768, +-32768,-32768,-32768,-32768,-32768, 818, 1023,-32768, 1010, 7863, + 7863,-32768,-32768, 584,-32768, 9590,-32768,-32768, 1021,-32768, +-32768,-32768, 2447, 766,-32768,-32768,-32768, 1024, 1026, 1036, + 6136,-32768,-32768, 668, 231, 1061, 567,-32768,-32768,-32768, + 1046,-32768, 8381, 1079, 1085, 1088, 8037, 73, 476,-32768, + 1093, 1139, 1094,-32768, 1971, 9379, 2582, 3725,-32768,-32768, + 1135,-32768,-32768,-32768, 7135,-32768,-32768,-32768, 2757, 2757, +-32768, 3954, 1989,-32768,-32768, 818, 818, 818,-32768, 1095, + 1053, 1054,-32768, 9521, 9521,-32768,-32768,-32768, 1103, 661, + 8381,-32768,-32768,-32768, 572, 572, 831, 831,-32768, 2607, +-32768,-32768,-32768, 801, 6483, 8381, 8381, 8381, 8381, 6483, +-32768, 8381, 1104,-32768,-32768, 9611, 575, 8381,-32768, 143, +-32768,-32768,-32768,-32768,-32768,-32768, 1062,-32768, 1122,-32768, +-32768, 818,-32768,-32768,-32768, 66,-32768,-32768,-32768,-32768, +-32768, 92,-32768,-32768,-32768,-32768,-32768,-32768,-32768, 765, + 6226, 1082, 5075,-32768,-32768,-32768,-32768, 1115, 8381, 1121, +-32768,-32768,-32768, 1090,-32768,-32768, 238, 672,-32768, 772, + 572, 8642, 459, 774, 258,-32768,-32768,-32768,-32768,-32768, +-32768,-32768,-32768, 6483, 6483,-32768,-32768,-32768,-32768,-32768, + 74, 8381, 8381, 9521, 656, 656, 1124, 1126,-32768,-32768, +-32768,-32768, 269,-32768, 1091,-32768, 1084, 1087, 1097, 1098, +-32768, 9544, 6483, 575,-32768, 1089,-32768,-32768,-32768, 818, +-32768,-32768, 509, 509, 7417,-32768, 1175, 1137, 1100,-32768, + 1141,-32768, 8124, 8381,-32768, 7237,-32768, 1146,-32768,-32768, + 629,-32768, 656,-32768,-32768, 656, 8982, 8982, 6573,-32768, +-32768,-32768, 765, 6663, 6663,-32768,-32768, 6483,-32768, 9521, + 9521,-32768, 831, 831, 6483, 6483, 801, 1102, 8729,-32768, +-32768,-32768,-32768, 6483,-32768,-32768,-32768,-32768, 8124,-32768, +-32768,-32768,-32768,-32768,-32768, 5674,-32768,-32768, 1109, 234, + 3239, 9567, 7237,-32768,-32768, 5168, 48,-32768,-32768, 1149, +-32768, 1150,-32768,-32768,-32768, 1160, 1163,-32768,-32768,-32768, +-32768, 282, 1123,-32768, 1127, 765, 7327, 518, 295, 5272, +-32768, 572,-32768,-32768, 296,-32768, 5376,-32768, 1214, 1168, +-32768,-32768, 6483, 6483, 8381,-32768,-32768,-32768,-32768, 37, +-32768,-32768,-32768, 8381, 1176,-32768, 1177,-32768, 765, 656, + 7237,-32768,-32768,-32768, 1147, 201, 1181,-32768,-32768, 6753, + 6753,-32768,-32768, 1143,-32768, 5764, 1148,-32768,-32768, 831, +-32768, 1158, 8381, 1214, 1183, 1214, 1151, 1152,-32768, 317, + 5480,-32768, 1198,-32768, 1156, 246,-32768,-32768,-32768,-32768, +-32768,-32768,-32768, 1153,-32768, 1254, 1208, 7327, 7327, 6483, + 1355, 765,-32768, 353,-32768,-32768,-32768,-32768, 1167, 1170, +-32768, 1271, 1219,-32768,-32768,-32768,-32768, 1281, 1282,-32768 }; static const short yypgoto[] = {-32768, - 1191,-32768,-32768, 986, 7, 1310,-32768,-32768,-32768,-32768, --32768,-32768,-32768, 507,-32768,-32768,-32768,-32768,-32768,-32768, --32768, -770, 1196, 1207,-32768,-32768,-32768,-32768, 1201,-32768, --32768, 496, 135,-32768,-32768,-32768, 2838, -25,-32768, 1221, - 888, -999,-32768, -88, 178,-32768, 895,-32768, 169, 139, - -1101,-32768, -524, 1474, -99, 619,-32768,-32768, -714, 3947, - 43, -240, 2252, 2872, 825, 1176, 432,-32768,-32768,-32768, --32768, -273,-32768, -116, -94,-32768, 266, 17, -276, 132, - 75, -106, -109, -3, 1594, 27, 1371, -118, -752, 364, --32768, -82,-32768,-32768, 265,-32768,-32768,-32768,-32768,-32768, - 327,-32768, 677,-32768, 155,-32768,-32768, 730, 769, 74, --32768,-32768,-32768, 560, -272, 13, 1335, 1336,-32768,-32768, --32768,-32768,-32768, -141,-32768, 500, 716,-32768, 559, 418, - 497, -414,-32768,-32768,-32768,-32768,-32768,-32768, 960,-32768, - 501, 835, 582, 889, 2241, 1820, -368,-32768, 3695, -55, - 10,-32768, 4252, -90, 717,-32768, 3290,-32768,-32768, 3834, - -4, 245, -328, 1372, 3416, 871, -214,-32768, 4134,-32768, - -1157, -942, -343, 117,-32768, 553, -97, -122,-32768,-32768, --32768, -1137, -860, -1112,-32768,-32768,-32768,-32768,-32768,-32768, + 1165,-32768,-32768, 958, 7, 1283,-32768,-32768,-32768,-32768, +-32768,-32768,-32768, 486,-32768,-32768,-32768,-32768,-32768,-32768, +-32768, -773, 1169, 1174,-32768,-32768,-32768,-32768, 1166,-32768, +-32768, 478, 126,-32768,-32768,-32768, 4325, -30,-32768, 1204, + 844, -998,-32768, -96, 162,-32768, 171,-32768, 153, 124, + -980,-32768, -480, 242, 564, 630,-32768,-32768, -722, 3685, + 1316, -262, 2309, 2833, 804, 159, 431,-32768,-32768,-32768, +-32768, -278,-32768, -110, -90,-32768, 233, 34, -210, 83, + 11, -91, -121, -3, 1446, -82, 1348, -127, -674, 329, +-32768, -186,-32768,-32768, 180,-32768,-32768,-32768,-32768,-32768, + 1092,-32768, 634,-32768, 122,-32768,-32768, 821, 742, 14, +-32768,-32768,-32768, 526, -285, 12, 1299, 1300,-32768,-32768, +-32768,-32768,-32768, -131,-32768, 473, 686,-32768, 533, 394, + 469, -411,-32768,-32768,-32768,-32768,-32768,-32768, 939,-32768, + 482, 829, 573, 857, 1683, 1544, -371,-32768, 1375, 0, + 1,-32768, 4129, -99, 646,-32768, 3274,-32768,-32768, 3935, + -4, 198, -327, 1336, 3574, 852, -188,-32768, 1912,-32768, + -1147, -942, -321, 101,-32768, 539, -106, -94,-32768,-32768, +-32768, -1132, -932, -1108,-32768,-32768,-32768,-32768,-32768,-32768, -32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768,-32768, --32768,-32768,-32768,-32768,-32768, -37,-32768,-32768,-32768,-32768, --32768, -425, 86,-32768, 90,-32768, -354, -133,-32768,-32768, - -293, 1052, -286,-32768,-32768, 40, 530,-32768, 57,-32768, +-32768,-32768,-32768,-32768,-32768, -43,-32768,-32768,-32768,-32768, +-32768, -421, 70,-32768, 69,-32768, -369, -132,-32768,-32768, + -258, 1015, -247,-32768,-32768, 60, 500,-32768, 127,-32768, -260 }; -#define YYLAST 9897 +#define YYLAST 9739 static const short yytable[] = { 66, - 46, 323, 525, 368, 677, 600, 557, 85, 351, 351, - 30, 533, 590, 559, 195, 85, 96, 315, 318, 103, - 103, 84, 103, 642, 536, 468, 179, 556, 66, 123, - 362, 291, 97, 232, 352, 347, 640, 359, 921, 150, - 412, 66, 195, 403, 404, 395, 353, 85, 1218, 960, - 1113, 1234, 1150, 8, 85, 505, -124, 834, 834, 505, - 143, 84, 505, -1, 1256, 196, 85, 1225, 75, 78, - 310, 345, 85, 96, 1263, 128, 557, 872, 44, -2, - 603, 655, 85, 559, 7, 8, 76, 513, 525, 287, - 150, 85, 77, 85, 95, 674, 103, 302, 342, 308, - 103, 189, 93, 103, 103, 103, 426, 122, 674, 618, - 1265, 301, 343, 1251, 1275, 66, 46, 150, 66, 311, - -473, 165, 19, -473, 429, 604, 835, 1301, 100, 100, - 605, 697, 1114, 363, 22, 150, 150, 150, 331, 1117, - 1278, 1095, 344, 348, 1317, 1057, 82, 1305, 566, 781, - 1150, 286, 1266, 88, 619, 1038, 190, 784, 427, 620, - 560, 150, 675, 606, 26, 339, 698, 100, -473, 513, - 966, -473, 713, -473, 89, 1157, 21, 93, 93, 66, - 417, 396, 387, -473, 100, 73, 176, 427, 1073, 103, - 514, 8, 621, 362, 44, 425, 349, 401, 538, 429, - 515, -473, -473, 529, 1054, -700, -473, 277, 90, 136, - 516, -700, 423, 517, 518, -473, 93, 8, 967, 295, - 297, 1278, 1278, 351, 351, 599, 85, 436, 165, 195, - 277, 21, 74, 93, 502, 165, 165, 1104, 190, 1110, - 93, 312, 75, 188, 595, 758, 1178, 530, 597, 598, - 596, 582, 8, 137, 138, 759, 581, 368, 416, 165, - 76, 533, 190, 362, 78, 310, 93, 85, 361, 760, - 100, 512, 513, 436, 436, 527, 403, 404, 99, 329, - 768, 150, 188, -230, 362, 100, 644, 770, 427, 315, - 318, 639, 583, 900, 455, 85, 363, 456, 390, 21, - 457, 584, 537, 165, 404, 603, 465, 678, 875, 103, - 193, 1230, 103, 1113, 311, 504, 697, 103, 646, 93, - 1113, 85, 96, 824, 769, 655, 330, -230, -230, 193, - 1310, 771, 21, 75, 93, 884, 585, 712, 97, 695, - 1153, -224, 391, 392, 1080, 425, 434, 193, 166, 167, - 604, 76, 165, -696, 679, 605, 435, 150, 66, 150, - 150, 527, 1080, 7, 100, 66, 363, 825, 1260, 1203, - 570, 150, 1311, 150, 1113, 150, 150, 150, 610, 118, - 614, 616, 885, 150, -231, 454, 119, 363, 606, 150, - 461, 1081, 150, 425, 193, 1114, 747, -103, 749, 750, - 95, 19, 1114, 1024, 1025, 85, 99, 425, 133, 1188, - 362, 150, 66, 22, 66, 417, 1204, 362, 134, 85, - 945, 160, 161, 1271, 1332, 1080, 1307, 12, -231, -231, - 799, 554, 664, 943, 1080, 190, 7, 506, 165, 507, - 193, 19, -225, 26, 647, 85, 85, 85, 85, 183, - 17, 21, 1080, 22, 7, 8, 1114, 288, 113, 513, - 1026, 680, 502, 826, 1348, 140, 1333, 290, 165, 165, - 1272, 75, 1282, 351, 19, 141, 463, 7, 8, 828, - -102, 1288, 1186, 26, -224, 821, 22, 815, 142, 76, - 703, 464, 19, 416, 590, 85, 165, 436, 833, 1327, - 657, 554, 362, 697, 22, 1214, 658, 827, 362, 436, - 436, 1349, 527, 363, 557, 19, 508, 754, 188, 66, - 363, 559, 361, 829, 533, 403, 429, 22, 193, 368, - 179, 755, 463, 787, 26, 556, 320, 536, 655, 113, - 113, 113, 78, 79, 168, 169, 170, 561, 324, 1215, - 150, 85, 193, 468, 321, 681, 362, 26, 78, 79, - 1062, 756, 1053, -287, 865, 84, 298, 299, 886, -287, - 1279, 616, 696, 113, 171, 699, 425, 788, 789, 235, - 705, 706, 707, 708, 709, 78, 310, 1135, 1136, 1137, - 21, 187, 80, 172, 277, 127, -508, 883, 722, -225, - 719, 188, 150, 150, 847, 363, 21, 754, 80, 81, - 847, 363, 188, -700, 1280, -700, -700, 7, 506, 340, - 677, 755, -700, 388, 389, 75, 150, 150, 165, 150, - 751, 1097, 128, 1088, 1083, 311, 373, 173, 174, 175, - 99, 385, 302, 76, -700, -700, -700, 698, -700, 85, - -700, 756, 636, 425, 368, 19, 923, 100, 847, 363, - 808, 645, 241, -700, -288, -700, -700, 22, 410, 934, - -288, 935, -700, 100, 75, 809, 21, 436, 160, 161, - 193, 362, 188, 1129, 12, 362, 425, 436, 436, 436, - 811, 424, 76, 430, -700, -700, 386, 26, -700, 432, - -700, 362, 188, 876, 21, 433, 93, 17, 878, 879, - 1058, 1059, 881, 1061, 439, 698, -27, 165, 434, -27, - 21, 431, 93, 397, 398, 963, 719, 964, 435, 965, - 571, -27, 188, 333, 758, 334, 13, 14, 362, 335, - 1159, 1160, 195, 115, 759, 362, 446, 85, 890, 891, - 892, 447, 315, 318, 1176, 165, 193, 450, 760, 315, - 318, 572, 449, 573, 451, 574, 452, 575, 436, 453, - 436, 193, 13, 14, 1190, 1191, 336, 85, 337, 13, - 14, 436, 338, 85, 363, 66, 66, 66, 363, 505, - 489, 490, 542, 949, 361, 1032, 1033, 545, 1033, 1078, - 1079, -81, 550, 85, 363, 85, 930, -81, -80, 1342, - 1343, 113, 113, 113, -80, 531, 8, 388, 1180, 7, - 8, 1222, 544, 11, 115, 115, 115, 547, 407, 548, - 408, 567, 455, 456, 409, 549, 150, 150, 150, 150, - 847, 363, 397, 1181, 150, 847, 847, 847, 363, 241, - 532, 388, 1187, 19, 442, 445, 349, 19, 115, 564, - 513, 427, 85, 21, -695, 93, 601, 21, 602, 22, - 1313, 1314, 150, 617, 70, 103, 626, 66, 417, 85, - 627, 607, 87, 920, 425, 425, 633, 425, 491, 685, - 98, 608, 455, 456, 104, 104, 641, 104, 686, 26, - 690, 516, 691, 70, 609, 518, 710, 820, 8, 648, - 711, 713, 1021, 722, 104, 766, 70, 767, 780, 361, - 436, 436, 87, 436, 782, 492, 493, 784, 801, 98, - 494, 495, 496, 497, 800, 649, 810, 455, 456, 554, - 650, 98, 8, 868, 812, -228, 814, 98, 816, 698, - 832, 817, 818, 66, 417, 21, 416, 93, 819, 857, - 823, 859, 860, 1162, 861, 104, 98, 862, 968, 649, - 866, 104, 864, 1063, 869, 104, 863, 867, 104, 104, - 104, 871, 292, 296, 877, 150, 66, 150, 880, 21, - 70, 93, 104, 70, 13, 14, 882, 1017, 399, 150, - 150, -332, 150, 887, 888, 893, 1103, 904, 1109, 894, - 104, 104, 104, 905, 898, 681, 899, 906, 901, 902, - -700, 903, -700, -700, -332, -332, 907, -332, 461, -700, - 66, 417, 416, 908, -101, 910, 104, 159, 160, 161, - 113, 911, 913, 557, 12, 1048, 113, 914, 1199, 1200, - 1346, -700, -700, 400, 70, -700, 915, -700, 916, 918, - 1233, 917, 919, 932, 104, 165, 1162, 17, 929, 1131, - 1132, 931, 594, 933, 402, 160, 161, 940, 938, 939, - 947, 12, 834, 100, 953, 948, 11, 944, 1010, 188, - 950, 193, 315, 318, 113, 961, 115, 115, 115, 646, - 1048, 98, 104, 847, 17, 1249, 1008, 1023, 1014, 416, - 1039, 1041, 8, 92, 10, 11, 1042, 1096, 356, 1043, - 12, 1044, 1050, 513, 486, 487, 488, 489, 490, 1162, - 21, 1060, 93, 1064, 1082, 15, 1055, 425, 425, 16, - 1056, 959, 98, 17, 514, 1065, 1182, 1066, 104, 104, - 70, 1069, 1087, 459, 515, 535, 104, 659, 660, 21, - 1068, 93, 1162, 1070, 516, 1071, 1195, 517, 518, 1074, - 98, 1300, 1075, 1138, 1076, 1090, 1091, 1092, 847, 847, - 847, 1099, 1098, 1115, 104, 425, 1101, 104, 425, 1122, - 1123, 1015, 104, 193, 1124, 19, 98, 1128, 661, 1149, - 1022, 357, 112, 1306, 1154, 21, 1155, 22, 1173, 1036, - 1169, 98, 1158, 1175, 662, 1347, 1201, 1177, 1202, 140, - 1205, 1206, 150, 1213, 1219, 455, 456, 1207, 1208, 141, - 362, 1269, 104, 70, 104, 104, 70, 26, 1209, 1220, - 70, 1221, 663, 1258, 1223, 1231, 104, 1247, 104, 1257, - 104, 104, 104, 1267, 1268, 1273, 1291, 1270, 104, 1295, - 1304, 1274, 7, 8, 104, 1309, 185, 104, 1080, 628, - 1312, 1320, 1315, 1318, 113, 113, 113, 1323, 1325, 1339, - 98, 113, 113, 113, 316, 319, 104, 70, 1326, 70, - 1329, 1341, 425, 1331, 98, 1337, 1350, 1286, 1351, 165, - 19, 7, 100, 513, 1352, 11, 1353, 1355, 1356, 325, - 21, 5, 22, 569, 955, 327, 461, 112, 962, 306, - 98, 98, 98, 98, 607, 115, 328, 1212, 1217, 1238, - 346, 115, 85, 363, 608, 459, 772, 1138, 459, 19, - 700, 702, 26, 704, 516, 1125, 1126, 609, 518, 21, - 714, 22, 1168, 100, 1106, 858, 185, 1246, 1133, 1134, - 831, 459, 954, 24, 889, 726, 1018, 124, 125, 870, - 98, 958, 104, 25, 48, 1072, 672, 803, 1035, 115, - 1034, 26, 952, 86, 104, 104, 27, 70, 753, 1003, - 48, 748, 1302, 513, 798, 1322, 8, 765, 10, 11, - 21, 1324, 93, 48, 12, 535, 484, 485, 486, 487, - 488, 489, 490, 1037, 514, 0, 155, -232, 0, 15, - 0, 624, 0, 16, 515, 104, 87, 17, 0, 186, - 0, 0, -232, -232, 516, 0, 0, 517, 518, -232, - 0, 230, 0, 21, 0, 93, 279, 48, 0, 0, - 0, -232, 0, 0, 0, 0, 1198, 0, 279, 279, - 0, 0, -232, -232, 0, -232, 155, -232, 554, 279, - 0, 0, 0, 0, 0, 0, 0, 104, 104, 70, - 752, 0, 0, 0, 922, 798, 0, 0, 0, 8, - 48, 10, 185, 155, 0, -232, -232, 12, 0, -232, - -232, 104, 104, 0, 104, 0, 0, 365, 0, -232, - 0, 0, 15, 0, 0, 0, 16, 0, 0, 0, - 17, 0, 1240, 1241, 98, 1242, 1243, 0, 0, 0, - 0, 0, 0, 70, 0, 0, 21, 0, 93, 113, - 0, 957, 0, 0, 413, 0, 7, 8, 92, 10, - 11, 0, 104, 0, 48, 12, 316, 319, 0, 115, - 115, 115, 104, 104, 104, 0, 115, 115, 115, 0, - 15, 0, 0, 0, 16, 0, 0, 0, 17, -425, - 0, 0, 0, 0, 19, 0, 1009, 0, 0, 0, - 0, 0, 0, 0, 21, 0, 22, 0, 0, 676, - 0, 186, 0, 414, 100, 0, 160, 161, 24, 0, - 358, 0, 12, 0, 113, 113, 113, 0, 25, 0, - 0, 0, 98, 0, 0, 0, 26, 0, 0, 279, - 0, 27, 1319, 0, 0, 17, 0, 0, 0, 1046, - 1049, 0, 230, 104, 513, 104, -425, 0, 0, 0, - 186, 21, 98, 93, 927, 0, 104, 0, 98, 0, - 798, 798, 798, 0, 229, 514, 0, 0, 535, 278, - 555, 0, 0, 0, 0, 515, 0, 0, 98, 0, - 98, 278, 278, 0, 0, 516, 459, 0, 524, 518, - 0, 0, 278, 98, 0, 1049, 48, 0, 0, 796, - 0, 0, 0, 7, 8, 0, 0, 0, 0, 0, - 0, 104, 104, 104, 104, 70, 0, 0, 0, 104, - 798, 798, 798, 0, 0, 0, 0, 0, 0, 0, - 364, 100, 0, 155, 427, 0, 186, 98, 0, 0, - 555, 19, 0, 0, 0, 0, 459, 104, 0, 0, - 104, 21, 70, 22, 98, 0, 139, 0, 0, 0, - 1016, 365, 0, 0, 0, 140, 0, 0, 0, 1142, - 0, 513, 0, 0, 1147, 141, 0, 0, 21, 0, - 93, 0, 0, 26, 112, 0, 0, 155, 142, 48, - 854, 459, 514, 0, 682, 104, 104, 0, 104, 0, - 0, 0, 515, 0, 0, 0, 0, 0, 0, 0, - 0, 279, 516, 0, 279, 517, 518, 358, 0, 279, - 682, 682, 682, 682, 115, 0, 0, 0, 70, 0, - 0, 0, 8, 279, 10, 11, 0, 279, 112, 0, - 12, 0, 0, 101, 105, 0, 0, 0, 0, 1192, - 1193, 0, 278, 0, 0, 15, 0, 0, 0, 16, - 104, 70, 104, 17, 358, 229, 0, 0, 0, 279, - 230, 0, 796, 0, 104, 104, 1094, 104, 1211, 21, - 0, 93, 498, 0, 0, 0, 0, 555, 0, 0, - 231, 0, 0, 364, 365, 280, 0, 0, 0, 115, - 115, 115, 0, 7, 100, 70, 0, 280, 280, 0, - 0, 0, 358, 0, 0, 0, 499, 0, 280, 0, - 7, 8, 0, 1239, 11, 0, 0, 314, 317, 0, - 1244, 1245, 0, 0, 0, 1143, 1144, 1145, 1146, 1250, - 0, 19, 0, 0, 0, 0, 0, 1152, 0, 0, - 0, 21, 0, 22, 0, 0, 366, 0, 19, 376, - 378, 513, 0, 364, 0, 108, 316, 946, 21, 358, - 22, 358, 358, 0, 0, 109, 0, 0, 798, 555, - 0, 1167, 843, 26, 364, 365, 0, 0, 110, 1174, - 0, 0, 844, 0, 0, 0, 0, 358, 1298, 1299, - 26, 0, 516, 358, 0, 845, 518, 482, 483, 484, - 485, 486, 487, 488, 489, 490, 0, 278, 0, 316, - 319, 0, 0, 0, 0, 0, 316, 319, 0, 0, - 0, 0, 0, 555, 278, 0, 0, 278, 0, 0, - 0, 0, 278, 278, 278, 278, 278, 0, 0, 0, - 0, 0, 0, 798, 798, 798, 278, 0, 358, 0, - 278, 0, 0, 1224, 413, 1344, 7, 8, 92, 10, - 11, 316, 946, 0, 0, 12, 0, 0, 280, 459, - 0, 0, 0, 0, 1224, 1224, 0, 0, 358, 0, - 15, 231, 278, 229, 16, 0, 0, 104, 17, -424, - 0, 0, 0, 0, 19, 0, 0, 0, 0, 1224, - 364, 0, 0, 0, 21, 0, 22, 364, 0, 366, - 0, 0, 682, 414, 0, 0, 924, 0, 24, 0, - 0, 6, 0, 7, 8, 9, 10, 11, 25, 0, - 0, 0, 12, 0, 0, 8, 26, 10, 11, 0, - 0, 27, 682, 12, 0, 13, 14, 15, 555, 0, - 0, 16, 365, 0, 0, 17, -424, 0, 15, 18, - 358, 19, 16, 0, 1303, 20, 17, 0, 555, 0, - 956, 21, 0, 22, 0, 0, 23, 0, 0, 366, - 726, 726, 21, 0, 93, 24, 0, 0, 0, 631, - 632, 0, 364, 1321, 0, 25, 992, 98, 364, 0, - 366, 0, 0, 26, 0, 555, 0, 0, 27, 0, - 0, 0, 365, 0, 28, 29, 0, 7, 100, 358, - 0, 185, 0, 0, 0, 0, 279, 0, 0, 0, - 0, 0, 358, 280, 358, 0, 0, 0, 0, 0, - 0, 0, 48, 0, 682, 0, 364, 0, 0, 0, - 280, 0, 0, 280, 0, 19, 0, 279, 280, 280, - 280, 280, 280, 0, 0, 21, 0, 22, 0, 0, - 0, 0, 280, 854, 0, 0, 280, 0, 0, 24, - 413, 0, 7, 8, 92, 10, 11, 0, 358, 25, - 358, 12, 358, 0, 0, 0, 0, 26, 0, 194, - 0, 0, 27, 0, 0, 0, 15, 0, 280, 231, - 16, 0, 0, 0, 17, -427, 0, 269, 48, 0, - 19, 0, 0, 773, 775, 0, 366, 0, 0, 0, - 21, 0, 22, 366, 0, 278, 0, 0, 0, 414, - 269, 0, 0, 0, 24, 0, 0, 322, 0, 316, - 319, 155, 0, 992, 25, 0, 0, 0, 0, 0, - 992, 0, 26, 0, 0, 278, 354, 27, 0, 0, - 0, 364, 0, 0, 0, 364, 0, 0, 360, 0, - 0, 394, -427, 0, 0, 0, 0, 0, 0, 0, - 0, 364, 0, 0, 0, 48, 413, 0, 7, 8, - 92, 10, 11, 0, 7, 8, 0, 12, 427, 0, - 0, 0, 0, 0, 0, 0, 841, 842, 366, 0, - 0, 0, 15, 0, 366, 0, 16, 0, 364, 0, - 17, -426, 0, 0, 0, 364, 19, 0, 0, 0, - 0, 0, 19, 0, 0, 513, 21, 992, 22, 278, - 0, 676, 21, 0, 22, 414, 0, 0, 7, 8, - 24, 0, 0, 0, 0, 0, 607, 278, 0, 0, - 25, 0, 366, 0, 0, 0, 608, 0, 26, 0, - 278, 0, 0, 27, 26, 0, 516, 0, 0, 609, - 518, 0, 8, 92, 10, 11, 19, 0, -426, 513, - 12, 462, 0, 0, 0, 0, 21, 0, 22, 0, - 0, 0, 0, 0, 0, 15, 0, 0, 0, 16, - 607, 992, 6, 17, 7, 8, 9, 10, 11, 1226, - 608, 0, 992, 12, 0, 0, 0, 0, 26, 21, - 516, 93, 0, 609, 518, 279, 0, 0, 15, 0, - 1226, 1226, 16, 0, 0, 0, 17, 7, 8, 0, - 0, 280, 19, 0, 0, 0, 326, 0, 0, 0, - 0, 358, 21, 0, 22, 1226, 0, 23, 0, 0, - 0, 0, 992, 0, 593, 360, 24, 0, 0, 992, - 0, 280, 992, 0, 0, 19, 25, 366, 0, 773, - 775, 366, 0, 0, 26, 21, 0, 22, 0, 27, - 1102, 0, 0, 992, 634, 28, 992, 366, 0, 140, - 637, 0, 0, 992, 0, 0, 0, 0, 0, 141, - 0, 0, 360, 0, 0, 0, 0, 26, 0, 0, - 0, 0, 142, 8, 92, 10, 11, 992, 0, 0, - 0, 12, 1004, 1005, 366, 656, 0, 0, 0, 1004, - 1005, 366, 992, 0, 692, 693, 15, 694, 358, 0, - 16, 0, 0, 0, 17, 280, 0, 992, 0, 0, - 360, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 21, 0, 93, 280, 992, 992, 0, 555, 7, 100, - 0, 0, 11, 0, 269, 0, 280, 593, 94, 0, - 723, 724, 0, 728, 729, 730, 731, 732, 733, 734, - 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, - 745, 746, 0, 0, 358, 0, 19, 360, 0, 360, - 360, 0, 0, 0, 0, 0, 21, 0, 22, 0, - 785, 786, 229, 0, 8, 785, 10, 0, 0, 0, - 108, 0, 12, 0, 0, 360, 0, 0, 278, 0, - 109, 360, 0, 229, 229, 0, 0, 15, 26, 0, - 0, 16, 0, 110, 0, 17, 805, 807, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 229, 0, - 0, 21, 0, 93, 0, 0, 0, 0, 0, 0, - 7, 8, 92, 10, 11, 0, 0, 356, 0, 12, - 0, 7, 8, 152, 10, 153, 360, 0, 0, 0, - 12, 839, 840, 593, 15, 0, 0, 0, 16, 83, - 0, 849, 17, 0, 0, 15, 0, 856, 19, 16, - 0, 83, 83, 17, 83, 0, 360, 0, 21, 19, - 22, 0, 0, 0, 0, 42, 0, 593, 0, 21, - 0, 22, 380, 0, 154, 0, 0, 0, 0, 178, - 0, 0, 381, 24, 0, 42, 42, 0, 111, 0, - 26, 873, 0, 25, 42, 382, 0, 0, 0, 0, - 357, 26, 0, 874, 0, 42, 27, 42, 0, 0, - 7, 8, 159, 160, 161, 0, 0, 0, 0, 12, - 364, 0, 0, 0, 0, 0, 0, 191, 83, 0, - 83, 83, 83, 0, 0, 83, 83, 83, 360, 0, - 0, 0, 17, 0, 0, 0, 0, 0, 19, 0, - 0, 513, 0, 0, 0, 0, 42, 0, 21, 909, - 22, 0, 42, 0, 191, 0, 42, 0, 0, 111, - 111, 111, 140, 0, 0, 0, 0, 0, 231, 0, - 0, 42, 141, 42, 42, 0, 0, 0, 925, 926, - 26, 928, 631, 632, 280, 1108, 593, 360, 0, 231, - 231, 42, 42, 111, 0, 0, 0, 0, 0, 0, - 360, 191, 360, 0, 0, 0, 0, 942, 0, 0, - 0, 83, 0, 0, 231, 0, 0, 42, 0, 0, - 0, 0, 0, 0, 0, 7, 8, 159, 160, 161, - 0, 951, 0, 0, 12, 42, 0, 0, 0, 0, - 0, 0, 0, 593, 0, 42, 0, 0, 0, 83, - 0, 0, 0, 0, 0, 0, 360, 17, 360, 0, - 360, 0, 0, 19, 0, 0, 513, 0, 1007, 100, - 0, 160, 161, 21, 0, 22, 0, 12, 0, 0, - 1011, 1012, 1013, 0, 0, 0, 0, 607, 593, 0, - 0, 0, 0, 83, 0, 83, 83, 608, 0, 0, - 17, 0, 1019, 1020, 0, 26, 0, 516, 0, 513, - 615, 518, 0, 0, 0, 0, 21, 121, 93, 7, - 8, 92, 10, 11, 0, 83, 0, 509, 12, 0, - 514, 83, 0, 0, 83, 191, 366, 42, 0, 83, - 515, 593, 593, 15, 0, 1051, 0, 16, 0, 0, - 516, 17, 0, 517, 518, 0, 0, 19, 0, 1067, - 0, 0, 0, 0, 0, 42, 0, 21, 42, 22, - 0, 0, 0, 42, 7, 8, 152, 10, 153, 0, - 0, 24, 0, 12, 0, 0, 0, 0, 0, 0, - 0, 25, 0, 0, 0, 0, 0, 593, 15, 26, - 0, 0, 16, 0, 27, 0, 17, 0, 0, 1089, - 0, 0, 19, 42, 42, 42, 42, 0, 0, 0, - 0, 42, 21, 0, 22, 0, 0, 42, 0, 42, - 0, 111, 111, 111, 0, 0, 24, 7, 8, 42, - 0, 11, 0, 1127, 0, 42, 25, 0, 42, 0, - 0, 0, 0, 83, 26, 0, 0, 1130, 0, 27, - 0, 0, 0, 0, 0, 0, 0, 42, 42, 0, - 42, 593, 0, 64, 0, 19, 593, 0, 1148, 0, - 0, 8, 152, 10, 153, 21, 0, 22, 1156, 12, - 0, 0, 0, 64, 64, 0, 116, 0, 0, 140, - 0, 0, 64, 0, 15, 0, 0, 0, 16, 141, - 0, 0, 17, 64, 0, 64, 0, 26, 0, 83, - 0, 0, 142, 0, 0, 0, 0, 0, 21, 83, - 93, 83, 83, 7, 8, 92, 10, 11, 0, 360, - 622, 0, 12, 0, 0, 0, 0, 0, 0, 0, - 0, 593, 593, 0, 0, 0, 0, 15, 0, 1196, - 1197, 16, 0, 509, 64, 17, 0, 0, 0, 0, - 64, 19, 0, 178, 64, 795, 0, 116, 116, 116, - 593, 21, 0, 22, 0, 0, 0, 0, 0, 64, - 0, 64, 64, 0, 0, 24, 8, 92, 10, 11, - 0, 1228, 1345, 0, 12, 25, 42, 0, 0, 64, - 64, 116, 0, 26, 0, 0, 0, 0, 27, 15, - 0, 0, 117, 16, 0, 593, 0, 17, 0, 0, - 0, 0, 593, 593, 0, 64, 360, 0, 0, 151, - 0, 593, 0, 21, 0, 93, -306, 8, -306, 10, - 185, 0, 0, 64, 0, 12, 0, 0, 42, 42, - 111, 0, 0, 64, 0, 0, 853, 0, 0, 0, - 15, 0, 0, 0, 16, 0, 0, 0, 17, 0, - 0, 0, 42, 42, -306, 42, 0, 513, 0, 0, - 151, 0, 0, 0, 21, 0, 93, 0, 0, 83, - 593, 593, 360, 117, 117, 117, 0, 0, 514, 83, - 83, 83, 0, 0, 111, 0, 0, 151, 515, 0, - 0, 0, 0, 0, 0, 0, -306, 0, 516, 0, - 0, 517, 518, 0, 0, 151, 151, 384, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 795, 0, - 1024, 100, 0, 0, 534, 64, 0, 0, 0, 0, - 0, 151, 0, 0, 0, 0, 0, 593, 0, 0, - 0, 0, 0, 0, 0, 0, 7, 8, 159, 160, - 161, 0, 0, 64, 0, 12, 64, 0, 19, 0, - 83, 64, 83, 0, 0, 0, 0, 0, 21, 0, - 22, 0, 0, 83, 0, 0, 0, 1026, 17, 0, - 589, 0, 24, 0, 19, 0, 0, 513, 0, 0, - 0, 0, 25, 0, 21, 0, 22, 437, 0, 0, - 26, 64, 64, 64, 64, 27, 0, 0, 607, 64, - 0, 795, 795, 795, 0, 64, 0, 64, 608, 116, - 116, 116, 0, 0, 0, 0, 26, 64, 516, 0, - 0, 609, 518, 64, 0, 0, 64, 0, 0, 0, - 0, 0, 0, 521, 521, 521, 0, 0, 0, 0, - 0, 151, 0, 0, 0, 64, 64, 0, 64, 0, - 0, 0, 42, 42, 111, 111, 111, 83, 191, 0, - 42, 853, 853, 853, 0, 0, 659, 8, 152, 10, - 153, 0, 0, 0, 0, 12, 479, 480, 481, 482, - 483, 484, 485, 486, 487, 488, 489, 490, 42, 0, - 15, 42, 0, 42, 16, 0, 0, 0, 17, 0, - 0, 0, 83, 83, 19, 83, 795, 795, 795, 0, - 0, 0, 0, 0, 21, 0, 22, 611, 0, 611, - 611, 521, 0, 662, 0, 0, 0, 0, 24, 0, - 0, 151, 0, 151, 0, 384, 384, 384, 25, 8, - 92, 10, 11, 151, 0, 356, 26, 12, 0, 151, - 0, 27, 151, 797, 0, 0, 0, 0, 0, 0, - 191, 0, 15, 0, 0, 0, 16, 0, 0, 42, - 17, 151, 0, 0, 377, 379, 383, 0, 0, 513, - 0, 0, 0, 0, 64, 0, 21, 0, 93, 0, - 0, 0, 0, 7, 100, 0, 0, 427, 0, 0, - 514, 42, 42, 42, 7, 8, 0, 0, 185, 0, - 515, 0, 0, 0, 0, 42, 42, 149, 42, 0, - 516, 0, 0, 517, 518, 0, 0, 0, 357, 0, - 0, 19, 0, 0, 0, 0, 64, 64, 116, 192, - 0, 21, 19, 22, 855, 0, 42, 0, 0, 0, - 0, 0, 21, 0, 22, 24, 0, 761, 192, 0, - 64, 64, 0, 64, 0, 25, 140, 0, 149, 521, - 521, 0, 521, 26, 0, 0, 141, 0, 27, 521, - 0, 0, 0, 0, 26, 0, 0, 0, 0, 142, - 0, 0, 116, 0, 0, 149, 0, 0, 0, 0, - 0, 0, 0, 7, 8, 0, 10, 440, 234, 235, - 611, 236, 12, 149, 149, 149, 0, 0, 0, 853, - 0, 0, 0, 393, 0, 0, 797, 15, 237, 238, - 239, 16, 0, 240, 0, 17, 0, 241, 242, 149, - 243, 19, 244, 245, 0, 0, 246, 247, 248, 249, - 250, 21, 0, 22, 0, 0, 0, 0, 0, 0, - 0, 0, 611, 611, 848, 0, 0, 0, 0, 192, - 848, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 256, 257, 258, 7, 8, 151, 151, 259, 151, - 0, 0, 260, 0, 853, 853, 853, 0, 0, 0, - 0, 0, 0, 0, 261, 0, 0, 0, 0, 0, - 629, 0, 630, 0, 377, 379, 383, 0, 384, 797, - 797, 797, 19, 0, 0, 0, 0, 534, 643, 0, - 0, 0, 21, 0, 22, 0, 0, 521, 42, 0, - 0, 0, 0, 0, 0, 0, 140, 437, 437, 437, - 669, 0, 589, 0, 0, 0, 141, 192, 0, 149, - 0, 0, 0, 0, 26, 0, 0, 0, 0, 142, - 64, 64, 116, 116, 116, 0, 0, 0, 64, 855, - 855, 855, 0, 0, 0, 0, 0, 8, 0, 10, - 185, 0, 0, 0, 0, 12, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 64, 0, 0, 64, - 15, 64, 0, 0, 16, 0, 0, 0, 17, 0, - 0, 0, 0, 0, 797, 797, 797, 513, 521, 0, - 521, 0, 0, 0, 21, 149, 93, 149, 149, 0, - 0, 521, 0, 0, 0, 521, 521, 521, 514, 149, - 0, 149, 0, 149, 149, 149, 0, 0, 515, 0, - 0, 149, 0, 0, 519, 519, 519, 149, 516, 0, - 149, 517, 518, 477, 478, 479, 480, 481, 482, 483, - 484, 485, 486, 487, 488, 489, 490, 64, 0, 149, - 0, 0, 0, 0, 0, 62, 611, 611, 848, 848, - 848, 0, 0, 0, 611, 848, 848, 848, 0, 0, - 0, 0, 0, 0, 0, 102, 106, 0, 0, 64, - 64, 64, 7, 8, 126, 0, 11, 0, 0, 0, - 0, 0, 151, 64, 64, 0, 64, 158, 0, 0, - 0, 377, 379, 383, 0, 0, 0, 0, 519, 383, - 519, 519, 519, 7, 8, 0, 0, 427, 0, 0, - 19, 0, 0, 0, 64, 629, 630, 0, 643, 0, - 21, 0, 22, 0, 0, 0, 0, 0, 0, 0, - 761, 761, 0, 761, 380, 0, 0, 0, 0, 0, - 0, 19, 307, 0, 381, 0, 309, 383, 0, 0, - 192, 21, 26, 22, 0, 0, 0, 382, 0, 0, - 0, 62, 0, 0, 332, 140, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 141, 0, 0, 149, 0, - 0, 102, 106, 26, 0, 0, 0, 855, 142, 0, - 0, 0, 0, 0, 0, 151, 0, 151, 0, 7, - 8, 522, 526, 528, 0, 0, 0, 0, 0, 611, - 611, 0, 611, 0, 0, 0, 0, 0, 0, 0, - 7, 8, 152, 10, 153, 422, 0, 0, 0, 12, - 149, 149, 846, 0, 0, 428, 0, 19, 846, 0, - 0, 0, 0, 0, 15, 0, 0, 21, 16, 22, - 519, 519, 17, 519, 149, 149, 0, 149, 19, 0, - 794, 380, 855, 855, 855, 0, 0, 0, 21, 0, - 22, 381, 0, 1105, 0, 0, 0, 0, 0, 26, - 0, 0, 24, 0, 382, 612, 846, 522, 526, 528, - 0, 519, 25, 0, 0, 0, 0, 0, 0, 0, - 26, 0, 0, 0, 0, 27, 64, 0, 0, 0, - 0, 0, 0, 384, 0, 0, 0, 1170, 0, 0, - 0, 0, 0, 0, 0, 629, 630, 377, 379, 383, - 0, 0, 0, 643, 377, 379, 383, 0, 0, 0, - 0, 0, 0, 519, 519, 519, 0, 0, 0, 0, - 0, 794, 0, 0, 0, 562, 0, 0, 563, 0, - 0, 1030, 0, 565, 469, 470, 471, 1171, 472, 473, - 474, 475, 476, 477, 478, 479, 480, 481, 482, 483, - 484, 485, 486, 487, 488, 489, 490, 0, 384, 384, - 384, 478, 479, 480, 481, 482, 483, 484, 485, 486, - 487, 488, 489, 490, 613, 0, 0, 0, 0, 0, - 0, 623, 0, 0, 0, 0, 0, 307, 519, 309, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 151, 0, 0, 428, 0, 774, 776, 473, - 474, 475, 476, 477, 478, 479, 480, 481, 482, 483, - 484, 485, 486, 487, 488, 489, 490, 670, 673, 0, - 422, 0, 0, 0, 149, 149, 149, 149, 846, 0, - 1006, 0, 149, 846, 846, 846, 0, 0, 526, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 629, 630, - 0, 643, 0, 0, 0, 0, 0, 0, 0, 0, - 149, 0, 0, 0, 0, 0, 0, 0, 0, 519, - 0, 519, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 519, 0, 0, 0, 794, 794, 794, 0, - 774, 776, 0, 0, 469, 470, 471, 0, 472, 473, + 46, 423, 465, 366, 673, 530, 321, 85, 314, 317, + 30, 586, 84, 553, 44, 85, 96, 638, 636, 103, + 103, 178, 103, 533, 350, 596, 915, 231, 66, 122, + 95, 97, 392, 400, 401, 349, 349, 351, 345, 149, + 554, 66, 955, 121, 360, 1107, 1212, 85, 1144, 409, + 1228, 556, 84, 830, 85, 1108, 502, 346, 502, 8, + 502, 164, 1111, 961, 88, 195, 85, 522, 1250, 194, + 830, 393, 85, 96, 599, 78, 309, 142, 1257, 651, + 424, 614, 85, 460, 165, 166, 290, 285, 286, 670, + 149, 85, 8, 85, 78, 309, 103, 194, 461, 307, + 103, 670, 420, 103, 103, 75, 100, 1259, 93, 554, + 347, 962, 100, 1269, 66, 46, 149, 66, 510, 600, + 556, 188, 831, 76, 601, 310, 615, -699, 300, 44, + 426, 616, 361, -699, 149, 149, 149, 82, 1272, 1295, + 73, 93, 100, 777, 310, 1144, 1299, 1089, 1311, 1260, + 577, 562, 522, 1033, 329, 93, 671, 602, 276, 21, + 149, 93, 693, 100, 617, 187, 709, 164, 1151, 557, + 294, 296, 100, 754, 164, 164, 1052, 175, 66, 414, + 1067, 276, 1219, 755, 337, 111, 750, 74, 103, 535, + 1049, 93, 340, 413, 422, -103, 75, 756, 164, 327, + 751, 384, -1, 510, 99, 867, 341, 360, 460, 653, + 21, 642, 93, 426, 76, 654, 398, -229, 359, 1272, + 1272, 93, 674, 558, 511, 85, 433, 499, 1245, 694, + 752, 1048, 311, 1224, 512, -2, 342, 593, 594, 159, + 160, 879, 164, 189, 513, 12, 328, 514, 515, 349, + 349, 595, 592, 530, 8, 366, 578, 8, 291, 295, + 1304, -229, -229, 192, 400, 401, 85, 315, 17, 675, + 509, 640, 433, 433, 524, -224, 360, 510, 314, 317, + 149, 100, 192, 194, 424, -124, 1074, -230, 880, 870, + 1254, 164, 401, 1172, 85, 361, 360, 579, 75, 111, + 192, 126, 1305, 93, 21, 1326, 580, 1107, 103, 526, + 1098, 103, 1104, 1074, 1107, 103, 76, 1108, 534, 85, + 96, 693, 651, 1197, 1108, 189, 301, 1147, 21, 187, + 93, -230, -230, 1075, 95, 97, 1265, 599, 127, 89, + 458, 581, 754, 422, 77, -225, 192, 1327, 1301, 894, + 1074, 1074, 755, 527, 100, 149, 66, 149, 149, 524, + 1182, 343, 708, 66, 361, 127, 756, 90, 1107, 149, + 1198, 149, 1074, 149, 149, 451, 164, 356, 1108, 811, + 149, 551, 600, 1266, 361, -695, 149, 601, 566, 149, + 422, 100, 192, 606, 11, 610, 612, 1276, 1282, 7, + 8, 21, 85, 93, 422, 164, 164, 1342, 149, 66, + 186, 66, 414, 939, 937, 431, 85, 297, 298, 1321, + 602, -285, 360, 99, 510, 432, 413, -285, 456, 360, + 764, 510, -699, 164, -699, -699, 117, 19, 21, 135, + 93, -699, 85, 85, 85, 85, 660, 385, 386, 22, + 551, 387, 511, 499, 1343, 783, 860, 112, 766, 187, + -286, 643, 512, -699, -699, -699, -286, -699, 693, -699, + 359, 189, 513, 804, 765, 514, 515, 820, 676, 26, + 192, 822, 118, 136, 137, 829, 7, 100, 805, 878, + 132, 586, 85, 133, 433, 388, 389, 349, 187, 784, + 785, 187, 767, 677, 192, 824, 433, 433, 100, 524, + 361, 424, 400, 360, 1180, 530, 66, 361, 553, 360, + 692, 821, 178, 695, 19, 823, 366, 465, 701, 702, + 703, 704, 705, 533, 651, 1091, 22, 315, 112, 112, + 750, 182, 276, 624, 99, 554, 718, 149, 85, 825, + 187, 1057, 1208, 84, 751, 21, 556, 93, 189, 7, + 503, 1273, 504, 287, 632, 164, 26, 360, 289, 431, + 881, 112, 422, 641, -27, 13, 14, -27, 747, 432, + -224, 7, 8, 356, 752, 612, 7, 8, 715, -27, + 394, 395, 78, 79, 7, 503, 1209, 19, 149, 149, + 842, 361, 318, 75, -81, 1274, 842, 361, 456, 22, + -81, 456, -102, 696, 698, 319, 700, 75, 673, 19, + -506, 76, 149, 149, 19, 149, 1077, 13, 14, 356, + 192, 22, 19, 240, 456, 76, 22, 234, 722, 505, + 21, -225, 80, 81, 22, 85, 331, 21, 332, 422, + 1082, 366, 333, 164, 842, 361, -80, 322, 426, 159, + 160, 26, -80, 187, 744, 12, 26, 8, 338, 10, + 761, 301, 114, 433, 26, 12, 407, 356, 807, 792, + 13, 14, 422, 433, 433, 433, 1027, 1028, 17, 1028, + 15, 164, 360, 371, 16, 421, 360, 427, 17, 357, + 78, 79, 167, 168, 169, 430, 192, 694, 158, 159, + 160, 75, 360, 715, 21, 12, 93, 486, 487, 871, + 1123, 192, 1072, 1073, 873, 874, 385, 1174, 876, 76, + 1053, 1054, 170, 1056, 356, 428, 356, 356, 17, 314, + 317, 359, 429, 85, 436, 314, 317, 443, 21, 444, + 80, 171, 446, 114, 114, 360, 1153, 1154, 447, 334, + 448, 335, 356, 111, 433, 336, 433, 449, 356, 849, + 1170, 450, 404, 85, 405, 502, 694, 433, 406, 85, + 361, 66, 66, 66, 361, 541, 114, 539, 567, 944, + 1184, 1185, 542, 194, 544, 172, 173, 174, 545, 85, + 361, 85, 546, 78, 309, 1129, 1130, 1131, 112, 112, + 547, 528, 8, 563, 885, 886, 887, 111, 347, 568, + -694, 569, 356, 570, 424, 571, 394, 1175, 385, 1181, + 914, 597, 149, 149, 149, 149, 598, 1216, 613, 149, + 842, 842, 842, 361, 622, 240, 529, 1336, 1337, 19, + 623, 792, 356, 310, 629, 70, 637, 85, 681, 21, + 718, 93, 682, 87, 439, 442, 359, 149, 1307, 1308, + 103, 98, 66, 414, 85, 104, 104, 686, 104, 422, + 422, 687, 422, 706, 70, 707, 551, 413, 483, 484, + 485, 486, 487, 100, 709, 104, 184, 70, 762, 13, + 14, 763, 776, 87, 778, 591, -330, 780, 796, 797, + 98, 399, 159, 160, 433, 433, 806, 433, 12, 808, + 810, 812, 98, 813, 814, 815, 921, 1016, 98, -330, + -330, 819, -330, 510, 356, 66, 66, 828, 1193, 1194, + 21, 17, 93, 1012, 852, 315, 104, 98, 66, 414, + 855, 635, 104, 862, 511, 963, 104, 856, 456, 104, + 104, 677, 857, 413, 512, 7, 100, 858, 861, 11, + 70, 866, 104, 70, 513, 872, 875, 514, 515, 877, + 149, 66, 149, 883, 882, 1156, 888, 889, 898, 642, + 104, 104, 104, 356, 149, 149, 892, 149, 315, 691, + 164, 893, 895, 19, 315, 111, 356, 896, 356, 694, + 897, 899, 900, 21, 901, 22, 104, 456, 1097, 902, + 1103, -101, 905, 114, 114, 66, 414, 24, 904, 907, + 1043, 1011, 908, 909, 70, 112, 912, 25, 910, 192, + 413, 112, 911, 923, 104, 26, 926, 913, 925, 315, + 27, 927, 932, 933, 7, 8, 743, 934, 745, 746, + 1227, 938, 356, 948, 356, 830, 356, 942, 8, 92, + 10, 11, 554, 943, 354, 945, 12, 314, 317, 956, + 1003, 98, 104, 1340, 1125, 1126, 1043, 1005, 1156, 112, + 795, 15, 19, 1300, 1009, 16, 1018, 842, 1034, 17, + 1036, 1037, 21, 1090, 22, -471, 1038, 138, -471, 1039, + 1055, 1045, 1059, 1050, 1064, 21, 139, 93, 1051, 1060, + 1076, 1061, 98, 1065, 1063, 1068, 140, 1069, 104, 104, + 70, 422, 422, 1081, 26, 532, 104, 1070, 1084, 141, + 1085, 192, 780, 1086, 817, 1093, 1092, 1088, 1109, 1095, + 98, 1156, 1116, -471, 1117, 1118, -471, 355, -471, 1132, + 1176, 590, 1122, 1143, 104, 1149, 1148, 104, -471, 1163, + 1167, 104, 842, 842, 842, 98, 1169, 1171, 1199, 422, + 1189, 1195, 422, 1196, 1156, 1200, -471, -471, 1201, 1213, + 98, -471, 1214, 1207, 8, 644, 1217, 1152, 1202, 1203, + -471, 1225, 1215, 1241, 1261, 1262, 1137, 1138, 1139, 1140, + 1251, 104, 70, 104, 104, 70, 149, 1263, 1146, 70, + 1264, 645, 1285, 1289, 1267, 104, 646, 104, 1268, 104, + 104, 1298, 1074, 164, 1303, 1306, 104, 1341, 1317, 360, + 1331, 21, 104, 93, 1309, 104, 8, 863, 1314, 1312, + 114, 1161, 1319, 1320, 1252, 1323, 114, 1325, 98, 1168, + 849, 458, 1333, 1335, 104, 70, 382, 70, 1344, 112, + 112, 1345, 98, 645, 1347, 112, 112, 112, 864, 1346, + 1349, 1350, 323, 565, 5, 396, 422, 325, -699, 950, + -699, -699, 326, 21, 344, 93, 957, -699, 98, 98, + 98, 98, 305, 710, 114, 1206, 1211, -699, 1232, -699, + -699, 1280, 768, 1162, 1100, 917, -699, 884, 1240, -699, + -699, 383, 1132, -699, 949, -699, 85, 361, 928, 827, + 929, 123, 124, 1218, 1013, 865, 315, 111, -699, -699, + 397, 953, -699, 356, -699, 1030, 1066, 86, 98, 456, + 104, 48, 668, 749, 1218, 1218, 1029, 187, 8, 92, + 10, 11, 104, 104, 1339, 70, 12, 48, 799, 947, + 1296, 998, 794, 1316, 1318, 0, 187, 488, 1032, 1218, + 48, 15, 620, 532, 958, 16, 959, 0, 960, 17, + 0, 655, 656, 154, 479, 480, 481, 482, 483, 484, + 485, 486, 487, 104, 87, 21, 185, 93, 0, 0, + 0, 0, 0, 551, 489, 490, 0, 0, 229, 491, + 492, 493, 494, 278, 48, 0, 0, 0, 0, 19, + 0, 0, 657, 0, 0, 278, 278, 0, 0, 21, + 356, 22, 853, 154, 1297, 0, 278, 0, 658, 0, + 0, 0, 0, 139, 104, 104, 70, 0, 0, 0, + 722, 722, 794, 140, 0, 0, 48, 0, 0, 154, + 0, 26, 0, 1315, 0, 0, 659, 0, 104, 104, + 0, 104, 0, 363, 114, 114, 0, 0, 0, 0, + 114, 114, 114, 0, 0, 0, 8, 92, 10, 11, + 0, 98, 0, 0, 12, 0, 356, 0, 7, 8, + 70, 0, 11, 375, 377, 380, 228, 0, 0, 15, + 0, 277, 0, 16, 0, 0, 0, 17, 0, 104, + 48, 0, 112, 277, 277, 0, 0, 0, 0, 104, + 104, 104, 0, 21, 277, 93, 19, 0, 0, 510, + 0, 0, 0, 0, 0, 0, 21, 0, 22, 0, + 0, 94, 0, 0, 0, 0, 452, 101, 105, 453, + 603, 916, 454, 0, 0, 0, 0, 185, 462, 0, + 604, 362, 0, 0, 0, 0, 0, 501, 26, 0, + 513, 0, 0, 605, 515, 0, 0, 0, 0, 98, + 0, 0, 0, 0, 0, 278, 0, 112, 112, 112, + 0, 0, 0, 8, 230, 10, 184, 0, 229, 279, + 104, 12, 104, 0, 0, 0, 185, 0, 952, 98, + 0, 279, 279, 104, 0, 98, 15, 794, 794, 794, + 16, 0, 279, 0, 17, 532, 552, 0, 0, 0, + 0, 313, 316, 0, 0, 98, 0, 98, 0, 0, + 21, 0, 93, 0, 0, 0, 0, 0, 816, 0, + 98, 48, 1004, 0, 0, 0, 0, 0, 0, 364, + 0, 0, 374, 376, 0, 0, 0, 0, 104, 104, + 104, 104, 0, 0, 0, 104, 794, 794, 794, 0, + 0, 0, 0, 277, 0, 0, 0, 0, 154, 0, + 0, 185, 0, 98, 0, 552, 228, 0, 0, 0, + 0, 0, 854, 104, 1041, 1044, 104, 0, 70, 0, + 98, 0, 0, 859, 0, 363, 481, 482, 483, 484, + 485, 486, 487, 0, 362, 0, 0, 114, 625, 0, + 626, 193, 375, 377, 0, 0, 0, 0, 0, 0, + 699, 154, 1243, 48, 0, 639, 0, 0, 678, 0, + 104, 104, 0, 104, 0, 0, 0, 7, 8, 0, + 0, 1044, 0, 0, 0, 278, 0, 665, 278, 0, + 0, 794, 794, 278, 678, 678, 678, 678, 320, 0, + 0, 279, 0, 0, 70, 0, 0, 278, 0, 0, + 0, 278, 0, 362, 230, 19, 0, 352, 510, 0, + 0, 0, 114, 114, 114, 21, 0, 22, 1294, 0, + 0, 0, 391, 362, 0, 0, 104, 70, 104, 603, + 0, 0, 364, 278, 229, 0, 0, 0, 0, 604, + 104, 104, 0, 104, 0, 1136, 0, 26, 0, 513, + 1141, 552, 605, 515, 0, 0, 277, 0, 363, 0, + 0, 0, 0, 0, 6, 0, 7, 8, 9, 10, + 11, 70, 0, 277, 0, 12, 277, 0, 0, 0, + 0, 277, 277, 277, 277, 277, 0, 0, 13, 14, + 15, 0, 954, 0, 16, 277, 0, 0, 17, 277, + 0, 364, 18, 0, 19, 0, 0, 0, 20, 0, + 0, 627, 628, 0, 21, 0, 22, 0, 0, 23, + 0, 364, 0, 0, 1186, 1187, 0, 0, 24, 0, + 0, 277, 228, 0, 0, 0, 0, 0, 25, 0, + 0, 1010, 552, 794, 0, 0, 26, 0, 363, 362, + 1017, 27, 0, 1205, 279, 0, 362, 28, 29, 1031, + 0, 0, 0, 7, 8, 0, 0, 375, 377, 380, + 0, 279, 0, 0, 279, 380, 0, 0, 0, 279, + 279, 279, 279, 279, 0, 0, 0, 0, -511, 0, + 0, 625, 626, 279, 639, 0, 552, 279, 1233, 0, + 0, 19, 0, -511, -511, 1238, 1239, 0, 0, 0, + -511, 21, 0, 22, 1244, 0, 1096, 0, 794, 794, + 794, 0, -511, 380, 0, 139, 0, 0, 0, 279, + 230, 0, 0, -511, -511, 140, -511, 0, -511, 100, + 362, 0, 424, 26, 769, 771, 362, 364, 141, 0, + 0, 0, 0, 630, 364, 0, 0, 0, 0, 633, + 0, 0, 104, 0, 0, 924, -511, -511, 0, 0, + -511, -511, 0, 1292, 1293, 0, 0, 0, 0, 510, + -511, 0, 0, 0, 0, 678, 21, 0, 93, 918, + 0, 452, 453, 0, 362, 1119, 1120, 0, 0, 0, + 511, 0, 0, 688, 689, 0, 690, 0, 1127, 1128, + 512, 0, 0, 0, 0, 678, 0, 0, 0, 0, + 513, 552, 0, 514, 515, 363, 8, 92, 10, 11, + 0, 0, 0, 0, 12, 0, 837, 838, 364, 0, + 1338, 552, 0, 951, 364, 0, 0, 0, 0, 15, + 452, 453, 0, 16, 0, 0, 0, 17, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 987, + 0, 0, 98, 21, 0, 93, 0, 0, 519, 523, + 525, 0, 0, 277, 363, 0, 0, 0, 0, 781, + 782, 0, 364, 0, 781, 452, 453, 0, 278, 0, + 0, 625, 626, 375, 377, 1192, 7, 100, 639, 375, + 377, 380, 0, 277, 48, 0, 678, 0, 0, 362, + 0, 0, 0, 362, 0, 0, 0, 0, 0, 0, + 1058, 0, 0, 0, 0, 0, 1025, 0, 0, 362, + 0, 0, 0, 0, 19, 452, 453, 0, 0, 0, + 0, 0, 0, 0, 21, 0, 22, 0, 0, 0, + 0, 608, 0, 519, 523, 525, 0, 0, 108, 835, + 836, 1234, 1235, 0, 1236, 1237, 0, 0, 109, 844, + 0, 279, 362, 0, 0, 851, 26, 0, 0, 0, + 48, 27, 0, 0, 0, 0, 277, 0, 0, 0, + 0, 410, 0, 7, 8, 92, 10, 11, 0, 0, + 0, 279, 12, 0, 277, 0, 0, 364, 0, 769, + 771, 364, 0, 154, 0, 987, 0, 15, 0, 868, + 0, 16, 987, 0, 0, 17, -423, 364, 0, 7, + 100, 19, 0, 184, 0, 0, 0, 0, 7, 100, + 0, 21, 11, 22, 0, 0, 672, 0, 0, 0, + 411, 0, 0, 625, 626, 24, 639, 48, 0, 0, + 0, 0, 999, 1000, 268, 25, 0, 19, 999, 1000, + 364, 1313, 0, 26, 0, 0, 19, 21, 27, 22, + 0, 0, 0, 0, 279, 0, 21, 268, 22, 0, + 0, 24, 0, -423, 0, 0, 0, 0, 1019, 1020, + 108, 25, 279, 772, 0, 774, 0, 0, 987, 26, + 109, 0, 774, 0, 27, 0, 919, 920, 26, 922, + 0, 0, 0, 27, 358, 0, 0, 410, 0, 7, + 8, 92, 10, 11, 0, 0, 19, 0, 12, 0, + 0, 0, 0, 523, 0, 936, 21, 0, 22, 0, + 0, 0, 0, 15, 0, 1021, 380, 16, 0, 0, + 139, 17, -422, 769, 771, 0, 0, 19, 0, 0, + 140, 0, 452, 453, 0, 0, 0, 21, 26, 22, + 0, 0, 987, 141, 0, 0, 411, 0, 0, 0, + 1220, 24, 0, 987, 0, 772, 774, 0, 0, 0, + 0, 25, 774, 0, 0, 1002, 278, 0, 0, 26, + 0, 1220, 1220, 0, 27, 0, 0, 1006, 1007, 1008, + 0, 0, 0, 0, 0, 0, 0, 0, 0, -422, + 0, 375, 377, 380, 0, 0, 1220, 0, 0, 0, + 0, 0, 0, 987, 0, 0, 0, 459, 0, 0, + 987, 0, 8, 987, 10, 11, 0, 0, 0, 0, + 12, 0, 0, 0, 7, 8, 158, 159, 160, 523, + 0, 0, 0, 12, 987, 15, 0, 987, 0, 16, + 0, 0, 0, 17, 987, 0, 0, 410, 228, 7, + 8, 92, 10, 11, 0, 1062, 17, 0, 12, 21, + 0, 93, 19, 0, 277, 510, 0, 0, 987, 228, + 228, 0, 21, 15, 22, 0, 0, 16, 0, 0, + 0, 17, -424, 987, 0, 0, 139, 19, 0, 589, + 358, 0, 0, 0, 228, 0, 140, 21, 987, 22, + 0, 0, 672, 0, 26, 0, 411, 0, 0, 1102, + 0, 24, 0, 0, 0, 987, 987, 0, 552, 0, + 930, 25, 931, 0, 0, 0, 0, 0, 0, 26, + 0, 0, 0, 935, 27, 0, 358, 0, 772, 774, + 1121, 0, 0, 0, 0, 0, 230, 0, 0, -424, + 0, 0, 0, 0, 0, 8, 0, 10, 11, 652, + 627, 628, 279, 12, 0, 0, 0, 230, 230, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, + 0, 0, 16, 0, 358, 1150, 17, 0, 930, 931, + 0, 772, 230, 0, 0, 935, 0, 772, 774, 7, + 8, 0, 21, 184, 93, 495, 0, 0, 268, 0, + 0, 589, 0, 0, 719, 720, 362, 724, 725, 726, + 727, 728, 729, 730, 731, 732, 733, 734, 735, 736, + 737, 738, 739, 740, 741, 742, 0, 19, 0, 496, + 510, 358, 0, 358, 358, 0, 0, 21, 0, 22, + 7, 8, 92, 10, 11, 0, 0, 354, 0, 12, + 0, 603, 100, 0, 159, 160, 0, 0, 0, 358, + 12, 604, 0, 0, 15, 358, 42, 0, 16, 26, + 0, 513, 17, 0, 605, 515, 0, 0, 19, 0, + 801, 803, 772, 17, 0, 0, 42, 42, 21, 110, + 22, 0, 510, 0, 0, 42, 0, 0, 0, 21, + 0, 93, 378, 0, 364, 0, 42, 0, 42, 0, + 0, 0, 379, 511, 0, 0, 0, 0, 0, 358, + 26, 0, 0, 512, 0, 141, 589, 0, 190, 0, + 355, 0, 0, 513, 0, 0, 521, 515, 0, 0, + 930, 931, 6, 935, 7, 8, 9, 10, 11, 358, + 0, 0, 0, 12, 0, 0, 0, 42, 0, 0, + 589, 0, 0, 42, 0, 190, 0, 42, 15, 0, + 110, 110, 16, 0, 0, 0, 17, 0, 0, 0, + 0, 42, 19, 42, 42, 0, 324, 0, 0, 0, + 0, 0, 21, 0, 22, 0, 869, 23, 0, 0, + 0, 42, 42, 110, 0, 0, 24, 0, 0, 0, + 0, 190, 0, 0, 0, 0, 25, 0, 0, 0, + 0, 0, 0, 0, 26, 0, 0, 42, 0, 27, + 0, 358, 0, 0, 0, 28, 721, 0, 7, 8, + 0, 10, 437, 233, 234, 42, 235, 12, 0, 0, + 0, 0, 903, 0, 0, 42, 0, 0, 0, 0, + 0, 0, 15, 236, 237, 238, 16, 0, 239, 0, + 17, 0, 240, 241, 0, 242, 19, 243, 244, 0, + 0, 245, 246, 247, 248, 249, 21, 0, 22, 589, + 358, 0, 0, 0, 0, -656, 0, 250, 0, 0, + 251, 0, 0, 358, 0, 358, 0, 0, 252, 253, + 254, 0, 0, 0, 0, 0, 255, 256, 257, 0, + 0, 0, 0, 258, 0, 0, 0, 259, 0, 0, + 0, 0, 0, 0, 946, 0, 0, 506, 0, 260, + 0, 0, 0, 0, 0, 190, 589, 42, 0, 7, + 8, 0, 10, 437, 233, 234, 0, 235, 12, 358, + 0, 358, 0, 358, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 15, 236, 42, 0, 16, 42, 239, + 0, 17, 42, 240, 241, 0, 242, 19, 243, 244, + 589, 0, 245, 246, 247, 248, 249, 21, 0, 22, + 0, 0, 0, 0, 1014, 1015, 0, 0, 250, 0, + 0, 251, 0, 0, 0, 0, 0, 1019, 100, 252, + 253, 254, 42, 42, 42, 42, 0, 255, 256, 257, + 42, 0, 0, 0, 438, 0, 42, 0, 42, 0, + 110, 110, 589, 589, 0, 0, 1046, 42, 0, 0, + 260, 0, 0, 42, 0, 19, 42, 0, 410, 0, + 7, 8, 92, 10, 11, 21, 0, 22, 0, 12, + 0, 7, 8, 0, 1021, 42, 42, 0, 42, 24, + 0, 0, 0, 0, 15, 0, 0, 0, 16, 25, + 0, 0, 17, -425, 0, 0, 0, 26, 19, 589, + 0, 0, 27, 0, 0, 0, 0, 64, 21, 19, + 22, 1083, 0, 0, 7, 8, 0, 411, 11, 21, + 0, 22, 24, 0, 0, 0, 0, 64, 64, 0, + 115, 0, 25, 139, 0, 0, 64, 0, 0, 0, + 26, 0, 0, 140, 0, 27, 0, 64, 0, 64, + 0, 26, 19, 0, 0, 510, 141, 0, 0, 1124, + -425, 0, 21, 0, 22, 7, 8, 92, 10, 11, + 0, 506, 354, 589, 12, 0, 839, 0, 589, 0, + 1142, 0, 0, 791, 0, 0, 840, 0, 0, 15, + 0, 0, 0, 16, 26, 0, 513, 17, 64, 605, + 515, 0, 0, 19, 64, 0, 510, 0, 64, 0, + 0, 115, 115, 21, 42, 22, 0, 0, 0, 0, + 0, 0, 64, 0, 64, 64, 0, 839, 0, 0, + 0, 8, 0, 10, 11, 0, 0, 840, 0, 12, + 358, 0, 64, 64, 115, 26, 0, 513, 0, 0, + 605, 515, 589, 589, 15, 355, 0, 0, 16, 0, + 1190, 1191, 17, 0, 0, 42, 42, 110, 64, 0, + 0, 0, 0, 848, 0, 0, 0, 0, 21, 0, + 93, 589, 0, 0, 0, 0, 64, 0, 0, 42, + 42, 0, 42, 0, 0, 0, 64, 0, 0, 0, + 0, 0, 1222, 476, 477, 478, 479, 480, 481, 482, + 483, 484, 485, 486, 487, 748, 0, 587, 0, 711, + 712, 110, 10, 437, 233, 234, 589, 235, 12, 0, + 0, 0, 0, 589, 589, 0, 0, 358, 0, 0, + 0, 0, 589, 15, 236, 237, 238, 16, 0, 239, + 0, 17, 0, 240, 241, 791, 242, 19, 243, 244, + 0, 0, 245, 246, 247, 248, 249, 21, 0, 713, + 588, 0, 0, 0, 7, 8, 0, 0, 250, 0, + 0, 251, 0, 0, 0, 0, 0, 531, 64, 252, + 253, 254, 0, 0, 0, 0, 0, 255, 256, 257, + 0, 589, 589, 358, 258, 714, 0, 0, 259, 0, + 0, 0, 19, 0, 0, 0, 64, 0, 0, 64, + 260, 0, 21, 64, 22, 0, 0, 0, 0, 0, + 116, 0, 0, 0, 0, 0, 378, 0, 0, 0, + 0, 0, 585, 0, 0, 0, 379, 150, 791, 791, + 0, 0, 0, 0, 26, 0, 0, 0, 0, 141, + 0, 0, 0, 64, 64, 64, 64, 0, 589, 0, + 0, 64, 0, 0, 0, 0, 0, 64, 0, 64, + 0, 115, 115, 0, 0, 0, 0, 0, 64, 0, + 0, 0, 0, 0, 64, 0, 0, 64, 150, 42, + 42, 110, 110, 0, 190, 0, 42, 848, 848, 848, + 0, 116, 116, 0, 0, 0, 64, 64, 0, 64, + 0, 0, 0, 0, 150, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 42, 0, 0, 42, 0, 42, + 0, 0, 150, 150, 381, 0, 0, 0, 0, 0, + 0, 0, 791, 791, 0, 1105, 0, 966, 967, 92, + 10, 232, 233, 234, 0, 235, 12, 968, 150, 969, + 970, 971, 972, 973, 974, 975, 976, 977, 978, 13, + 14, 15, 236, 237, 238, 16, 0, 239, 0, 17, + 0, 240, 241, 0, 242, 19, 243, 244, 0, 0, + 245, 246, 247, 248, 249, 21, 190, 979, 347, 0, + 980, 0, 0, 0, 0, 42, 250, 0, 0, 251, + 0, 0, 0, 0, 793, 0, 0, 252, 253, 254, + 0, 0, 0, 0, 434, 255, 256, 257, 0, 0, + 0, 0, 258, 0, 981, 0, 259, 42, 42, 42, + 0, 0, 0, 0, 0, 64, 0, 1106, 260, 0, + 0, 42, 42, 0, 42, 7, 8, 0, 0, 11, + 0, 8, 92, 10, 11, 0, 0, 354, 0, 12, + 518, 518, 518, 0, 0, 0, 0, 0, 150, 0, + 0, 0, 42, 0, 15, 0, 0, 0, 16, 0, + 0, 0, 17, 19, 0, 0, 64, 64, 115, 0, + 0, 510, 0, 21, 850, 22, 0, 0, 21, 0, + 93, 0, 0, 0, 0, 0, 0, 139, 0, 0, + 64, 64, 511, 64, 0, 0, 0, 140, 0, 0, + 0, 0, 512, 0, 0, 26, 0, 0, 0, 0, + 141, 0, 513, 0, 0, 514, 515, 0, 0, 0, + 355, 0, 115, 607, 848, 607, 607, 518, 0, 120, + 0, 7, 8, 92, 10, 11, 0, 150, 0, 150, + 12, 381, 381, 0, 0, 0, 7, 8, 150, 0, + 424, 516, 516, 516, 150, 15, 793, 150, 0, 16, + 0, 0, 0, 17, 0, 0, 0, 0, 148, 19, + 0, 0, 0, 0, 0, 0, 150, 0, 0, 21, + 0, 22, 0, 0, 19, 0, 0, 510, 0, 0, + 191, 0, 0, 24, 21, 0, 22, 0, 0, 848, + 848, 848, 0, 25, 0, 0, 7, 100, 603, 191, + 424, 26, 0, 0, 0, 0, 27, 0, 604, 148, + 0, 0, 0, 0, 0, 0, 26, 0, 513, 0, + 0, 605, 515, 0, 516, 0, 516, 516, 516, 0, + 0, 0, 0, 42, 19, 148, 0, 0, 0, 793, + 793, 0, 0, 0, 21, 0, 22, 531, 0, 0, + 0, 0, 757, 148, 148, 148, 0, 0, 24, 0, + 0, 0, 0, 390, 518, 518, 0, 518, 25, 0, + 0, 0, 585, 0, 518, 0, 26, 0, 0, 148, + 0, 27, 0, 0, 0, 0, 0, 0, 0, 0, + 64, 64, 115, 115, 0, 0, 0, 64, 850, 850, + 850, 0, 0, 0, 0, 607, 0, 0, 0, 191, + 0, 0, 62, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 64, 0, 0, 64, 0, + 64, 0, 102, 106, 0, 0, 0, 100, 0, 159, + 160, 125, 0, 793, 793, 12, 0, 0, 0, 0, + 0, 0, 0, 0, 157, 0, 607, 607, 843, 0, + 0, 0, 0, 0, 843, 0, 0, 0, 17, 0, + 0, 0, 0, 0, 0, 516, 516, 510, 516, 0, + 150, 150, 0, 150, 21, 790, 93, 0, 8, 151, + 10, 152, 0, 0, 0, 0, 12, 191, 511, 148, + 0, 0, 0, 0, 0, 0, 64, 0, 512, 306, + 0, 15, 381, 308, 0, 16, 516, 0, 513, 17, + 0, 514, 515, 0, 0, 0, 0, 62, 0, 0, + 330, 518, 7, 8, 0, 21, 184, 93, 64, 64, + 64, 434, 434, 434, 0, 0, 0, 102, 106, 0, + 0, 0, 64, 64, 0, 64, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 516, 516, 516, + 19, 0, 0, 0, 148, 790, 148, 148, 0, 0, + 21, 0, 22, 64, 0, 0, 0, 0, 148, 0, + 148, 419, 148, 148, 139, 0, 7, 8, 0, 148, + 11, 425, 0, 0, 140, 148, 0, 0, 148, 0, + 0, 0, 26, 0, 0, 0, 83, 141, 0, 0, + 0, 0, 518, 0, 518, 0, 0, 148, 83, 83, + 0, 83, 0, 0, 19, 518, 0, 0, 0, 518, + 518, 518, 516, 0, 21, 0, 22, 0, 0, 0, + 0, 0, 0, 0, 0, 850, 177, 0, 378, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 379, 0, + 0, 0, 0, 0, 0, 0, 26, 0, 0, 0, + 0, 141, 0, 0, 0, 0, 0, 0, 0, 0, + 607, 607, 843, 843, 0, 0, 0, 607, 843, 843, + 843, 0, 0, 0, 0, 83, 0, 83, 83, 83, + 0, 0, 83, 83, 0, 7, 8, 0, 0, 424, + 0, 559, 0, 0, 560, 150, 0, 0, 561, 0, + 850, 850, 850, 516, 0, 516, 0, 0, 191, 0, + 0, 0, 0, 0, 0, 0, 516, 0, 0, 0, + 790, 790, 790, 19, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 21, 0, 22, 148, 0, 0, 609, + 0, 0, 757, 757, 64, 757, 619, 139, 0, 0, + 0, 0, 306, 0, 308, 0, 0, 140, 0, 0, + 0, 0, 0, 518, 518, 26, 0, 83, 0, 425, + 141, 516, 516, 516, 516, 0, 0, 0, 516, 790, + 790, 790, 0, 0, 0, 0, 0, 148, 148, 841, + 0, 666, 669, 0, 419, 841, 0, 0, 0, 0, + -304, 8, -304, 10, 184, 83, 0, 0, 150, 12, + 150, 148, 148, 0, 148, 0, 0, 0, 0, 0, + 0, 0, 607, 607, 15, 607, 0, 0, 16, 0, + 0, 0, 17, 0, 0, 0, 0, 0, -304, 0, + 0, 510, 0, 841, 0, 0, 0, 0, 21, 83, + 93, 83, 83, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 511, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 512, 0, 790, 790, 0, 0, 0, 0, + -304, 83, 513, 0, 0, 514, 515, 83, 0, 0, + 83, 0, 0, 0, 83, 471, 472, 473, 474, 475, + 476, 477, 478, 479, 480, 481, 482, 483, 484, 485, + 486, 487, 353, 0, 7, 8, 92, 10, 232, 233, + 234, 354, 235, 12, 0, 381, 0, 0, 0, 0, + 0, 0, 0, 516, 516, 0, 516, 0, 15, 236, + 237, 238, 16, 0, 239, 0, 17, 0, 240, 241, + 0, 242, 19, 243, 244, 0, 0, 245, 246, 247, + 248, 249, 21, 0, 22, 0, 0, 0, 0, 0, + 0, 0, 0, 250, 0, 0, 251, 0, 0, 0, + 0, 102, 106, 0, 252, 253, 254, 0, 0, 0, + 0, 0, 255, 256, 257, 0, 0, 0, 0, 258, + 381, 381, 381, 259, 355, 559, 560, 83, 561, 0, + 0, 0, 0, -666, 0, 260, 0, 0, 0, 0, + 0, 148, 148, 148, 148, 0, 1001, 0, 148, 841, + 841, 841, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 150, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 148, 0, 0, 0, + 0, 455, 0, 7, 8, 92, 10, 232, 233, 234, + 354, 235, 12, 83, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 83, 0, 83, 83, 15, 236, 237, + 238, 16, 0, 239, 0, 17, 0, 240, 241, 0, + 242, 19, 243, 244, 510, 0, 245, 246, 247, 248, + 249, 21, 0, 22, -237, 0, 0, 0, 0, 0, + 0, 0, 250, 0, 0, 940, 0, 177, 191, 0, + 0, 0, 0, 252, 253, 941, 0, 0, 0, 0, + 0, 255, 256, 257, 0, 513, 0, 0, 788, 515, + 0, 0, 259, 355, 0, 0, 7, 8, 158, 159, + 160, 0, 0, 0, 260, 12, 0, 0, 0, 148, + 0, 148, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 148, 148, 0, 148, 0, 17, 0, + 0, 0, 0, 0, 19, 0, 0, 510, 0, 0, + 0, 0, 0, 0, 21, 0, 22, 0, 0, 0, + 0, 0, 0, 0, 0, 306, 308, 0, 603, 0, + 0, 0, 425, 0, 0, 0, 0, 0, 604, 0, + 0, 0, 0, 0, 0, 0, 26, 0, 513, 0, + 0, 611, 515, 0, 0, 0, 0, 0, 0, 0, + 1026, 0, 83, 1026, 0, 419, 0, 0, 0, 0, + 0, 0, 83, 83, 83, 0, 455, 0, 7, 8, + 92, 10, 232, 233, 234, 354, 235, 12, 0, 0, + 0, 0, 0, 0, 0, 0, 841, 0, 0, 0, + 0, 0, 15, 236, 237, 238, 16, 0, 239, 0, + 17, 0, 240, 241, 0, 242, 19, 243, 244, 510, + 0, 245, 246, 247, 248, 249, 21, 0, 22, -237, + 0, 0, 0, 0, 0, 0, 0, 250, 0, 0, + 845, 419, 0, 0, 1164, 0, 0, 0, 252, 253, + 846, 0, 0, 83, 0, 83, 255, 256, 257, 0, + 513, 0, 0, 847, 515, 0, 83, 259, 355, 0, + 0, 841, 841, 841, 1101, 0, 0, 0, 0, 260, + 0, 0, 0, 0, 0, 0, 0, 559, 560, 0, + 561, 466, 467, 468, 1165, 469, 470, 471, 472, 473, 474, 475, 476, 477, 478, 479, 480, 481, 482, 483, - 484, 485, 486, 487, 488, 489, 490, 476, 477, 478, - 479, 480, 481, 482, 483, 484, 485, 486, 487, 488, - 489, 490, 192, 0, 0, 0, 0, 519, 519, 519, - 519, 519, 1045, 0, 0, 519, 794, 794, 794, 0, - 0, 0, 383, 0, 7, 8, 92, 10, 11, 0, - 0, 356, 0, 12, 0, 526, 0, 0, 0, 0, - 0, 0, 0, 149, 0, 149, 0, 0, 15, 0, - 0, 0, 16, 0, 0, 0, 17, 149, 149, 0, - 149, 0, 19, 0, 0, 513, 0, 0, 0, 0, - 0, 0, 21, 0, 22, 0, 0, 0, 102, 106, - 0, 0, 0, 0, 0, 0, 843, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 844, 377, 379, 383, - 0, 0, 562, 563, 26, 565, 516, 0, 0, 845, - 518, 0, 0, 0, 357, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 936, 0, 937, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 941, - 0, 0, 0, 774, 776, 475, 476, 477, 478, 479, - 480, 481, 482, 483, 484, 485, 486, 487, 488, 489, - 490, 846, 0, 0, 0, 0, 0, 0, 0, 0, - 519, 519, 0, 519, 0, 0, 0, 0, 0, 0, - 686, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 936, 937, 774, 776, 0, 0, - 0, 0, 941, 774, 776, 469, 470, 471, 0, 472, - 473, 474, 475, 476, 477, 478, 479, 480, 481, 482, - 483, 484, 485, 486, 487, 488, 489, 490, 0, 0, - 0, 0, 0, 0, 0, 0, 846, 846, 846, 0, - 0, 0, 1111, 0, 971, 972, 92, 10, 233, 234, - 235, 0, 236, 12, 973, 0, 974, 975, 976, 977, - 978, 979, 980, 981, 982, 983, 13, 14, 15, 237, - 238, 239, 16, 0, 240, 0, 17, 0, 241, 242, - 149, 243, 19, 244, 245, 0, 0, 246, 247, 248, - 249, 250, 21, 0, 984, 349, 0, 985, 0, 0, - 0, 0, 0, 251, 0, 0, 252, 0, 0, 0, - 0, 0, 307, 309, 253, 254, 255, 0, 0, 0, - 428, 0, 256, 257, 258, 0, 0, 0, 0, 259, - 0, 986, 0, 260, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 1112, 261, 0, 0, 1031, 0, - 0, 1031, 0, 422, 0, 0, 0, 936, 937, 0, - 941, 1261, 0, 971, 972, 92, 10, 233, 234, 235, - 0, 236, 12, 973, 0, 974, 975, 976, 977, 978, - 979, 980, 981, 982, 983, 13, 14, 15, 237, 238, - 239, 16, 0, 240, 0, 17, 0, 241, 242, 0, - 243, 19, 244, 245, 0, 0, 246, 247, 248, 249, - 250, 21, 0, 984, 349, 0, 985, 0, 0, 0, - 0, 0, 251, 0, 0, 252, 0, 0, 0, 422, - 0, 0, 0, 253, 254, 255, 0, 0, 0, 0, - 0, 256, 257, 258, 0, 0, 0, 0, 259, 0, - 986, 0, 260, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 1107, 1262, 261, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 562, 563, 0, 565, 0, + 484, 485, 486, 487, 0, 148, 0, 0, 419, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 1255, 0, + 966, 967, 92, 10, 232, 233, 234, 0, 235, 12, + 968, 0, 969, 970, 971, 972, 973, 974, 975, 976, + 977, 978, 13, 14, 15, 236, 237, 238, 16, 83, + 239, 0, 17, 0, 240, 241, 0, 242, 19, 243, + 244, 0, 0, 245, 246, 247, 248, 249, 21, 0, + 979, 347, 0, 980, 0, 0, 0, 0, 0, 250, + 0, 0, 251, 0, 0, 0, 0, 0, 0, 0, + 252, 253, 254, 83, 83, 0, 83, 0, 255, 256, + 257, 0, 0, 0, 0, 258, 0, 981, 0, 259, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 1283, 0, 971, 972, 92, 10, 233, - 234, 235, 0, 236, 12, 973, 422, 974, 975, 976, - 977, 978, 979, 980, 981, 982, 983, 13, 14, 15, - 237, 238, 239, 16, 0, 240, 0, 17, 0, 241, - 242, 0, 243, 19, 244, 245, 0, 0, 246, 247, - 248, 249, 250, 21, 0, 984, 349, 0, 985, 0, - 0, 0, 0, 0, 251, 0, 0, 252, 0, 0, - 0, 0, 0, 0, 0, 253, 254, 255, 0, 0, - 0, 0, 0, 256, 257, 258, 0, 0, 0, 0, - 259, 0, 986, 0, 260, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 1284, 261, 1283, 0, 971, - 972, 92, 10, 233, 234, 235, 0, 236, 12, 973, - 0, 974, 975, 976, 977, 978, 979, 980, 981, 982, - 983, 13, 14, 15, 237, 238, 239, 16, 0, 240, - 0, 17, 0, 241, 242, 0, 243, 19, 244, 245, - 0, 0, 246, 247, 248, 249, 250, 21, 0, 984, - 349, 0, 985, 0, 0, 0, 0, 0, 251, 0, - 0, 252, 0, 0, 0, 0, 0, 0, 0, 253, - 254, 255, 0, 0, 0, 0, 0, 256, 257, 258, - 0, 0, 0, 0, 259, 0, 986, 0, 260, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 1289, - 261, 1283, 0, 971, 972, 92, 10, 233, 234, 235, - 0, 236, 12, 973, 0, 974, 975, 976, 977, 978, - 979, 980, 981, 982, 983, 13, 14, 15, 237, 238, - 239, 16, 0, 240, 0, 17, 0, 241, 242, 0, - 243, 19, 244, 245, 0, 0, 246, 247, 248, 249, - 250, 21, 0, 984, 349, 0, 985, 0, 0, 0, - 0, 0, 251, 0, 0, 252, 0, 0, 0, 0, - 0, 0, 0, 253, 254, 255, 0, 0, 0, 0, - 0, 256, 257, 258, 0, 0, 0, 0, 259, 0, - 986, 0, 260, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 1328, 261, 970, 0, 971, 972, 92, - 10, 233, 234, 235, 0, 236, 12, 973, 0, 974, - 975, 976, 977, 978, 979, 980, 981, 982, 983, 13, - 14, 15, 237, 238, 239, 16, 0, 240, 0, 17, - 0, 241, 242, 0, 243, 19, 244, 245, 0, 0, - 246, 247, 248, 249, 250, 21, 0, 984, 349, 0, - 985, 0, 0, 0, 0, 0, 251, 0, 0, 252, - 0, 0, 0, 0, 0, 0, 0, 253, 254, 255, - 0, 0, 0, 0, 0, 256, 257, 258, 0, 0, - 0, 0, 259, 0, 986, 1255, 260, 971, 972, 92, - 10, 233, 234, 235, 0, 236, 12, 973, 261, 974, - 975, 976, 977, 978, 979, 980, 981, 982, 983, 13, - 14, 15, 237, 238, 239, 16, 0, 240, 0, 17, - 0, 241, 242, 0, 243, 19, 244, 245, 0, 0, - 246, 247, 248, 249, 250, 21, 0, 984, 349, 0, - 985, 0, 0, 0, 0, 0, 251, 0, 0, 252, - 0, 0, 0, 0, 0, 0, 0, 253, 254, 255, - 0, 0, 0, 0, 0, 256, 257, 258, 0, 0, - 0, 0, 259, 0, 986, 1316, 260, 971, 972, 92, - 10, 233, 234, 235, 0, 236, 12, 973, 261, 974, - 975, 976, 977, 978, 979, 980, 981, 982, 983, 13, - 14, 15, 237, 238, 239, 16, 0, 240, 0, 17, - 0, 241, 242, 0, 243, 19, 244, 245, 0, 0, - 246, 247, 248, 249, 250, 21, 0, 984, 349, 0, - 985, 0, 0, 0, 0, 0, 251, 0, 0, 252, - 0, 0, 0, 0, 0, 0, 0, 253, 254, 255, - 0, 0, 0, 0, 0, 256, 257, 258, 0, 0, - 0, 0, 259, 0, 986, 458, 260, 7, 8, 92, - 10, 233, 234, 235, 356, 236, 12, 0, 261, 0, + 1256, 260, 1277, 0, 966, 967, 92, 10, 232, 233, + 234, 0, 235, 12, 968, 0, 969, 970, 971, 972, + 973, 974, 975, 976, 977, 978, 13, 14, 15, 236, + 237, 238, 16, 0, 239, 0, 17, 0, 240, 241, + 0, 242, 19, 243, 244, 0, 0, 245, 246, 247, + 248, 249, 21, 0, 979, 347, 0, 980, 0, 0, + 0, 0, 0, 250, 0, 0, 251, 0, 0, 0, + 0, 0, 0, 0, 252, 253, 254, 0, 0, 0, + 0, 0, 255, 256, 257, 0, 0, 0, 0, 258, + 0, 981, 0, 259, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 1278, 260, 1277, 0, 966, 967, + 92, 10, 232, 233, 234, 0, 235, 12, 968, 0, + 969, 970, 971, 972, 973, 974, 975, 976, 977, 978, + 13, 14, 15, 236, 237, 238, 16, 0, 239, 0, + 17, 0, 240, 241, 0, 242, 19, 243, 244, 0, + 0, 245, 246, 247, 248, 249, 21, 0, 979, 347, + 0, 980, 0, 0, 0, 0, 0, 250, 0, 0, + 251, 0, 0, 0, 0, 0, 0, 0, 252, 253, + 254, 0, 0, 0, 0, 0, 255, 256, 257, 0, + 0, 0, 0, 258, 0, 981, 0, 259, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 1283, 260, + 1277, 0, 966, 967, 92, 10, 232, 233, 234, 0, + 235, 12, 968, 0, 969, 970, 971, 972, 973, 974, + 975, 976, 977, 978, 13, 14, 15, 236, 237, 238, + 16, 0, 239, 0, 17, 0, 240, 241, 0, 242, + 19, 243, 244, 0, 0, 245, 246, 247, 248, 249, + 21, 0, 979, 347, 0, 980, 0, 0, 0, 0, + 0, 250, 0, 0, 251, 0, 0, 0, 0, 0, + 0, 0, 252, 253, 254, 0, 0, 0, 0, 0, + 255, 256, 257, 0, 0, 0, 0, 258, 0, 981, + 0, 259, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 1322, 260, 965, 0, 966, 967, 92, 10, + 232, 233, 234, 0, 235, 12, 968, 0, 969, 970, + 971, 972, 973, 974, 975, 976, 977, 978, 13, 14, + 15, 236, 237, 238, 16, 0, 239, 0, 17, 0, + 240, 241, 0, 242, 19, 243, 244, 0, 0, 245, + 246, 247, 248, 249, 21, 0, 979, 347, 0, 980, + 0, 0, 0, 0, 0, 250, 0, 0, 251, 0, + 0, 0, 0, 0, 0, 0, 252, 253, 254, 0, + 0, 0, 0, 0, 255, 256, 257, 0, 0, 0, + 0, 258, 0, 981, 1249, 259, 966, 967, 92, 10, + 232, 233, 234, 0, 235, 12, 968, 260, 969, 970, + 971, 972, 973, 974, 975, 976, 977, 978, 13, 14, + 15, 236, 237, 238, 16, 0, 239, 0, 17, 0, + 240, 241, 0, 242, 19, 243, 244, 0, 0, 245, + 246, 247, 248, 249, 21, 0, 979, 347, 0, 980, + 0, 0, 0, 0, 0, 250, 0, 0, 251, 0, + 0, 0, 0, 0, 0, 0, 252, 253, 254, 0, + 0, 0, 0, 0, 255, 256, 257, 0, 0, 0, + 0, 258, 0, 981, 1310, 259, 966, 967, 92, 10, + 232, 233, 234, 0, 235, 12, 968, 260, 969, 970, + 971, 972, 973, 974, 975, 976, 977, 978, 13, 14, + 15, 236, 237, 238, 16, 0, 239, 0, 17, 0, + 240, 241, 0, 242, 19, 243, 244, 0, 0, 245, + 246, 247, 248, 249, 21, 0, 979, 347, 0, 980, + 0, 0, 0, 0, 0, 250, 0, 0, 251, 0, + 0, 0, 0, 0, 0, 0, 252, 253, 254, 0, + 0, 0, 0, 0, 255, 256, 257, 0, 0, 0, + 0, 258, 0, 981, 634, 259, 7, 8, 92, 10, + 232, 233, 234, 354, 235, 12, 0, 260, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 15, 237, 238, 239, 16, 0, 240, 0, 17, - 0, 241, 242, 0, 243, 19, 244, 245, 513, 0, - 246, 247, 248, 249, 250, 21, 0, 22, -239, 0, - 0, 0, 0, 0, 0, 0, 251, 0, 0, 790, - 0, 0, 0, 0, 0, 0, 0, 253, 254, 791, - 0, 0, 0, 0, 0, 256, 257, 258, 0, 516, - 0, 0, 792, 518, 0, 0, 260, 357, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 458, 261, 7, - 8, 92, 10, 233, 234, 235, 356, 236, 12, 0, + 15, 236, 237, 238, 16, 0, 239, 0, 17, 0, + 240, 241, 0, 242, 19, 243, 244, 0, 0, 245, + 246, 247, 248, 249, 21, 0, 22, 0, 0, 0, + 0, 0, 0, 0, 0, 250, 0, 0, 251, 0, + 0, 0, 0, 0, 0, 0, 252, 253, 254, 0, + 0, 0, 0, 0, 255, 256, 257, 0, 0, 0, + 0, 258, 0, 0, 0, 259, 355, 0, 0, 0, + 0, 0, 0, 0, 0, -666, 587, 260, 711, 712, + 0, 10, 437, 233, 234, 0, 235, 12, 474, 475, + 476, 477, 478, 479, 480, 481, 482, 483, 484, 485, + 486, 487, 15, 236, 237, 238, 16, 0, 239, 0, + 17, 0, 240, 241, 0, 242, 19, 243, 244, 0, + 0, 245, 246, 247, 248, 249, 21, 0, 713, 588, + 0, 0, 0, 0, 0, 0, 0, 250, 0, 0, + 251, 0, 0, 0, 0, 0, 0, 0, 252, 253, + 254, 0, 0, 0, 0, 0, 255, 256, 257, 0, + 0, 0, 0, 258, 714, 0, 587, 259, 711, 712, + 0, 10, 437, 233, 234, 0, 235, 12, 826, 260, + 0, 0, 0, 0, 1042, 0, 0, 0, 0, 0, + 0, 0, 15, 236, 237, 238, 16, 0, 239, 0, + 17, 0, 240, 241, 0, 242, 19, 243, 244, 0, + 0, 245, 246, 247, 248, 249, 21, 0, 713, 588, + 0, 0, 0, 0, 0, 0, 0, 250, 0, 0, + 251, 0, 0, 0, 0, 0, 0, 0, 252, 253, + 254, 0, 0, 0, 0, 0, 255, 256, 257, 0, + 0, 0, 0, 258, 0, 0, 587, 259, 711, 712, + 0, 10, 437, 233, 234, 0, 235, 12, -384, 260, + 0, 0, 0, 0, 1042, 0, 0, 0, 0, 0, + 0, 0, 15, 236, 237, 238, 16, 0, 239, 0, + 17, 0, 240, 241, 0, 242, 19, 243, 244, 0, + 0, 245, 246, 247, 248, 249, 21, 0, 713, 588, + 0, 0, 0, 0, 0, 0, 0, 250, 0, 0, + 251, 0, 0, 0, 0, 0, 0, 0, 252, 253, + 254, 0, 0, 0, 0, 0, 255, 256, 257, 0, + 0, 0, 0, 258, 0, 0, 1158, 259, 7, 8, + 92, 10, 232, 233, 234, 0, 235, 12, 1071, 260, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 15, 237, 238, 239, 16, 0, 240, - 0, 17, 0, 241, 242, 0, 243, 19, 244, 245, - 513, 0, 246, 247, 248, 249, 250, 21, 0, 22, - -239, 0, 0, 0, 0, 0, 0, 0, 251, 0, - 0, 850, 0, 0, 0, 0, 0, 0, 0, 253, - 254, 851, 0, 0, 0, 0, 0, 256, 257, 258, - 0, 516, 0, 0, 852, 518, 0, 0, 260, 357, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 355, - 261, 7, 8, 92, 10, 233, 234, 235, 356, 236, - 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 15, 237, 238, 239, 16, - 0, 240, 0, 17, 0, 241, 242, 0, 243, 19, - 244, 245, 0, 0, 246, 247, 248, 249, 250, 21, - 0, 22, 0, 0, 0, 0, 0, 0, 0, 0, - 251, 0, 0, 252, 0, 0, 0, 0, 0, 0, - 0, 253, 254, 255, 0, 0, 0, 0, 0, 256, - 257, 258, 0, 0, 0, 0, 259, 0, 0, 0, - 260, 357, 0, 0, 0, 0, 0, 0, 0, 0, - -667, 638, 261, 7, 8, 92, 10, 233, 234, 235, - 356, 236, 12, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 15, 237, 238, - 239, 16, 0, 240, 0, 17, 0, 241, 242, 0, - 243, 19, 244, 245, 0, 0, 246, 247, 248, 249, - 250, 21, 0, 22, 0, 0, 0, 0, 0, 0, - 0, 0, 251, 0, 0, 252, 0, 0, 0, 0, - 0, 0, 0, 253, 254, 255, 0, 0, 0, 0, - 0, 256, 257, 258, 0, 0, 0, 0, 259, 0, - 0, 0, 260, 357, 0, 0, 0, 0, 0, 0, - 0, 0, -667, 591, 261, 715, 716, 0, 10, 440, - 234, 235, 0, 236, 12, 0, 0, 0, 0, 0, + 0, 0, 15, 236, 237, 238, 16, 0, 239, 0, + 17, 0, 240, 241, 0, 242, 19, 243, 244, 0, + 0, 245, 246, 247, 248, 249, 21, 0, 22, 1159, + 0, 1160, 0, 0, 0, 0, 0, 250, 0, 0, + 251, 0, 0, 0, 0, 0, 0, 0, 252, 253, + 254, 0, 0, 0, 0, 0, 255, 256, 257, 196, + 0, 0, 8, 258, 10, 11, 0, 259, 0, 0, + 12, 0, 0, 0, 0, 0, 0, 0, 0, 260, + 0, 0, 0, 0, 0, 15, 0, 0, 0, 16, + 0, 0, 0, 17, 0, 197, 198, 0, 0, 0, + 0, 0, 199, 0, 0, 0, 0, 0, 0, 21, + 0, 93, 0, 200, 0, 201, 202, 203, 0, 204, + 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, + 215, 216, 217, 218, 219, 220, 221, 0, 0, 222, + 223, 224, 0, 455, 225, 7, 8, 226, 10, 232, + 233, 234, 0, 235, 12, 0, 0, 0, 0, 0, + 0, 0, 227, 0, 0, 0, 0, 0, 0, 15, + 236, 237, 238, 16, 0, 239, 0, 17, 0, 240, + 241, 0, 242, 19, 243, 244, 0, 0, 245, 246, + 247, 248, 249, 21, 0, 22, -237, 0, 0, 0, + 0, 0, 0, 0, 250, 0, 0, 251, 0, 0, + 0, 0, 0, 0, 0, 252, 253, 254, 0, 0, + 0, 0, 0, 255, 256, 257, 0, 0, 0, 0, + 258, 0, 0, 587, 259, 7, 8, 0, 10, 437, + 233, 234, 0, 235, 12, 0, 260, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, - 237, 238, 239, 16, 0, 240, 0, 17, 0, 241, - 242, 0, 243, 19, 244, 245, 0, 0, 246, 247, - 248, 249, 250, 21, 0, 717, 592, 0, 0, 0, - 0, 0, 0, 0, 251, 0, 0, 252, 0, 0, - 0, 0, 0, 0, 0, 253, 254, 255, 0, 0, - 0, 0, 0, 256, 257, 258, 0, 0, 0, 0, - 259, 718, 0, 591, 260, 715, 716, 0, 10, 440, - 234, 235, 0, 236, 12, 830, 261, 0, 0, 0, - 0, 1047, 0, 0, 0, 0, 0, 0, 0, 15, - 237, 238, 239, 16, 0, 240, 0, 17, 0, 241, - 242, 0, 243, 19, 244, 245, 0, 0, 246, 247, - 248, 249, 250, 21, 0, 717, 592, 0, 0, 0, - 0, 0, 0, 0, 251, 0, 0, 252, 0, 0, - 0, 0, 0, 0, 0, 253, 254, 255, 0, 0, - 0, 0, 0, 256, 257, 258, 0, 0, 0, 0, - 259, 0, 0, 591, 260, 715, 716, 0, 10, 440, - 234, 235, 0, 236, 12, -386, 261, 0, 0, 0, - 0, 1047, 0, 0, 0, 0, 0, 0, 0, 15, - 237, 238, 239, 16, 0, 240, 0, 17, 0, 241, - 242, 0, 243, 19, 244, 245, 0, 0, 246, 247, - 248, 249, 250, 21, 0, 717, 592, 0, 0, 0, - 0, 0, 0, 0, 251, 0, 0, 252, 0, 0, - 0, 0, 0, 0, 0, 253, 254, 255, 0, 0, - 0, 0, 0, 256, 257, 258, 0, 0, 0, 0, - 259, 0, 0, 1164, 260, 7, 8, 92, 10, 233, - 234, 235, 0, 236, 12, 1077, 261, 0, 0, 0, + 236, 237, 238, 16, 0, 239, 0, 17, 0, 240, + 241, 0, 242, 19, 243, 244, 0, 0, 245, 246, + 247, 248, 249, 21, 0, 22, 588, 0, 0, 0, + 0, 0, 0, 0, 250, 0, 0, 251, 0, 0, + 0, 0, 0, 0, 0, 252, 253, 254, 0, 0, + 0, 0, 0, 255, 256, 257, 0, 0, 0, 0, + 258, 0, 0, 455, 259, 7, 8, 0, 10, 232, + 233, 234, 0, 235, 12, 0, 260, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, - 237, 238, 239, 16, 0, 240, 0, 17, 0, 241, - 242, 0, 243, 19, 244, 245, 0, 0, 246, 247, - 248, 249, 250, 21, 0, 22, 1165, 0, 1166, 0, - 0, 0, 0, 0, 251, 0, 0, 252, 0, 0, - 0, 0, 0, 0, 0, 253, 254, 255, 0, 0, - 0, 0, 0, 256, 257, 258, 0, 0, 0, 0, - 259, 0, 0, 591, 260, 715, 716, 0, 10, 440, - 234, 235, 0, 236, 12, 0, 261, 0, 0, 0, + 236, 237, 238, 16, 0, 239, 0, 17, 0, 240, + 241, 0, 242, 19, 243, 244, 0, 0, 245, 246, + 247, 248, 249, 21, 0, 22, -237, 0, 0, 0, + 0, 0, 0, 0, 250, 0, 0, 1177, 0, 0, + 0, 0, 0, 0, 0, 252, 253, 1178, 0, 0, + 0, 0, 0, 255, 256, 257, 0, 0, 0, 0, + 1179, 0, 0, 1229, 259, 7, 8, 0, 10, 232, + 233, 234, 0, 235, 12, 0, 260, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, - 237, 238, 239, 16, 0, 240, 0, 17, 0, 241, - 242, 0, 243, 19, 244, 245, 0, 0, 246, 247, - 248, 249, 250, 21, 0, 717, 592, 0, 0, 0, - 0, 0, 0, 0, 251, 0, 0, 252, 0, 0, - 0, 0, 0, 0, 0, 253, 254, 255, 0, 0, - 0, 0, 0, 256, 257, 258, 0, 0, 0, 0, - 259, 718, 197, 0, 260, 8, 0, 10, 11, 0, - 0, 0, 0, 12, 0, 0, 261, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, - 0, 0, 16, 0, 0, 0, 17, 0, 198, 199, - 0, 0, 0, 0, 0, 200, 0, 0, 0, 0, - 0, 0, 21, 0, 93, 0, 201, 0, 202, 203, - 204, 0, 205, 206, 207, 208, 209, 210, 211, 212, - 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, - 0, 0, 223, 224, 225, 0, 458, 226, 7, 8, - 227, 10, 233, 234, 235, 0, 236, 12, 0, 0, - 0, 0, 0, 0, 0, 228, 0, 0, 0, 0, - 0, 0, 15, 237, 238, 239, 16, 0, 240, 0, - 17, 0, 241, 242, 0, 243, 19, 244, 245, 0, - 0, 246, 247, 248, 249, 250, 21, 0, 22, -239, - 0, 0, 0, 0, 0, 0, 0, 251, 0, 0, - 252, 0, 0, 0, 0, 0, 0, 0, 253, 254, - 255, 0, 0, 0, 0, 0, 256, 257, 258, 0, - 0, 0, 0, 259, 0, 0, 591, 260, 7, 8, - 0, 10, 440, 234, 235, 0, 236, 12, 0, 261, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 15, 237, 238, 239, 16, 0, 240, 0, - 17, 0, 241, 242, 0, 243, 19, 244, 245, 0, - 0, 246, 247, 248, 249, 250, 21, 0, 22, 592, - 0, 0, 0, 0, 0, 0, 0, 251, 0, 0, - 252, 0, 0, 0, 0, 0, 0, 0, 253, 254, - 255, 0, 0, 0, 0, 0, 256, 257, 258, 0, - 0, 0, 0, 259, 0, 0, 725, 260, 7, 8, - 0, 10, 440, 234, 235, 0, 236, 12, 0, 261, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 15, 237, 238, 239, 16, 0, 240, 0, - 17, 0, 241, 242, 0, 243, 19, 244, 245, 0, - 0, 246, 247, 248, 249, 250, 21, 0, 22, 0, - 0, 0, 0, 0, 0, -657, 0, 251, 0, 0, - 252, 0, 0, 0, 0, 0, 0, 0, 253, 254, - 255, 0, 0, 0, 0, 0, 256, 257, 258, 0, - 0, 0, 0, 259, 0, 0, 458, 260, 7, 8, - 0, 10, 233, 234, 235, 0, 236, 12, 0, 261, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 15, 237, 238, 239, 16, 0, 240, 0, - 17, 0, 241, 242, 0, 243, 19, 244, 245, 0, - 0, 246, 247, 248, 249, 250, 21, 0, 22, -239, - 0, 0, 0, 0, 0, 0, 0, 251, 0, 0, - 895, 0, 0, 0, 0, 0, 0, 0, 253, 254, - 896, 0, 0, 0, 0, 0, 256, 257, 258, 0, - 0, 0, 0, 897, 0, 0, 458, 260, 7, 8, - 0, 10, 233, 234, 235, 0, 236, 12, 0, 261, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 15, 237, 238, 239, 16, 0, 240, 0, - 17, 0, 241, 242, 0, 243, 19, 244, 245, 0, - 0, 246, 247, 248, 249, 250, 21, 0, 22, -239, - 0, 0, 0, 0, 0, 0, 0, 251, 0, 0, - 1183, 0, 0, 0, 0, 0, 0, 0, 253, 254, - 1184, 0, 0, 0, 0, 0, 256, 257, 258, 0, - 0, 0, 0, 1185, 0, 0, 1235, 260, 7, 8, - 0, 10, 233, 234, 235, 0, 236, 12, 0, 261, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 15, 237, 238, 239, 16, 0, 240, 0, - 17, 0, 241, 242, 0, 243, 19, 244, 245, 0, - 0, 246, 247, 248, 249, 250, 21, 0, 22, 0, - 0, -139, 0, 0, 0, 0, 0, 251, 0, 0, - 252, 0, 0, 0, 0, 0, 0, 0, 253, 254, - 255, 0, 0, 0, 0, 0, 256, 257, 258, 0, - 0, 0, 0, 259, 0, 0, 725, 260, 7, 8, - 0, 10, 440, 234, 235, 0, 236, 12, 0, 261, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 15, 237, 238, 239, 16, 0, 240, 0, - 17, 0, 241, 242, 0, 243, 19, 244, 245, 0, - 0, 246, 247, 248, 249, 250, 21, 0, 22, 0, - 0, 0, 0, 0, 0, 0, 0, 251, 0, 0, - 252, 0, 0, 0, 0, 0, 0, 0, 253, 254, - 255, 0, 0, 0, 0, 0, 256, 257, 258, 0, - 0, 0, 0, 259, 0, 0, 0, 260, 0, 0, - 0, 0, 0, 0, 0, 0, 0, -657, 804, 261, - 7, 8, 0, 10, 440, 234, 235, 0, 236, 12, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 15, 237, 238, 239, 16, 0, - 240, 0, 17, 0, 241, 242, 0, 243, 19, 244, - 245, 0, 0, 246, 247, 248, 249, 250, 21, 0, - 22, 0, 0, 0, 0, 0, 0, 0, 0, 251, - 0, 0, 252, 0, 0, 0, 0, 0, 0, 0, - 253, 254, 255, 0, 0, 0, 0, 0, 256, 257, - 258, 0, 0, 0, 0, 259, 0, 0, 806, 260, - 7, 8, 0, 10, 440, 234, 235, 0, 236, 12, - 0, 261, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 15, 237, 238, 239, 16, 0, - 240, 0, 17, 0, 241, 242, 0, 243, 19, 244, - 245, 0, 0, 246, 247, 248, 249, 250, 21, 0, - 22, 0, 0, 0, 0, 0, 0, 0, 0, 251, - 0, 0, 252, 0, 0, 0, 0, 0, 0, 0, - 253, 254, 255, 0, 0, 0, 0, 0, 256, 257, - 258, 0, 0, 0, 0, 259, 0, 7, 8, 260, - 10, 440, 234, 235, 0, 236, 12, 0, 0, 0, - 0, 261, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 15, 237, 238, 239, 16, 0, 240, 0, 17, - 0, 241, 242, 0, 243, 19, 244, 245, 0, 0, - 246, 247, 248, 249, 250, 21, 0, 22, 0, 0, - 0, 0, 0, 0, 0, 0, 251, 0, 0, 252, - 0, 0, 0, 0, 0, 0, 0, 253, 254, 255, - 0, 0, 0, 0, 0, 256, 257, 258, 0, 0, - 0, 0, 259, 0, 0, 0, 260, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 261, 764, - 971, 972, 92, 10, 233, 234, 235, 0, 236, 12, - 973, 0, 974, 975, 976, 977, 978, 979, 980, 981, - 982, 983, 13, 14, 15, 237, 238, 239, 16, 0, - 240, 0, 17, 0, 241, 242, 0, 243, 19, 244, - 245, 0, 0, 246, 247, 248, 249, 250, 21, 0, - 984, 349, 0, 985, 0, 0, 0, 0, 0, 251, - 0, 0, 252, 0, 0, 0, 0, 0, 0, 0, - 253, 254, 255, 0, 0, 0, 0, 0, 256, 257, - 258, 0, 0, 0, 0, 259, 0, 986, 0, 260, + 236, 237, 238, 16, 0, 239, 0, 17, 0, 240, + 241, 0, 242, 19, 243, 244, 0, 0, 245, 246, + 247, 248, 249, 21, 0, 22, 0, 0, -139, 0, + 0, 0, 0, 0, 250, 0, 0, 251, 0, 0, + 0, 0, 0, 0, 0, 252, 253, 254, 0, 0, + 0, 0, 0, 255, 256, 257, 0, 0, 0, 0, + 258, 0, 0, 721, 259, 7, 8, 0, 10, 437, + 233, 234, 0, 235, 12, 0, 260, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, + 236, 237, 238, 16, 0, 239, 0, 17, 0, 240, + 241, 0, 242, 19, 243, 244, 0, 0, 245, 246, + 247, 248, 249, 21, 0, 22, 0, 0, 0, 0, + 0, 0, 0, 0, 250, 0, 0, 251, 0, 0, + 0, 0, 0, 0, 0, 252, 253, 254, 0, 0, + 0, 0, 0, 255, 256, 257, 0, 0, 0, 0, + 258, 0, 0, 0, 259, 0, 0, 0, 0, 0, + 0, 0, 0, 0, -656, 800, 260, 7, 8, 0, + 10, 437, 233, 234, 0, 235, 12, 475, 476, 477, + 478, 479, 480, 481, 482, 483, 484, 485, 486, 487, + 0, 15, 236, 237, 238, 16, 0, 239, 0, 17, + 0, 240, 241, 0, 242, 19, 243, 244, 0, 0, + 245, 246, 247, 248, 249, 21, 0, 22, 0, 0, + 0, 0, 0, 0, 0, 0, 250, 0, 0, 251, + 0, 0, 0, 0, 0, 0, 0, 252, 253, 254, + 0, 0, 0, 0, 0, 255, 256, 257, 0, 0, + 0, 0, 258, 0, 0, 802, 259, 7, 8, 0, + 10, 437, 233, 234, 0, 235, 12, 0, 260, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1116, 261, 971, 972, 92, 10, 233, 234, 235, 0, - 236, 12, 973, 0, 974, 975, 976, 977, 978, 979, - 980, 981, 982, 983, 13, 14, 15, 237, 238, 239, - 16, 0, 240, 0, 17, 0, 241, 242, 0, 243, - 19, 244, 245, 0, 0, 246, 247, 248, 249, 250, - 21, 0, 984, 349, 0, 985, 0, 0, 0, 0, - 0, 251, 0, 0, 252, 0, 0, 0, 0, 0, - 0, 0, 253, 254, 255, 0, 0, 0, 0, 0, - 256, 257, 258, 0, 0, 0, 0, 259, 0, 986, - 0, 260, 971, 972, 92, 10, 233, 234, 235, 0, - 236, 12, 973, 261, 974, 975, 976, 977, 978, 979, - 980, 981, 982, 983, 13, 14, 15, 237, 238, 239, - 16, 0, 240, 0, 17, 0, 241, 242, 0, 243, - 19, 244, 245, 0, 0, 246, 247, 248, 249, 250, - 21, 0, 984, 1276, 0, 985, 0, 0, 0, 0, - 0, 251, 0, 0, 252, 0, 0, 0, 0, 0, - 0, 0, 253, 254, 255, 0, 0, 0, 0, 0, - 256, 257, 258, 0, 0, 0, 0, 259, 0, 986, - 0, 260, 971, 972, 92, 10, 233, 234, 235, 0, - 236, 12, 973, 261, 974, 975, 976, 977, 978, 979, - 980, 981, 982, 983, 13, 14, 15, 237, 238, 239, - 16, 0, 240, 0, 17, 0, 241, 242, 0, 243, - 19, 244, 245, 0, 0, 246, 247, 248, 249, 250, - 21, 0, 984, 0, 0, 985, 0, 0, 0, 0, - 0, 251, 0, 0, 252, 0, 0, 0, 0, 0, - 0, 0, 253, 254, 255, 0, 0, 0, 0, 0, - 256, 257, 258, 0, 0, 0, 0, 259, 0, 986, - 0, 260, 7, 8, 92, 10, 233, 234, 235, 356, - 236, 12, 0, 261, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 15, 237, 238, 239, - 16, 0, 240, 0, 17, 0, 241, 242, 0, 243, - 19, 244, 245, 513, 0, 246, 247, 248, 249, 250, - 21, 0, 22, 0, 0, 0, 0, 0, 0, 0, - 0, 251, 0, 0, 790, 0, 0, 0, 0, 0, - 0, 0, 253, 254, 791, 0, 0, 0, 0, 0, - 256, 257, 258, 0, 516, 0, 0, 792, 518, 0, - 0, 260, 357, 7, 8, 92, 10, 233, 234, 235, - 356, 236, 12, 261, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 15, 237, 238, - 239, 16, 0, 240, 0, 17, 0, 241, 242, 0, - 243, 19, 244, 245, 513, 0, 246, 247, 248, 249, - 250, 21, 0, 22, 0, 0, 0, 0, 0, 0, - 0, 0, 251, 0, 0, 850, 0, 0, 0, 0, - 0, 0, 0, 253, 254, 851, 0, 0, 0, 0, - 0, 256, 257, 258, 0, 516, 0, 0, 852, 518, - 0, 0, 260, 357, 7, 8, 0, 10, 233, 234, - 235, 0, 236, 12, 261, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 15, 237, - 238, 239, 16, 0, 240, 0, 17, 0, 241, 242, - 0, 243, 19, 244, 245, 513, 0, 246, 247, 248, - 249, 250, 21, 0, 22, 0, 0, 0, 0, 0, - 0, 0, 0, 251, 0, 0, 790, 0, 0, 0, - 0, 0, 0, 0, 253, 254, 791, 0, 0, 0, - 0, 0, 256, 257, 258, 0, 516, 0, 0, 792, - 518, 7, 8, 0, 10, 233, 234, 235, 0, 236, - 12, 0, 0, 0, 0, 261, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 15, 237, 238, 239, 16, - 0, 240, 0, 17, 0, 241, 242, 0, 243, 19, - 244, 245, 513, 0, 246, 247, 248, 249, 250, 21, + 0, 15, 236, 237, 238, 16, 0, 239, 0, 17, + 0, 240, 241, 0, 242, 19, 243, 244, 0, 0, + 245, 246, 247, 248, 249, 21, 0, 22, 0, 0, + 0, 0, 0, 0, 0, 0, 250, 0, 0, 251, + 0, 0, 0, 0, 0, 0, 0, 252, 253, 254, + 0, 0, 0, 0, 0, 255, 256, 257, 0, 0, + 0, 0, 258, 0, 7, 8, 259, 10, 437, 233, + 234, 0, 235, 12, 0, 0, 0, 0, 260, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 15, 236, + 237, 238, 16, 0, 239, 0, 17, 0, 240, 241, + 0, 242, 19, 243, 244, 0, 0, 245, 246, 247, + 248, 249, 21, 0, 22, 0, 0, 0, 0, 0, + 0, 0, 0, 250, 0, 0, 251, 0, 0, 0, + 0, 0, 0, 0, 252, 253, 254, 0, 0, 0, + 0, 0, 255, 256, 257, 0, 0, 0, 0, 258, + 0, 0, 0, 259, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 260, 760, 966, 967, 92, + 10, 232, 233, 234, 0, 235, 12, 968, 0, 969, + 970, 971, 972, 973, 974, 975, 976, 977, 978, 13, + 14, 15, 236, 237, 238, 16, 0, 239, 0, 17, + 0, 240, 241, 0, 242, 19, 243, 244, 0, 0, + 245, 246, 247, 248, 249, 21, 0, 979, 347, 0, + 980, 0, 0, 0, 0, 0, 250, 0, 0, 251, + 0, 0, 0, 0, 0, 0, 0, 252, 253, 254, + 0, 0, 0, 0, 0, 255, 256, 257, 0, 0, + 0, 0, 258, 0, 981, 0, 259, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1110, 260, 966, + 967, 92, 10, 232, 233, 234, 0, 235, 12, 968, + 0, 969, 970, 971, 972, 973, 974, 975, 976, 977, + 978, 13, 14, 15, 236, 237, 238, 16, 0, 239, + 0, 17, 0, 240, 241, 0, 242, 19, 243, 244, + 0, 0, 245, 246, 247, 248, 249, 21, 0, 979, + 347, 0, 980, 0, 0, 0, 0, 0, 250, 0, + 0, 251, 0, 0, 0, 0, 0, 0, 0, 252, + 253, 254, 0, 0, 0, 0, 0, 255, 256, 257, + 0, 0, 0, 0, 258, 0, 981, 0, 259, 966, + 967, 92, 10, 232, 233, 234, 0, 235, 12, 968, + 260, 969, 970, 971, 972, 973, 974, 975, 976, 977, + 978, 13, 14, 15, 236, 237, 238, 16, 0, 239, + 0, 17, 0, 240, 241, 0, 242, 19, 243, 244, + 0, 0, 245, 246, 247, 248, 249, 21, 0, 979, + 1270, 0, 980, 0, 0, 0, 0, 0, 250, 0, + 0, 251, 0, 0, 0, 0, 0, 0, 0, 252, + 253, 254, 0, 0, 0, 0, 0, 255, 256, 257, + 0, 0, 0, 0, 258, 0, 981, 0, 259, 966, + 967, 92, 10, 232, 233, 234, 0, 235, 12, 968, + 260, 969, 970, 971, 972, 973, 974, 975, 976, 977, + 978, 13, 14, 15, 236, 237, 238, 16, 0, 239, + 0, 17, 0, 240, 241, 0, 242, 19, 243, 244, + 0, 0, 245, 246, 247, 248, 249, 21, 0, 979, + 0, 0, 980, 0, 0, 0, 0, 0, 250, 0, + 0, 251, 0, 0, 0, 0, 0, 0, 0, 252, + 253, 254, 0, 0, 0, 0, 0, 255, 256, 257, + 0, 0, 0, 0, 258, 0, 981, 0, 259, 7, + 8, 92, 10, 232, 233, 234, 354, 235, 12, 0, + 260, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 15, 236, 237, 238, 16, 0, 239, + 0, 17, 0, 240, 241, 0, 242, 19, 243, 244, + 510, 0, 245, 246, 247, 248, 249, 21, 0, 22, + 0, 0, 0, 0, 0, 0, 0, 0, 250, 0, + 0, 786, 0, 0, 0, 0, 0, 0, 0, 252, + 253, 787, 0, 0, 0, 0, 0, 255, 256, 257, + 0, 513, 0, 0, 788, 515, 0, 0, 259, 355, + 7, 8, 92, 10, 232, 233, 234, 354, 235, 12, + 260, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 15, 236, 237, 238, 16, 0, + 239, 0, 17, 0, 240, 241, 0, 242, 19, 243, + 244, 510, 0, 245, 246, 247, 248, 249, 21, 0, + 22, 0, 0, 0, 0, 0, 0, 0, 0, 250, + 0, 0, 845, 0, 0, 0, 0, 0, 0, 0, + 252, 253, 846, 0, 0, 0, 0, 0, 255, 256, + 257, 0, 513, 0, 0, 847, 515, 0, 0, 259, + 355, 7, 8, 0, 10, 232, 233, 234, 0, 235, + 12, 260, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 15, 236, 237, 238, 16, + 0, 239, 0, 17, 0, 240, 241, 0, 242, 19, + 243, 244, 510, 0, 245, 246, 247, 248, 249, 21, 0, 22, 0, 0, 0, 0, 0, 0, 0, 0, - 251, 0, 0, 850, 0, 0, 0, 0, 0, 0, - 0, 253, 254, 851, 0, 0, 0, 0, 0, 256, - 257, 258, 0, 516, 0, 0, 852, 518, 7, 8, - 0, 10, 233, 234, 235, 0, 236, 12, 0, 0, - 0, 0, 261, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 15, 237, 238, 239, 16, 0, 240, 0, - 17, 0, 241, 242, 0, 243, 19, 244, 245, 0, - 0, 246, 247, 248, 249, 250, 21, 0, 22, 0, - 0, 0, 0, 0, 0, 0, 0, 251, 0, 0, - 252, 0, 0, 0, 0, 305, 0, 0, 253, 254, - 255, 0, 0, 0, 0, 0, 256, 257, 258, 0, - 0, 0, 0, 259, 0, 7, 8, 260, 10, 440, - 234, 235, 0, 236, 12, 0, 0, 0, 0, 261, + 250, 0, 0, 786, 0, 0, 0, 0, 0, 0, + 0, 252, 253, 787, 0, 0, 0, 0, 0, 255, + 256, 257, 0, 513, 0, 0, 788, 515, 7, 8, + 0, 10, 232, 233, 234, 0, 235, 12, 0, 0, + 0, 0, 260, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 15, 236, 237, 238, 16, 0, 239, 0, + 17, 0, 240, 241, 0, 242, 19, 243, 244, 510, + 0, 245, 246, 247, 248, 249, 21, 0, 22, 0, + 0, 0, 0, 0, 0, 0, 0, 250, 0, 0, + 845, 0, 0, 0, 0, 0, 0, 0, 252, 253, + 846, 0, 0, 0, 0, 0, 255, 256, 257, 0, + 513, 0, 0, 847, 515, 7, 8, 0, 10, 232, + 233, 234, 0, 235, 12, 0, 0, 0, 0, 260, 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, - 237, 238, 239, 16, 0, 240, 0, 17, 0, 241, - 242, 0, 243, 19, 244, 245, 0, 0, 246, 247, - 248, 249, 250, 21, 0, 22, 0, 0, 1093, 0, - 0, 0, 0, 0, 251, 0, 0, 252, 0, 0, - 0, 0, 0, 0, 0, 253, 254, 255, 0, 0, - 0, 0, 0, 256, 257, 258, 0, 0, 0, 0, - 259, 0, 7, 8, 260, 10, 233, 234, 235, 0, - 236, 12, 0, 0, 0, 0, 261, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 15, 237, 238, 239, - 16, 0, 240, 0, 17, 0, 241, 242, 0, 243, - 19, 244, 245, 0, 0, 246, 247, 248, 249, 250, + 236, 237, 238, 16, 0, 239, 0, 17, 0, 240, + 241, 0, 242, 19, 243, 244, 510, 0, 245, 246, + 247, 248, 249, 21, 0, 22, 0, 0, 0, 0, + 0, 0, 0, 0, 250, 0, 0, 940, 0, 0, + 0, 0, 0, 0, 0, 252, 253, 941, 0, 0, + 0, 0, 0, 255, 256, 257, 0, 513, 0, 0, + 788, 515, 7, 8, 0, 10, 232, 233, 234, 0, + 235, 12, 0, 0, 0, 0, 260, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 15, 236, 237, 238, + 16, 0, 239, 0, 17, 0, 240, 241, 0, 242, + 19, 243, 244, 0, 0, 245, 246, 247, 248, 249, 21, 0, 22, 0, 0, 0, 0, 0, 0, 0, - 0, 251, 0, 0, 252, 0, 0, 0, 0, 0, - 0, 0, 253, 254, 255, 0, 0, 0, 0, 0, - 256, 257, 258, 0, 0, 0, 0, 259, 0, 7, - 8, 260, 10, 440, 234, 235, 0, 236, 12, 0, - 0, 0, 0, 261, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 15, 237, 238, 239, 16, 0, 240, - 0, 17, 0, 241, 242, 0, 243, 19, 244, 245, - 0, 0, 246, 247, 248, 249, 250, 21, 0, 22, - 466, 0, 0, 0, 0, 0, 0, 0, 251, 0, - 0, 252, 0, 0, 0, 0, 0, 0, 0, 253, - 254, 255, 0, 0, 0, 0, 0, 256, 257, 258, - 0, 0, 7, 8, 467, 10, 440, 234, 235, 0, - 236, 12, 0, 0, 0, 0, 0, 0, 0, 0, - 261, 0, 0, 0, 0, 0, 15, 237, 238, 239, - 16, 0, 240, 0, 17, 0, 241, 242, 0, 243, - 19, 244, 245, 0, 0, 246, 247, 248, 249, 250, - 21, 0, 22, 0, 0, 0, 0, 0, 0, 0, - 0, 251, 0, 0, 252, 0, 0, 0, 0, 0, - 0, 0, 253, 254, 255, 0, 0, 0, 0, 0, - 256, 257, 258, 0, 0, 0, 0, 259, 503, 7, - 8, 0, 10, 440, 234, 235, 0, 236, 12, 0, - 0, 0, 0, 261, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 15, 237, 238, 239, 16, 0, 240, - 0, 17, 0, 241, 242, 0, 243, 19, 244, 245, - 0, 0, 246, 247, 248, 249, 250, 21, 0, 22, - 0, 0, 0, 0, 0, 0, 0, 0, 251, 0, - 0, 252, 0, 0, 0, 0, 0, 0, 0, 253, - 254, 255, 0, 0, 0, 0, 0, 256, 257, 258, - 0, 0, 0, 0, 259, 0, 7, 701, 260, 10, - 440, 234, 235, 0, 236, 12, 0, 0, 0, 0, - 261, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 15, 237, 238, 239, 16, 0, 240, 0, 17, 0, - 241, 242, 0, 243, 19, 244, 245, 0, 0, 246, - 247, 248, 249, 250, 21, 0, 22, 0, 0, 0, - 0, 0, 0, 0, 0, 251, 0, 0, 252, 0, - 0, 0, 0, 0, 0, 0, 253, 254, 255, 0, - 0, 0, 0, 0, 256, 257, 258, 0, 0, 0, - 0, 259, 0, 7, 8, 260, 10, 440, 234, 235, - 0, 236, 12, 0, 0, 0, 0, 261, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 15, 237, 238, - 239, 16, 0, 240, 0, 17, 0, 241, 242, 0, - 243, 19, 244, 245, 0, 0, 246, 247, 248, 249, - 250, 21, 0, 22, 0, 0, 0, 0, 0, 0, - 0, 0, 251, 0, 0, 895, 0, 0, 0, 0, - 0, 0, 0, 253, 254, 896, 0, 0, 0, 0, - 0, 256, 257, 258, 0, 0, 0, 0, 897, 0, - 7, 8, 260, 10, 440, 234, 235, 0, 236, 12, - 0, 0, 0, 0, 261, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 15, 237, 238, 239, 16, 0, - 240, 0, 17, 0, 241, 242, 0, 243, 19, 244, - 245, 0, 0, 246, 247, 248, 249, 250, 21, 0, - 22, 0, 0, 0, 0, 0, 0, 0, 0, 251, - 0, 0, 1183, 0, 0, 0, 0, 0, 0, 0, - 253, 254, 1184, 0, 0, 0, 0, 0, 256, 257, - 258, 0, 0, 0, 0, 1185, 0, 1248, 8, 260, - 10, 440, 234, 235, 0, 236, 12, 0, 0, 0, - 0, 261, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 15, 237, 238, 239, 16, 0, 240, 0, 17, - 0, 241, 242, 0, 243, 19, 244, 245, 0, 0, - 246, 247, 248, 249, 250, 21, 0, 22, 0, 0, - 0, 0, 0, 0, 0, 0, 251, 0, 0, 252, - 0, 0, 0, 0, 0, 0, 0, 253, 254, 255, - 0, 0, 0, 0, 0, 256, 257, 258, 0, 0, - 0, 0, 259, 0, 7, 8, 260, 10, 440, 234, - 235, 0, 236, 12, 0, 0, 0, 0, 261, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 15, 237, - 238, 239, 16, 0, 240, 0, 17, 0, 241, 242, - 0, 243, 19, 244, 245, 0, 0, 246, 247, 248, - 249, 250, 21, 0, 22, 0, 0, 0, 0, 0, - 0, 0, 0, 251, 0, 0, 252, 0, 0, 0, - 0, 0, 0, 0, 253, 254, 255, 0, 0, 0, - 0, 0, 256, 257, 258, 0, 0, 7, 8, 259, - 10, 440, 234, 235, 0, 236, 12, 0, 0, 0, - 0, 0, 0, 0, 0, 261, 0, 0, 0, 0, - 0, 15, 237, 238, 239, 16, 0, 240, 0, 17, - 0, 241, 242, 0, 243, 19, 244, 245, 0, 0, - 246, 247, 248, 249, 250, 21, 0, 22, 0, 0, - 0, 0, 0, 0, 0, 0, 251, 0, 0, 895, - 0, 0, 0, 0, 0, 0, 0, 253, 254, 896, - 0, 0, 0, 0, 0, 256, 257, 258, 0, 0, - 7, 8, 897, 10, 233, 234, 235, 0, 236, 12, - 0, 0, 0, 0, 0, 0, 0, 0, 261, 0, - 0, 0, 0, 0, 15, 237, 238, 239, 16, 0, - 240, 0, 17, 0, 241, 242, 0, 243, 19, 244, - 245, 0, 0, 246, 247, 248, 249, 250, 21, 0, - 22, 0, 0, 0, 0, 0, 0, 0, 0, 251, - 0, 0, 1183, 0, 0, 0, 0, 0, 0, 0, - 253, 254, 1184, 0, 0, 0, 0, 0, 256, 257, - 258, 0, 0, 7, 8, 1185, 10, 440, 234, 235, - 0, 236, 12, 0, 0, 0, 0, 0, 0, 0, - 0, 261, 0, 0, 0, 0, 0, 15, 237, 0, - 0, 16, 0, 240, 0, 17, 0, 241, 242, 0, - 243, 19, 244, 245, 0, 0, 246, 247, 248, 249, - 250, 21, 0, 22, 0, 0, 0, 0, 0, 0, - 0, 0, 251, 0, 0, 252, 0, 0, 0, 0, - 0, 0, 0, 253, 254, 255, 0, 0, 0, 0, - 0, 256, 257, 258, 0, 0, 7, 8, 441, 10, - 440, 234, 235, 0, 236, 12, 0, 0, 0, 0, - 0, 0, 0, 0, 261, 0, 0, 0, 0, 0, - 15, 237, 0, 0, 16, 0, 240, 0, 17, 0, - 241, 242, 0, 243, 19, 244, 245, 0, 0, 246, - 247, 248, 249, 250, 21, 0, 22, 0, 0, 0, - 0, 0, 0, 0, 0, 251, 0, 0, 252, 0, - 0, 0, 0, 0, 0, 0, 253, 254, 255, 0, - 0, 0, 0, 0, 256, 257, 258, 0, 0, 0, - 0, 444, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 546, 0, 469, 470, 471, 261, 472, 473, - 474, 475, 476, 477, 478, 479, 480, 481, 482, 483, - 484, 485, 486, 487, 488, 489, 490, 469, 470, 471, - 1210, 472, 473, 474, 475, 476, 477, 478, 479, 480, - 481, 482, 483, 484, 485, 486, 487, 488, 489, 490, - 469, 470, 471, 1259, 472, 473, 474, 475, 476, 477, + 0, 250, 0, 0, 251, 0, 0, 0, 0, 304, + 0, 0, 252, 253, 254, 0, 0, 0, 0, 0, + 255, 256, 257, 0, 0, 0, 0, 258, 0, 7, + 8, 259, 10, 437, 233, 234, 0, 235, 12, 0, + 0, 0, 0, 260, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 15, 236, 237, 238, 16, 0, 239, + 0, 17, 0, 240, 241, 0, 242, 19, 243, 244, + 0, 0, 245, 246, 247, 248, 249, 21, 0, 22, + 0, 0, 1087, 0, 0, 0, 0, 0, 250, 0, + 0, 251, 0, 0, 0, 0, 0, 0, 0, 252, + 253, 254, 0, 0, 0, 0, 0, 255, 256, 257, + 0, 0, 0, 0, 258, 0, 7, 8, 259, 10, + 232, 233, 234, 0, 235, 12, 0, 0, 0, 0, + 260, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 15, 236, 237, 238, 16, 0, 239, 0, 17, 0, + 240, 241, 0, 242, 19, 243, 244, 0, 0, 245, + 246, 247, 248, 249, 21, 0, 22, 0, 0, 0, + 0, 0, 0, 0, 0, 250, 0, 0, 251, 0, + 0, 0, 0, 0, 0, 0, 252, 253, 254, 0, + 0, 0, 0, 0, 255, 256, 257, 0, 0, 0, + 0, 258, 0, 7, 8, 259, 10, 437, 233, 234, + 0, 235, 12, 0, 0, 0, 0, 260, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 15, 236, 237, + 238, 16, 0, 239, 0, 17, 0, 240, 241, 0, + 242, 19, 243, 244, 0, 0, 245, 246, 247, 248, + 249, 21, 0, 22, 463, 0, 0, 0, 0, 0, + 0, 0, 250, 0, 0, 251, 0, 0, 0, 0, + 0, 0, 0, 252, 253, 254, 0, 0, 0, 0, + 0, 255, 256, 257, 0, 0, 7, 8, 464, 10, + 437, 233, 234, 0, 235, 12, 0, 0, 0, 0, + 0, 0, 0, 0, 260, 0, 0, 0, 0, 0, + 15, 236, 237, 238, 16, 0, 239, 0, 17, 0, + 240, 241, 0, 242, 19, 243, 244, 0, 0, 245, + 246, 247, 248, 249, 21, 0, 22, 0, 0, 0, + 0, 0, 0, 0, 0, 250, 0, 0, 251, 0, + 0, 0, 0, 0, 0, 0, 252, 253, 254, 0, + 0, 0, 0, 0, 255, 256, 257, 0, 0, 0, + 0, 258, 500, 7, 8, 0, 10, 437, 233, 234, + 0, 235, 12, 0, 0, 0, 0, 260, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 15, 236, 237, + 238, 16, 0, 239, 0, 17, 0, 240, 241, 0, + 242, 19, 243, 244, 0, 0, 245, 246, 247, 248, + 249, 21, 0, 22, 0, 0, 0, 0, 0, 0, + 0, 0, 250, 0, 0, 251, 0, 0, 0, 0, + 0, 0, 0, 252, 253, 254, 0, 0, 0, 0, + 0, 255, 256, 257, 0, 0, 0, 0, 258, 0, + 7, 697, 259, 10, 437, 233, 234, 0, 235, 12, + 0, 0, 0, 0, 260, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 15, 236, 237, 238, 16, 0, + 239, 0, 17, 0, 240, 241, 0, 242, 19, 243, + 244, 0, 0, 245, 246, 247, 248, 249, 21, 0, + 22, 0, 0, 0, 0, 0, 0, 0, 0, 250, + 0, 0, 251, 0, 0, 0, 0, 0, 0, 0, + 252, 253, 254, 0, 0, 0, 0, 0, 255, 256, + 257, 0, 0, 0, 0, 258, 0, 7, 8, 259, + 10, 437, 233, 234, 0, 235, 12, 0, 0, 0, + 0, 260, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 15, 236, 237, 238, 16, 0, 239, 0, 17, + 0, 240, 241, 0, 242, 19, 243, 244, 0, 0, + 245, 246, 247, 248, 249, 21, 0, 22, 0, 0, + 0, 0, 0, 0, 0, 0, 250, 0, 0, 890, + 0, 0, 0, 0, 0, 0, 0, 252, 253, 891, + 0, 0, 0, 0, 0, 255, 256, 257, 0, 0, + 0, 0, 258, 0, 7, 8, 259, 10, 437, 233, + 234, 0, 235, 12, 0, 0, 0, 0, 260, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 15, 236, + 237, 238, 16, 0, 239, 0, 17, 0, 240, 241, + 0, 242, 19, 243, 244, 0, 0, 245, 246, 247, + 248, 249, 21, 0, 22, 0, 0, 0, 0, 0, + 0, 0, 0, 250, 0, 0, 1177, 0, 0, 0, + 0, 0, 0, 0, 252, 253, 1178, 0, 0, 0, + 0, 0, 255, 256, 257, 0, 0, 0, 0, 1179, + 0, 1242, 8, 259, 10, 437, 233, 234, 0, 235, + 12, 0, 0, 0, 0, 260, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 15, 236, 237, 238, 16, + 0, 239, 0, 17, 0, 240, 241, 0, 242, 19, + 243, 244, 0, 0, 245, 246, 247, 248, 249, 21, + 0, 22, 0, 0, 0, 0, 0, 0, 0, 0, + 250, 0, 0, 251, 0, 0, 0, 0, 0, 0, + 0, 252, 253, 254, 0, 0, 0, 0, 0, 255, + 256, 257, 0, 0, 0, 0, 258, 0, 7, 8, + 259, 10, 437, 233, 234, 0, 235, 12, 0, 0, + 0, 0, 260, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 15, 236, 237, 238, 16, 0, 239, 0, + 17, 0, 240, 241, 0, 242, 19, 243, 244, 0, + 0, 245, 246, 247, 248, 249, 21, 0, 22, 0, + 0, 0, 0, 0, 0, 0, 0, 250, 0, 0, + 251, 0, 0, 0, 0, 0, 0, 0, 252, 253, + 254, 0, 0, 0, 0, 0, 255, 256, 257, 0, + 0, 7, 8, 258, 10, 437, 233, 234, 0, 235, + 12, 0, 0, 0, 0, 0, 0, 0, 0, 260, + 0, 0, 0, 0, 0, 15, 236, 237, 238, 16, + 0, 239, 0, 17, 0, 240, 241, 0, 242, 19, + 243, 244, 0, 0, 245, 246, 247, 248, 249, 21, + 0, 22, 0, 0, 0, 0, 0, 0, 0, 0, + 250, 0, 0, 890, 0, 0, 0, 0, 0, 0, + 0, 252, 253, 891, 0, 0, 0, 0, 0, 255, + 256, 257, 0, 0, 7, 8, 258, 10, 232, 233, + 234, 0, 235, 12, 0, 0, 0, 0, 0, 0, + 0, 0, 260, 0, 0, 0, 0, 0, 15, 236, + 237, 238, 16, 0, 239, 0, 17, 0, 240, 241, + 0, 242, 19, 243, 244, 0, 0, 245, 246, 247, + 248, 249, 21, 0, 22, 0, 0, 0, 0, 0, + 0, 0, 0, 250, 0, 0, 1177, 0, 0, 0, + 0, 0, 0, 0, 252, 253, 1178, 0, 0, 0, + 0, 0, 255, 256, 257, 0, 0, 7, 8, 1179, + 10, 437, 233, 234, 0, 235, 12, 0, 0, 0, + 0, 0, 0, 0, 0, 260, 0, 0, 0, 0, + 0, 15, 236, 0, 0, 16, 0, 239, 0, 17, + 0, 240, 241, 0, 242, 19, 243, 244, 0, 0, + 245, 246, 247, 248, 249, 21, 0, 22, 0, 0, + 0, 0, 0, 0, 0, 0, 250, 0, 0, 251, + 0, 0, 0, 0, 0, 0, 0, 252, 253, 254, + 0, 0, 0, 0, 0, 255, 256, 257, 0, 0, + 7, 8, 441, 10, 437, 233, 234, 0, 235, 12, + 0, 0, 0, 0, 0, 0, 0, 0, 260, 0, + 0, 0, 0, 0, 15, 236, 237, 238, 16, 0, + 239, 0, 17, 0, 240, 241, 0, 242, 19, 243, + 244, 0, 0, 245, 246, 247, 248, 249, 21, 0, + 22, 0, 7, 8, 158, 159, 160, 0, 0, 0, + 0, 12, 0, 0, 0, 0, 0, 7, 8, 151, + 10, 152, 0, 0, 0, 0, 12, 0, 255, 256, + 257, 0, 0, 0, 17, 258, 0, 0, 0, 259, + 19, 15, 0, 510, 0, 16, 0, 0, 0, 17, + 21, 260, 22, 0, 0, 19, 0, 0, 0, 0, + 0, 0, 0, 0, 603, 21, 0, 22, 0, 0, + 153, 0, 0, 0, 604, 0, 0, 0, 0, 24, + 0, 0, 26, 0, 513, 0, 0, 605, 515, 25, + 0, 7, 8, 92, 10, 11, 0, 26, 618, 0, + 12, 0, 27, 0, 0, 0, 0, 0, 655, 8, + 151, 10, 152, 0, 0, 15, 0, 12, 0, 16, + 0, 0, 0, 17, 0, 0, 0, 0, 0, 19, + 0, 0, 15, 0, 0, 0, 16, 0, 0, 21, + 17, 22, 0, 0, 0, 0, 19, 0, 0, 0, + 0, 0, 0, 24, 0, 0, 21, 0, 22, 0, + 0, 0, 0, 25, 0, 658, 0, 0, 0, 0, + 24, 26, 0, 0, 0, 0, 27, 0, 0, 0, + 25, 7, 8, 151, 10, 152, 0, 0, 26, 0, + 12, 0, 0, 27, 0, 0, 0, 0, 7, 8, + 151, 10, 152, 0, 0, 15, 0, 12, 0, 16, + 0, 0, 0, 17, 0, 0, 0, 0, 0, 19, + 0, 0, 15, 0, 0, 0, 16, 0, 0, 21, + 17, 22, 0, 0, 1099, 0, 19, 0, 0, 0, + 0, 0, 8, 24, 10, 184, 21, 0, 22, 0, + 12, 0, 0, 25, 0, 0, 0, 0, 0, 0, + 24, 26, 0, 0, 0, 15, 27, 0, 0, 16, + 25, 0, 0, 17, 0, 0, 0, 0, 26, 0, + 0, 0, 510, 27, 0, 0, 0, 0, 0, 21, + 0, 93, 0, 0, 0, 0, 0, 0, 0, 0, + 466, 467, 468, 511, 469, 470, 471, 472, 473, 474, + 475, 476, 477, 512, 479, 480, 481, 482, 483, 484, + 485, 486, 487, 513, 0, 0, 514, 515, 466, 467, + 468, 0, 469, 470, 471, 472, 473, 474, 475, 476, + 477, 478, 479, 480, 481, 482, 483, 484, 485, 486, + 487, 543, 682, 466, 467, 468, 0, 469, 470, 471, + 472, 473, 474, 475, 476, 477, 478, 479, 480, 481, + 482, 483, 484, 485, 486, 487, 1040, 466, 467, 468, + 0, 469, 470, 471, 472, 473, 474, 475, 476, 477, 478, 479, 480, 481, 482, 483, 484, 485, 486, 487, - 488, 489, 490, 469, 470, 471, 0, 472, 473, 474, + 466, 467, 468, 1204, 469, 470, 471, 472, 473, 474, 475, 476, 477, 478, 479, 480, 481, 482, 483, 484, - 485, 486, 487, 488, 489, 490, 469, 470, 471, 0, - 472, 473, 474, 475, 476, 477, 478, 479, 480, 0, - 482, 483, 484, 485, 486, 487, 488, 489, 490, 471, - 0, 472, 473, 474, 475, 476, 477, 478, 479, 480, - 481, 482, 483, 484, 485, 486, 487, 488, 489, 490, + 485, 486, 487, 466, 467, 468, 1253, 469, 470, 471, + 472, 473, 474, 475, 476, 477, 478, 479, 480, 481, + 482, 483, 484, 485, 486, 487, 466, 467, 468, 0, + 469, 470, 471, 472, 473, 474, 475, 476, 477, 478, + 479, 480, 481, 482, 483, 484, 485, 486, 487, 468, + 0, 469, 470, 471, 472, 473, 474, 475, 476, 477, + 478, 479, 480, 481, 482, 483, 484, 485, 486, 487, + 470, 471, 472, 473, 474, 475, 476, 477, 478, 479, + 480, 481, 482, 483, 484, 485, 486, 487, 472, 473, 474, 475, 476, 477, 478, 479, 480, 481, 482, 483, - 484, 485, 486, 487, 488, 489, 490 + 484, 485, 486, 487, 473, 474, 475, 476, 477, 478, + 479, 480, 481, 482, 483, 484, 485, 486, 487 }; static const short yycheck[] = { 4, - 4, 118, 279, 137, 419, 349, 300, 12, 131, 132, - 4, 285, 341, 300, 70, 20, 20, 108, 109, 24, - 25, 12, 27, 392, 285, 266, 52, 300, 33, 33, - 137, 87, 20, 71, 132, 130, 391, 137, 753, 44, - 182, 46, 98, 162, 163, 155, 135, 52, 1161, 820, - 993, 1189, 1052, 4, 59, 9, 56, 34, 34, 9, - 44, 52, 9, 0, 1222, 70, 71, 1169, 51, 3, - 4, 56, 77, 77, 1232, 60, 370, 60, 4, 0, - 10, 410, 87, 370, 3, 4, 69, 44, 365, 77, - 95, 96, 45, 98, 20, 36, 101, 97, 44, 104, - 105, 62, 53, 108, 109, 110, 189, 33, 36, 10, - 60, 95, 58, 1215, 1252, 120, 120, 122, 123, 53, - 7, 48, 41, 10, 75, 55, 103, 103, 4, 4, - 60, 88, 993, 137, 53, 140, 141, 142, 122, 1000, - 1253, 75, 88, 1, 1302, 102, 12, 1285, 102, 518, - 1150, 77, 102, 88, 55, 102, 75, 44, 7, 60, - 302, 166, 103, 93, 83, 126, 443, 4, 55, 44, - 55, 58, 102, 60, 88, 103, 51, 53, 53, 184, - 184, 155, 143, 70, 4, 56, 52, 7, 959, 194, - 65, 4, 93, 300, 120, 189, 54, 158, 287, 75, - 75, 88, 89, 44, 919, 54, 93, 76, 3, 44, - 85, 60, 186, 88, 89, 102, 53, 4, 103, 88, - 89, 1334, 1335, 346, 347, 348, 231, 232, 155, 285, - 99, 51, 103, 53, 272, 162, 163, 990, 75, 992, - 53, 107, 51, 92, 344, 65, 56, 88, 346, 347, - 345, 3, 4, 88, 89, 75, 339, 391, 184, 186, - 69, 535, 75, 370, 3, 4, 53, 272, 137, 89, - 4, 276, 44, 278, 279, 280, 395, 396, 69, 56, - 44, 286, 92, 44, 391, 4, 396, 44, 7, 380, - 381, 391, 44, 102, 252, 300, 300, 255, 44, 51, - 258, 53, 286, 230, 423, 10, 264, 56, 663, 314, - 66, 1172, 317, 1256, 53, 273, 88, 322, 401, 53, - 1263, 326, 326, 44, 88, 654, 103, 88, 89, 85, - 60, 88, 51, 51, 53, 55, 88, 460, 326, 439, - 1055, 102, 88, 89, 56, 339, 65, 103, 55, 56, - 55, 69, 279, 58, 103, 60, 75, 362, 363, 364, - 365, 366, 56, 3, 4, 370, 370, 88, 1229, 55, - 331, 376, 102, 378, 1317, 380, 381, 382, 362, 88, - 364, 365, 102, 388, 44, 251, 54, 391, 93, 394, - 259, 103, 397, 387, 150, 1256, 496, 60, 498, 499, - 326, 41, 1263, 3, 4, 410, 69, 401, 56, 103, - 517, 416, 417, 53, 419, 419, 102, 524, 51, 424, - 789, 6, 7, 55, 60, 56, 1287, 12, 88, 89, - 530, 300, 416, 788, 56, 75, 3, 4, 365, 6, - 196, 41, 102, 83, 405, 450, 451, 452, 453, 54, - 35, 51, 56, 53, 3, 4, 1317, 103, 27, 44, - 60, 422, 500, 44, 55, 65, 102, 54, 395, 396, - 102, 51, 103, 596, 41, 75, 55, 3, 4, 44, - 60, 103, 56, 83, 102, 585, 53, 570, 88, 69, - 448, 70, 41, 419, 823, 500, 423, 502, 596, 103, - 54, 370, 609, 88, 53, 44, 60, 88, 615, 514, - 515, 102, 517, 517, 808, 41, 83, 44, 92, 524, - 524, 808, 391, 88, 798, 644, 75, 53, 284, 663, - 556, 58, 55, 44, 83, 808, 102, 798, 867, 108, - 109, 110, 3, 4, 5, 6, 7, 70, 103, 88, - 555, 556, 308, 794, 102, 424, 663, 83, 3, 4, - 929, 88, 89, 54, 647, 556, 55, 56, 685, 60, - 44, 555, 441, 142, 35, 444, 570, 88, 89, 9, - 449, 450, 451, 452, 453, 3, 4, 5, 6, 7, - 51, 1, 53, 54, 463, 23, 102, 680, 467, 102, - 466, 92, 607, 608, 609, 609, 51, 44, 53, 54, - 615, 615, 92, 23, 88, 25, 26, 3, 4, 3, - 1035, 58, 32, 55, 56, 51, 631, 632, 555, 634, - 499, 60, 60, 977, 60, 53, 105, 98, 99, 100, - 69, 1, 97, 69, 54, 55, 56, 924, 58, 654, - 60, 88, 388, 647, 788, 41, 756, 4, 663, 663, - 55, 397, 37, 23, 54, 25, 26, 53, 60, 769, - 60, 771, 32, 4, 51, 70, 51, 682, 6, 7, - 436, 788, 92, 60, 12, 792, 680, 692, 693, 694, - 556, 88, 69, 89, 54, 55, 56, 83, 58, 60, - 60, 808, 92, 664, 51, 105, 53, 35, 669, 670, - 925, 926, 673, 928, 88, 992, 55, 644, 65, 58, - 51, 89, 53, 55, 56, 825, 592, 827, 75, 829, - 23, 70, 92, 54, 65, 56, 25, 26, 845, 60, - 1084, 1085, 798, 27, 75, 852, 88, 752, 692, 693, - 694, 88, 843, 844, 1098, 682, 512, 69, 89, 850, - 851, 54, 88, 56, 69, 58, 69, 60, 773, 69, - 775, 527, 25, 26, 1118, 1119, 54, 782, 56, 25, - 26, 786, 60, 788, 788, 790, 791, 792, 792, 9, - 78, 79, 103, 798, 663, 878, 879, 55, 881, 55, - 56, 54, 3, 808, 808, 810, 764, 60, 54, 1334, - 1335, 380, 381, 382, 60, 3, 4, 55, 56, 3, - 4, 1165, 102, 7, 108, 109, 110, 102, 54, 102, - 56, 103, 790, 791, 60, 102, 841, 842, 843, 844, - 845, 845, 55, 56, 849, 850, 851, 852, 852, 37, - 38, 55, 56, 41, 236, 237, 54, 41, 142, 102, - 44, 7, 867, 51, 58, 53, 102, 51, 102, 53, - 1296, 1297, 877, 102, 4, 880, 58, 882, 882, 884, - 105, 65, 12, 752, 878, 879, 102, 881, 44, 88, - 20, 75, 850, 851, 24, 25, 105, 27, 32, 83, - 105, 85, 105, 33, 88, 89, 102, 581, 4, 5, - 102, 102, 873, 782, 44, 51, 46, 6, 105, 788, - 925, 926, 52, 928, 88, 81, 82, 44, 55, 59, - 86, 87, 88, 89, 58, 31, 58, 895, 896, 808, - 36, 71, 4, 5, 58, 102, 56, 77, 56, 1226, - 102, 56, 56, 958, 958, 51, 882, 53, 56, 58, - 55, 635, 102, 1086, 102, 95, 96, 102, 834, 31, - 88, 101, 646, 931, 36, 105, 105, 55, 108, 109, - 110, 60, 88, 89, 55, 990, 991, 992, 55, 51, - 120, 53, 122, 123, 25, 26, 60, 866, 1, 1004, - 1005, 32, 1007, 88, 58, 102, 990, 70, 992, 102, - 140, 141, 142, 70, 102, 884, 102, 70, 102, 102, - 23, 102, 25, 26, 55, 56, 70, 58, 897, 32, - 1035, 1035, 958, 102, 60, 60, 166, 5, 6, 7, - 609, 55, 102, 1337, 12, 911, 615, 60, 1131, 1132, - 1337, 54, 55, 56, 184, 58, 102, 60, 105, 102, - 1177, 103, 102, 83, 194, 992, 1189, 35, 89, 1030, - 1031, 105, 343, 44, 5, 6, 7, 105, 102, 102, - 102, 12, 34, 4, 103, 102, 7, 105, 58, 92, - 102, 847, 1183, 1184, 663, 102, 380, 381, 382, 1182, - 966, 231, 232, 1108, 35, 1205, 102, 102, 58, 1035, - 88, 88, 4, 5, 6, 7, 88, 983, 10, 88, - 12, 88, 103, 44, 75, 76, 77, 78, 79, 1252, - 51, 105, 53, 6, 60, 27, 102, 1131, 1132, 31, - 102, 815, 272, 35, 65, 102, 1107, 102, 278, 279, - 280, 105, 88, 259, 75, 285, 286, 3, 4, 51, - 102, 53, 1285, 102, 85, 103, 1127, 88, 89, 102, - 300, 1271, 102, 1039, 102, 60, 56, 56, 1183, 1184, - 1185, 7, 54, 14, 314, 1179, 56, 317, 1182, 58, - 102, 865, 322, 949, 102, 41, 326, 60, 44, 60, - 874, 93, 27, 1286, 105, 51, 44, 53, 56, 883, - 88, 341, 1078, 56, 60, 1338, 58, 88, 58, 65, - 88, 102, 1227, 105, 15, 1183, 1184, 102, 102, 75, - 1337, 58, 362, 363, 364, 365, 366, 83, 102, 56, - 370, 103, 88, 1227, 56, 56, 376, 102, 378, 102, - 380, 381, 382, 56, 56, 102, 9, 58, 388, 56, - 56, 102, 3, 4, 394, 88, 7, 397, 56, 375, - 55, 91, 102, 102, 843, 844, 845, 56, 102, 9, - 410, 850, 851, 852, 109, 110, 416, 417, 102, 419, - 58, 56, 1286, 102, 424, 88, 102, 1258, 102, 1226, - 41, 3, 4, 44, 9, 7, 56, 0, 0, 119, - 51, 2, 53, 328, 808, 120, 1185, 142, 823, 99, - 450, 451, 452, 453, 65, 609, 120, 1150, 1160, 1191, - 130, 615, 1337, 1337, 75, 441, 512, 1203, 444, 41, - 446, 447, 83, 449, 85, 1019, 1020, 88, 89, 51, - 463, 53, 1087, 4, 991, 626, 7, 1203, 1032, 1033, - 592, 467, 803, 65, 688, 471, 867, 33, 33, 654, - 500, 813, 502, 75, 4, 958, 417, 543, 882, 663, - 880, 83, 801, 12, 514, 515, 88, 517, 500, 837, - 20, 497, 1276, 44, 524, 1310, 4, 503, 6, 7, - 51, 1312, 53, 33, 12, 535, 73, 74, 75, 76, - 77, 78, 79, 884, 65, -1, 46, 10, -1, 27, - -1, 370, -1, 31, 75, 555, 556, 35, -1, 59, - -1, -1, 25, 26, 85, -1, -1, 88, 89, 32, - -1, 71, -1, 51, -1, 53, 76, 77, -1, -1, - -1, 44, -1, -1, -1, -1, 1130, -1, 88, 89, - -1, -1, 55, 56, -1, 58, 96, 60, 1337, 99, - -1, -1, -1, -1, -1, -1, -1, 607, 608, 609, - 88, -1, -1, -1, 755, 615, -1, -1, -1, 4, - 120, 6, 7, 123, -1, 88, 89, 12, -1, 92, - 93, 631, 632, -1, 634, -1, -1, 137, -1, 102, - -1, -1, 27, -1, -1, -1, 31, -1, -1, -1, - 35, -1, 1196, 1197, 654, 1199, 1200, -1, -1, -1, - -1, -1, -1, 663, -1, -1, 51, -1, 53, 1108, - -1, 812, -1, -1, 1, -1, 3, 4, 5, 6, - 7, -1, 682, -1, 184, 12, 381, 382, -1, 843, - 844, 845, 692, 693, 694, -1, 850, 851, 852, -1, - 27, -1, -1, -1, 31, -1, -1, -1, 35, 36, - -1, -1, -1, -1, 41, -1, 857, -1, -1, -1, - -1, -1, -1, -1, 51, -1, 53, -1, -1, 56, - -1, 231, -1, 60, 4, -1, 6, 7, 65, -1, - 137, -1, 12, -1, 1183, 1184, 1185, -1, 75, -1, - -1, -1, 752, -1, -1, -1, 83, -1, -1, 259, - -1, 88, 1306, -1, -1, 35, -1, -1, -1, 910, - 911, -1, 272, 773, 44, 775, 103, -1, -1, -1, - 280, 51, 782, 53, 760, -1, 786, -1, 788, -1, - 790, 791, 792, -1, 71, 65, -1, -1, 798, 76, - 300, -1, -1, -1, -1, 75, -1, -1, 808, -1, - 810, 88, 89, -1, -1, 85, 792, -1, 88, 89, - -1, -1, 99, 823, -1, 966, 326, -1, -1, 524, - -1, -1, -1, 3, 4, -1, -1, -1, -1, -1, - -1, 841, 842, 843, 844, 845, -1, -1, -1, 849, - 850, 851, 852, -1, -1, -1, -1, -1, -1, -1, - 137, 4, -1, 363, 7, -1, 366, 867, -1, -1, - 370, 41, -1, -1, -1, -1, 852, 877, -1, -1, - 880, 51, 882, 53, 884, -1, 56, -1, -1, -1, - 866, 391, -1, -1, -1, 65, -1, -1, -1, 1040, - -1, 44, -1, -1, 1045, 75, -1, -1, 51, -1, - 53, -1, -1, 83, 609, -1, -1, 417, 88, 419, - 615, 897, 65, -1, 424, 925, 926, -1, 928, -1, - -1, -1, 75, -1, -1, -1, -1, -1, -1, -1, - -1, 441, 85, -1, 444, 88, 89, 344, -1, 449, - 450, 451, 452, 453, 1108, -1, -1, -1, 958, -1, - -1, -1, 4, 463, 6, 7, -1, 467, 663, -1, - 12, -1, -1, 24, 25, -1, -1, -1, -1, 1120, - 1121, -1, 259, -1, -1, 27, -1, -1, -1, 31, - 990, 991, 992, 35, 391, 272, -1, -1, -1, 499, - 500, -1, 697, -1, 1004, 1005, 982, 1007, 1149, 51, - -1, 53, 54, -1, -1, -1, -1, 517, -1, -1, - 71, -1, -1, 300, 524, 76, -1, -1, -1, 1183, - 1184, 1185, -1, 3, 4, 1035, -1, 88, 89, -1, - -1, -1, 439, -1, -1, -1, 88, -1, 99, -1, - 3, 4, -1, 1194, 7, -1, -1, 108, 109, -1, - 1201, 1202, -1, -1, -1, 1041, 1042, 1043, 1044, 1210, - -1, 41, -1, -1, -1, -1, -1, 1053, -1, -1, - -1, 51, -1, 53, -1, -1, 137, -1, 41, 140, - 141, 44, -1, 370, -1, 65, 791, 792, 51, 496, - 53, 498, 499, -1, -1, 75, -1, -1, 1108, 609, - -1, 1087, 65, 83, 391, 615, -1, -1, 88, 1095, - -1, -1, 75, -1, -1, -1, -1, 524, 1269, 1270, - 83, -1, 85, 530, -1, 88, 89, 71, 72, 73, - 74, 75, 76, 77, 78, 79, -1, 424, -1, 844, - 845, -1, -1, -1, -1, -1, 851, 852, -1, -1, - -1, -1, -1, 663, 441, -1, -1, 444, -1, -1, - -1, -1, 449, 450, 451, 452, 453, -1, -1, -1, - -1, -1, -1, 1183, 1184, 1185, 463, -1, 585, -1, - 467, -1, -1, 1169, 1, 1336, 3, 4, 5, 6, - 7, 896, 897, -1, -1, 12, -1, -1, 259, 1185, - -1, -1, -1, -1, 1190, 1191, -1, -1, 615, -1, - 27, 272, 499, 500, 31, -1, -1, 1227, 35, 36, - -1, -1, -1, -1, 41, -1, -1, -1, -1, 1215, - 517, -1, -1, -1, 51, -1, 53, 524, -1, 300, - -1, -1, 752, 60, -1, -1, 756, -1, 65, -1, - -1, 1, -1, 3, 4, 5, 6, 7, 75, -1, - -1, -1, 12, -1, -1, 4, 83, 6, 7, -1, - -1, 88, 782, 12, -1, 25, 26, 27, 788, -1, - -1, 31, 792, -1, -1, 35, 103, -1, 27, 39, - 697, 41, 31, -1, 1280, 45, 35, -1, 808, -1, - 810, 51, -1, 53, -1, -1, 56, -1, -1, 370, - 1296, 1297, 51, -1, 53, 65, -1, -1, -1, 380, - 381, -1, 609, 1309, -1, 75, 836, 1337, 615, -1, - 391, -1, -1, 83, -1, 845, -1, -1, 88, -1, - -1, -1, 852, -1, 94, 95, -1, 3, 4, 756, - -1, 7, -1, -1, -1, -1, 866, -1, -1, -1, - -1, -1, 769, 424, 771, -1, -1, -1, -1, -1, - -1, -1, 882, -1, 884, -1, 663, -1, -1, -1, - 441, -1, -1, 444, -1, 41, -1, 897, 449, 450, - 451, 452, 453, -1, -1, 51, -1, 53, -1, -1, - -1, -1, 463, 1108, -1, -1, 467, -1, -1, 65, - 1, -1, 3, 4, 5, 6, 7, -1, 825, 75, - 827, 12, 829, -1, -1, -1, -1, 83, -1, 69, - -1, -1, 88, -1, -1, -1, 27, -1, 499, 500, - 31, -1, -1, -1, 35, 36, -1, 76, 958, -1, - 41, -1, -1, 514, 515, -1, 517, -1, -1, -1, - 51, -1, 53, 524, -1, 752, -1, -1, -1, 60, - 99, -1, -1, -1, 65, -1, -1, 117, -1, 1184, - 1185, 991, -1, 993, 75, -1, -1, -1, -1, -1, - 1000, -1, 83, -1, -1, 782, 136, 88, -1, -1, - -1, 788, -1, -1, -1, 792, -1, -1, 137, -1, - -1, 151, 103, -1, -1, -1, -1, -1, -1, -1, - -1, 808, -1, -1, -1, 1035, 1, -1, 3, 4, - 5, 6, 7, -1, 3, 4, -1, 12, 7, -1, - -1, -1, -1, -1, -1, -1, 607, 608, 609, -1, - -1, -1, 27, -1, 615, -1, 31, -1, 845, -1, - 35, 36, -1, -1, -1, 852, 41, -1, -1, -1, - -1, -1, 41, -1, -1, 44, 51, 1087, 53, 866, - -1, 56, 51, -1, 53, 60, -1, -1, 3, 4, - 65, -1, -1, -1, -1, -1, 65, 884, -1, -1, - 75, -1, 663, -1, -1, -1, 75, -1, 83, -1, - 897, -1, -1, 88, 83, -1, 85, -1, -1, 88, - 89, -1, 4, 5, 6, 7, 41, -1, 103, 44, - 12, 260, -1, -1, -1, -1, 51, -1, 53, -1, - -1, -1, -1, -1, -1, 27, -1, -1, -1, 31, - 65, 1161, 1, 35, 3, 4, 5, 6, 7, 1169, - 75, -1, 1172, 12, -1, -1, -1, -1, 83, 51, - 85, 53, -1, 88, 89, 1185, -1, -1, 27, -1, - 1190, 1191, 31, -1, -1, -1, 35, 3, 4, -1, - -1, 752, 41, -1, -1, -1, 45, -1, -1, -1, - -1, 1108, 51, -1, 53, 1215, -1, 56, -1, -1, - -1, -1, 1222, -1, 343, 344, 65, -1, -1, 1229, - -1, 782, 1232, -1, -1, 41, 75, 788, -1, 790, - 791, 792, -1, -1, 83, 51, -1, 53, -1, 88, - 56, -1, -1, 1253, 384, 94, 1256, 808, -1, 65, - 390, -1, -1, 1263, -1, -1, -1, -1, -1, 75, - -1, -1, 391, -1, -1, -1, -1, 83, -1, -1, - -1, -1, 88, 4, 5, 6, 7, 1287, -1, -1, - -1, 12, 843, 844, 845, 414, -1, -1, -1, 850, - 851, 852, 1302, -1, 434, 435, 27, 437, 1205, -1, - 31, -1, -1, -1, 35, 866, -1, 1317, -1, -1, - 439, -1, -1, -1, -1, -1, -1, -1, -1, -1, - 51, -1, 53, 884, 1334, 1335, -1, 1337, 3, 4, - -1, -1, 7, -1, 463, -1, 897, 466, 69, -1, - 469, 470, -1, 472, 473, 474, 475, 476, 477, 478, - 479, 480, 481, 482, 483, 484, 485, 486, 487, 488, - 489, 490, -1, -1, 1271, -1, 41, 496, -1, 498, - 499, -1, -1, -1, -1, -1, 51, -1, 53, -1, - 520, 521, 1169, -1, 4, 525, 6, -1, -1, -1, - 65, -1, 12, -1, -1, 524, -1, -1, 1185, -1, - 75, 530, -1, 1190, 1191, -1, -1, 27, 83, -1, - -1, 31, -1, 88, -1, 35, 545, 546, -1, -1, - -1, -1, -1, -1, -1, -1, -1, -1, 1215, -1, - -1, 51, -1, 53, -1, -1, -1, -1, -1, -1, + 4, 188, 265, 136, 416, 284, 117, 12, 108, 109, + 4, 339, 12, 299, 4, 20, 20, 389, 388, 24, + 25, 52, 27, 284, 131, 347, 749, 71, 33, 33, + 20, 20, 154, 161, 162, 130, 131, 134, 129, 44, + 299, 46, 816, 33, 136, 988, 1155, 52, 1047, 181, + 1183, 299, 52, 34, 59, 988, 9, 1, 9, 4, + 9, 48, 995, 55, 88, 70, 71, 278, 1216, 70, + 34, 154, 77, 77, 10, 3, 4, 44, 1226, 407, + 7, 10, 87, 55, 55, 56, 87, 77, 77, 36, + 95, 96, 4, 98, 3, 4, 101, 98, 70, 104, + 105, 36, 185, 108, 109, 51, 4, 60, 53, 368, + 54, 103, 4, 1246, 119, 119, 121, 122, 44, 55, + 368, 62, 103, 69, 60, 53, 55, 54, 95, 119, + 75, 60, 136, 60, 139, 140, 141, 12, 1247, 103, + 56, 53, 4, 515, 53, 1144, 1279, 75, 1296, 102, + 337, 102, 363, 102, 121, 53, 103, 93, 76, 51, + 165, 53, 88, 4, 93, 92, 102, 154, 103, 301, + 88, 89, 4, 65, 161, 162, 102, 52, 183, 183, + 954, 99, 1163, 75, 125, 27, 44, 103, 193, 286, + 913, 53, 44, 183, 188, 60, 51, 89, 185, 56, + 58, 142, 0, 44, 69, 60, 58, 299, 55, 54, + 51, 398, 53, 75, 69, 60, 157, 44, 136, 1328, + 1329, 53, 56, 70, 65, 230, 231, 271, 1209, 440, + 88, 89, 107, 1166, 75, 0, 88, 344, 345, 6, + 7, 55, 229, 75, 85, 12, 103, 88, 89, 344, + 345, 346, 343, 532, 4, 388, 3, 4, 88, 89, + 60, 88, 89, 66, 392, 393, 271, 109, 35, 103, + 275, 393, 277, 278, 279, 102, 368, 44, 378, 379, + 285, 4, 85, 284, 7, 56, 56, 44, 102, 659, + 1223, 278, 420, 56, 299, 299, 388, 44, 51, 141, + 103, 23, 102, 53, 51, 60, 53, 1250, 313, 44, + 985, 316, 987, 56, 1257, 320, 69, 1250, 285, 324, + 324, 88, 650, 55, 1257, 75, 97, 1050, 51, 92, + 53, 88, 89, 103, 324, 324, 55, 10, 60, 88, + 258, 88, 65, 337, 45, 102, 149, 102, 1281, 102, + 56, 56, 75, 88, 4, 360, 361, 362, 363, 364, + 103, 56, 457, 368, 368, 60, 89, 3, 1311, 374, + 102, 376, 56, 378, 379, 250, 363, 136, 1311, 566, + 385, 299, 55, 102, 388, 58, 391, 60, 329, 394, + 384, 4, 195, 360, 7, 362, 363, 103, 103, 3, + 4, 51, 407, 53, 398, 392, 393, 55, 413, 414, + 1, 416, 416, 785, 784, 65, 421, 55, 56, 103, + 93, 54, 514, 69, 44, 75, 416, 60, 258, 521, + 44, 44, 23, 420, 25, 26, 88, 41, 51, 44, + 53, 32, 447, 448, 449, 450, 413, 55, 56, 53, + 368, 44, 65, 497, 102, 44, 643, 27, 44, 92, + 54, 402, 75, 54, 55, 56, 60, 58, 88, 60, + 388, 75, 85, 55, 88, 88, 89, 44, 419, 83, + 283, 44, 54, 88, 89, 592, 3, 4, 70, 676, + 56, 819, 497, 51, 499, 88, 89, 592, 92, 88, + 89, 92, 88, 421, 307, 44, 511, 512, 4, 514, + 514, 7, 640, 605, 56, 794, 521, 521, 804, 611, + 438, 88, 553, 441, 41, 88, 659, 790, 446, 447, + 448, 449, 450, 794, 862, 60, 53, 379, 108, 109, + 44, 54, 460, 373, 69, 804, 464, 552, 553, 88, + 92, 923, 44, 553, 58, 51, 804, 53, 75, 3, + 4, 44, 6, 103, 385, 552, 83, 659, 54, 65, + 681, 141, 566, 394, 55, 25, 26, 58, 496, 75, + 102, 3, 4, 342, 88, 552, 3, 4, 463, 70, + 55, 56, 3, 4, 3, 4, 88, 41, 603, 604, + 605, 605, 102, 51, 54, 88, 611, 611, 438, 53, + 60, 441, 60, 443, 444, 102, 446, 51, 1030, 41, + 102, 69, 627, 628, 41, 630, 60, 25, 26, 388, + 433, 53, 41, 37, 464, 69, 53, 9, 468, 83, + 51, 102, 53, 54, 53, 650, 54, 51, 56, 643, + 972, 784, 60, 640, 659, 659, 54, 103, 75, 6, + 7, 83, 60, 92, 494, 12, 83, 4, 3, 6, + 500, 97, 27, 678, 83, 12, 60, 436, 553, 521, + 25, 26, 676, 688, 689, 690, 873, 874, 35, 876, + 27, 678, 784, 105, 31, 88, 788, 89, 35, 136, + 3, 4, 5, 6, 7, 105, 509, 918, 5, 6, + 7, 51, 804, 588, 51, 12, 53, 78, 79, 660, + 60, 524, 55, 56, 665, 666, 55, 56, 669, 69, + 919, 920, 35, 922, 493, 89, 495, 496, 35, 839, + 840, 659, 60, 748, 88, 845, 846, 88, 51, 88, + 53, 54, 88, 108, 109, 847, 1078, 1079, 69, 54, + 69, 56, 521, 605, 769, 60, 771, 69, 527, 611, + 1092, 69, 54, 778, 56, 9, 987, 782, 60, 784, + 784, 786, 787, 788, 788, 102, 141, 103, 23, 794, + 1112, 1113, 55, 794, 102, 98, 99, 100, 102, 804, + 804, 806, 102, 3, 4, 5, 6, 7, 378, 379, + 3, 3, 4, 103, 688, 689, 690, 659, 54, 54, + 58, 56, 581, 58, 7, 60, 55, 56, 55, 56, + 748, 102, 837, 838, 839, 840, 102, 1159, 102, 844, + 845, 846, 847, 847, 58, 37, 38, 1328, 1329, 41, + 105, 693, 611, 53, 102, 4, 105, 862, 88, 51, + 778, 53, 32, 12, 235, 236, 784, 872, 1290, 1291, + 875, 20, 877, 877, 879, 24, 25, 105, 27, 873, + 874, 105, 876, 102, 33, 102, 804, 877, 75, 76, + 77, 78, 79, 4, 102, 44, 7, 46, 51, 25, + 26, 6, 105, 52, 88, 342, 32, 44, 58, 55, + 59, 5, 6, 7, 919, 920, 58, 922, 12, 58, + 56, 56, 71, 56, 56, 56, 756, 868, 77, 55, + 56, 55, 58, 44, 693, 940, 941, 102, 1125, 1126, + 51, 35, 53, 861, 58, 787, 95, 96, 953, 953, + 102, 388, 101, 55, 65, 830, 105, 102, 788, 108, + 109, 879, 102, 953, 75, 3, 4, 105, 88, 7, + 119, 60, 121, 122, 85, 55, 55, 88, 89, 60, + 985, 986, 987, 58, 88, 1080, 102, 102, 70, 1176, + 139, 140, 141, 752, 999, 1000, 102, 1002, 840, 436, + 987, 102, 102, 41, 846, 847, 765, 102, 767, 1220, + 102, 70, 70, 51, 70, 53, 165, 847, 985, 102, + 987, 60, 55, 378, 379, 1030, 1030, 65, 60, 102, + 905, 861, 60, 102, 183, 605, 102, 75, 105, 842, + 1030, 611, 103, 89, 193, 83, 83, 102, 105, 891, + 88, 44, 102, 102, 3, 4, 493, 105, 495, 496, + 1171, 105, 821, 103, 823, 34, 825, 102, 4, 5, + 6, 7, 1331, 102, 10, 102, 12, 1177, 1178, 102, + 102, 230, 231, 1331, 1025, 1026, 961, 58, 1183, 659, + 527, 27, 41, 1280, 58, 31, 102, 1102, 88, 35, + 88, 88, 51, 978, 53, 7, 88, 56, 10, 88, + 105, 103, 6, 102, 105, 51, 65, 53, 102, 102, + 60, 102, 271, 103, 102, 102, 75, 102, 277, 278, + 279, 1125, 1126, 88, 83, 284, 285, 102, 60, 88, + 56, 944, 44, 56, 581, 7, 54, 977, 14, 56, + 299, 1246, 58, 55, 102, 102, 58, 93, 60, 1034, + 1101, 341, 60, 60, 313, 44, 105, 316, 70, 88, + 56, 320, 1177, 1178, 1179, 324, 56, 88, 88, 1173, + 1121, 58, 1176, 58, 1279, 102, 88, 89, 102, 15, + 339, 93, 56, 105, 4, 5, 56, 1072, 102, 102, + 102, 56, 103, 102, 56, 56, 1036, 1037, 1038, 1039, + 102, 360, 361, 362, 363, 364, 1221, 58, 1048, 368, + 58, 31, 9, 56, 102, 374, 36, 376, 102, 378, + 379, 56, 56, 1220, 88, 55, 385, 1332, 56, 1331, + 88, 51, 391, 53, 102, 394, 4, 5, 91, 102, + 605, 1081, 102, 102, 1221, 58, 611, 102, 407, 1089, + 1102, 1179, 9, 56, 413, 414, 1, 416, 102, 839, + 840, 102, 421, 31, 56, 845, 846, 847, 36, 9, + 0, 0, 118, 326, 2, 1, 1280, 119, 23, 804, + 25, 26, 119, 51, 129, 53, 819, 32, 447, 448, + 449, 450, 99, 460, 659, 1144, 1154, 23, 1185, 25, + 26, 1252, 509, 1081, 986, 752, 32, 684, 1197, 54, + 55, 56, 1197, 58, 799, 60, 1331, 1331, 765, 588, + 767, 33, 33, 1163, 862, 650, 1178, 1179, 54, 55, + 56, 809, 58, 1102, 60, 877, 953, 12, 497, 1179, + 499, 4, 414, 497, 1184, 1185, 875, 92, 4, 5, + 6, 7, 511, 512, 10, 514, 12, 20, 540, 797, + 1270, 833, 521, 1304, 1306, -1, 92, 44, 879, 1209, + 33, 27, 368, 532, 821, 31, 823, -1, 825, 35, + -1, 3, 4, 46, 71, 72, 73, 74, 75, 76, + 77, 78, 79, 552, 553, 51, 59, 53, -1, -1, + -1, -1, -1, 1331, 81, 82, -1, -1, 71, 86, + 87, 88, 89, 76, 77, -1, -1, -1, -1, 41, + -1, -1, 44, -1, -1, 88, 89, -1, -1, 51, + 1199, 53, 622, 96, 1274, -1, 99, -1, 60, -1, + -1, -1, -1, 65, 603, 604, 605, -1, -1, -1, + 1290, 1291, 611, 75, -1, -1, 119, -1, -1, 122, + -1, 83, -1, 1303, -1, -1, 88, -1, 627, 628, + -1, 630, -1, 136, 839, 840, -1, -1, -1, -1, + 845, 846, 847, -1, -1, -1, 4, 5, 6, 7, + -1, 650, -1, -1, 12, -1, 1265, -1, 3, 4, + 659, -1, 7, 139, 140, 141, 71, -1, -1, 27, + -1, 76, -1, 31, -1, -1, -1, 35, -1, 678, + 183, -1, 1102, 88, 89, -1, -1, -1, -1, 688, + 689, 690, -1, 51, 99, 53, 41, -1, -1, 44, + -1, -1, -1, -1, -1, -1, 51, -1, 53, -1, + -1, 69, -1, -1, -1, -1, 251, 24, 25, 254, + 65, 751, 257, -1, -1, -1, -1, 230, 263, -1, + 75, 136, -1, -1, -1, -1, -1, 272, 83, -1, + 85, -1, -1, 88, 89, -1, -1, -1, -1, 748, + -1, -1, -1, -1, -1, 258, -1, 1177, 1178, 1179, + -1, -1, -1, 4, 71, 6, 7, -1, 271, 76, + 769, 12, 771, -1, -1, -1, 279, -1, 808, 778, + -1, 88, 89, 782, -1, 784, 27, 786, 787, 788, + 31, -1, 99, -1, 35, 794, 299, -1, -1, -1, + -1, 108, 109, -1, -1, 804, -1, 806, -1, -1, + 51, -1, 53, -1, -1, -1, -1, -1, 577, -1, + 819, 324, 852, -1, -1, -1, -1, -1, -1, 136, + -1, -1, 139, 140, -1, -1, -1, -1, 837, 838, + 839, 840, -1, -1, -1, 844, 845, 846, 847, -1, + -1, -1, -1, 258, -1, -1, -1, -1, 361, -1, + -1, 364, -1, 862, -1, 368, 271, -1, -1, -1, + -1, -1, 631, 872, 904, 905, 875, -1, 877, -1, + 879, -1, -1, 642, -1, 388, 73, 74, 75, 76, + 77, 78, 79, -1, 299, -1, -1, 1102, 374, -1, + 376, 69, 378, 379, -1, -1, -1, -1, -1, -1, + 445, 414, 1199, 416, -1, 391, -1, -1, 421, -1, + 919, 920, -1, 922, -1, -1, -1, 3, 4, -1, + -1, 961, -1, -1, -1, 438, -1, 413, 441, -1, + -1, 940, 941, 446, 447, 448, 449, 450, 116, -1, + -1, 258, -1, -1, 953, -1, -1, 460, -1, -1, + -1, 464, -1, 368, 271, 41, -1, 135, 44, -1, + -1, -1, 1177, 1178, 1179, 51, -1, 53, 1265, -1, + -1, -1, 150, 388, -1, -1, 985, 986, 987, 65, + -1, -1, 299, 496, 497, -1, -1, -1, -1, 75, + 999, 1000, -1, 1002, -1, 1035, -1, 83, -1, 85, + 1040, 514, 88, 89, -1, -1, 421, -1, 521, -1, + -1, -1, -1, -1, 1, -1, 3, 4, 5, 6, + 7, 1030, -1, 438, -1, 12, 441, -1, -1, -1, + -1, 446, 447, 448, 449, 450, -1, -1, 25, 26, + 27, -1, 811, -1, 31, 460, -1, -1, 35, 464, + -1, 368, 39, -1, 41, -1, -1, -1, 45, -1, + -1, 378, 379, -1, 51, -1, 53, -1, -1, 56, + -1, 388, -1, -1, 1114, 1115, -1, -1, 65, -1, + -1, 496, 497, -1, -1, -1, -1, -1, 75, -1, + -1, 860, 605, 1102, -1, -1, 83, -1, 611, 514, + 869, 88, -1, 1143, 421, -1, 521, 94, 95, 878, + -1, -1, -1, 3, 4, -1, -1, 603, 604, 605, + -1, 438, -1, -1, 441, 611, -1, -1, -1, 446, + 447, 448, 449, 450, -1, -1, -1, -1, 10, -1, + -1, 627, 628, 460, 630, -1, 659, 464, 1188, -1, + -1, 41, -1, 25, 26, 1195, 1196, -1, -1, -1, + 32, 51, -1, 53, 1204, -1, 56, -1, 1177, 1178, + 1179, -1, 44, 659, -1, 65, -1, -1, -1, 496, + 497, -1, -1, 55, 56, 75, 58, -1, 60, 4, + 605, -1, 7, 83, 511, 512, 611, 514, 88, -1, + -1, -1, -1, 381, 521, -1, -1, -1, -1, 387, + -1, -1, 1221, -1, -1, 760, 88, 89, -1, -1, + 92, 93, -1, 1263, 1264, -1, -1, -1, -1, 44, + 102, -1, -1, -1, -1, 748, 51, -1, 53, 752, + -1, 786, 787, -1, 659, 1014, 1015, -1, -1, -1, + 65, -1, -1, 431, 432, -1, 434, -1, 1027, 1028, + 75, -1, -1, -1, -1, 778, -1, -1, -1, -1, + 85, 784, -1, 88, 89, 788, 4, 5, 6, 7, + -1, -1, -1, -1, 12, -1, 603, 604, 605, -1, + 1330, 804, -1, 806, 611, -1, -1, -1, -1, 27, + 845, 846, -1, 31, -1, -1, -1, 35, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, -1, 832, + -1, -1, 1331, 51, -1, 53, -1, -1, 277, 278, + 279, -1, -1, 748, 847, -1, -1, -1, -1, 517, + 518, -1, 659, -1, 522, 890, 891, -1, 861, -1, + -1, 837, 838, 839, 840, 1124, 3, 4, 844, 845, + 846, 847, -1, 778, 877, -1, 879, -1, -1, 784, + -1, -1, -1, 788, -1, -1, -1, -1, -1, -1, + 925, -1, -1, -1, -1, -1, 872, -1, -1, 804, + -1, -1, -1, -1, 41, 940, 941, -1, -1, -1, + -1, -1, -1, -1, 51, -1, 53, -1, -1, -1, + -1, 360, -1, 362, 363, 364, -1, -1, 65, 597, + 598, 1190, 1191, -1, 1193, 1194, -1, -1, 75, 607, + -1, 748, 847, -1, -1, 613, 83, -1, -1, -1, + 953, 88, -1, -1, -1, -1, 861, -1, -1, -1, + -1, 1, -1, 3, 4, 5, 6, 7, -1, -1, + -1, 778, 12, -1, 879, -1, -1, 784, -1, 786, + 787, 788, -1, 986, -1, 988, -1, 27, -1, 657, + -1, 31, 995, -1, -1, 35, 36, 804, -1, 3, + 4, 41, -1, 7, -1, -1, -1, -1, 3, 4, + -1, 51, 7, 53, -1, -1, 56, -1, -1, -1, + 60, -1, -1, 999, 1000, 65, 1002, 1030, -1, -1, + -1, -1, 839, 840, 76, 75, -1, 41, 845, 846, + 847, 1300, -1, 83, -1, -1, 41, 51, 88, 53, + -1, -1, -1, -1, 861, -1, 51, 99, 53, -1, + -1, 65, -1, 103, -1, -1, -1, -1, 3, 4, + 65, 75, 879, 512, -1, 514, -1, -1, 1081, 83, + 75, -1, 521, -1, 88, -1, 754, 755, 83, 757, + -1, -1, -1, 88, 136, -1, -1, 1, -1, 3, + 4, 5, 6, 7, -1, -1, 41, -1, 12, -1, + -1, -1, -1, 552, -1, 783, 51, -1, 53, -1, + -1, -1, -1, 27, -1, 60, 1102, 31, -1, -1, + 65, 35, 36, 940, 941, -1, -1, 41, -1, -1, + 75, -1, 1177, 1178, -1, -1, -1, 51, 83, 53, + -1, -1, 1155, 88, -1, -1, 60, -1, -1, -1, + 1163, 65, -1, 1166, -1, 604, 605, -1, -1, -1, + -1, 75, 611, -1, -1, 843, 1179, -1, -1, 83, + -1, 1184, 1185, -1, 88, -1, -1, 855, 856, 857, + -1, -1, -1, -1, -1, -1, -1, -1, -1, 103, + -1, 1177, 1178, 1179, -1, -1, 1209, -1, -1, -1, + -1, -1, -1, 1216, -1, -1, -1, 259, -1, -1, + 1223, -1, 4, 1226, 6, 7, -1, -1, -1, -1, + 12, -1, -1, -1, 3, 4, 5, 6, 7, 678, + -1, -1, -1, 12, 1247, 27, -1, 1250, -1, 31, + -1, -1, -1, 35, 1257, -1, -1, 1, 1163, 3, + 4, 5, 6, 7, -1, 933, 35, -1, 12, 51, + -1, 53, 41, -1, 1179, 44, -1, -1, 1281, 1184, + 1185, -1, 51, 27, 53, -1, -1, 31, -1, -1, + -1, 35, 36, 1296, -1, -1, 65, 41, -1, 341, + 342, -1, -1, -1, 1209, -1, 75, 51, 1311, 53, + -1, -1, 56, -1, 83, -1, 60, -1, -1, 88, + -1, 65, -1, -1, -1, 1328, 1329, -1, 1331, -1, + 769, 75, 771, -1, -1, -1, -1, -1, -1, 83, + -1, -1, -1, 782, 88, -1, 388, -1, 787, 788, + 1018, -1, -1, -1, -1, -1, 1163, -1, -1, 103, + -1, -1, -1, -1, -1, 4, -1, 6, 7, 411, + 1177, 1178, 1179, 12, -1, -1, -1, 1184, 1185, -1, + -1, -1, -1, -1, -1, -1, -1, -1, 27, -1, + -1, -1, 31, -1, 436, 1063, 35, -1, 837, 838, + -1, 840, 1209, -1, -1, 844, -1, 846, 847, 3, + 4, -1, 51, 7, 53, 54, -1, -1, 460, -1, + -1, 463, -1, -1, 466, 467, 1331, 469, 470, 471, + 472, 473, 474, 475, 476, 477, 478, 479, 480, 481, + 482, 483, 484, 485, 486, 487, -1, 41, -1, 88, + 44, 493, -1, 495, 496, -1, -1, 51, -1, 53, 3, 4, 5, 6, 7, -1, -1, 10, -1, 12, - -1, 3, 4, 5, 6, 7, 585, -1, -1, -1, - 12, 601, 602, 592, 27, -1, -1, -1, 31, 12, - -1, 611, 35, -1, -1, 27, -1, 617, 41, 31, - -1, 24, 25, 35, 27, -1, 615, -1, 51, 41, - 53, -1, -1, -1, -1, 4, -1, 626, -1, 51, - -1, 53, 65, -1, 56, -1, -1, -1, -1, 52, - -1, -1, 75, 65, -1, 24, 25, -1, 27, -1, - 83, 661, -1, 75, 33, 88, -1, -1, -1, -1, - 93, 83, -1, 662, -1, 44, 88, 46, -1, -1, - 3, 4, 5, 6, 7, -1, -1, -1, -1, 12, - 1337, -1, -1, -1, -1, -1, -1, 66, 101, -1, - 103, 104, 105, -1, -1, 108, 109, 110, 697, -1, + -1, 65, 4, -1, 6, 7, -1, -1, -1, 521, + 12, 75, -1, -1, 27, 527, 4, -1, 31, 83, + -1, 85, 35, -1, 88, 89, -1, -1, 41, -1, + 542, 543, 941, 35, -1, -1, 24, 25, 51, 27, + 53, -1, 44, -1, -1, 33, -1, -1, -1, 51, + -1, 53, 65, -1, 1331, -1, 44, -1, 46, -1, + -1, -1, 75, 65, -1, -1, -1, -1, -1, 581, + 83, -1, -1, 75, -1, 88, 588, -1, 66, -1, + 93, -1, -1, 85, -1, -1, 88, 89, -1, -1, + 999, 1000, 1, 1002, 3, 4, 5, 6, 7, 611, + -1, -1, -1, 12, -1, -1, -1, 95, -1, -1, + 622, -1, -1, 101, -1, 103, -1, 105, 27, -1, + 108, 109, 31, -1, -1, -1, 35, -1, -1, -1, + -1, 119, 41, 121, 122, -1, 45, -1, -1, -1, + -1, -1, 51, -1, 53, -1, 658, 56, -1, -1, + -1, 139, 140, 141, -1, -1, 65, -1, -1, -1, + -1, 149, -1, -1, -1, -1, 75, -1, -1, -1, + -1, -1, -1, -1, 83, -1, -1, 165, -1, 88, + -1, 693, -1, -1, -1, 94, 1, -1, 3, 4, + -1, 6, 7, 8, 9, 183, 11, 12, -1, -1, + -1, -1, 714, -1, -1, 193, -1, -1, -1, -1, + -1, -1, 27, 28, 29, 30, 31, -1, 33, -1, + 35, -1, 37, 38, -1, 40, 41, 42, 43, -1, + -1, 46, 47, 48, 49, 50, 51, -1, 53, 751, + 752, -1, -1, -1, -1, 60, -1, 62, -1, -1, + 65, -1, -1, 765, -1, 767, -1, -1, 73, 74, + 75, -1, -1, -1, -1, -1, 81, 82, 83, -1, + -1, -1, -1, 88, -1, -1, -1, 92, -1, -1, + -1, -1, -1, -1, 796, -1, -1, 275, -1, 104, + -1, -1, -1, -1, -1, 283, 808, 285, -1, 3, + 4, -1, 6, 7, 8, 9, -1, 11, 12, 821, + -1, 823, -1, 825, -1, -1, -1, -1, -1, -1, + -1, -1, -1, 27, 28, 313, -1, 31, 316, 33, + -1, 35, 320, 37, 38, -1, 40, 41, 42, 43, + 852, -1, 46, 47, 48, 49, 50, 51, -1, 53, + -1, -1, -1, -1, 866, 867, -1, -1, 62, -1, + -1, 65, -1, -1, -1, -1, -1, 3, 4, 73, + 74, 75, 360, 361, 362, 363, -1, 81, 82, 83, + 368, -1, -1, -1, 88, -1, 374, -1, 376, -1, + 378, 379, 904, 905, -1, -1, 908, 385, -1, -1, + 104, -1, -1, 391, -1, 41, 394, -1, 1, -1, + 3, 4, 5, 6, 7, 51, -1, 53, -1, 12, + -1, 3, 4, -1, 60, 413, 414, -1, 416, 65, + -1, -1, -1, -1, 27, -1, -1, -1, 31, 75, + -1, -1, 35, 36, -1, -1, -1, 83, 41, 961, + -1, -1, 88, -1, -1, -1, -1, 4, 51, 41, + 53, 973, -1, -1, 3, 4, -1, 60, 7, 51, + -1, 53, 65, -1, -1, -1, -1, 24, 25, -1, + 27, -1, 75, 65, -1, -1, 33, -1, -1, -1, + 83, -1, -1, 75, -1, 88, -1, 44, -1, 46, + -1, 83, 41, -1, -1, 44, 88, -1, -1, 1021, + 103, -1, 51, -1, 53, 3, 4, 5, 6, 7, + -1, 509, 10, 1035, 12, -1, 65, -1, 1040, -1, + 1042, -1, -1, 521, -1, -1, 75, -1, -1, 27, + -1, -1, -1, 31, 83, -1, 85, 35, 95, 88, + 89, -1, -1, 41, 101, -1, 44, -1, 105, -1, + -1, 108, 109, 51, 552, 53, -1, -1, -1, -1, + -1, -1, 119, -1, 121, 122, -1, 65, -1, -1, + -1, 4, -1, 6, 7, -1, -1, 75, -1, 12, + 1102, -1, 139, 140, 141, 83, -1, 85, -1, -1, + 88, 89, 1114, 1115, 27, 93, -1, -1, 31, -1, + 1122, 1123, 35, -1, -1, 603, 604, 605, 165, -1, + -1, -1, -1, 611, -1, -1, -1, -1, 51, -1, + 53, 1143, -1, -1, -1, -1, 183, -1, -1, 627, + 628, -1, 630, -1, -1, -1, 193, -1, -1, -1, + -1, -1, 1164, 68, 69, 70, 71, 72, 73, 74, + 75, 76, 77, 78, 79, 88, -1, 1, -1, 3, + 4, 659, 6, 7, 8, 9, 1188, 11, 12, -1, + -1, -1, -1, 1195, 1196, -1, -1, 1199, -1, -1, + -1, -1, 1204, 27, 28, 29, 30, 31, -1, 33, + -1, 35, -1, 37, 38, 693, 40, 41, 42, 43, + -1, -1, 46, 47, 48, 49, 50, 51, -1, 53, + 54, -1, -1, -1, 3, 4, -1, -1, 62, -1, + -1, 65, -1, -1, -1, -1, -1, 284, 285, 73, + 74, 75, -1, -1, -1, -1, -1, 81, 82, 83, + -1, 1263, 1264, 1265, 88, 89, -1, -1, 92, -1, + -1, -1, 41, -1, -1, -1, 313, -1, -1, 316, + 104, -1, 51, 320, 53, -1, -1, -1, -1, -1, + 27, -1, -1, -1, -1, -1, 65, -1, -1, -1, + -1, -1, 339, -1, -1, -1, 75, 44, 786, 787, + -1, -1, -1, -1, 83, -1, -1, -1, -1, 88, + -1, -1, -1, 360, 361, 362, 363, -1, 1330, -1, + -1, 368, -1, -1, -1, -1, -1, 374, -1, 376, + -1, 378, 379, -1, -1, -1, -1, -1, 385, -1, + -1, -1, -1, -1, 391, -1, -1, 394, 95, 837, + 838, 839, 840, -1, 842, -1, 844, 845, 846, 847, + -1, 108, 109, -1, -1, -1, 413, 414, -1, 416, + -1, -1, -1, -1, 121, -1, -1, -1, -1, -1, + -1, -1, -1, -1, 872, -1, -1, 875, -1, 877, + -1, -1, 139, 140, 141, -1, -1, -1, -1, -1, + -1, -1, 890, 891, -1, 1, -1, 3, 4, 5, + 6, 7, 8, 9, -1, 11, 12, 13, 165, 15, + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, + 26, 27, 28, 29, 30, 31, -1, 33, -1, 35, + -1, 37, 38, -1, 40, 41, 42, 43, -1, -1, + 46, 47, 48, 49, 50, 51, 944, 53, 54, -1, + 56, -1, -1, -1, -1, 953, 62, -1, -1, 65, + -1, -1, -1, -1, 521, -1, -1, 73, 74, 75, + -1, -1, -1, -1, 231, 81, 82, 83, -1, -1, + -1, -1, 88, -1, 90, -1, 92, 985, 986, 987, + -1, -1, -1, -1, -1, 552, -1, 103, 104, -1, + -1, 999, 1000, -1, 1002, 3, 4, -1, -1, 7, + -1, 4, 5, 6, 7, -1, -1, 10, -1, 12, + 277, 278, 279, -1, -1, -1, -1, -1, 285, -1, + -1, -1, 1030, -1, 27, -1, -1, -1, 31, -1, + -1, -1, 35, 41, -1, -1, 603, 604, 605, -1, + -1, 44, -1, 51, 611, 53, -1, -1, 51, -1, + 53, -1, -1, -1, -1, -1, -1, 65, -1, -1, + 627, 628, 65, 630, -1, -1, -1, 75, -1, -1, + -1, -1, 75, -1, -1, 83, -1, -1, -1, -1, + 88, -1, 85, -1, -1, 88, 89, -1, -1, -1, + 93, -1, 659, 360, 1102, 362, 363, 364, -1, 1, + -1, 3, 4, 5, 6, 7, -1, 374, -1, 376, + 12, 378, 379, -1, -1, -1, 3, 4, 385, -1, + 7, 277, 278, 279, 391, 27, 693, 394, -1, 31, + -1, -1, -1, 35, -1, -1, -1, -1, 44, 41, + -1, -1, -1, -1, -1, -1, 413, -1, -1, 51, + -1, 53, -1, -1, 41, -1, -1, 44, -1, -1, + 66, -1, -1, 65, 51, -1, 53, -1, -1, 1177, + 1178, 1179, -1, 75, -1, -1, 3, 4, 65, 85, + 7, 83, -1, -1, -1, -1, 88, -1, 75, 95, + -1, -1, -1, -1, -1, -1, 83, -1, 85, -1, + -1, 88, 89, -1, 360, -1, 362, 363, 364, -1, + -1, -1, -1, 1221, 41, 121, -1, -1, -1, 786, + 787, -1, -1, -1, 51, -1, 53, 794, -1, -1, + -1, -1, 499, 139, 140, 141, -1, -1, 65, -1, + -1, -1, -1, 149, 511, 512, -1, 514, 75, -1, + -1, -1, 819, -1, 521, -1, 83, -1, -1, 165, + -1, 88, -1, -1, -1, -1, -1, -1, -1, -1, + 837, 838, 839, 840, -1, -1, -1, 844, 845, 846, + 847, -1, -1, -1, -1, 552, -1, -1, -1, 195, + -1, -1, 4, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, 872, -1, -1, 875, -1, + 877, -1, 24, 25, -1, -1, -1, 4, -1, 6, + 7, 33, -1, 890, 891, 12, -1, -1, -1, -1, + -1, -1, -1, -1, 46, -1, 603, 604, 605, -1, + -1, -1, -1, -1, 611, -1, -1, -1, 35, -1, + -1, -1, -1, -1, -1, 511, 512, 44, 514, -1, + 627, 628, -1, 630, 51, 521, 53, -1, 4, 5, + 6, 7, -1, -1, -1, -1, 12, 283, 65, 285, + -1, -1, -1, -1, -1, -1, 953, -1, 75, 101, + -1, 27, 659, 105, -1, 31, 552, -1, 85, 35, + -1, 88, 89, -1, -1, -1, -1, 119, -1, -1, + 122, 678, 3, 4, -1, 51, 7, 53, 985, 986, + 987, 688, 689, 690, -1, -1, -1, 139, 140, -1, + -1, -1, 999, 1000, -1, 1002, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, 603, 604, 605, + 41, -1, -1, -1, 360, 611, 362, 363, -1, -1, + 51, -1, 53, 1030, -1, -1, -1, -1, 374, -1, + 376, 183, 378, 379, 65, -1, 3, 4, -1, 385, + 7, 193, -1, -1, 75, 391, -1, -1, 394, -1, + -1, -1, 83, -1, -1, -1, 12, 88, -1, -1, + -1, -1, 769, -1, 771, -1, -1, 413, 24, 25, + -1, 27, -1, -1, 41, 782, -1, -1, -1, 786, + 787, 788, 678, -1, 51, -1, 53, -1, -1, -1, + -1, -1, -1, -1, -1, 1102, 52, -1, 65, -1, + -1, -1, -1, -1, -1, -1, -1, -1, 75, -1, + -1, -1, -1, -1, -1, -1, 83, -1, -1, -1, + -1, 88, -1, -1, -1, -1, -1, -1, -1, -1, + 837, 838, 839, 840, -1, -1, -1, 844, 845, 846, + 847, -1, -1, -1, -1, 101, -1, 103, 104, 105, + -1, -1, 108, 109, -1, 3, 4, -1, -1, 7, + -1, 313, -1, -1, 316, 872, -1, -1, 320, -1, + 1177, 1178, 1179, 769, -1, 771, -1, -1, 524, -1, + -1, -1, -1, -1, -1, -1, 782, -1, -1, -1, + 786, 787, 788, 41, -1, -1, -1, -1, -1, -1, + -1, -1, -1, 51, -1, 53, 552, -1, -1, 361, + -1, -1, 919, 920, 1221, 922, 368, 65, -1, -1, + -1, -1, 374, -1, 376, -1, -1, 75, -1, -1, + -1, -1, -1, 940, 941, 83, -1, 193, -1, 391, + 88, 837, 838, 839, 840, -1, -1, -1, 844, 845, + 846, 847, -1, -1, -1, -1, -1, 603, 604, 605, + -1, 413, 414, -1, 416, 611, -1, -1, -1, -1, + 3, 4, 5, 6, 7, 231, -1, -1, 985, 12, + 987, 627, 628, -1, 630, -1, -1, -1, -1, -1, + -1, -1, 999, 1000, 27, 1002, -1, -1, 31, -1, -1, -1, 35, -1, -1, -1, -1, -1, 41, -1, - -1, 44, -1, -1, -1, -1, 95, -1, 51, 718, - 53, -1, 101, -1, 103, -1, 105, -1, -1, 108, - 109, 110, 65, -1, -1, -1, -1, -1, 1169, -1, - -1, 120, 75, 122, 123, -1, -1, -1, 758, 759, - 83, 761, 1183, 1184, 1185, 88, 755, 756, -1, 1190, - 1191, 140, 141, 142, -1, -1, -1, -1, -1, -1, - 769, 150, 771, -1, -1, -1, -1, 787, -1, -1, - -1, 194, -1, -1, 1215, -1, -1, 166, -1, -1, - -1, -1, -1, -1, -1, 3, 4, 5, 6, 7, - -1, 800, -1, -1, 12, 184, -1, -1, -1, -1, - -1, -1, -1, 812, -1, 194, -1, -1, -1, 232, - -1, -1, -1, -1, -1, -1, 825, 35, 827, -1, - 829, -1, -1, 41, -1, -1, 44, -1, 848, 4, - -1, 6, 7, 51, -1, 53, -1, 12, -1, -1, - 860, 861, 862, -1, -1, -1, -1, 65, 857, -1, - -1, -1, -1, 276, -1, 278, 279, 75, -1, -1, - 35, -1, 871, 872, -1, 83, -1, 85, -1, 44, - 88, 89, -1, -1, -1, -1, 51, 1, 53, 3, - 4, 5, 6, 7, -1, 308, -1, 276, 12, -1, - 65, 314, -1, -1, 317, 284, 1337, 286, -1, 322, - 75, 910, 911, 27, -1, 914, -1, 31, -1, -1, - 85, 35, -1, 88, 89, -1, -1, 41, -1, 939, - -1, -1, -1, -1, -1, 314, -1, 51, 317, 53, - -1, -1, -1, 322, 3, 4, 5, 6, 7, -1, - -1, 65, -1, 12, -1, -1, -1, -1, -1, -1, - -1, 75, -1, -1, -1, -1, -1, 966, 27, 83, - -1, -1, 31, -1, 88, -1, 35, -1, -1, 978, - -1, -1, 41, 362, 363, 364, 365, -1, -1, -1, - -1, 370, 51, -1, 53, -1, -1, 376, -1, 378, - -1, 380, 381, 382, -1, -1, 65, 3, 4, 388, - -1, 7, -1, 1023, -1, 394, 75, -1, 397, -1, - -1, -1, -1, 436, 83, -1, -1, 1026, -1, 88, - -1, -1, -1, -1, -1, -1, -1, 416, 417, -1, - 419, 1040, -1, 4, -1, 41, 1045, -1, 1047, -1, - -1, 4, 5, 6, 7, 51, -1, 53, 1068, 12, - -1, -1, -1, 24, 25, -1, 27, -1, -1, 65, - -1, -1, 33, -1, 27, -1, -1, -1, 31, 75, - -1, -1, 35, 44, -1, 46, -1, 83, -1, 502, - -1, -1, 88, -1, -1, -1, -1, -1, 51, 512, - 53, 514, 515, 3, 4, 5, 6, 7, -1, 1108, - 10, -1, 12, -1, -1, -1, -1, -1, -1, -1, - -1, 1120, 1121, -1, -1, -1, -1, 27, -1, 1128, - 1129, 31, -1, 512, 95, 35, -1, -1, -1, -1, - 101, 41, -1, 556, 105, 524, -1, 108, 109, 110, - 1149, 51, -1, 53, -1, -1, -1, -1, -1, 120, - -1, 122, 123, -1, -1, 65, 4, 5, 6, 7, - -1, 1170, 10, -1, 12, 75, 555, -1, -1, 140, - 141, 142, -1, 83, -1, -1, -1, -1, 88, 27, - -1, -1, 27, 31, -1, 1194, -1, 35, -1, -1, - -1, -1, 1201, 1202, -1, 166, 1205, -1, -1, 44, - -1, 1210, -1, 51, -1, 53, 3, 4, 5, 6, - 7, -1, -1, 184, -1, 12, -1, -1, 607, 608, - 609, -1, -1, 194, -1, -1, 615, -1, -1, -1, - 27, -1, -1, -1, 31, -1, -1, -1, 35, -1, - -1, -1, 631, 632, 41, 634, -1, 44, -1, -1, - 95, -1, -1, -1, 51, -1, 53, -1, -1, 682, - 1269, 1270, 1271, 108, 109, 110, -1, -1, 65, 692, - 693, 694, -1, -1, 663, -1, -1, 122, 75, -1, + -1, 44, -1, 659, -1, -1, -1, -1, 51, 275, + 53, 277, 278, -1, -1, -1, -1, -1, -1, -1, + -1, -1, 65, -1, -1, -1, -1, -1, -1, -1, + -1, -1, 75, -1, 940, 941, -1, -1, -1, -1, + 83, 307, 85, -1, -1, 88, 89, 313, -1, -1, + 316, -1, -1, -1, 320, 63, 64, 65, 66, 67, + 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, + 78, 79, 1, -1, 3, 4, 5, 6, 7, 8, + 9, 10, 11, 12, -1, 1102, -1, -1, -1, -1, + -1, -1, -1, 999, 1000, -1, 1002, -1, 27, 28, + 29, 30, 31, -1, 33, -1, 35, -1, 37, 38, + -1, 40, 41, 42, 43, -1, -1, 46, 47, 48, + 49, 50, 51, -1, 53, -1, -1, -1, -1, -1, + -1, -1, -1, 62, -1, -1, 65, -1, -1, -1, + -1, 603, 604, -1, 73, 74, 75, -1, -1, -1, + -1, -1, 81, 82, 83, -1, -1, -1, -1, 88, + 1177, 1178, 1179, 92, 93, 627, 628, 433, 630, -1, + -1, -1, -1, 102, -1, 104, -1, -1, -1, -1, + -1, 837, 838, 839, 840, -1, 842, -1, 844, 845, + 846, 847, -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, 1221, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, 872, -1, -1, -1, + -1, 1, -1, 3, 4, 5, 6, 7, 8, 9, + 10, 11, 12, 499, -1, -1, -1, -1, -1, -1, + -1, -1, -1, 509, -1, 511, 512, 27, 28, 29, + 30, 31, -1, 33, -1, 35, -1, 37, 38, -1, + 40, 41, 42, 43, 44, -1, 46, 47, 48, 49, + 50, 51, -1, 53, 54, -1, -1, -1, -1, -1, + -1, -1, 62, -1, -1, 65, -1, 553, 944, -1, + -1, -1, -1, 73, 74, 75, -1, -1, -1, -1, + -1, 81, 82, 83, -1, 85, -1, -1, 88, 89, + -1, -1, 92, 93, -1, -1, 3, 4, 5, 6, + 7, -1, -1, -1, 104, 12, -1, -1, -1, 985, + -1, 987, -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, 999, 1000, -1, 1002, -1, 35, -1, + -1, -1, -1, -1, 41, -1, -1, 44, -1, -1, + -1, -1, -1, -1, 51, -1, 53, -1, -1, -1, + -1, -1, -1, -1, -1, 837, 838, -1, 65, -1, + -1, -1, 844, -1, -1, -1, -1, -1, 75, -1, -1, -1, -1, -1, -1, -1, 83, -1, 85, -1, - -1, 88, 89, -1, -1, 140, 141, 142, -1, -1, - -1, -1, -1, -1, -1, -1, -1, -1, 697, -1, - 3, 4, -1, -1, 285, 286, -1, -1, -1, -1, - -1, 166, -1, -1, -1, -1, -1, 1336, -1, -1, - -1, -1, -1, -1, -1, -1, 3, 4, 5, 6, - 7, -1, -1, 314, -1, 12, 317, -1, 41, -1, - 773, 322, 775, -1, -1, -1, -1, -1, 51, -1, - 53, -1, -1, 786, -1, -1, -1, 60, 35, -1, - 341, -1, 65, -1, 41, -1, -1, 44, -1, -1, - -1, -1, 75, -1, 51, -1, 53, 232, -1, -1, - 83, 362, 363, 364, 365, 88, -1, -1, 65, 370, - -1, 790, 791, 792, -1, 376, -1, 378, 75, 380, - 381, 382, -1, -1, -1, -1, 83, 388, 85, -1, - -1, 88, 89, 394, -1, -1, 397, -1, -1, -1, - -1, -1, -1, 278, 279, 280, -1, -1, -1, -1, - -1, 286, -1, -1, -1, 416, 417, -1, 419, -1, - -1, -1, 841, 842, 843, 844, 845, 880, 847, -1, - 849, 850, 851, 852, -1, -1, 3, 4, 5, 6, - 7, -1, -1, -1, -1, 12, 68, 69, 70, 71, - 72, 73, 74, 75, 76, 77, 78, 79, 877, -1, - 27, 880, -1, 882, 31, -1, -1, -1, 35, -1, - -1, -1, 925, 926, 41, 928, 895, 896, 897, -1, - -1, -1, -1, -1, 51, -1, 53, 362, -1, 364, - 365, 366, -1, 60, -1, -1, -1, -1, 65, -1, - -1, 376, -1, 378, -1, 380, 381, 382, 75, 4, - 5, 6, 7, 388, -1, 10, 83, 12, -1, 394, - -1, 88, 397, 524, -1, -1, -1, -1, -1, -1, - 949, -1, 27, -1, -1, -1, 31, -1, -1, 958, - 35, 416, -1, -1, 140, 141, 142, -1, -1, 44, - -1, -1, -1, -1, 555, -1, 51, -1, 53, -1, - -1, -1, -1, 3, 4, -1, -1, 7, -1, -1, - 65, 990, 991, 992, 3, 4, -1, -1, 7, -1, - 75, -1, -1, -1, -1, 1004, 1005, 44, 1007, -1, - 85, -1, -1, 88, 89, -1, -1, -1, 93, -1, - -1, 41, -1, -1, -1, -1, 607, 608, 609, 66, - -1, 51, 41, 53, 615, -1, 1035, -1, -1, -1, - -1, -1, 51, -1, 53, 65, -1, 502, 85, -1, - 631, 632, -1, 634, -1, 75, 65, -1, 95, 514, - 515, -1, 517, 83, -1, -1, 75, -1, 88, 524, - -1, -1, -1, -1, 83, -1, -1, -1, -1, 88, - -1, -1, 663, -1, -1, 122, -1, -1, -1, -1, - -1, -1, -1, 3, 4, -1, 6, 7, 8, 9, - 555, 11, 12, 140, 141, 142, -1, -1, -1, 1108, - -1, -1, -1, 150, -1, -1, 697, 27, 28, 29, - 30, 31, -1, 33, -1, 35, -1, 37, 38, 166, - 40, 41, 42, 43, -1, -1, 46, 47, 48, 49, - 50, 51, -1, 53, -1, -1, -1, -1, -1, -1, - -1, -1, 607, 608, 609, -1, -1, -1, -1, 196, - 615, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, 81, 82, 83, 3, 4, 631, 632, 88, 634, - -1, -1, 92, -1, 1183, 1184, 1185, -1, -1, -1, - -1, -1, -1, -1, 104, -1, -1, -1, -1, -1, - 376, -1, 378, -1, 380, 381, 382, -1, 663, 790, - 791, 792, 41, -1, -1, -1, -1, 798, 394, -1, - -1, -1, 51, -1, 53, -1, -1, 682, 1227, -1, - -1, -1, -1, -1, -1, -1, 65, 692, 693, 694, - 416, -1, 823, -1, -1, -1, 75, 284, -1, 286, - -1, -1, -1, -1, 83, -1, -1, -1, -1, 88, - 841, 842, 843, 844, 845, -1, -1, -1, 849, 850, - 851, 852, -1, -1, -1, -1, -1, 4, -1, 6, - 7, -1, -1, -1, -1, 12, -1, -1, -1, -1, - -1, -1, -1, -1, -1, -1, 877, -1, -1, 880, - 27, 882, -1, -1, 31, -1, -1, -1, 35, -1, - -1, -1, -1, -1, 895, 896, 897, 44, 773, -1, - 775, -1, -1, -1, 51, 362, 53, 364, 365, -1, - -1, 786, -1, -1, -1, 790, 791, 792, 65, 376, - -1, 378, -1, 380, 381, 382, -1, -1, 75, -1, - -1, 388, -1, -1, 278, 279, 280, 394, 85, -1, - 397, 88, 89, 66, 67, 68, 69, 70, 71, 72, - 73, 74, 75, 76, 77, 78, 79, 958, -1, 416, - -1, -1, -1, -1, -1, 4, 841, 842, 843, 844, - 845, -1, -1, -1, 849, 850, 851, 852, -1, -1, - -1, -1, -1, -1, -1, 24, 25, -1, -1, 990, - 991, 992, 3, 4, 33, -1, 7, -1, -1, -1, - -1, -1, 877, 1004, 1005, -1, 1007, 46, -1, -1, - -1, 607, 608, 609, -1, -1, -1, -1, 362, 615, - 364, 365, 366, 3, 4, -1, -1, 7, -1, -1, - 41, -1, -1, -1, 1035, 631, 632, -1, 634, -1, - 51, -1, 53, -1, -1, -1, -1, -1, -1, -1, - 925, 926, -1, 928, 65, -1, -1, -1, -1, -1, - -1, 41, 101, -1, 75, -1, 105, 663, -1, -1, - 527, 51, 83, 53, -1, -1, -1, 88, -1, -1, - -1, 120, -1, -1, 123, 65, -1, -1, -1, -1, - -1, -1, -1, -1, -1, 75, -1, -1, 555, -1, - -1, 140, 141, 83, -1, -1, -1, 1108, 88, -1, - -1, -1, -1, -1, -1, 990, -1, 992, -1, 3, - 4, 278, 279, 280, -1, -1, -1, -1, -1, 1004, - 1005, -1, 1007, -1, -1, -1, -1, -1, -1, -1, - 3, 4, 5, 6, 7, 184, -1, -1, -1, 12, - 607, 608, 609, -1, -1, 194, -1, 41, 615, -1, - -1, -1, -1, -1, 27, -1, -1, 51, 31, 53, - 514, 515, 35, 517, 631, 632, -1, 634, 41, -1, - 524, 65, 1183, 1184, 1185, -1, -1, -1, 51, -1, - 53, 75, -1, 56, -1, -1, -1, -1, -1, 83, - -1, -1, 65, -1, 88, 362, 663, 364, 365, 366, - -1, 555, 75, -1, -1, -1, -1, -1, -1, -1, - 83, -1, -1, -1, -1, 88, 1227, -1, -1, -1, - -1, -1, -1, 1108, -1, -1, -1, 10, -1, -1, - -1, -1, -1, -1, -1, 841, 842, 843, 844, 845, - -1, -1, -1, 849, 850, 851, 852, -1, -1, -1, - -1, -1, -1, 607, 608, 609, -1, -1, -1, -1, - -1, 615, -1, -1, -1, 314, -1, -1, 317, -1, - -1, 877, -1, 322, 57, 58, 59, 60, 61, 62, - 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, - 73, 74, 75, 76, 77, 78, 79, -1, 1183, 1184, - 1185, 67, 68, 69, 70, 71, 72, 73, 74, 75, - 76, 77, 78, 79, 363, -1, -1, -1, -1, -1, - -1, 370, -1, -1, -1, -1, -1, 376, 682, 378, + -1, 88, 89, -1, -1, -1, -1, -1, -1, -1, + 872, -1, 678, 875, -1, 877, -1, -1, -1, -1, + -1, -1, 688, 689, 690, -1, 1, -1, 3, 4, + 5, 6, 7, 8, 9, 10, 11, 12, -1, -1, + -1, -1, -1, -1, -1, -1, 1102, -1, -1, -1, + -1, -1, 27, 28, 29, 30, 31, -1, 33, -1, + 35, -1, 37, 38, -1, 40, 41, 42, 43, 44, + -1, 46, 47, 48, 49, 50, 51, -1, 53, 54, + -1, -1, -1, -1, -1, -1, -1, 62, -1, -1, + 65, 953, -1, -1, 10, -1, -1, -1, 73, 74, + 75, -1, -1, 769, -1, 771, 81, 82, 83, -1, + 85, -1, -1, 88, 89, -1, 782, 92, 93, -1, + -1, 1177, 1178, 1179, 986, -1, -1, -1, -1, 104, + -1, -1, -1, -1, -1, -1, -1, 999, 1000, -1, + 1002, 57, 58, 59, 60, 61, 62, 63, 64, 65, + 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, + 76, 77, 78, 79, -1, 1221, -1, -1, 1030, -1, + -1, -1, -1, -1, -1, -1, -1, -1, 1, -1, + 3, 4, 5, 6, 7, 8, 9, -1, 11, 12, + 13, -1, 15, 16, 17, 18, 19, 20, 21, 22, + 23, 24, 25, 26, 27, 28, 29, 30, 31, 875, + 33, -1, 35, -1, 37, 38, -1, 40, 41, 42, + 43, -1, -1, 46, 47, 48, 49, 50, 51, -1, + 53, 54, -1, 56, -1, -1, -1, -1, -1, 62, + -1, -1, 65, -1, -1, -1, -1, -1, -1, -1, + 73, 74, 75, 919, 920, -1, 922, -1, 81, 82, + 83, -1, -1, -1, -1, 88, -1, 90, -1, 92, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, 1227, -1, -1, 394, -1, 514, 515, 62, - 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, - 73, 74, 75, 76, 77, 78, 79, 416, 417, -1, - 419, -1, -1, -1, 841, 842, 843, 844, 845, -1, - 847, -1, 849, 850, 851, 852, -1, -1, 555, -1, - -1, -1, -1, -1, -1, -1, -1, -1, 1004, 1005, - -1, 1007, -1, -1, -1, -1, -1, -1, -1, -1, - 877, -1, -1, -1, -1, -1, -1, -1, -1, 773, - -1, 775, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, 786, -1, -1, -1, 790, 791, 792, -1, - 607, 608, -1, -1, 57, 58, 59, -1, 61, 62, - 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, - 73, 74, 75, 76, 77, 78, 79, 65, 66, 67, - 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, - 78, 79, 949, -1, -1, -1, -1, 841, 842, 843, - 844, 845, 105, -1, -1, 849, 850, 851, 852, -1, - -1, -1, 1108, -1, 3, 4, 5, 6, 7, -1, - -1, 10, -1, 12, -1, 682, -1, -1, -1, -1, - -1, -1, -1, 990, -1, 992, -1, -1, 27, -1, - -1, -1, 31, -1, -1, -1, 35, 1004, 1005, -1, - 1007, -1, 41, -1, -1, 44, -1, -1, -1, -1, - -1, -1, 51, -1, 53, -1, -1, -1, 607, 608, - -1, -1, -1, -1, -1, -1, 65, -1, -1, -1, - -1, -1, -1, -1, -1, -1, 75, 1183, 1184, 1185, - -1, -1, 631, 632, 83, 634, 85, -1, -1, 88, - 89, -1, -1, -1, 93, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, -1, 773, -1, 775, -1, - -1, -1, -1, -1, -1, -1, -1, -1, -1, 786, - -1, -1, -1, 790, 791, 64, 65, 66, 67, 68, - 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, - 79, 1108, -1, -1, -1, -1, -1, -1, -1, -1, - 1004, 1005, -1, 1007, -1, -1, -1, -1, -1, -1, - 32, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, 841, 842, 843, 844, -1, -1, - -1, -1, 849, 850, 851, 57, 58, 59, -1, 61, - 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, - 72, 73, 74, 75, 76, 77, 78, 79, -1, -1, - -1, -1, -1, -1, -1, -1, 1183, 1184, 1185, -1, - -1, -1, 1, -1, 3, 4, 5, 6, 7, 8, + 103, 104, 1, -1, 3, 4, 5, 6, 7, 8, 9, -1, 11, 12, 13, -1, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, -1, 33, -1, 35, -1, 37, 38, - 1227, 40, 41, 42, 43, -1, -1, 46, 47, 48, + -1, 40, 41, 42, 43, -1, -1, 46, 47, 48, 49, 50, 51, -1, 53, 54, -1, 56, -1, -1, -1, -1, -1, 62, -1, -1, 65, -1, -1, -1, - -1, -1, 841, 842, 73, 74, 75, -1, -1, -1, - 849, -1, 81, 82, 83, -1, -1, -1, -1, 88, + -1, -1, -1, -1, 73, 74, 75, -1, -1, -1, + -1, -1, 81, 82, 83, -1, -1, -1, -1, 88, -1, 90, -1, 92, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, 103, 104, -1, -1, 877, -1, - -1, 880, -1, 882, -1, -1, -1, 1004, 1005, -1, - 1007, 1, -1, 3, 4, 5, 6, 7, 8, 9, - -1, 11, 12, 13, -1, 15, 16, 17, 18, 19, - 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, - 30, 31, -1, 33, -1, 35, -1, 37, 38, -1, - 40, 41, 42, 43, -1, -1, 46, 47, 48, 49, - 50, 51, -1, 53, 54, -1, 56, -1, -1, -1, - -1, -1, 62, -1, -1, 65, -1, -1, -1, 958, - -1, -1, -1, 73, 74, 75, -1, -1, -1, -1, - -1, 81, 82, 83, -1, -1, -1, -1, 88, -1, - 90, -1, 92, -1, -1, -1, -1, -1, -1, -1, - -1, -1, 991, 103, 104, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, 1004, 1005, -1, 1007, -1, - -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, 1, -1, 3, 4, 5, 6, 7, - 8, 9, -1, 11, 12, 13, 1035, 15, 16, 17, - 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, - 28, 29, 30, 31, -1, 33, -1, 35, -1, 37, - 38, -1, 40, 41, 42, 43, -1, -1, 46, 47, - 48, 49, 50, 51, -1, 53, 54, -1, 56, -1, - -1, -1, -1, -1, 62, -1, -1, 65, -1, -1, - -1, -1, -1, -1, -1, 73, 74, 75, -1, -1, - -1, -1, -1, 81, 82, 83, -1, -1, -1, -1, - 88, -1, 90, -1, 92, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, 103, 104, 1, -1, 3, - 4, 5, 6, 7, 8, 9, -1, 11, 12, 13, - -1, 15, 16, 17, 18, 19, 20, 21, 22, 23, - 24, 25, 26, 27, 28, 29, 30, 31, -1, 33, - -1, 35, -1, 37, 38, -1, 40, 41, 42, 43, - -1, -1, 46, 47, 48, 49, 50, 51, -1, 53, - 54, -1, 56, -1, -1, -1, -1, -1, 62, -1, - -1, 65, -1, -1, -1, -1, -1, -1, -1, 73, - 74, 75, -1, -1, -1, -1, -1, 81, 82, 83, - -1, -1, -1, -1, 88, -1, 90, -1, 92, -1, - -1, -1, -1, -1, -1, -1, -1, -1, -1, 103, - 104, 1, -1, 3, 4, 5, 6, 7, 8, 9, - -1, 11, 12, 13, -1, 15, 16, 17, 18, 19, - 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, - 30, 31, -1, 33, -1, 35, -1, 37, 38, -1, - 40, 41, 42, 43, -1, -1, 46, 47, 48, 49, - 50, 51, -1, 53, 54, -1, 56, -1, -1, -1, - -1, -1, 62, -1, -1, 65, -1, -1, -1, -1, - -1, -1, -1, 73, 74, 75, -1, -1, -1, -1, - -1, 81, 82, 83, -1, -1, -1, -1, 88, -1, - 90, -1, 92, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, 103, 104, 1, -1, 3, 4, 5, - 6, 7, 8, 9, -1, 11, 12, 13, -1, 15, - 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, - 26, 27, 28, 29, 30, 31, -1, 33, -1, 35, - -1, 37, 38, -1, 40, 41, 42, 43, -1, -1, - 46, 47, 48, 49, 50, 51, -1, 53, 54, -1, - 56, -1, -1, -1, -1, -1, 62, -1, -1, 65, - -1, -1, -1, -1, -1, -1, -1, 73, 74, 75, - -1, -1, -1, -1, -1, 81, 82, 83, -1, -1, - -1, -1, 88, -1, 90, 1, 92, 3, 4, 5, - 6, 7, 8, 9, -1, 11, 12, 13, 104, 15, - 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, - 26, 27, 28, 29, 30, 31, -1, 33, -1, 35, - -1, 37, 38, -1, 40, 41, 42, 43, -1, -1, - 46, 47, 48, 49, 50, 51, -1, 53, 54, -1, - 56, -1, -1, -1, -1, -1, 62, -1, -1, 65, - -1, -1, -1, -1, -1, -1, -1, 73, 74, 75, - -1, -1, -1, -1, -1, 81, 82, 83, -1, -1, - -1, -1, 88, -1, 90, 1, 92, 3, 4, 5, - 6, 7, 8, 9, -1, 11, 12, 13, 104, 15, - 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, - 26, 27, 28, 29, 30, 31, -1, 33, -1, 35, - -1, 37, 38, -1, 40, 41, 42, 43, -1, -1, - 46, 47, 48, 49, 50, 51, -1, 53, 54, -1, - 56, -1, -1, -1, -1, -1, 62, -1, -1, 65, - -1, -1, -1, -1, -1, -1, -1, 73, 74, 75, - -1, -1, -1, -1, -1, 81, 82, 83, -1, -1, - -1, -1, 88, -1, 90, 1, 92, 3, 4, 5, - 6, 7, 8, 9, 10, 11, 12, -1, 104, -1, + -1, -1, -1, -1, 103, 104, 1, -1, 3, 4, + 5, 6, 7, 8, 9, -1, 11, 12, 13, -1, + 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, + 25, 26, 27, 28, 29, 30, 31, -1, 33, -1, + 35, -1, 37, 38, -1, 40, 41, 42, 43, -1, + -1, 46, 47, 48, 49, 50, 51, -1, 53, 54, + -1, 56, -1, -1, -1, -1, -1, 62, -1, -1, + 65, -1, -1, -1, -1, -1, -1, -1, 73, 74, + 75, -1, -1, -1, -1, -1, 81, 82, 83, -1, + -1, -1, -1, 88, -1, 90, -1, 92, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, 103, 104, + 1, -1, 3, 4, 5, 6, 7, 8, 9, -1, + 11, 12, 13, -1, 15, 16, 17, 18, 19, 20, + 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, + 31, -1, 33, -1, 35, -1, 37, 38, -1, 40, + 41, 42, 43, -1, -1, 46, 47, 48, 49, 50, + 51, -1, 53, 54, -1, 56, -1, -1, -1, -1, + -1, 62, -1, -1, 65, -1, -1, -1, -1, -1, + -1, -1, 73, 74, 75, -1, -1, -1, -1, -1, + 81, 82, 83, -1, -1, -1, -1, 88, -1, 90, + -1, 92, -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, 103, 104, 1, -1, 3, 4, 5, 6, + 7, 8, 9, -1, 11, 12, 13, -1, 15, 16, + 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, + 27, 28, 29, 30, 31, -1, 33, -1, 35, -1, + 37, 38, -1, 40, 41, 42, 43, -1, -1, 46, + 47, 48, 49, 50, 51, -1, 53, 54, -1, 56, + -1, -1, -1, -1, -1, 62, -1, -1, 65, -1, + -1, -1, -1, -1, -1, -1, 73, 74, 75, -1, + -1, -1, -1, -1, 81, 82, 83, -1, -1, -1, + -1, 88, -1, 90, 1, 92, 3, 4, 5, 6, + 7, 8, 9, -1, 11, 12, 13, 104, 15, 16, + 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, + 27, 28, 29, 30, 31, -1, 33, -1, 35, -1, + 37, 38, -1, 40, 41, 42, 43, -1, -1, 46, + 47, 48, 49, 50, 51, -1, 53, 54, -1, 56, + -1, -1, -1, -1, -1, 62, -1, -1, 65, -1, + -1, -1, -1, -1, -1, -1, 73, 74, 75, -1, + -1, -1, -1, -1, 81, 82, 83, -1, -1, -1, + -1, 88, -1, 90, 1, 92, 3, 4, 5, 6, + 7, 8, 9, -1, 11, 12, 13, 104, 15, 16, + 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, + 27, 28, 29, 30, 31, -1, 33, -1, 35, -1, + 37, 38, -1, 40, 41, 42, 43, -1, -1, 46, + 47, 48, 49, 50, 51, -1, 53, 54, -1, 56, + -1, -1, -1, -1, -1, 62, -1, -1, 65, -1, + -1, -1, -1, -1, -1, -1, 73, 74, 75, -1, + -1, -1, -1, -1, 81, 82, 83, -1, -1, -1, + -1, 88, -1, 90, 1, 92, 3, 4, 5, 6, + 7, 8, 9, 10, 11, 12, -1, 104, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, 27, 28, 29, 30, 31, -1, 33, -1, 35, - -1, 37, 38, -1, 40, 41, 42, 43, 44, -1, - 46, 47, 48, 49, 50, 51, -1, 53, 54, -1, - -1, -1, -1, -1, -1, -1, 62, -1, -1, 65, - -1, -1, -1, -1, -1, -1, -1, 73, 74, 75, - -1, -1, -1, -1, -1, 81, 82, 83, -1, 85, - -1, -1, 88, 89, -1, -1, 92, 93, -1, -1, - -1, -1, -1, -1, -1, -1, -1, 1, 104, 3, - 4, 5, 6, 7, 8, 9, 10, 11, 12, -1, + 27, 28, 29, 30, 31, -1, 33, -1, 35, -1, + 37, 38, -1, 40, 41, 42, 43, -1, -1, 46, + 47, 48, 49, 50, 51, -1, 53, -1, -1, -1, + -1, -1, -1, -1, -1, 62, -1, -1, 65, -1, + -1, -1, -1, -1, -1, -1, 73, 74, 75, -1, + -1, -1, -1, -1, 81, 82, 83, -1, -1, -1, + -1, 88, -1, -1, -1, 92, 93, -1, -1, -1, + -1, -1, -1, -1, -1, 102, 1, 104, 3, 4, + -1, 6, 7, 8, 9, -1, 11, 12, 66, 67, + 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, + 78, 79, 27, 28, 29, 30, 31, -1, 33, -1, + 35, -1, 37, 38, -1, 40, 41, 42, 43, -1, + -1, 46, 47, 48, 49, 50, 51, -1, 53, 54, + -1, -1, -1, -1, -1, -1, -1, 62, -1, -1, + 65, -1, -1, -1, -1, -1, -1, -1, 73, 74, + 75, -1, -1, -1, -1, -1, 81, 82, 83, -1, + -1, -1, -1, 88, 89, -1, 1, 92, 3, 4, + -1, 6, 7, 8, 9, -1, 11, 12, 103, 104, + -1, -1, -1, -1, 19, -1, -1, -1, -1, -1, + -1, -1, 27, 28, 29, 30, 31, -1, 33, -1, + 35, -1, 37, 38, -1, 40, 41, 42, 43, -1, + -1, 46, 47, 48, 49, 50, 51, -1, 53, 54, + -1, -1, -1, -1, -1, -1, -1, 62, -1, -1, + 65, -1, -1, -1, -1, -1, -1, -1, 73, 74, + 75, -1, -1, -1, -1, -1, 81, 82, 83, -1, + -1, -1, -1, 88, -1, -1, 1, 92, 3, 4, + -1, 6, 7, 8, 9, -1, 11, 12, 103, 104, + -1, -1, -1, -1, 19, -1, -1, -1, -1, -1, + -1, -1, 27, 28, 29, 30, 31, -1, 33, -1, + 35, -1, 37, 38, -1, 40, 41, 42, 43, -1, + -1, 46, 47, 48, 49, 50, 51, -1, 53, 54, + -1, -1, -1, -1, -1, -1, -1, 62, -1, -1, + 65, -1, -1, -1, -1, -1, -1, -1, 73, 74, + 75, -1, -1, -1, -1, -1, 81, 82, 83, -1, + -1, -1, -1, 88, -1, -1, 1, 92, 3, 4, + 5, 6, 7, 8, 9, -1, 11, 12, 103, 104, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, 27, 28, 29, 30, 31, -1, 33, - -1, 35, -1, 37, 38, -1, 40, 41, 42, 43, - 44, -1, 46, 47, 48, 49, 50, 51, -1, 53, - 54, -1, -1, -1, -1, -1, -1, -1, 62, -1, - -1, 65, -1, -1, -1, -1, -1, -1, -1, 73, - 74, 75, -1, -1, -1, -1, -1, 81, 82, 83, - -1, 85, -1, -1, 88, 89, -1, -1, 92, 93, - -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, - 104, 3, 4, 5, 6, 7, 8, 9, 10, 11, - 12, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, 27, 28, 29, 30, 31, - -1, 33, -1, 35, -1, 37, 38, -1, 40, 41, - 42, 43, -1, -1, 46, 47, 48, 49, 50, 51, - -1, 53, -1, -1, -1, -1, -1, -1, -1, -1, - 62, -1, -1, 65, -1, -1, -1, -1, -1, -1, - -1, 73, 74, 75, -1, -1, -1, -1, -1, 81, - 82, 83, -1, -1, -1, -1, 88, -1, -1, -1, - 92, 93, -1, -1, -1, -1, -1, -1, -1, -1, - 102, 1, 104, 3, 4, 5, 6, 7, 8, 9, - 10, 11, 12, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, -1, -1, 27, 28, 29, - 30, 31, -1, 33, -1, 35, -1, 37, 38, -1, - 40, 41, 42, 43, -1, -1, 46, 47, 48, 49, - 50, 51, -1, 53, -1, -1, -1, -1, -1, -1, - -1, -1, 62, -1, -1, 65, -1, -1, -1, -1, - -1, -1, -1, 73, 74, 75, -1, -1, -1, -1, - -1, 81, 82, 83, -1, -1, -1, -1, 88, -1, - -1, -1, 92, 93, -1, -1, -1, -1, -1, -1, - -1, -1, 102, 1, 104, 3, 4, -1, 6, 7, + -1, -1, 27, 28, 29, 30, 31, -1, 33, -1, + 35, -1, 37, 38, -1, 40, 41, 42, 43, -1, + -1, 46, 47, 48, 49, 50, 51, -1, 53, 54, + -1, 56, -1, -1, -1, -1, -1, 62, -1, -1, + 65, -1, -1, -1, -1, -1, -1, -1, 73, 74, + 75, -1, -1, -1, -1, -1, 81, 82, 83, 1, + -1, -1, 4, 88, 6, 7, -1, 92, -1, -1, + 12, -1, -1, -1, -1, -1, -1, -1, -1, 104, + -1, -1, -1, -1, -1, 27, -1, -1, -1, 31, + -1, -1, -1, 35, -1, 37, 38, -1, -1, -1, + -1, -1, 44, -1, -1, -1, -1, -1, -1, 51, + -1, 53, -1, 55, -1, 57, 58, 59, -1, 61, + 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, + 72, 73, 74, 75, 76, 77, 78, -1, -1, 81, + 82, 83, -1, 1, 86, 3, 4, 89, 6, 7, 8, 9, -1, 11, 12, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, -1, -1, -1, -1, 27, + -1, -1, 104, -1, -1, -1, -1, -1, -1, 27, 28, 29, 30, 31, -1, 33, -1, 35, -1, 37, 38, -1, 40, 41, 42, 43, -1, -1, 46, 47, 48, 49, 50, 51, -1, 53, 54, -1, -1, -1, -1, -1, -1, -1, 62, -1, -1, 65, -1, -1, -1, -1, -1, -1, -1, 73, 74, 75, -1, -1, -1, -1, -1, 81, 82, 83, -1, -1, -1, -1, - 88, 89, -1, 1, 92, 3, 4, -1, 6, 7, - 8, 9, -1, 11, 12, 103, 104, -1, -1, -1, - -1, 19, -1, -1, -1, -1, -1, -1, -1, 27, + 88, -1, -1, 1, 92, 3, 4, -1, 6, 7, + 8, 9, -1, 11, 12, -1, 104, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, -1, 27, 28, 29, 30, 31, -1, 33, -1, 35, -1, 37, 38, -1, 40, 41, 42, 43, -1, -1, 46, 47, 48, 49, 50, 51, -1, 53, 54, -1, -1, -1, @@ -2835,20 +2829,20 @@ -1, -1, -1, -1, -1, 73, 74, 75, -1, -1, -1, -1, -1, 81, 82, 83, -1, -1, -1, -1, 88, -1, -1, 1, 92, 3, 4, -1, 6, 7, - 8, 9, -1, 11, 12, 103, 104, -1, -1, -1, - -1, 19, -1, -1, -1, -1, -1, -1, -1, 27, + 8, 9, -1, 11, 12, -1, 104, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, -1, -1, 27, 28, 29, 30, 31, -1, 33, -1, 35, -1, 37, 38, -1, 40, 41, 42, 43, -1, -1, 46, 47, 48, 49, 50, 51, -1, 53, 54, -1, -1, -1, -1, -1, -1, -1, 62, -1, -1, 65, -1, -1, -1, -1, -1, -1, -1, 73, 74, 75, -1, -1, -1, -1, -1, 81, 82, 83, -1, -1, -1, -1, - 88, -1, -1, 1, 92, 3, 4, 5, 6, 7, - 8, 9, -1, 11, 12, 103, 104, -1, -1, -1, + 88, -1, -1, 1, 92, 3, 4, -1, 6, 7, + 8, 9, -1, 11, 12, -1, 104, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 27, 28, 29, 30, 31, -1, 33, -1, 35, -1, 37, 38, -1, 40, 41, 42, 43, -1, -1, 46, 47, - 48, 49, 50, 51, -1, 53, 54, -1, 56, -1, + 48, 49, 50, 51, -1, 53, -1, -1, 56, -1, -1, -1, -1, -1, 62, -1, -1, 65, -1, -1, -1, -1, -1, -1, -1, 73, 74, 75, -1, -1, -1, -1, -1, 81, 82, 83, -1, -1, -1, -1, @@ -2857,177 +2851,97 @@ -1, -1, -1, -1, -1, -1, -1, -1, -1, 27, 28, 29, 30, 31, -1, 33, -1, 35, -1, 37, 38, -1, 40, 41, 42, 43, -1, -1, 46, 47, - 48, 49, 50, 51, -1, 53, 54, -1, -1, -1, + 48, 49, 50, 51, -1, 53, -1, -1, -1, -1, -1, -1, -1, -1, 62, -1, -1, 65, -1, -1, -1, -1, -1, -1, -1, 73, 74, 75, -1, -1, -1, -1, -1, 81, 82, 83, -1, -1, -1, -1, - 88, 89, 1, -1, 92, 4, -1, 6, 7, -1, - -1, -1, -1, 12, -1, -1, 104, -1, -1, -1, - -1, -1, -1, -1, -1, -1, -1, -1, 27, -1, - -1, -1, 31, -1, -1, -1, 35, -1, 37, 38, - -1, -1, -1, -1, -1, 44, -1, -1, -1, -1, - -1, -1, 51, -1, 53, -1, 55, -1, 57, 58, - 59, -1, 61, 62, 63, 64, 65, 66, 67, 68, - 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, - -1, -1, 81, 82, 83, -1, 1, 86, 3, 4, - 89, 6, 7, 8, 9, -1, 11, 12, -1, -1, - -1, -1, -1, -1, -1, 104, -1, -1, -1, -1, - -1, -1, 27, 28, 29, 30, 31, -1, 33, -1, - 35, -1, 37, 38, -1, 40, 41, 42, 43, -1, - -1, 46, 47, 48, 49, 50, 51, -1, 53, 54, - -1, -1, -1, -1, -1, -1, -1, 62, -1, -1, - 65, -1, -1, -1, -1, -1, -1, -1, 73, 74, - 75, -1, -1, -1, -1, -1, 81, 82, 83, -1, - -1, -1, -1, 88, -1, -1, 1, 92, 3, 4, - -1, 6, 7, 8, 9, -1, 11, 12, -1, 104, - -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, 27, 28, 29, 30, 31, -1, 33, -1, - 35, -1, 37, 38, -1, 40, 41, 42, 43, -1, - -1, 46, 47, 48, 49, 50, 51, -1, 53, 54, - -1, -1, -1, -1, -1, -1, -1, 62, -1, -1, - 65, -1, -1, -1, -1, -1, -1, -1, 73, 74, - 75, -1, -1, -1, -1, -1, 81, 82, 83, -1, - -1, -1, -1, 88, -1, -1, 1, 92, 3, 4, - -1, 6, 7, 8, 9, -1, 11, 12, -1, 104, - -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, 27, 28, 29, 30, 31, -1, 33, -1, - 35, -1, 37, 38, -1, 40, 41, 42, 43, -1, - -1, 46, 47, 48, 49, 50, 51, -1, 53, -1, - -1, -1, -1, -1, -1, 60, -1, 62, -1, -1, - 65, -1, -1, -1, -1, -1, -1, -1, 73, 74, - 75, -1, -1, -1, -1, -1, 81, 82, 83, -1, - -1, -1, -1, 88, -1, -1, 1, 92, 3, 4, - -1, 6, 7, 8, 9, -1, 11, 12, -1, 104, - -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, 27, 28, 29, 30, 31, -1, 33, -1, - 35, -1, 37, 38, -1, 40, 41, 42, 43, -1, - -1, 46, 47, 48, 49, 50, 51, -1, 53, 54, - -1, -1, -1, -1, -1, -1, -1, 62, -1, -1, - 65, -1, -1, -1, -1, -1, -1, -1, 73, 74, - 75, -1, -1, -1, -1, -1, 81, 82, 83, -1, - -1, -1, -1, 88, -1, -1, 1, 92, 3, 4, - -1, 6, 7, 8, 9, -1, 11, 12, -1, 104, - -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, 27, 28, 29, 30, 31, -1, 33, -1, - 35, -1, 37, 38, -1, 40, 41, 42, 43, -1, - -1, 46, 47, 48, 49, 50, 51, -1, 53, 54, - -1, -1, -1, -1, -1, -1, -1, 62, -1, -1, - 65, -1, -1, -1, -1, -1, -1, -1, 73, 74, - 75, -1, -1, -1, -1, -1, 81, 82, 83, -1, - -1, -1, -1, 88, -1, -1, 1, 92, 3, 4, - -1, 6, 7, 8, 9, -1, 11, 12, -1, 104, - -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, 27, 28, 29, 30, 31, -1, 33, -1, - 35, -1, 37, 38, -1, 40, 41, 42, 43, -1, - -1, 46, 47, 48, 49, 50, 51, -1, 53, -1, - -1, 56, -1, -1, -1, -1, -1, 62, -1, -1, - 65, -1, -1, -1, -1, -1, -1, -1, 73, 74, - 75, -1, -1, -1, -1, -1, 81, 82, 83, -1, - -1, -1, -1, 88, -1, -1, 1, 92, 3, 4, - -1, 6, 7, 8, 9, -1, 11, 12, -1, 104, - -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, 27, 28, 29, 30, 31, -1, 33, -1, - 35, -1, 37, 38, -1, 40, 41, 42, 43, -1, - -1, 46, 47, 48, 49, 50, 51, -1, 53, -1, - -1, -1, -1, -1, -1, -1, -1, 62, -1, -1, - 65, -1, -1, -1, -1, -1, -1, -1, 73, 74, - 75, -1, -1, -1, -1, -1, 81, 82, 83, -1, - -1, -1, -1, 88, -1, -1, -1, 92, -1, -1, - -1, -1, -1, -1, -1, -1, -1, 102, 1, 104, - 3, 4, -1, 6, 7, 8, 9, -1, 11, 12, - -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, 27, 28, 29, 30, 31, -1, - 33, -1, 35, -1, 37, 38, -1, 40, 41, 42, - 43, -1, -1, 46, 47, 48, 49, 50, 51, -1, - 53, -1, -1, -1, -1, -1, -1, -1, -1, 62, - -1, -1, 65, -1, -1, -1, -1, -1, -1, -1, - 73, 74, 75, -1, -1, -1, -1, -1, 81, 82, - 83, -1, -1, -1, -1, 88, -1, -1, 1, 92, - 3, 4, -1, 6, 7, 8, 9, -1, 11, 12, - -1, 104, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, 27, 28, 29, 30, 31, -1, - 33, -1, 35, -1, 37, 38, -1, 40, 41, 42, - 43, -1, -1, 46, 47, 48, 49, 50, 51, -1, - 53, -1, -1, -1, -1, -1, -1, -1, -1, 62, - -1, -1, 65, -1, -1, -1, -1, -1, -1, -1, - 73, 74, 75, -1, -1, -1, -1, -1, 81, 82, - 83, -1, -1, -1, -1, 88, -1, 3, 4, 92, - 6, 7, 8, 9, -1, 11, 12, -1, -1, -1, - -1, 104, -1, -1, -1, -1, -1, -1, -1, -1, + 88, -1, -1, -1, 92, -1, -1, -1, -1, -1, + -1, -1, -1, -1, 102, 1, 104, 3, 4, -1, + 6, 7, 8, 9, -1, 11, 12, 67, 68, 69, + 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, -1, 27, 28, 29, 30, 31, -1, 33, -1, 35, -1, 37, 38, -1, 40, 41, 42, 43, -1, -1, 46, 47, 48, 49, 50, 51, -1, 53, -1, -1, - -1, -1, -1, -1, -1, -1, 62, -1, -1, 65, - -1, -1, -1, -1, -1, -1, -1, 73, 74, 75, - -1, -1, -1, -1, -1, 81, 82, 83, -1, -1, - -1, -1, 88, -1, -1, -1, 92, -1, -1, -1, - -1, -1, -1, -1, -1, -1, -1, -1, 104, 105, - 3, 4, 5, 6, 7, 8, 9, -1, 11, 12, - 13, -1, 15, 16, 17, 18, 19, 20, 21, 22, - 23, 24, 25, 26, 27, 28, 29, 30, 31, -1, - 33, -1, 35, -1, 37, 38, -1, 40, 41, 42, - 43, -1, -1, 46, 47, 48, 49, 50, 51, -1, - 53, 54, -1, 56, -1, -1, -1, -1, -1, 62, - -1, -1, 65, -1, -1, -1, -1, -1, -1, -1, - 73, 74, 75, -1, -1, -1, -1, -1, 81, 82, - 83, -1, -1, -1, -1, 88, -1, 90, -1, 92, - -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - 103, 104, 3, 4, 5, 6, 7, 8, 9, -1, - 11, 12, 13, -1, 15, 16, 17, 18, 19, 20, - 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, - 31, -1, 33, -1, 35, -1, 37, 38, -1, 40, - 41, 42, 43, -1, -1, 46, 47, 48, 49, 50, - 51, -1, 53, 54, -1, 56, -1, -1, -1, -1, - -1, 62, -1, -1, 65, -1, -1, -1, -1, -1, - -1, -1, 73, 74, 75, -1, -1, -1, -1, -1, - 81, 82, 83, -1, -1, -1, -1, 88, -1, 90, - -1, 92, 3, 4, 5, 6, 7, 8, 9, -1, - 11, 12, 13, 104, 15, 16, 17, 18, 19, 20, - 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, - 31, -1, 33, -1, 35, -1, 37, 38, -1, 40, - 41, 42, 43, -1, -1, 46, 47, 48, 49, 50, - 51, -1, 53, 54, -1, 56, -1, -1, -1, -1, - -1, 62, -1, -1, 65, -1, -1, -1, -1, -1, - -1, -1, 73, 74, 75, -1, -1, -1, -1, -1, - 81, 82, 83, -1, -1, -1, -1, 88, -1, 90, - -1, 92, 3, 4, 5, 6, 7, 8, 9, -1, - 11, 12, 13, 104, 15, 16, 17, 18, 19, 20, - 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, - 31, -1, 33, -1, 35, -1, 37, 38, -1, 40, - 41, 42, 43, -1, -1, 46, 47, 48, 49, 50, - 51, -1, 53, -1, -1, 56, -1, -1, -1, -1, - -1, 62, -1, -1, 65, -1, -1, -1, -1, -1, - -1, -1, 73, 74, 75, -1, -1, -1, -1, -1, - 81, 82, 83, -1, -1, -1, -1, 88, -1, 90, - -1, 92, 3, 4, 5, 6, 7, 8, 9, 10, - 11, 12, -1, 104, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, -1, 27, 28, 29, 30, - 31, -1, 33, -1, 35, -1, 37, 38, -1, 40, - 41, 42, 43, 44, -1, 46, 47, 48, 49, 50, - 51, -1, 53, -1, -1, -1, -1, -1, -1, -1, - -1, 62, -1, -1, 65, -1, -1, -1, -1, -1, - -1, -1, 73, 74, 75, -1, -1, -1, -1, -1, - 81, 82, 83, -1, 85, -1, -1, 88, 89, -1, - -1, 92, 93, 3, 4, 5, 6, 7, 8, 9, - 10, 11, 12, 104, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, -1, -1, 27, 28, 29, - 30, 31, -1, 33, -1, 35, -1, 37, 38, -1, - 40, 41, 42, 43, 44, -1, 46, 47, 48, 49, - 50, 51, -1, 53, -1, -1, -1, -1, -1, -1, - -1, -1, 62, -1, -1, 65, -1, -1, -1, -1, - -1, -1, -1, 73, 74, 75, -1, -1, -1, -1, - -1, 81, 82, 83, -1, 85, -1, -1, 88, 89, - -1, -1, 92, 93, 3, 4, -1, 6, 7, 8, - 9, -1, 11, 12, 104, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, -1, 62, -1, -1, 65, + -1, -1, -1, -1, -1, -1, -1, 73, 74, 75, + -1, -1, -1, -1, -1, 81, 82, 83, -1, -1, + -1, -1, 88, -1, -1, 1, 92, 3, 4, -1, + 6, 7, 8, 9, -1, 11, 12, -1, 104, -1, + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, + -1, 27, 28, 29, 30, 31, -1, 33, -1, 35, + -1, 37, 38, -1, 40, 41, 42, 43, -1, -1, + 46, 47, 48, 49, 50, 51, -1, 53, -1, -1, + -1, -1, -1, -1, -1, -1, 62, -1, -1, 65, + -1, -1, -1, -1, -1, -1, -1, 73, 74, 75, + -1, -1, -1, -1, -1, 81, 82, 83, -1, -1, + -1, -1, 88, -1, 3, 4, 92, 6, 7, 8, + 9, -1, 11, 12, -1, -1, -1, -1, 104, -1, -1, -1, -1, -1, -1, -1, -1, -1, 27, 28, 29, 30, 31, -1, 33, -1, 35, -1, 37, 38, - -1, 40, 41, 42, 43, 44, -1, 46, 47, 48, + -1, 40, 41, 42, 43, -1, -1, 46, 47, 48, 49, 50, 51, -1, 53, -1, -1, -1, -1, -1, -1, -1, -1, 62, -1, -1, 65, -1, -1, -1, -1, -1, -1, -1, 73, 74, 75, -1, -1, -1, - -1, -1, 81, 82, 83, -1, 85, -1, -1, 88, - 89, 3, 4, -1, 6, 7, 8, 9, -1, 11, - 12, -1, -1, -1, -1, 104, -1, -1, -1, -1, + -1, -1, 81, 82, 83, -1, -1, -1, -1, 88, + -1, -1, -1, 92, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, -1, 104, 105, 3, 4, 5, + 6, 7, 8, 9, -1, 11, 12, 13, -1, 15, + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, + 26, 27, 28, 29, 30, 31, -1, 33, -1, 35, + -1, 37, 38, -1, 40, 41, 42, 43, -1, -1, + 46, 47, 48, 49, 50, 51, -1, 53, 54, -1, + 56, -1, -1, -1, -1, -1, 62, -1, -1, 65, + -1, -1, -1, -1, -1, -1, -1, 73, 74, 75, + -1, -1, -1, -1, -1, 81, 82, 83, -1, -1, + -1, -1, 88, -1, 90, -1, 92, -1, -1, -1, + -1, -1, -1, -1, -1, -1, -1, 103, 104, 3, + 4, 5, 6, 7, 8, 9, -1, 11, 12, 13, + -1, 15, 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, -1, 33, + -1, 35, -1, 37, 38, -1, 40, 41, 42, 43, + -1, -1, 46, 47, 48, 49, 50, 51, -1, 53, + 54, -1, 56, -1, -1, -1, -1, -1, 62, -1, + -1, 65, -1, -1, -1, -1, -1, -1, -1, 73, + 74, 75, -1, -1, -1, -1, -1, 81, 82, 83, + -1, -1, -1, -1, 88, -1, 90, -1, 92, 3, + 4, 5, 6, 7, 8, 9, -1, 11, 12, 13, + 104, 15, 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, -1, 33, + -1, 35, -1, 37, 38, -1, 40, 41, 42, 43, + -1, -1, 46, 47, 48, 49, 50, 51, -1, 53, + 54, -1, 56, -1, -1, -1, -1, -1, 62, -1, + -1, 65, -1, -1, -1, -1, -1, -1, -1, 73, + 74, 75, -1, -1, -1, -1, -1, 81, 82, 83, + -1, -1, -1, -1, 88, -1, 90, -1, 92, 3, + 4, 5, 6, 7, 8, 9, -1, 11, 12, 13, + 104, 15, 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, -1, 33, + -1, 35, -1, 37, 38, -1, 40, 41, 42, 43, + -1, -1, 46, 47, 48, 49, 50, 51, -1, 53, + -1, -1, 56, -1, -1, -1, -1, -1, 62, -1, + -1, 65, -1, -1, -1, -1, -1, -1, -1, 73, + 74, 75, -1, -1, -1, -1, -1, 81, 82, 83, + -1, -1, -1, -1, 88, -1, 90, -1, 92, 3, + 4, 5, 6, 7, 8, 9, 10, 11, 12, -1, + 104, -1, -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, 27, 28, 29, 30, 31, -1, 33, + -1, 35, -1, 37, 38, -1, 40, 41, 42, 43, + 44, -1, 46, 47, 48, 49, 50, 51, -1, 53, + -1, -1, -1, -1, -1, -1, -1, -1, 62, -1, + -1, 65, -1, -1, -1, -1, -1, -1, -1, 73, + 74, 75, -1, -1, -1, -1, -1, 81, 82, 83, + -1, 85, -1, -1, 88, 89, -1, -1, 92, 93, + 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, + 104, -1, -1, -1, -1, -1, -1, -1, -1, -1, + -1, -1, -1, -1, 27, 28, 29, 30, 31, -1, + 33, -1, 35, -1, 37, 38, -1, 40, 41, 42, + 43, 44, -1, 46, 47, 48, 49, 50, 51, -1, + 53, -1, -1, -1, -1, -1, -1, -1, -1, 62, + -1, -1, 65, -1, -1, -1, -1, -1, -1, -1, + 73, 74, 75, -1, -1, -1, -1, -1, 81, 82, + 83, -1, 85, -1, -1, 88, 89, -1, -1, 92, + 93, 3, 4, -1, 6, 7, 8, 9, -1, 11, + 12, 104, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 27, 28, 29, 30, 31, -1, 33, -1, 35, -1, 37, 38, -1, 40, 41, 42, 43, 44, -1, 46, 47, 48, 49, 50, 51, @@ -3038,27 +2952,27 @@ -1, 6, 7, 8, 9, -1, 11, 12, -1, -1, -1, -1, 104, -1, -1, -1, -1, -1, -1, -1, -1, -1, 27, 28, 29, 30, 31, -1, 33, -1, - 35, -1, 37, 38, -1, 40, 41, 42, 43, -1, + 35, -1, 37, 38, -1, 40, 41, 42, 43, 44, -1, 46, 47, 48, 49, 50, 51, -1, 53, -1, -1, -1, -1, -1, -1, -1, -1, 62, -1, -1, - 65, -1, -1, -1, -1, 70, -1, -1, 73, 74, + 65, -1, -1, -1, -1, -1, -1, -1, 73, 74, 75, -1, -1, -1, -1, -1, 81, 82, 83, -1, - -1, -1, -1, 88, -1, 3, 4, 92, 6, 7, + 85, -1, -1, 88, 89, 3, 4, -1, 6, 7, 8, 9, -1, 11, 12, -1, -1, -1, -1, 104, -1, -1, -1, -1, -1, -1, -1, -1, -1, 27, 28, 29, 30, 31, -1, 33, -1, 35, -1, 37, - 38, -1, 40, 41, 42, 43, -1, -1, 46, 47, - 48, 49, 50, 51, -1, 53, -1, -1, 56, -1, + 38, -1, 40, 41, 42, 43, 44, -1, 46, 47, + 48, 49, 50, 51, -1, 53, -1, -1, -1, -1, -1, -1, -1, -1, 62, -1, -1, 65, -1, -1, -1, -1, -1, -1, -1, 73, 74, 75, -1, -1, - -1, -1, -1, 81, 82, 83, -1, -1, -1, -1, - 88, -1, 3, 4, 92, 6, 7, 8, 9, -1, + -1, -1, -1, 81, 82, 83, -1, 85, -1, -1, + 88, 89, 3, 4, -1, 6, 7, 8, 9, -1, 11, 12, -1, -1, -1, -1, 104, -1, -1, -1, -1, -1, -1, -1, -1, -1, 27, 28, 29, 30, 31, -1, 33, -1, 35, -1, 37, 38, -1, 40, 41, 42, 43, -1, -1, 46, 47, 48, 49, 50, 51, -1, 53, -1, -1, -1, -1, -1, -1, -1, - -1, 62, -1, -1, 65, -1, -1, -1, -1, -1, + -1, 62, -1, -1, 65, -1, -1, -1, -1, 70, -1, -1, 73, 74, 75, -1, -1, -1, -1, -1, 81, 82, 83, -1, -1, -1, -1, 88, -1, 3, 4, 92, 6, 7, 8, 9, -1, 11, 12, -1, @@ -3066,24 +2980,7 @@ -1, -1, -1, 27, 28, 29, 30, 31, -1, 33, -1, 35, -1, 37, 38, -1, 40, 41, 42, 43, -1, -1, 46, 47, 48, 49, 50, 51, -1, 53, - 54, -1, -1, -1, -1, -1, -1, -1, 62, -1, - -1, 65, -1, -1, -1, -1, -1, -1, -1, 73, - 74, 75, -1, -1, -1, -1, -1, 81, 82, 83, - -1, -1, 3, 4, 88, 6, 7, 8, 9, -1, - 11, 12, -1, -1, -1, -1, -1, -1, -1, -1, - 104, -1, -1, -1, -1, -1, 27, 28, 29, 30, - 31, -1, 33, -1, 35, -1, 37, 38, -1, 40, - 41, 42, 43, -1, -1, 46, 47, 48, 49, 50, - 51, -1, 53, -1, -1, -1, -1, -1, -1, -1, - -1, 62, -1, -1, 65, -1, -1, -1, -1, -1, - -1, -1, 73, 74, 75, -1, -1, -1, -1, -1, - 81, 82, 83, -1, -1, -1, -1, 88, 89, 3, - 4, -1, 6, 7, 8, 9, -1, 11, 12, -1, - -1, -1, -1, 104, -1, -1, -1, -1, -1, -1, - -1, -1, -1, 27, 28, 29, 30, 31, -1, 33, - -1, 35, -1, 37, 38, -1, 40, 41, 42, 43, - -1, -1, 46, 47, 48, 49, 50, 51, -1, 53, - -1, -1, -1, -1, -1, -1, -1, -1, 62, -1, + -1, -1, 56, -1, -1, -1, -1, -1, 62, -1, -1, 65, -1, -1, -1, -1, -1, -1, -1, 73, 74, 75, -1, -1, -1, -1, -1, 81, 82, 83, -1, -1, -1, -1, 88, -1, 3, 4, 92, 6, @@ -3100,6 +2997,23 @@ -1, -1, -1, -1, -1, -1, -1, 27, 28, 29, 30, 31, -1, 33, -1, 35, -1, 37, 38, -1, 40, 41, 42, 43, -1, -1, 46, 47, 48, 49, + 50, 51, -1, 53, 54, -1, -1, -1, -1, -1, + -1, -1, 62, -1, -1, 65, -1, -1, -1, -1, + -1, -1, -1, 73, 74, 75, -1, -1, -1, -1, + -1, 81, 82, 83, -1, -1, 3, 4, 88, 6, + 7, 8, 9, -1, 11, 12, -1, -1, -1, -1, + -1, -1, -1, -1, 104, -1, -1, -1, -1, -1, + 27, 28, 29, 30, 31, -1, 33, -1, 35, -1, + 37, 38, -1, 40, 41, 42, 43, -1, -1, 46, + 47, 48, 49, 50, 51, -1, 53, -1, -1, -1, + -1, -1, -1, -1, -1, 62, -1, -1, 65, -1, + -1, -1, -1, -1, -1, -1, 73, 74, 75, -1, + -1, -1, -1, -1, 81, 82, 83, -1, -1, -1, + -1, 88, 89, 3, 4, -1, 6, 7, 8, 9, + -1, 11, 12, -1, -1, -1, -1, 104, -1, -1, + -1, -1, -1, -1, -1, -1, -1, 27, 28, 29, + 30, 31, -1, 33, -1, 35, -1, 37, 38, -1, + 40, 41, 42, 43, -1, -1, 46, 47, 48, 49, 50, 51, -1, 53, -1, -1, -1, -1, -1, -1, -1, -1, 62, -1, -1, 65, -1, -1, -1, -1, -1, -1, -1, 73, 74, 75, -1, -1, -1, -1, @@ -3129,10 +3043,44 @@ 49, 50, 51, -1, 53, -1, -1, -1, -1, -1, -1, -1, -1, 62, -1, -1, 65, -1, -1, -1, -1, -1, -1, -1, 73, 74, 75, -1, -1, -1, + -1, -1, 81, 82, 83, -1, -1, -1, -1, 88, + -1, 3, 4, 92, 6, 7, 8, 9, -1, 11, + 12, -1, -1, -1, -1, 104, -1, -1, -1, -1, + -1, -1, -1, -1, -1, 27, 28, 29, 30, 31, + -1, 33, -1, 35, -1, 37, 38, -1, 40, 41, + 42, 43, -1, -1, 46, 47, 48, 49, 50, 51, + -1, 53, -1, -1, -1, -1, -1, -1, -1, -1, + 62, -1, -1, 65, -1, -1, -1, -1, -1, -1, + -1, 73, 74, 75, -1, -1, -1, -1, -1, 81, + 82, 83, -1, -1, -1, -1, 88, -1, 3, 4, + 92, 6, 7, 8, 9, -1, 11, 12, -1, -1, + -1, -1, 104, -1, -1, -1, -1, -1, -1, -1, + -1, -1, 27, 28, 29, 30, 31, -1, 33, -1, + 35, -1, 37, 38, -1, 40, 41, 42, 43, -1, + -1, 46, 47, 48, 49, 50, 51, -1, 53, -1, + -1, -1, -1, -1, -1, -1, -1, 62, -1, -1, + 65, -1, -1, -1, -1, -1, -1, -1, 73, 74, + 75, -1, -1, -1, -1, -1, 81, 82, 83, -1, + -1, 3, 4, 88, 6, 7, 8, 9, -1, 11, + 12, -1, -1, -1, -1, -1, -1, -1, -1, 104, + -1, -1, -1, -1, -1, 27, 28, 29, 30, 31, + -1, 33, -1, 35, -1, 37, 38, -1, 40, 41, + 42, 43, -1, -1, 46, 47, 48, 49, 50, 51, + -1, 53, -1, -1, -1, -1, -1, -1, -1, -1, + 62, -1, -1, 65, -1, -1, -1, -1, -1, -1, + -1, 73, 74, 75, -1, -1, -1, -1, -1, 81, + 82, 83, -1, -1, 3, 4, 88, 6, 7, 8, + 9, -1, 11, 12, -1, -1, -1, -1, -1, -1, + -1, -1, 104, -1, -1, -1, -1, -1, 27, 28, + 29, 30, 31, -1, 33, -1, 35, -1, 37, 38, + -1, 40, 41, 42, 43, -1, -1, 46, 47, 48, + 49, 50, 51, -1, 53, -1, -1, -1, -1, -1, + -1, -1, -1, 62, -1, -1, 65, -1, -1, -1, + -1, -1, -1, -1, 73, 74, 75, -1, -1, -1, -1, -1, 81, 82, 83, -1, -1, 3, 4, 88, 6, 7, 8, 9, -1, 11, 12, -1, -1, -1, -1, -1, -1, -1, -1, 104, -1, -1, -1, -1, - -1, 27, 28, 29, 30, 31, -1, 33, -1, 35, + -1, 27, 28, -1, -1, 31, -1, 33, -1, 35, -1, 37, 38, -1, 40, 41, 42, 43, -1, -1, 46, 47, 48, 49, 50, 51, -1, 53, -1, -1, -1, -1, -1, -1, -1, -1, 62, -1, -1, 65, @@ -3143,43 +3091,60 @@ -1, -1, -1, -1, 27, 28, 29, 30, 31, -1, 33, -1, 35, -1, 37, 38, -1, 40, 41, 42, 43, -1, -1, 46, 47, 48, 49, 50, 51, -1, - 53, -1, -1, -1, -1, -1, -1, -1, -1, 62, - -1, -1, 65, -1, -1, -1, -1, -1, -1, -1, - 73, 74, 75, -1, -1, -1, -1, -1, 81, 82, - 83, -1, -1, 3, 4, 88, 6, 7, 8, 9, - -1, 11, 12, -1, -1, -1, -1, -1, -1, -1, - -1, 104, -1, -1, -1, -1, -1, 27, 28, -1, - -1, 31, -1, 33, -1, 35, -1, 37, 38, -1, - 40, 41, 42, 43, -1, -1, 46, 47, 48, 49, - 50, 51, -1, 53, -1, -1, -1, -1, -1, -1, - -1, -1, 62, -1, -1, 65, -1, -1, -1, -1, - -1, -1, -1, 73, 74, 75, -1, -1, -1, -1, - -1, 81, 82, 83, -1, -1, 3, 4, 88, 6, - 7, 8, 9, -1, 11, 12, -1, -1, -1, -1, - -1, -1, -1, -1, 104, -1, -1, -1, -1, -1, - 27, 28, -1, -1, 31, -1, 33, -1, 35, -1, - 37, 38, -1, 40, 41, 42, 43, -1, -1, 46, - 47, 48, 49, 50, 51, -1, 53, -1, -1, -1, - -1, -1, -1, -1, -1, 62, -1, -1, 65, -1, - -1, -1, -1, -1, -1, -1, 73, 74, 75, -1, - -1, -1, -1, -1, 81, 82, 83, -1, -1, -1, - -1, 88, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, 55, -1, 57, 58, 59, 104, 61, 62, - 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, - 73, 74, 75, 76, 77, 78, 79, 57, 58, 59, - 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, + 53, -1, 3, 4, 5, 6, 7, -1, -1, -1, + -1, 12, -1, -1, -1, -1, -1, 3, 4, 5, + 6, 7, -1, -1, -1, -1, 12, -1, 81, 82, + 83, -1, -1, -1, 35, 88, -1, -1, -1, 92, + 41, 27, -1, 44, -1, 31, -1, -1, -1, 35, + 51, 104, 53, -1, -1, 41, -1, -1, -1, -1, + -1, -1, -1, -1, 65, 51, -1, 53, -1, -1, + 56, -1, -1, -1, 75, -1, -1, -1, -1, 65, + -1, -1, 83, -1, 85, -1, -1, 88, 89, 75, + -1, 3, 4, 5, 6, 7, -1, 83, 10, -1, + 12, -1, 88, -1, -1, -1, -1, -1, 3, 4, + 5, 6, 7, -1, -1, 27, -1, 12, -1, 31, + -1, -1, -1, 35, -1, -1, -1, -1, -1, 41, + -1, -1, 27, -1, -1, -1, 31, -1, -1, 51, + 35, 53, -1, -1, -1, -1, 41, -1, -1, -1, + -1, -1, -1, 65, -1, -1, 51, -1, 53, -1, + -1, -1, -1, 75, -1, 60, -1, -1, -1, -1, + 65, 83, -1, -1, -1, -1, 88, -1, -1, -1, + 75, 3, 4, 5, 6, 7, -1, -1, 83, -1, + 12, -1, -1, 88, -1, -1, -1, -1, 3, 4, + 5, 6, 7, -1, -1, 27, -1, 12, -1, 31, + -1, -1, -1, 35, -1, -1, -1, -1, -1, 41, + -1, -1, 27, -1, -1, -1, 31, -1, -1, 51, + 35, 53, -1, -1, 56, -1, 41, -1, -1, -1, + -1, -1, 4, 65, 6, 7, 51, -1, 53, -1, + 12, -1, -1, 75, -1, -1, -1, -1, -1, -1, + 65, 83, -1, -1, -1, 27, 88, -1, -1, 31, + 75, -1, -1, 35, -1, -1, -1, -1, 83, -1, + -1, -1, 44, 88, -1, -1, -1, -1, -1, 51, + -1, 53, -1, -1, -1, -1, -1, -1, -1, -1, + 57, 58, 59, 65, 61, 62, 63, 64, 65, 66, + 67, 68, 69, 75, 71, 72, 73, 74, 75, 76, + 77, 78, 79, 85, -1, -1, 88, 89, 57, 58, + 59, -1, 61, 62, 63, 64, 65, 66, 67, 68, + 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, + 79, 55, 32, 57, 58, 59, -1, 61, 62, 63, + 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, + 74, 75, 76, 77, 78, 79, 105, 57, 58, 59, + -1, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, - 77, 78, 79, 57, 58, 59, -1, 61, 62, 63, + 77, 78, 79, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 57, 58, 59, -1, - 61, 62, 63, 64, 65, 66, 67, 68, 69, -1, + 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 59, -1, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, - 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, - 73, 74, 75, 76, 77, 78, 79 + 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, + 72, 73, 74, 75, 76, 77, 78, 79, 64, 65, + 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, + 76, 77, 78, 79, 65, 66, 67, 68, 69, 70, + 71, 72, 73, 74, 75, 76, 77, 78, 79 }; /* -*-C-*- Note some compilers choke on comments on `#line' lines. */ #line 3 "/usr/local/lib/bison.simple" @@ -3364,23 +3329,8 @@ #endif #line 184 "/usr/local/lib/bison.simple" - -/* The user can define YYPARSE_PARAM as the name of an argument to be passed - into yyparse. The argument should have type void *. - It should actually point to an object. - Grammar actions can access the variable by casting it - to the proper pointer type. */ - -#ifdef YYPARSE_PARAM -#define YYPARSE_PARAM_DECL void *YYPARSE_PARAM; -#else -#define YYPARSE_PARAM -#define YYPARSE_PARAM_DECL -#endif - int -yyparse(YYPARSE_PARAM) - YYPARSE_PARAM_DECL +yyparse() { register int yystate; register int yyn; @@ -4767,21 +4717,13 @@ #line 1253 "parse.y" { yyval.ttype = build_parse_node (ADDR_EXPR, yyvsp[0].ttype); ; break;} -case 228: -#line 1255 "parse.y" -{ yyval.ttype = yyvsp[-1].ttype; ; - break;} -case 231: -#line 1262 "parse.y" +case 230: +#line 1260 "parse.y" { push_nested_class (TREE_TYPE (OP0 (yyval.ttype)), 3); TREE_COMPLEXITY (yyval.ttype) = current_class_depth; ; break;} -case 232: -#line 1265 "parse.y" -{ yyval.ttype = finish_decl_parsing (yyvsp[-1].ttype); ; - break;} -case 233: -#line 1270 "parse.y" +case 231: +#line 1266 "parse.y" { if (TREE_CODE (yyval.ttype) == BIT_NOT_EXPR) yyval.ttype = build_x_unary_op (BIT_NOT_EXPR, TREE_OPERAND (yyval.ttype, 0)); @@ -4801,20 +4743,20 @@ yyval.ttype = do_identifier (yyval.ttype); ; break;} -case 236: -#line 1291 "parse.y" +case 234: +#line 1287 "parse.y" { yyval.ttype = combine_strings (yyval.ttype); ; break;} -case 237: -#line 1293 "parse.y" +case 235: +#line 1289 "parse.y" { yyval.ttype = yyvsp[-1].ttype; ; break;} -case 238: -#line 1295 "parse.y" +case 236: +#line 1291 "parse.y" { yyval.ttype = error_mark_node; ; break;} -case 239: -#line 1297 "parse.y" +case 237: +#line 1293 "parse.y" { if (current_function_decl == 0) { error ("braced-group within expression allowed only inside a function"); @@ -4823,8 +4765,8 @@ keep_next_level (); yyval.ttype = expand_start_stmt_expr (); ; break;} -case 240: -#line 1305 "parse.y" +case 238: +#line 1301 "parse.y" { tree rtl_exp; if (flag_ansi) pedwarn ("ANSI C++ forbids braced-groups within expressions"); @@ -4846,16 +4788,16 @@ yyval.ttype = yyvsp[-1].ttype; ; break;} -case 241: -#line 1326 "parse.y" +case 239: +#line 1322 "parse.y" { /* [eichin:19911016.1902EST] */ yyval.ttype = build_x_function_call (yyvsp[-3].ttype, yyvsp[-1].ttype, current_class_decl); /* here we instantiate_class_template as needed... */ do_pending_templates (); ; break;} -case 242: -#line 1330 "parse.y" +case 240: +#line 1326 "parse.y" { if (TREE_CODE (yyvsp[-1].ttype) == CALL_EXPR && TREE_TYPE (yyvsp[-1].ttype) != void_type_node) @@ -4864,8 +4806,8 @@ yyval.ttype = yyvsp[-1].ttype; ; break;} -case 243: -#line 1338 "parse.y" +case 241: +#line 1334 "parse.y" { yyval.ttype = build_x_function_call (yyval.ttype, NULL_TREE, current_class_decl); if (TREE_CODE (yyval.ttype) == CALL_EXPR @@ -4873,12 +4815,12 @@ yyval.ttype = require_complete_type (yyval.ttype); ; break;} -case 244: -#line 1345 "parse.y" +case 242: +#line 1341 "parse.y" { yyval.ttype = grok_array_decl (yyval.ttype, yyvsp[-1].ttype); ; break;} -case 245: -#line 1347 "parse.y" +case 243: +#line 1343 "parse.y" { /* If we get an OFFSET_REF, turn it into what it really means (e.g., a COMPONENT_REF). This way if we've got, say, a reference to a static member that's being operated @@ -4888,14 +4830,14 @@ yyval.ttype = resolve_offset_ref (yyval.ttype); yyval.ttype = build_x_unary_op (POSTINCREMENT_EXPR, yyval.ttype); ; break;} -case 246: -#line 1356 "parse.y" +case 244: +#line 1352 "parse.y" { if (TREE_CODE (yyval.ttype) == OFFSET_REF) yyval.ttype = resolve_offset_ref (yyval.ttype); yyval.ttype = build_x_unary_op (POSTDECREMENT_EXPR, yyval.ttype); ; break;} -case 247: -#line 1361 "parse.y" +case 245: +#line 1357 "parse.y" { if (current_class_decl) { #ifdef WARNING_ABOUT_CCD @@ -4919,8 +4861,8 @@ } ; break;} -case 248: -#line 1384 "parse.y" +case 246: +#line 1380 "parse.y" { tree type; tree id = yyval.ttype; @@ -4965,37 +4907,37 @@ } ; break;} -case 250: -#line 1429 "parse.y" +case 248: +#line 1425 "parse.y" { tree type = groktypename (yyvsp[-4].ttype); yyval.ttype = build_dynamic_cast (type, yyvsp[-1].ttype); ; break;} -case 251: -#line 1432 "parse.y" +case 249: +#line 1428 "parse.y" { tree type = groktypename (yyvsp[-4].ttype); yyval.ttype = build_static_cast (type, yyvsp[-1].ttype); ; break;} -case 252: -#line 1435 "parse.y" +case 250: +#line 1431 "parse.y" { tree type = groktypename (yyvsp[-4].ttype); yyval.ttype = build_reinterpret_cast (type, yyvsp[-1].ttype); ; break;} -case 253: -#line 1438 "parse.y" +case 251: +#line 1434 "parse.y" { tree type = groktypename (yyvsp[-4].ttype); yyval.ttype = build_const_cast (type, yyvsp[-1].ttype); ; break;} -case 254: -#line 1441 "parse.y" +case 252: +#line 1437 "parse.y" { yyval.ttype = build_typeid (yyvsp[-1].ttype); ; break;} -case 255: -#line 1443 "parse.y" +case 253: +#line 1439 "parse.y" { tree type = groktypename (yyvsp[-1].ttype); yyval.ttype = get_typeid (type); ; break;} -case 256: -#line 1446 "parse.y" +case 254: +#line 1442 "parse.y" { do_scoped_id: yyval.ttype = IDENTIFIER_GLOBAL_VALUE (yyvsp[0].ttype); @@ -5035,8 +4977,8 @@ ; break;} -case 257: -#line 1485 "parse.y" +case 255: +#line 1481 "parse.y" { got_scope = NULL_TREE; if (TREE_CODE (yyvsp[0].ttype) == IDENTIFIER_NODE) @@ -5044,28 +4986,28 @@ yyval.ttype = yyvsp[0].ttype; ; break;} +case 256: +#line 1488 "parse.y" +{ yyval.ttype = build_offset_ref (OP0 (yyval.ttype), OP1 (yyval.ttype)); ; + break;} +case 257: +#line 1490 "parse.y" +{ yyval.ttype = build_member_call (OP0 (yyval.ttype), OP1 (yyval.ttype), yyvsp[-1].ttype); ; + break;} case 258: #line 1492 "parse.y" -{ yyval.ttype = build_offset_ref (OP0 (yyval.ttype), OP1 (yyval.ttype)); ; +{ yyval.ttype = build_member_call (OP0 (yyval.ttype), OP1 (yyval.ttype), NULL_TREE); ; break;} case 259: #line 1494 "parse.y" -{ yyval.ttype = build_member_call (OP0 (yyval.ttype), OP1 (yyval.ttype), yyvsp[-1].ttype); ; +{ yyval.ttype = build_component_ref (yyval.ttype, yyvsp[0].ttype, NULL_TREE, 1); ; break;} case 260: #line 1496 "parse.y" -{ yyval.ttype = build_member_call (OP0 (yyval.ttype), OP1 (yyval.ttype), NULL_TREE); ; +{ yyval.ttype = build_object_ref (yyval.ttype, OP0 (yyvsp[0].ttype), OP1 (yyvsp[0].ttype)); ; break;} case 261: #line 1498 "parse.y" -{ yyval.ttype = build_component_ref (yyval.ttype, yyvsp[0].ttype, NULL_TREE, 1); ; - break;} -case 262: -#line 1500 "parse.y" -{ yyval.ttype = build_object_ref (yyval.ttype, OP0 (yyvsp[0].ttype), OP1 (yyvsp[0].ttype)); ; - break;} -case 263: -#line 1502 "parse.y" { #if 0 /* This is a future direction of this code, but because @@ -5081,8 +5023,8 @@ #endif ; break;} -case 264: -#line 1517 "parse.y" +case 262: +#line 1513 "parse.y" { #if 0 /* This is a future direction of this code, but because @@ -5098,8 +5040,8 @@ #endif ; break;} -case 265: -#line 1532 "parse.y" +case 263: +#line 1528 "parse.y" { if (IS_SIGNATURE (IDENTIFIER_TYPE_VALUE (OP0 (yyvsp[-3].ttype)))) { @@ -5111,8 +5053,8 @@ yyval.ttype = build_scoped_method_call (yyval.ttype, OP0 (yyvsp[-3].ttype), OP1 (yyvsp[-3].ttype), yyvsp[-1].ttype); ; break;} -case 266: -#line 1543 "parse.y" +case 264: +#line 1539 "parse.y" { if (IS_SIGNATURE (IDENTIFIER_TYPE_VALUE (OP0 (yyvsp[-1].ttype)))) { @@ -5124,8 +5066,8 @@ yyval.ttype = build_scoped_method_call (yyval.ttype, OP0 (yyvsp[-1].ttype), OP1 (yyvsp[-1].ttype), NULL_TREE); ; break;} -case 267: -#line 1555 "parse.y" +case 265: +#line 1551 "parse.y" { if (TREE_CODE (TREE_TYPE (yyvsp[-3].ttype)) != TREE_CODE (TREE_TYPE (IDENTIFIER_GLOBAL_VALUE (yyvsp[-1].ttype)))) @@ -5133,8 +5075,8 @@ yyval.ttype = convert (void_type_node, yyvsp[-3].ttype); ; break;} -case 268: -#line 1562 "parse.y" +case 266: +#line 1558 "parse.y" { if (yyvsp[-4].ttype != yyvsp[-1].ttype) cp_error ("destructor specifier `%T::~%T()' must have matching names", yyvsp[-4].ttype, yyvsp[-1].ttype); @@ -5144,36 +5086,36 @@ yyval.ttype = convert (void_type_node, yyvsp[-5].ttype); ; break;} -case 269: -#line 1611 "parse.y" +case 267: +#line 1607 "parse.y" { yyval.itype = 0; ; break;} -case 270: -#line 1613 "parse.y" +case 268: +#line 1609 "parse.y" { got_scope = NULL_TREE; yyval.itype = 1; ; break;} -case 271: -#line 1617 "parse.y" +case 269: +#line 1613 "parse.y" { yyval.itype = 0; ; break;} -case 272: -#line 1619 "parse.y" +case 270: +#line 1615 "parse.y" { got_scope = NULL_TREE; yyval.itype = 1; ; break;} -case 273: -#line 1624 "parse.y" +case 271: +#line 1620 "parse.y" { yyval.ttype = true_node; ; break;} -case 274: -#line 1626 "parse.y" +case 272: +#line 1622 "parse.y" { yyval.ttype = false_node; ; break;} -case 276: -#line 1633 "parse.y" +case 274: +#line 1629 "parse.y" { yyval.ttype = chainon (yyval.ttype, yyvsp[0].ttype); ; break;} -case 277: -#line 1638 "parse.y" +case 275: +#line 1634 "parse.y" { if (! current_function_parms_stored) store_parm_decls (); @@ -5184,14 +5126,14 @@ keep_next_level (); ; break;} -case 279: -#line 1651 "parse.y" +case 277: +#line 1647 "parse.y" { yyval.ttype = build_x_arrow (yyval.ttype); ; break;} -case 280: -#line 1659 "parse.y" +case 278: +#line 1655 "parse.y" { tree d = get_decl_list (yyvsp[-2].ttype); int yes = suspend_momentary (); d = start_decl (yyvsp[-1].ttype, d, 0, NULL_TREE); @@ -5201,8 +5143,8 @@ note_got_semicolon (yyvsp[-2].ttype); ; break;} -case 281: -#line 1668 "parse.y" +case 279: +#line 1664 "parse.y" { tree d = yyvsp[-2].ttype; int yes = suspend_momentary (); d = start_decl (yyvsp[-1].ttype, d, 0, NULL_TREE); @@ -5211,164 +5153,164 @@ note_list_got_semicolon (yyvsp[-2].ttype); ; break;} -case 282: -#line 1676 "parse.y" +case 280: +#line 1672 "parse.y" { resume_momentary (yyvsp[-1].itype); if (IS_AGGR_TYPE_CODE (TREE_CODE (yyvsp[-2].ttype))) note_got_semicolon (yyvsp[-2].ttype); ; break;} -case 283: -#line 1682 "parse.y" +case 281: +#line 1678 "parse.y" { resume_momentary (yyvsp[-1].itype); note_list_got_semicolon (yyvsp[-2].ttype); ; break;} -case 284: -#line 1687 "parse.y" +case 282: +#line 1683 "parse.y" { resume_momentary (yyvsp[-1].itype); ; break;} -case 285: -#line 1689 "parse.y" +case 283: +#line 1685 "parse.y" { shadow_tag (yyvsp[-1].ttype); note_list_got_semicolon (yyvsp[-1].ttype); ; break;} -case 286: -#line 1694 "parse.y" +case 284: +#line 1690 "parse.y" { warning ("empty declaration"); ; break;} -case 289: -#line 1708 "parse.y" +case 287: +#line 1704 "parse.y" { yyval.ttype = build_parse_node (CALL_EXPR, NULL_TREE, empty_parms (), NULL_TREE); ; break;} -case 290: -#line 1711 "parse.y" +case 288: +#line 1707 "parse.y" { yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, empty_parms (), NULL_TREE); ; break;} +case 289: +#line 1714 "parse.y" +{ yyval.ttype = build_decl_list (yyval.ttype, yyvsp[0].ttype); ; + break;} +case 290: +#line 1716 "parse.y" +{ yyval.ttype = build_decl_list (yyval.ttype, yyvsp[0].ttype); ; + break;} case 291: #line 1718 "parse.y" -{ yyval.ttype = build_decl_list (yyval.ttype, yyvsp[0].ttype); ; +{ yyval.ttype = build_decl_list (get_decl_list (yyval.ttype), yyvsp[0].ttype); ; break;} case 292: #line 1720 "parse.y" -{ yyval.ttype = build_decl_list (yyval.ttype, yyvsp[0].ttype); ; +{ yyval.ttype = build_decl_list (yyval.ttype, NULL_TREE); ; break;} case 293: #line 1722 "parse.y" -{ yyval.ttype = build_decl_list (get_decl_list (yyval.ttype), yyvsp[0].ttype); ; - break;} -case 294: -#line 1724 "parse.y" { yyval.ttype = build_decl_list (yyval.ttype, NULL_TREE); ; break;} -case 295: -#line 1726 "parse.y" -{ yyval.ttype = build_decl_list (yyval.ttype, NULL_TREE); ; +case 296: +#line 1735 "parse.y" +{ yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[0].ttype, yyval.ttype); ; + break;} +case 297: +#line 1737 "parse.y" +{ yyval.ttype = decl_tree_cons (NULL_TREE, yyval.ttype, yyvsp[0].ttype); ; break;} case 298: #line 1739 "parse.y" -{ yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[0].ttype, yyval.ttype); ; +{ yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[-1].ttype, chainon (yyvsp[0].ttype, yyval.ttype)); ; break;} case 299: #line 1741 "parse.y" -{ yyval.ttype = decl_tree_cons (NULL_TREE, yyval.ttype, yyvsp[0].ttype); ; +{ yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[-1].ttype, chainon (yyvsp[0].ttype, yyval.ttype)); ; break;} case 300: #line 1743 "parse.y" -{ yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[-1].ttype, chainon (yyvsp[0].ttype, yyval.ttype)); ; - break;} -case 301: -#line 1745 "parse.y" -{ yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[-1].ttype, chainon (yyvsp[0].ttype, yyval.ttype)); ; - break;} -case 302: -#line 1747 "parse.y" { yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[-2].ttype, chainon (yyvsp[-1].ttype, chainon (yyvsp[0].ttype, yyval.ttype))); ; break;} -case 303: -#line 1753 "parse.y" +case 301: +#line 1749 "parse.y" { if (extra_warnings) warning ("`%s' is not at beginning of declaration", IDENTIFIER_POINTER (yyval.ttype)); yyval.ttype = build_decl_list (NULL_TREE, yyval.ttype); ; break;} -case 304: -#line 1758 "parse.y" +case 302: +#line 1754 "parse.y" { yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[0].ttype, yyval.ttype); ; break;} -case 305: -#line 1760 "parse.y" +case 303: +#line 1756 "parse.y" { if (extra_warnings) warning ("`%s' is not at beginning of declaration", IDENTIFIER_POINTER (yyvsp[0].ttype)); yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[0].ttype, yyval.ttype); ; break;} -case 306: -#line 1772 "parse.y" +case 304: +#line 1768 "parse.y" { TREE_STATIC (yyval.ttype) = 1; ; break;} -case 307: -#line 1774 "parse.y" +case 305: +#line 1770 "parse.y" { yyval.ttype = IDENTIFIER_AS_LIST (yyval.ttype); ; break;} -case 308: -#line 1776 "parse.y" +case 306: +#line 1772 "parse.y" { yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[0].ttype, yyval.ttype); TREE_STATIC (yyval.ttype) = 1; ; break;} -case 309: -#line 1779 "parse.y" +case 307: +#line 1775 "parse.y" { if (extra_warnings && TREE_STATIC (yyval.ttype)) warning ("`%s' is not at beginning of declaration", IDENTIFIER_POINTER (yyvsp[0].ttype)); yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[0].ttype, yyval.ttype); TREE_STATIC (yyval.ttype) = TREE_STATIC (yyvsp[-1].ttype); ; break;} -case 310: -#line 1795 "parse.y" +case 308: +#line 1791 "parse.y" { yyval.ttype = get_decl_list (yyval.ttype); ; break;} -case 311: -#line 1797 "parse.y" +case 309: +#line 1793 "parse.y" { yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[0].ttype, yyval.ttype); ; break;} -case 312: -#line 1799 "parse.y" +case 310: +#line 1795 "parse.y" { yyval.ttype = decl_tree_cons (NULL_TREE, yyval.ttype, yyvsp[0].ttype); ; break;} -case 313: -#line 1801 "parse.y" +case 311: +#line 1797 "parse.y" { yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[-1].ttype, chainon (yyvsp[0].ttype, yyval.ttype)); ; break;} -case 314: -#line 1806 "parse.y" +case 312: +#line 1802 "parse.y" { yyval.ttype = build_decl_list (NULL_TREE, yyval.ttype); ; break;} -case 315: -#line 1808 "parse.y" +case 313: +#line 1804 "parse.y" { yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[0].ttype, yyval.ttype); ; break;} -case 319: -#line 1819 "parse.y" +case 317: +#line 1815 "parse.y" { yyval.ttype = TREE_TYPE (yyvsp[-1].ttype); if (flag_ansi) pedwarn ("ANSI C++ forbids `typeof'"); ; break;} -case 320: -#line 1823 "parse.y" +case 318: +#line 1819 "parse.y" { yyval.ttype = groktypename (yyvsp[-1].ttype); if (flag_ansi) pedwarn ("ANSI C++ forbids `typeof'"); ; break;} -case 321: -#line 1827 "parse.y" +case 319: +#line 1823 "parse.y" { tree type = TREE_TYPE (yyvsp[-1].ttype); if (IS_AGGR_TYPE (type)) @@ -5383,8 +5325,8 @@ } ; break;} -case 322: -#line 1841 "parse.y" +case 320: +#line 1837 "parse.y" { tree type = groktypename (yyvsp[-1].ttype); if (IS_AGGR_TYPE (type)) @@ -5399,16 +5341,16 @@ } ; break;} -case 332: -#line 1880 "parse.y" +case 330: +#line 1876 "parse.y" { yyval.ttype = NULL_TREE; ; break;} -case 333: -#line 1882 "parse.y" +case 331: +#line 1878 "parse.y" { if (TREE_CHAIN (yyvsp[-1].ttype)) yyvsp[-1].ttype = combine_strings (yyvsp[-1].ttype); yyval.ttype = yyvsp[-1].ttype; ; break;} -case 334: -#line 1887 "parse.y" +case 332: +#line 1883 "parse.y" { current_declspecs = yyvsp[-5].ttype; if (TREE_CODE (current_declspecs) != TREE_LIST) current_declspecs = get_decl_list (current_declspecs); @@ -5423,13 +5365,13 @@ yyval.ttype = start_decl (yyvsp[-4].ttype, current_declspecs, 1, yyvsp[-3].ttype); cplus_decl_attributes (yyval.ttype, yyvsp[-1].ttype); ; break;} -case 335: -#line 1902 "parse.y" +case 333: +#line 1898 "parse.y" { finish_decl (yyvsp[-1].ttype, yyvsp[0].ttype, yyvsp[-4].ttype, 0); yyval.itype = yyvsp[-2].itype; ; break;} -case 336: -#line 1905 "parse.y" +case 334: +#line 1901 "parse.y" { tree d; current_declspecs = yyvsp[-4].ttype; if (TREE_CODE (current_declspecs) != TREE_LIST) @@ -5446,35 +5388,35 @@ cplus_decl_attributes (d, yyvsp[0].ttype); finish_decl (d, NULL_TREE, yyvsp[-1].ttype, 0); ; break;} -case 337: -#line 1924 "parse.y" +case 335: +#line 1920 "parse.y" { yyval.ttype = start_decl (yyvsp[-4].ttype, current_declspecs, 1, yyvsp[-3].ttype); cplus_decl_attributes (yyval.ttype, yyvsp[-1].ttype); ; break;} -case 338: -#line 1928 "parse.y" +case 336: +#line 1924 "parse.y" { finish_decl (yyvsp[-1].ttype, yyvsp[0].ttype, yyvsp[-4].ttype, 0); ; break;} -case 339: -#line 1930 "parse.y" +case 337: +#line 1926 "parse.y" { yyval.ttype = start_decl (yyvsp[-3].ttype, current_declspecs, 0, yyvsp[-2].ttype); cplus_decl_attributes (yyval.ttype, yyvsp[0].ttype); finish_decl (yyval.ttype, NULL_TREE, yyvsp[-1].ttype, 0); ; break;} -case 340: -#line 1937 "parse.y" +case 338: +#line 1933 "parse.y" { current_declspecs = yyvsp[-5].ttype; yyvsp[0].itype = suspend_momentary (); yyval.ttype = start_decl (yyvsp[-4].ttype, current_declspecs, 1, yyvsp[-3].ttype); cplus_decl_attributes (yyval.ttype, yyvsp[-1].ttype); ; break;} -case 341: -#line 1943 "parse.y" +case 339: +#line 1939 "parse.y" { finish_decl (yyvsp[-1].ttype, yyvsp[0].ttype, yyvsp[-4].ttype, 0); yyval.itype = yyvsp[-2].itype; ; break;} -case 342: -#line 1946 "parse.y" +case 340: +#line 1942 "parse.y" { tree d; current_declspecs = yyvsp[-4].ttype; yyval.itype = suspend_momentary (); @@ -5482,20 +5424,20 @@ cplus_decl_attributes (d, yyvsp[0].ttype); finish_decl (d, NULL_TREE, yyvsp[-1].ttype, 0); ; break;} -case 343: -#line 1956 "parse.y" +case 341: +#line 1952 "parse.y" { current_declspecs = NULL_TREE; yyvsp[0].itype = suspend_momentary (); yyval.ttype = start_decl (yyvsp[-4].ttype, current_declspecs, 1, yyvsp[-3].ttype); cplus_decl_attributes (yyval.ttype, yyvsp[-1].ttype); ; break;} -case 344: -#line 1962 "parse.y" +case 342: +#line 1958 "parse.y" { finish_decl (yyvsp[-1].ttype, yyvsp[0].ttype, yyvsp[-4].ttype, 0); yyval.itype = yyvsp[-2].itype; ; break;} -case 345: -#line 1965 "parse.y" +case 343: +#line 1961 "parse.y" { tree d; current_declspecs = NULL_TREE; yyval.itype = suspend_momentary (); @@ -5503,147 +5445,147 @@ cplus_decl_attributes (d, yyvsp[0].ttype); finish_decl (d, NULL_TREE, yyvsp[-1].ttype, 0); ; break;} -case 346: -#line 1977 "parse.y" +case 344: +#line 1973 "parse.y" { yyval.ttype = NULL_TREE; ; break;} -case 347: -#line 1979 "parse.y" +case 345: +#line 1975 "parse.y" { yyval.ttype = yyvsp[0].ttype; ; break;} -case 348: -#line 1984 "parse.y" +case 346: +#line 1980 "parse.y" { yyval.ttype = yyvsp[0].ttype; ; break;} -case 349: -#line 1986 "parse.y" +case 347: +#line 1982 "parse.y" { yyval.ttype = chainon (yyvsp[-1].ttype, yyvsp[0].ttype); ; break;} -case 350: -#line 1991 "parse.y" +case 348: +#line 1987 "parse.y" { yyval.ttype = yyvsp[-2].ttype; ; break;} -case 351: -#line 1996 "parse.y" +case 349: +#line 1992 "parse.y" { yyval.ttype = build_tree_list (NULL_TREE, yyvsp[0].ttype); ; break;} -case 352: -#line 1998 "parse.y" +case 350: +#line 1994 "parse.y" { yyval.ttype = chainon (yyvsp[-2].ttype, build_tree_list (NULL_TREE, yyvsp[0].ttype)); ; break;} -case 353: -#line 2003 "parse.y" +case 351: +#line 1999 "parse.y" { yyval.ttype = NULL_TREE; ; break;} -case 354: -#line 2005 "parse.y" +case 352: +#line 2001 "parse.y" { yyval.ttype = yyvsp[0].ttype; ; break;} -case 355: -#line 2007 "parse.y" +case 353: +#line 2003 "parse.y" { yyval.ttype = tree_cons (yyvsp[-3].ttype, NULL_TREE, build_tree_list (NULL_TREE, yyvsp[-1].ttype)); ; break;} -case 356: -#line 2009 "parse.y" +case 354: +#line 2005 "parse.y" { yyval.ttype = tree_cons (yyvsp[-5].ttype, NULL_TREE, tree_cons (NULL_TREE, yyvsp[-3].ttype, yyvsp[-1].ttype)); ; break;} -case 357: -#line 2011 "parse.y" +case 355: +#line 2007 "parse.y" { yyval.ttype = tree_cons (yyvsp[-3].ttype, NULL_TREE, yyvsp[-1].ttype); ; break;} -case 362: -#line 2027 "parse.y" +case 360: +#line 2023 "parse.y" { yyval.ttype = build_tree_list (NULL_TREE, yyvsp[0].ttype); ; break;} -case 363: -#line 2029 "parse.y" +case 361: +#line 2025 "parse.y" { yyval.ttype = chainon (yyvsp[-2].ttype, build_tree_list (NULL_TREE, yyvsp[0].ttype)); ; break;} -case 365: -#line 2035 "parse.y" +case 363: +#line 2031 "parse.y" { yyval.ttype = build_nt (CONSTRUCTOR, NULL_TREE, NULL_TREE); TREE_HAS_CONSTRUCTOR (yyval.ttype) = 1; ; break;} -case 366: -#line 2038 "parse.y" +case 364: +#line 2034 "parse.y" { yyval.ttype = build_nt (CONSTRUCTOR, NULL_TREE, nreverse (yyvsp[-1].ttype)); TREE_HAS_CONSTRUCTOR (yyval.ttype) = 1; ; break;} -case 367: -#line 2041 "parse.y" +case 365: +#line 2037 "parse.y" { yyval.ttype = build_nt (CONSTRUCTOR, NULL_TREE, nreverse (yyvsp[-2].ttype)); TREE_HAS_CONSTRUCTOR (yyval.ttype) = 1; ; break;} -case 368: -#line 2044 "parse.y" +case 366: +#line 2040 "parse.y" { yyval.ttype = NULL_TREE; ; break;} -case 369: -#line 2051 "parse.y" +case 367: +#line 2047 "parse.y" { yyval.ttype = build_tree_list (NULL_TREE, yyval.ttype); ; break;} -case 370: -#line 2053 "parse.y" +case 368: +#line 2049 "parse.y" { yyval.ttype = tree_cons (NULL_TREE, yyvsp[0].ttype, yyval.ttype); ; break;} -case 371: -#line 2056 "parse.y" +case 369: +#line 2052 "parse.y" { yyval.ttype = build_tree_list (yyvsp[-2].ttype, yyvsp[0].ttype); ; break;} -case 372: -#line 2058 "parse.y" +case 370: +#line 2054 "parse.y" { yyval.ttype = tree_cons (yyvsp[-2].ttype, yyvsp[0].ttype, yyval.ttype); ; break;} -case 373: -#line 2060 "parse.y" +case 371: +#line 2056 "parse.y" { yyval.ttype = build_tree_list (yyval.ttype, yyvsp[0].ttype); ; break;} -case 374: -#line 2062 "parse.y" +case 372: +#line 2058 "parse.y" { yyval.ttype = tree_cons (yyvsp[-2].ttype, yyvsp[0].ttype, yyval.ttype); ; break;} -case 375: -#line 2067 "parse.y" +case 373: +#line 2063 "parse.y" { yyvsp[0].itype = suspend_momentary (); yyval.ttype = start_enum (yyvsp[-1].ttype); ; break;} -case 376: -#line 2070 "parse.y" +case 374: +#line 2066 "parse.y" { yyval.ttype = finish_enum (yyvsp[-3].ttype, yyvsp[-2].ttype); resume_momentary ((int) yyvsp[-4].itype); check_for_missing_semicolon (yyvsp[-3].ttype); ; break;} -case 377: -#line 2074 "parse.y" +case 375: +#line 2070 "parse.y" { yyval.ttype = finish_enum (start_enum (yyvsp[-2].ttype), NULL_TREE); check_for_missing_semicolon (yyval.ttype); ; break;} -case 378: -#line 2077 "parse.y" +case 376: +#line 2073 "parse.y" { yyvsp[0].itype = suspend_momentary (); yyval.ttype = start_enum (make_anon_name ()); ; break;} -case 379: -#line 2080 "parse.y" +case 377: +#line 2076 "parse.y" { yyval.ttype = finish_enum (yyvsp[-3].ttype, yyvsp[-2].ttype); resume_momentary ((int) yyvsp[-5].itype); check_for_missing_semicolon (yyvsp[-3].ttype); ; break;} -case 380: -#line 2084 "parse.y" +case 378: +#line 2080 "parse.y" { yyval.ttype = finish_enum (start_enum (make_anon_name()), NULL_TREE); check_for_missing_semicolon (yyval.ttype); ; break;} -case 381: -#line 2087 "parse.y" +case 379: +#line 2083 "parse.y" { yyval.ttype = xref_tag (enum_type_node, yyvsp[0].ttype, NULL_TREE, 0); ; break;} -case 382: -#line 2089 "parse.y" +case 380: +#line 2085 "parse.y" { yyval.ttype = xref_tag (enum_type_node, yyvsp[0].ttype, NULL_TREE, 0); ; break;} -case 383: -#line 2093 "parse.y" +case 381: +#line 2089 "parse.y" { int semi; tree id; @@ -5695,8 +5637,8 @@ if (! semi) check_for_missing_semicolon (yyval.ttype); ; break;} -case 384: -#line 2144 "parse.y" +case 382: +#line 2140 "parse.y" { #if 0 /* It's no longer clear what the following error is supposed to @@ -5710,72 +5652,72 @@ #endif ; break;} -case 388: -#line 2166 "parse.y" +case 386: +#line 2162 "parse.y" { if (pedantic) pedwarn ("comma at end of enumerator list"); ; break;} -case 390: -#line 2171 "parse.y" +case 388: +#line 2167 "parse.y" { error ("storage class specifier `%s' not allowed after struct or class", IDENTIFIER_POINTER (yyvsp[0].ttype)); ; break;} -case 391: -#line 2173 "parse.y" +case 389: +#line 2169 "parse.y" { error ("type specifier `%s' not allowed after struct or class", IDENTIFIER_POINTER (yyvsp[0].ttype)); ; break;} -case 392: -#line 2175 "parse.y" +case 390: +#line 2171 "parse.y" { error ("type qualifier `%s' not allowed after struct or class", IDENTIFIER_POINTER (yyvsp[0].ttype)); ; break;} -case 393: -#line 2177 "parse.y" +case 391: +#line 2173 "parse.y" { error ("no body nor ';' separates two class, struct or union declarations"); ; break;} -case 394: -#line 2182 "parse.y" +case 392: +#line 2178 "parse.y" { yyungetc (';', 1); current_aggr = yyval.ttype; yyval.ttype = yyvsp[-1].ttype; if (yyvsp[-3].ttype == ridpointers[(int) RID_TEMPLATE]) instantiate_class_template (yyval.ttype, 2); ; break;} -case 395: -#line 2191 "parse.y" +case 393: +#line 2187 "parse.y" { current_aggr = yyval.ttype; yyval.ttype = yyvsp[0].ttype; ; break;} -case 396: -#line 2193 "parse.y" +case 394: +#line 2189 "parse.y" { current_aggr = yyval.ttype; yyval.ttype = yyvsp[0].ttype; ; break;} -case 397: -#line 2195 "parse.y" +case 395: +#line 2191 "parse.y" { current_aggr = yyval.ttype; yyval.ttype = yyvsp[0].ttype; ; break;} -case 398: -#line 2197 "parse.y" +case 396: +#line 2193 "parse.y" { yyungetc ('{', 1); aggr2: current_aggr = yyval.ttype; yyval.ttype = yyvsp[-1].ttype; overload_template_name (yyval.ttype, 0); ; break;} -case 399: -#line 2203 "parse.y" +case 397: +#line 2199 "parse.y" { yyungetc (':', 1); goto aggr2; ; break;} -case 401: -#line 2209 "parse.y" +case 399: +#line 2205 "parse.y" { current_aggr = yyval.ttype; yyval.ttype = yyvsp[0].ttype; ; break;} -case 402: -#line 2213 "parse.y" +case 400: +#line 2209 "parse.y" { yyval.ttype = xref_tag (current_aggr, yyvsp[0].ttype, NULL_TREE, 1); ; break;} -case 403: -#line 2216 "parse.y" +case 401: +#line 2212 "parse.y" { yyval.ttype = xref_defn_tag (current_aggr, yyvsp[0].ttype, NULL_TREE); ; break;} -case 404: -#line 2221 "parse.y" +case 402: +#line 2217 "parse.y" { if (yyvsp[0].ttype) yyval.ttype = xref_tag (current_aggr, yyvsp[-2].ttype, yyvsp[0].ttype, 1); @@ -5783,8 +5725,8 @@ yyval.ttype = yyvsp[-1].ttype; ; break;} -case 405: -#line 2230 "parse.y" +case 403: +#line 2226 "parse.y" { if (yyvsp[0].ttype) yyval.ttype = xref_defn_tag (current_aggr, yyvsp[-2].ttype, yyvsp[0].ttype); @@ -5792,29 +5734,29 @@ yyval.ttype = yyvsp[-1].ttype; ; break;} -case 406: -#line 2239 "parse.y" +case 404: +#line 2235 "parse.y" { yyval.ttype = xref_tag (yyval.ttype, make_anon_name (), NULL_TREE, 0); yyungetc ('{', 1); ; break;} -case 409: -#line 2247 "parse.y" +case 407: +#line 2243 "parse.y" { yyval.ttype = NULL_TREE; ; break;} -case 410: -#line 2249 "parse.y" +case 408: +#line 2245 "parse.y" { yyungetc(':', 1); yyval.ttype = NULL_TREE; ; break;} -case 411: -#line 2251 "parse.y" +case 409: +#line 2247 "parse.y" { yyval.ttype = yyvsp[0].ttype; ; break;} -case 413: -#line 2257 "parse.y" +case 411: +#line 2253 "parse.y" { yyval.ttype = chainon (yyval.ttype, yyvsp[0].ttype); ; break;} -case 414: -#line 2262 "parse.y" +case 412: +#line 2258 "parse.y" { tree type; do_base_class1: @@ -5842,8 +5784,8 @@ yyval.ttype = build_tree_list ((tree)access_default, yyval.ttype); ; break;} -case 415: -#line 2289 "parse.y" +case 413: +#line 2285 "parse.y" { tree type; do_base_class2: @@ -5873,8 +5815,8 @@ yyval.ttype = build_tree_list ((tree) yyval.ttype, yyvsp[0].ttype); ; break;} -case 417: -#line 2322 "parse.y" +case 415: +#line 2318 "parse.y" { if (current_aggr == signature_type_node) { @@ -5897,8 +5839,8 @@ } ; break;} -case 418: -#line 2344 "parse.y" +case 416: +#line 2340 "parse.y" { if (current_aggr == signature_type_node) { @@ -5921,14 +5863,14 @@ } ; break;} -case 420: -#line 2370 "parse.y" +case 418: +#line 2366 "parse.y" { if (yyval.ttype != ridpointers[(int)RID_VIRTUAL]) sorry ("non-virtual access"); yyval.itype = access_default_virtual; ; break;} -case 421: -#line 2374 "parse.y" +case 419: +#line 2370 "parse.y" { int err = 0; if (yyvsp[0].itype == access_protected) { @@ -5955,8 +5897,8 @@ } ; break;} -case 422: -#line 2400 "parse.y" +case 420: +#line 2396 "parse.y" { if (yyvsp[0].ttype != ridpointers[(int)RID_VIRTUAL]) sorry ("non-virtual access"); if (yyval.itype == access_public) @@ -5964,8 +5906,8 @@ else if (yyval.itype == access_private) yyval.itype = access_private_virtual; ; break;} -case 423: -#line 2409 "parse.y" +case 421: +#line 2405 "parse.y" { tree t = yyvsp[-1].ttype; push_obstacks_nochange (); end_temporary_allocation (); @@ -6026,12 +5968,12 @@ #endif ; break;} -case 424: -#line 2472 "parse.y" +case 422: +#line 2468 "parse.y" { yyval.ttype = NULL_TREE; ; break;} -case 425: -#line 2474 "parse.y" +case 423: +#line 2470 "parse.y" { if (current_aggr == signature_type_node) yyval.ttype = build_tree_list ((tree) access_public, yyval.ttype); @@ -6039,8 +5981,8 @@ yyval.ttype = build_tree_list ((tree) access_default, yyval.ttype); ; break;} -case 426: -#line 2481 "parse.y" +case 424: +#line 2477 "parse.y" { tree visspec = (tree) yyvsp[-2].itype; @@ -6052,20 +5994,20 @@ yyval.ttype = chainon (yyval.ttype, build_tree_list (visspec, yyvsp[0].ttype)); ; break;} -case 427: -#line 2492 "parse.y" +case 425: +#line 2488 "parse.y" { if (current_aggr == signature_type_node) error ("access specifier not allowed in signature"); ; break;} -case 428: -#line 2502 "parse.y" +case 426: +#line 2498 "parse.y" { if (yyval.ttype == void_type_node) yyval.ttype = NULL_TREE; ; break;} -case 429: -#line 2505 "parse.y" +case 427: +#line 2501 "parse.y" { /* In pushdecl, we created a reverse list of names in this binding level. Make sure that the chain of what we're trying to add isn't the item itself @@ -6079,64 +6021,64 @@ } ; break;} -case 432: -#line 2523 "parse.y" +case 430: +#line 2519 "parse.y" { error ("missing ';' before right brace"); yyungetc ('}', 0); ; break;} -case 433: -#line 2528 "parse.y" +case 431: +#line 2524 "parse.y" { yyval.ttype = finish_method (yyval.ttype); ; break;} -case 434: -#line 2530 "parse.y" +case 432: +#line 2526 "parse.y" { yyval.ttype = finish_method (yyval.ttype); ; break;} -case 435: -#line 2538 "parse.y" +case 433: +#line 2534 "parse.y" { yyval.ttype = grok_x_components (yyval.ttype, yyvsp[0].ttype); ; break;} -case 436: -#line 2542 "parse.y" +case 434: +#line 2538 "parse.y" { yyval.ttype = grok_x_components (yyval.ttype, yyvsp[0].ttype); ; break;} -case 437: -#line 2546 "parse.y" +case 435: +#line 2542 "parse.y" { yyval.ttype = grokfield (yyval.ttype, NULL_TREE, yyvsp[-2].ttype, NULL_TREE, yyvsp[-1].ttype); cplus_decl_attributes (yyval.ttype, yyvsp[0].ttype); ; break;} -case 438: -#line 2549 "parse.y" +case 436: +#line 2545 "parse.y" { yyval.ttype = grokbitfield (NULL_TREE, NULL_TREE, yyvsp[0].ttype); ; break;} -case 439: -#line 2551 "parse.y" +case 437: +#line 2547 "parse.y" { yyval.ttype = NULL_TREE; ; break;} -case 440: -#line 2562 "parse.y" +case 438: +#line 2558 "parse.y" { yyval.ttype = build_parse_node (CALL_EXPR, TREE_VALUE (yyvsp[-4].ttype), yyvsp[-2].ttype, yyvsp[0].ttype); yyval.ttype = grokfield (yyval.ttype, TREE_CHAIN (yyvsp[-4].ttype), NULL_TREE, NULL_TREE, NULL_TREE); ; break;} -case 441: -#line 2567 "parse.y" +case 439: +#line 2563 "parse.y" { yyval.ttype = build_parse_node (CALL_EXPR, TREE_VALUE (yyvsp[-2].ttype), empty_parms (), yyvsp[0].ttype); yyval.ttype = grokfield (yyval.ttype, TREE_CHAIN (yyvsp[-2].ttype), NULL_TREE, NULL_TREE, NULL_TREE); ; break;} -case 442: -#line 2576 "parse.y" +case 440: +#line 2572 "parse.y" { yyval.ttype = NULL_TREE; ; break;} -case 444: -#line 2579 "parse.y" +case 442: +#line 2575 "parse.y" { /* In this context, void_type_node encodes friends. They have been recorded elsewhere. */ @@ -6146,12 +6088,12 @@ yyval.ttype = chainon (yyval.ttype, yyvsp[0].ttype); ; break;} -case 445: -#line 2591 "parse.y" +case 443: +#line 2587 "parse.y" { yyval.ttype = NULL_TREE; ; break;} -case 447: -#line 2594 "parse.y" +case 445: +#line 2590 "parse.y" { /* In this context, void_type_node encodes friends. They have been recorded elsewhere. */ @@ -6161,105 +6103,105 @@ yyval.ttype = chainon (yyval.ttype, yyvsp[0].ttype); ; break;} -case 452: -#line 2616 "parse.y" +case 450: +#line 2612 "parse.y" { current_declspecs = yyvsp[-4].ttype; yyval.ttype = grokfield (yyval.ttype, current_declspecs, yyvsp[-2].ttype, NULL_TREE, yyvsp[-1].ttype); cplus_decl_attributes (yyval.ttype, yyvsp[0].ttype); ; break;} -case 453: -#line 2620 "parse.y" +case 451: +#line 2616 "parse.y" { current_declspecs = yyvsp[-6].ttype; yyval.ttype = grokfield (yyval.ttype, current_declspecs, yyvsp[-4].ttype, yyvsp[0].ttype, yyvsp[-3].ttype); cplus_decl_attributes (yyval.ttype, yyvsp[-2].ttype); ; break;} -case 454: -#line 2624 "parse.y" +case 452: +#line 2620 "parse.y" { current_declspecs = yyvsp[-4].ttype; yyval.ttype = grokbitfield (yyval.ttype, current_declspecs, yyvsp[-1].ttype); cplus_decl_attributes (yyval.ttype, yyvsp[0].ttype); ; break;} -case 455: -#line 2631 "parse.y" +case 453: +#line 2627 "parse.y" { current_declspecs = yyvsp[-4].ttype; yyval.ttype = grokfield (yyval.ttype, current_declspecs, yyvsp[-2].ttype, NULL_TREE, yyvsp[-1].ttype); cplus_decl_attributes (yyval.ttype, yyvsp[0].ttype); ; break;} -case 456: -#line 2635 "parse.y" +case 454: +#line 2631 "parse.y" { current_declspecs = yyvsp[-6].ttype; yyval.ttype = grokfield (yyval.ttype, current_declspecs, yyvsp[-4].ttype, yyvsp[0].ttype, yyvsp[-3].ttype); cplus_decl_attributes (yyval.ttype, yyvsp[-2].ttype); ; break;} -case 457: -#line 2639 "parse.y" +case 455: +#line 2635 "parse.y" { current_declspecs = yyvsp[-4].ttype; yyval.ttype = grokbitfield (yyval.ttype, current_declspecs, yyvsp[-1].ttype); cplus_decl_attributes (yyval.ttype, yyvsp[0].ttype); ; break;} -case 458: -#line 2643 "parse.y" +case 456: +#line 2639 "parse.y" { current_declspecs = yyvsp[-3].ttype; yyval.ttype = grokbitfield (NULL_TREE, current_declspecs, yyvsp[-1].ttype); cplus_decl_attributes (yyval.ttype, yyvsp[0].ttype); ; break;} -case 459: -#line 2650 "parse.y" +case 457: +#line 2646 "parse.y" { yyval.ttype = grokfield (yyval.ttype, current_declspecs, yyvsp[-2].ttype, NULL_TREE, yyvsp[-1].ttype); cplus_decl_attributes (yyval.ttype, yyvsp[0].ttype); ; break;} -case 460: -#line 2653 "parse.y" +case 458: +#line 2649 "parse.y" { yyval.ttype = grokfield (yyval.ttype, current_declspecs, yyvsp[-4].ttype, yyvsp[0].ttype, yyvsp[-3].ttype); cplus_decl_attributes (yyval.ttype, yyvsp[-2].ttype); ; break;} -case 461: -#line 2656 "parse.y" +case 459: +#line 2652 "parse.y" { yyval.ttype = grokbitfield (yyval.ttype, current_declspecs, yyvsp[-1].ttype); cplus_decl_attributes (yyval.ttype, yyvsp[0].ttype); ; break;} -case 462: -#line 2662 "parse.y" +case 460: +#line 2658 "parse.y" { yyval.ttype = grokfield (yyval.ttype, current_declspecs, yyvsp[-2].ttype, NULL_TREE, yyvsp[-1].ttype); cplus_decl_attributes (yyval.ttype, yyvsp[0].ttype); ; break;} -case 463: -#line 2665 "parse.y" +case 461: +#line 2661 "parse.y" { yyval.ttype = grokfield (yyval.ttype, current_declspecs, yyvsp[-4].ttype, yyvsp[0].ttype, yyvsp[-3].ttype); cplus_decl_attributes (yyval.ttype, yyvsp[-2].ttype); ; break;} -case 464: -#line 2668 "parse.y" +case 462: +#line 2664 "parse.y" { yyval.ttype = grokbitfield (yyval.ttype, current_declspecs, yyvsp[-1].ttype); cplus_decl_attributes (yyval.ttype, yyvsp[0].ttype); ; break;} -case 465: -#line 2671 "parse.y" +case 463: +#line 2667 "parse.y" { yyval.ttype = grokbitfield (NULL_TREE, current_declspecs, yyvsp[-1].ttype); cplus_decl_attributes (yyval.ttype, yyvsp[0].ttype); ; break;} -case 467: -#line 2682 "parse.y" +case 465: +#line 2678 "parse.y" { TREE_CHAIN (yyvsp[0].ttype) = yyval.ttype; yyval.ttype = yyvsp[0].ttype; ; break;} -case 468: -#line 2687 "parse.y" +case 466: +#line 2683 "parse.y" { yyval.ttype = build_enumerator (yyval.ttype, NULL_TREE); ; break;} -case 469: -#line 2689 "parse.y" +case 467: +#line 2685 "parse.y" { yyval.ttype = build_enumerator (yyval.ttype, yyvsp[0].ttype); ; break;} -case 470: -#line 2695 "parse.y" +case 468: +#line 2691 "parse.y" { yyval.ttype = build_decl_list (yyval.ttype, yyvsp[0].ttype); ; break;} -case 471: -#line 2697 "parse.y" +case 469: +#line 2693 "parse.y" { yyval.ttype = build_decl_list (yyval.ttype, NULL_TREE); ; break;} -case 472: -#line 2701 "parse.y" +case 470: +#line 2697 "parse.y" { if (flag_ansi) pedwarn ("ANSI C++ forbids array dimensions with parenthesized type in new"); @@ -6267,54 +6209,54 @@ yyval.ttype = build_decl_list (TREE_PURPOSE (yyvsp[-4].ttype), yyval.ttype); ; break;} -case 473: -#line 2711 "parse.y" +case 471: +#line 2707 "parse.y" { yyval.ttype = NULL_TREE; ; break;} +case 472: +#line 2709 "parse.y" +{ yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[0].ttype, yyval.ttype); ; + break;} +case 473: +#line 2714 "parse.y" +{ yyval.ttype = IDENTIFIER_AS_LIST (yyval.ttype); ; + break;} case 474: -#line 2713 "parse.y" +#line 2716 "parse.y" { yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[0].ttype, yyval.ttype); ; break;} case 475: -#line 2718 "parse.y" -{ yyval.ttype = IDENTIFIER_AS_LIST (yyval.ttype); ; +#line 2724 "parse.y" +{ yyval.itype = suspend_momentary (); ; break;} case 476: -#line 2720 "parse.y" -{ yyval.ttype = decl_tree_cons (NULL_TREE, yyvsp[0].ttype, yyval.ttype); ; +#line 2725 "parse.y" +{ resume_momentary ((int) yyvsp[-1].itype); yyval.ttype = yyvsp[0].ttype; ; break;} case 477: -#line 2728 "parse.y" -{ yyval.itype = suspend_momentary (); ; +#line 2732 "parse.y" +{ yyval.ttype = make_pointer_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ; break;} case 478: -#line 2729 "parse.y" -{ resume_momentary ((int) yyvsp[-1].itype); yyval.ttype = yyvsp[0].ttype; ; +#line 2734 "parse.y" +{ yyval.ttype = make_reference_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ; break;} case 479: #line 2736 "parse.y" -{ yyval.ttype = make_pointer_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ; +{ yyval.ttype = make_pointer_declarator (NULL_TREE, yyvsp[0].ttype); ; break;} case 480: #line 2738 "parse.y" -{ yyval.ttype = make_reference_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ; +{ yyval.ttype = make_reference_declarator (NULL_TREE, yyvsp[0].ttype); ; break;} case 481: #line 2740 "parse.y" -{ yyval.ttype = make_pointer_declarator (NULL_TREE, yyvsp[0].ttype); ; - break;} -case 482: -#line 2742 "parse.y" -{ yyval.ttype = make_reference_declarator (NULL_TREE, yyvsp[0].ttype); ; - break;} -case 483: -#line 2744 "parse.y" { tree arg = make_pointer_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); yyval.ttype = build_parse_node (SCOPE_REF, yyvsp[-2].ttype, arg); ; break;} -case 485: -#line 2752 "parse.y" +case 483: +#line 2748 "parse.y" { /* Remember that this name has been used in the class definition, as per [class.scope0] */ @@ -6328,277 +6270,285 @@ } ; break;} -case 487: -#line 2769 "parse.y" +case 485: +#line 2765 "parse.y" { yyval.ttype = yyvsp[0].ttype; ; break;} +case 486: +#line 2770 "parse.y" +{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, yyvsp[-2].ttype, yyvsp[0].ttype); ; + break;} +case 487: +#line 2772 "parse.y" +{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, yyvsp[-2].ttype, yyvsp[0].ttype); ; + break;} case 488: #line 2774 "parse.y" -{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, yyvsp[-2].ttype, yyvsp[0].ttype); ; +{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, empty_parms (), yyvsp[0].ttype); ; break;} case 489: #line 2776 "parse.y" -{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, yyvsp[-2].ttype, yyvsp[0].ttype); ; +{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, NULL_TREE, NULL_TREE); ; break;} case 490: #line 2778 "parse.y" -{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, empty_parms (), yyvsp[0].ttype); ; +{ yyval.ttype = build_parse_node (ARRAY_REF, yyval.ttype, yyvsp[-1].ttype); ; break;} case 491: #line 2780 "parse.y" -{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, NULL_TREE, NULL_TREE); ; +{ yyval.ttype = build_parse_node (ARRAY_REF, yyval.ttype, NULL_TREE); ; break;} case 492: #line 2782 "parse.y" -{ yyval.ttype = build_parse_node (ARRAY_REF, yyval.ttype, yyvsp[-1].ttype); ; +{ yyval.ttype = yyvsp[-1].ttype; ; break;} case 493: #line 2784 "parse.y" -{ yyval.ttype = build_parse_node (ARRAY_REF, yyval.ttype, NULL_TREE); ; - break;} -case 494: -#line 2786 "parse.y" -{ yyval.ttype = yyvsp[-1].ttype; ; - break;} -case 495: -#line 2788 "parse.y" { push_nested_class (TREE_TYPE (yyval.ttype), 3); yyval.ttype = build_parse_node (SCOPE_REF, yyval.ttype, yyvsp[0].ttype); TREE_COMPLEXITY (yyval.ttype) = current_class_depth; ; break;} -case 497: -#line 2799 "parse.y" +case 495: +#line 2795 "parse.y" { yyval.ttype = make_pointer_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ; break;} -case 498: -#line 2801 "parse.y" +case 496: +#line 2797 "parse.y" { yyval.ttype = make_reference_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ; break;} -case 499: -#line 2803 "parse.y" +case 497: +#line 2799 "parse.y" { yyval.ttype = make_pointer_declarator (NULL_TREE, yyvsp[0].ttype); ; break;} -case 500: -#line 2805 "parse.y" +case 498: +#line 2801 "parse.y" { yyval.ttype = make_reference_declarator (NULL_TREE, yyvsp[0].ttype); ; break;} -case 501: -#line 2807 "parse.y" +case 499: +#line 2803 "parse.y" { tree arg = make_pointer_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); yyval.ttype = build_parse_node (SCOPE_REF, yyvsp[-2].ttype, arg); ; break;} -case 503: -#line 2815 "parse.y" +case 501: +#line 2811 "parse.y" { yyval.ttype = make_pointer_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ; break;} -case 504: -#line 2817 "parse.y" +case 502: +#line 2813 "parse.y" { yyval.ttype = make_reference_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ; break;} -case 505: -#line 2819 "parse.y" +case 503: +#line 2815 "parse.y" { yyval.ttype = make_pointer_declarator (NULL_TREE, yyvsp[0].ttype); ; break;} -case 506: -#line 2821 "parse.y" +case 504: +#line 2817 "parse.y" { yyval.ttype = make_reference_declarator (NULL_TREE, yyvsp[0].ttype); ; break;} -case 507: -#line 2823 "parse.y" +case 505: +#line 2819 "parse.y" { tree arg = make_pointer_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); yyval.ttype = build_parse_node (SCOPE_REF, yyvsp[-2].ttype, arg); ; break;} +case 507: +#line 2827 "parse.y" +{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, yyvsp[-2].ttype, yyvsp[0].ttype); ; + break;} +case 508: +#line 2829 "parse.y" +{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, yyvsp[-2].ttype, yyvsp[0].ttype); ; + break;} case 509: #line 2831 "parse.y" -{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, yyvsp[-2].ttype, yyvsp[0].ttype); ; +{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, empty_parms (), yyvsp[0].ttype); ; break;} case 510: #line 2833 "parse.y" -{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, yyvsp[-2].ttype, yyvsp[0].ttype); ; +{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, NULL_TREE, NULL_TREE); ; break;} case 511: #line 2835 "parse.y" -{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, empty_parms (), yyvsp[0].ttype); ; +{ yyval.ttype = finish_decl_parsing (yyvsp[-1].ttype); ; break;} case 512: #line 2837 "parse.y" -{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, NULL_TREE, NULL_TREE); ; +{ yyval.ttype = yyvsp[-1].ttype; ; break;} case 513: #line 2839 "parse.y" -{ yyval.ttype = yyvsp[-1].ttype; ; +{ yyval.ttype = build_parse_node (ARRAY_REF, yyval.ttype, yyvsp[-1].ttype); ; break;} case 514: #line 2841 "parse.y" -{ yyval.ttype = build_parse_node (ARRAY_REF, yyval.ttype, yyvsp[-1].ttype); ; - break;} -case 515: -#line 2843 "parse.y" { yyval.ttype = build_parse_node (ARRAY_REF, yyval.ttype, NULL_TREE); ; break;} -case 516: -#line 2848 "parse.y" +case 515: +#line 2846 "parse.y" { got_scope = NULL_TREE; yyval.ttype = build_parse_node (SCOPE_REF, yyval.ttype, yyvsp[0].ttype); ; break;} -case 517: -#line 2854 "parse.y" +case 516: +#line 2852 "parse.y" { got_scope = NULL_TREE; yyval.ttype = build_parse_node (SCOPE_REF, yyval.ttype, yyvsp[0].ttype); ; break;} -case 519: -#line 2861 "parse.y" +case 518: +#line 2859 "parse.y" { yyval.ttype = yyvsp[0].ttype; ; break;} +case 519: +#line 2864 "parse.y" +{ yyval.ttype = build_functional_cast (yyval.ttype, yyvsp[-1].ttype); ; + break;} case 520: #line 2866 "parse.y" -{ yyval.ttype = build_functional_cast (yyval.ttype, yyvsp[-1].ttype); ; +{ yyval.ttype = reparse_decl_as_expr (yyval.ttype, yyvsp[-1].ttype); ; break;} case 521: #line 2868 "parse.y" -{ yyval.ttype = reparse_decl_as_expr (yyval.ttype, yyvsp[-1].ttype); ; - break;} -case 522: -#line 2870 "parse.y" { yyval.ttype = reparse_absdcl_as_expr (yyval.ttype, yyvsp[0].ttype); ; break;} -case 526: -#line 2881 "parse.y" +case 525: +#line 2879 "parse.y" { yyval.ttype = yyvsp[0].ttype; ; break;} +case 526: +#line 2886 "parse.y" +{ got_scope = TREE_TYPE (yyval.ttype); ; + break;} case 527: #line 2888 "parse.y" { got_scope = TREE_TYPE (yyval.ttype); ; break;} -case 528: -#line 2890 "parse.y" -{ got_scope = TREE_TYPE (yyval.ttype); ; +case 529: +#line 2904 "parse.y" +{ yyval.ttype = yyvsp[0].ttype; ; break;} -case 530: -#line 2906 "parse.y" +case 531: +#line 2910 "parse.y" { yyval.ttype = yyvsp[0].ttype; ; break;} case 532: -#line 2912 "parse.y" -{ yyval.ttype = yyvsp[0].ttype; ; +#line 2915 "parse.y" +{ got_scope = NULL_TREE; ; break;} case 533: #line 2917 "parse.y" -{ got_scope = NULL_TREE; ; +{ yyval.ttype = yyvsp[-1].ttype; got_scope = NULL_TREE; ; break;} case 534: -#line 2919 "parse.y" -{ yyval.ttype = yyvsp[-1].ttype; got_scope = NULL_TREE; ; +#line 2924 "parse.y" +{ got_scope = void_type_node; ; break;} case 535: -#line 2926 "parse.y" -{ got_scope = void_type_node; ; +#line 2930 "parse.y" +{ yyval.ttype = make_pointer_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ; break;} case 536: #line 2932 "parse.y" -{ yyval.ttype = make_pointer_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ; +{ yyval.ttype = make_pointer_declarator (yyvsp[0].ttype, NULL_TREE); ; break;} case 537: #line 2934 "parse.y" -{ yyval.ttype = make_pointer_declarator (yyvsp[0].ttype, NULL_TREE); ; +{ yyval.ttype = make_reference_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ; break;} case 538: #line 2936 "parse.y" -{ yyval.ttype = make_reference_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ; +{ yyval.ttype = make_reference_declarator (yyvsp[0].ttype, NULL_TREE); ; break;} case 539: #line 2938 "parse.y" -{ yyval.ttype = make_reference_declarator (yyvsp[0].ttype, NULL_TREE); ; - break;} -case 540: -#line 2940 "parse.y" { tree arg = make_pointer_declarator (yyvsp[0].ttype, NULL_TREE); yyval.ttype = build_parse_node (SCOPE_REF, yyvsp[-1].ttype, arg); ; break;} -case 541: -#line 2944 "parse.y" +case 540: +#line 2942 "parse.y" { tree arg = make_pointer_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); yyval.ttype = build_parse_node (SCOPE_REF, yyvsp[-2].ttype, arg); ; break;} +case 542: +#line 2951 "parse.y" +{ yyval.ttype = build_parse_node (ARRAY_REF, NULL_TREE, yyvsp[-1].ttype); ; + break;} case 543: #line 2953 "parse.y" -{ yyval.ttype = build_parse_node (ARRAY_REF, NULL_TREE, yyvsp[-1].ttype); ; +{ yyval.ttype = build_parse_node (ARRAY_REF, yyval.ttype, yyvsp[-1].ttype); ; break;} case 544: -#line 2955 "parse.y" -{ yyval.ttype = build_parse_node (ARRAY_REF, yyval.ttype, yyvsp[-1].ttype); ; +#line 2959 "parse.y" +{ yyval.ttype = make_pointer_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ; break;} case 545: #line 2961 "parse.y" -{ yyval.ttype = make_pointer_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ; +{ yyval.ttype = make_pointer_declarator (NULL_TREE, yyvsp[0].ttype); ; break;} case 546: #line 2963 "parse.y" -{ yyval.ttype = make_pointer_declarator (NULL_TREE, yyvsp[0].ttype); ; +{ yyval.ttype = make_pointer_declarator (yyvsp[0].ttype, NULL_TREE); ; break;} case 547: #line 2965 "parse.y" -{ yyval.ttype = make_pointer_declarator (yyvsp[0].ttype, NULL_TREE); ; +{ yyval.ttype = make_pointer_declarator (NULL_TREE, NULL_TREE); ; break;} case 548: #line 2967 "parse.y" -{ yyval.ttype = make_pointer_declarator (NULL_TREE, NULL_TREE); ; +{ yyval.ttype = make_reference_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ; break;} case 549: #line 2969 "parse.y" -{ yyval.ttype = make_reference_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ; +{ yyval.ttype = make_reference_declarator (NULL_TREE, yyvsp[0].ttype); ; break;} case 550: #line 2971 "parse.y" -{ yyval.ttype = make_reference_declarator (NULL_TREE, yyvsp[0].ttype); ; +{ yyval.ttype = make_reference_declarator (yyvsp[0].ttype, NULL_TREE); ; break;} case 551: #line 2973 "parse.y" -{ yyval.ttype = make_reference_declarator (yyvsp[0].ttype, NULL_TREE); ; +{ yyval.ttype = make_reference_declarator (NULL_TREE, NULL_TREE); ; break;} case 552: #line 2975 "parse.y" -{ yyval.ttype = make_reference_declarator (NULL_TREE, NULL_TREE); ; - break;} -case 553: -#line 2977 "parse.y" { tree arg = make_pointer_declarator (yyvsp[0].ttype, NULL_TREE); yyval.ttype = build_parse_node (SCOPE_REF, yyvsp[-1].ttype, arg); ; break;} -case 554: -#line 2981 "parse.y" +case 553: +#line 2979 "parse.y" { tree arg = make_pointer_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); yyval.ttype = build_parse_node (SCOPE_REF, yyvsp[-2].ttype, arg); ; break;} -case 556: -#line 2990 "parse.y" +case 555: +#line 2988 "parse.y" { yyval.ttype = yyvsp[-1].ttype; ; break;} +case 557: +#line 2992 "parse.y" +{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, yyvsp[-2].ttype, yyvsp[0].ttype); ; + break;} case 558: #line 2994 "parse.y" -{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, yyvsp[-2].ttype, yyvsp[0].ttype); ; +{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, empty_parms (), yyvsp[0].ttype); ; break;} case 559: #line 2996 "parse.y" -{ yyval.ttype = build_parse_node (CALL_EXPR, yyval.ttype, empty_parms (), yyvsp[0].ttype); ; +{ yyval.ttype = build_parse_node (ARRAY_REF, yyval.ttype, yyvsp[-1].ttype); ; break;} case 560: #line 2998 "parse.y" -{ yyval.ttype = build_parse_node (ARRAY_REF, yyval.ttype, yyvsp[-1].ttype); ; +{ yyval.ttype = build_parse_node (ARRAY_REF, yyval.ttype, NULL_TREE); ; break;} case 561: #line 3000 "parse.y" -{ yyval.ttype = build_parse_node (ARRAY_REF, yyval.ttype, NULL_TREE); ; +{ yyval.ttype = build_parse_node (CALL_EXPR, NULL_TREE, yyvsp[-2].ttype, yyvsp[0].ttype); ; break;} case 562: #line 3002 "parse.y" -{ yyval.ttype = build_parse_node (CALL_EXPR, NULL_TREE, yyvsp[-2].ttype, yyvsp[0].ttype); ; +{ TREE_OPERAND (yyval.ttype, 2) = yyvsp[0].ttype; ; break;} case 563: #line 3004 "parse.y" @@ -6606,31 +6556,27 @@ break;} case 564: #line 3006 "parse.y" -{ TREE_OPERAND (yyval.ttype, 2) = yyvsp[0].ttype; ; +{ yyval.ttype = build_parse_node (ARRAY_REF, NULL_TREE, yyvsp[-1].ttype); ; break;} case 565: #line 3008 "parse.y" -{ yyval.ttype = build_parse_node (ARRAY_REF, NULL_TREE, yyvsp[-1].ttype); ; - break;} -case 566: -#line 3010 "parse.y" { yyval.ttype = build_parse_node (ARRAY_REF, NULL_TREE, NULL_TREE); ; break;} -case 572: -#line 3032 "parse.y" +case 571: +#line 3030 "parse.y" { emit_line_note (input_filename, lineno); pushlevel (0); clear_last_expr (); push_momentary (); expand_start_bindings (0); ; break;} -case 574: -#line 3044 "parse.y" +case 573: +#line 3042 "parse.y" { if (flag_ansi) pedwarn ("ANSI C++ forbids label declarations"); ; break;} -case 577: -#line 3055 "parse.y" +case 576: +#line 3053 "parse.y" { tree link; for (link = yyvsp[-1].ttype; link; link = TREE_CHAIN (link)) { @@ -6640,63 +6586,63 @@ } ; break;} -case 578: -#line 3069 "parse.y" +case 577: +#line 3067 "parse.y" {; break;} -case 580: -#line 3074 "parse.y" +case 579: +#line 3072 "parse.y" { expand_end_bindings (getdecls (), kept_level_p(), 1); yyval.ttype = poplevel (kept_level_p (), 1, 0); pop_momentary (); ; break;} -case 581: -#line 3078 "parse.y" +case 580: +#line 3076 "parse.y" { expand_end_bindings (getdecls (), kept_level_p(), 1); yyval.ttype = poplevel (kept_level_p (), 1, 0); pop_momentary (); ; break;} -case 582: -#line 3082 "parse.y" +case 581: +#line 3080 "parse.y" { expand_end_bindings (getdecls (), kept_level_p(), 1); yyval.ttype = poplevel (kept_level_p (), 0, 0); pop_momentary (); ; break;} -case 583: -#line 3086 "parse.y" +case 582: +#line 3084 "parse.y" { expand_end_bindings (getdecls (), kept_level_p(), 1); yyval.ttype = poplevel (kept_level_p (), 0, 0); pop_momentary (); ; break;} -case 584: -#line 3093 "parse.y" +case 583: +#line 3091 "parse.y" { cond_stmt_keyword = "if"; ; break;} -case 585: -#line 3095 "parse.y" +case 584: +#line 3093 "parse.y" { emit_line_note (input_filename, lineno); expand_start_cond (yyvsp[0].ttype, 0); ; break;} -case 587: -#line 3102 "parse.y" +case 586: +#line 3100 "parse.y" { finish_stmt (); ; break;} -case 588: -#line 3104 "parse.y" +case 587: +#line 3102 "parse.y" { expand_end_bindings (getdecls (), kept_level_p (), 1); yyval.ttype = poplevel (kept_level_p (), 1, 0); pop_momentary (); ; break;} -case 589: -#line 3111 "parse.y" +case 588: +#line 3109 "parse.y" +{ finish_stmt (); ; + break;} +case 590: +#line 3115 "parse.y" { finish_stmt (); ; break;} case 591: #line 3117 "parse.y" -{ finish_stmt (); ; - break;} -case 592: -#line 3119 "parse.y" { tree expr = yyvsp[-1].ttype; emit_line_note (input_filename, lineno); @@ -6710,82 +6656,82 @@ clear_momentary (); finish_stmt (); ; break;} -case 593: -#line 3132 "parse.y" +case 592: +#line 3130 "parse.y" { expand_start_else (); ; break;} -case 594: -#line 3134 "parse.y" +case 593: +#line 3132 "parse.y" { expand_end_cond (); expand_end_bindings (getdecls (), kept_level_p (), 1); poplevel (kept_level_p (), 1, 0); pop_momentary (); finish_stmt (); ; break;} -case 595: -#line 3140 "parse.y" +case 594: +#line 3138 "parse.y" { expand_end_cond (); expand_end_bindings (getdecls (), kept_level_p (), 1); poplevel (kept_level_p (), 1, 0); pop_momentary (); finish_stmt (); ; break;} -case 596: -#line 3146 "parse.y" +case 595: +#line 3144 "parse.y" { emit_nop (); emit_line_note (input_filename, lineno); expand_start_loop (1); cond_stmt_keyword = "while"; ; break;} +case 596: +#line 3149 "parse.y" +{ expand_exit_loop_if_false (0, yyvsp[0].ttype); ; + break;} case 597: #line 3151 "parse.y" -{ expand_exit_loop_if_false (0, yyvsp[0].ttype); ; - break;} -case 598: -#line 3153 "parse.y" { expand_end_bindings (getdecls (), kept_level_p (), 1); poplevel (kept_level_p (), 1, 0); pop_momentary (); expand_end_loop (); finish_stmt (); ; break;} -case 599: -#line 3159 "parse.y" +case 598: +#line 3157 "parse.y" { emit_nop (); emit_line_note (input_filename, lineno); expand_start_loop_continue_elsewhere (1); ; break;} -case 600: -#line 3163 "parse.y" +case 599: +#line 3161 "parse.y" { expand_loop_continue_here (); cond_stmt_keyword = "do"; ; break;} -case 601: -#line 3166 "parse.y" +case 600: +#line 3164 "parse.y" { emit_line_note (input_filename, lineno); expand_exit_loop_if_false (0, yyvsp[-1].ttype); expand_end_loop (); clear_momentary (); finish_stmt (); ; break;} -case 602: -#line 3172 "parse.y" +case 601: +#line 3170 "parse.y" { emit_nop (); emit_line_note (input_filename, lineno); if (yyvsp[0].ttype) cplus_expand_expr_stmt (yyvsp[0].ttype); expand_start_loop_continue_elsewhere (1); ; break;} -case 603: -#line 3177 "parse.y" +case 602: +#line 3175 "parse.y" { emit_line_note (input_filename, lineno); if (yyvsp[-1].ttype) expand_exit_loop_if_false (0, yyvsp[-1].ttype); ; break;} -case 604: -#line 3182 "parse.y" +case 603: +#line 3180 "parse.y" { push_momentary (); ; break;} -case 605: -#line 3184 "parse.y" +case 604: +#line 3182 "parse.y" { emit_line_note (input_filename, lineno); expand_end_bindings (getdecls (), kept_level_p (), 1); poplevel (kept_level_p (), 1, 0); @@ -6796,24 +6742,24 @@ expand_end_loop (); finish_stmt (); ; break;} -case 606: -#line 3194 "parse.y" +case 605: +#line 3192 "parse.y" { emit_nop (); emit_line_note (input_filename, lineno); expand_start_loop_continue_elsewhere (1); ; break;} -case 607: -#line 3198 "parse.y" +case 606: +#line 3196 "parse.y" { emit_line_note (input_filename, lineno); if (yyvsp[-1].ttype) expand_exit_loop_if_false (0, yyvsp[-1].ttype); ; break;} -case 608: -#line 3203 "parse.y" +case 607: +#line 3201 "parse.y" { push_momentary (); yyvsp[0].itype = lineno; ; break;} -case 609: -#line 3206 "parse.y" +case 608: +#line 3204 "parse.y" { emit_line_note (input_filename, (int) yyvsp[-2].itype); expand_end_bindings (getdecls (), kept_level_p (), 1); poplevel (kept_level_p (), 1, 0); @@ -6825,16 +6771,16 @@ finish_stmt (); ; break;} -case 610: -#line 3217 "parse.y" +case 609: +#line 3215 "parse.y" { emit_line_note (input_filename, lineno); c_expand_start_case (yyvsp[-1].ttype); /* Don't let the tree nodes for $4 be discarded by clear_momentary during the parsing of the next stmt. */ push_momentary (); ; break;} -case 611: -#line 3223 "parse.y" +case 610: +#line 3221 "parse.y" { expand_end_case (yyvsp[-3].ttype); pop_momentary (); expand_end_bindings (getdecls (), kept_level_p (), 1); @@ -6842,8 +6788,8 @@ pop_momentary (); finish_stmt (); ; break;} -case 612: -#line 3230 "parse.y" +case 611: +#line 3228 "parse.y" { register tree value = check_cp_case_value (yyvsp[-1].ttype); register tree label = build_decl (LABEL_DECL, NULL_TREE, NULL_TREE); @@ -6868,8 +6814,8 @@ define_case_label (label); ; break;} -case 614: -#line 3255 "parse.y" +case 613: +#line 3253 "parse.y" { register tree value1 = check_cp_case_value (yyvsp[-3].ttype); register tree value2 = check_cp_case_value (yyvsp[-1].ttype); register tree label @@ -6901,8 +6847,8 @@ define_case_label (label); ; break;} -case 616: -#line 3287 "parse.y" +case 615: +#line 3285 "parse.y" { tree duplicate; register tree label @@ -6918,40 +6864,40 @@ define_case_label (NULL_TREE); ; break;} -case 618: -#line 3303 "parse.y" +case 617: +#line 3301 "parse.y" { emit_line_note (input_filename, lineno); if ( ! expand_exit_something ()) error ("break statement not within loop or switch"); ; break;} -case 619: -#line 3307 "parse.y" +case 618: +#line 3305 "parse.y" { emit_line_note (input_filename, lineno); if (! expand_continue_loop (0)) error ("continue statement not within a loop"); ; break;} -case 620: -#line 3311 "parse.y" +case 619: +#line 3309 "parse.y" { emit_line_note (input_filename, lineno); c_expand_return (NULL_TREE); ; break;} -case 621: -#line 3314 "parse.y" +case 620: +#line 3312 "parse.y" { emit_line_note (input_filename, lineno); c_expand_return (yyvsp[-1].ttype); finish_stmt (); ; break;} -case 622: -#line 3319 "parse.y" +case 621: +#line 3317 "parse.y" { if (TREE_CHAIN (yyvsp[-2].ttype)) yyvsp[-2].ttype = combine_strings (yyvsp[-2].ttype); emit_line_note (input_filename, lineno); expand_asm (yyvsp[-2].ttype); finish_stmt (); ; break;} -case 623: -#line 3326 "parse.y" +case 622: +#line 3324 "parse.y" { if (TREE_CHAIN (yyvsp[-4].ttype)) yyvsp[-4].ttype = combine_strings (yyvsp[-4].ttype); emit_line_note (input_filename, lineno); c_expand_asm_operands (yyvsp[-4].ttype, yyvsp[-2].ttype, NULL_TREE, NULL_TREE, @@ -6960,8 +6906,8 @@ finish_stmt (); ; break;} -case 624: -#line 3335 "parse.y" +case 623: +#line 3333 "parse.y" { if (TREE_CHAIN (yyvsp[-6].ttype)) yyvsp[-6].ttype = combine_strings (yyvsp[-6].ttype); emit_line_note (input_filename, lineno); c_expand_asm_operands (yyvsp[-6].ttype, yyvsp[-4].ttype, yyvsp[-2].ttype, NULL_TREE, @@ -6970,8 +6916,8 @@ finish_stmt (); ; break;} -case 625: -#line 3345 "parse.y" +case 624: +#line 3343 "parse.y" { if (TREE_CHAIN (yyvsp[-8].ttype)) yyvsp[-8].ttype = combine_strings (yyvsp[-8].ttype); emit_line_note (input_filename, lineno); c_expand_asm_operands (yyvsp[-8].ttype, yyvsp[-6].ttype, yyvsp[-4].ttype, yyvsp[-2].ttype, @@ -6980,83 +6926,83 @@ finish_stmt (); ; break;} -case 626: -#line 3353 "parse.y" +case 625: +#line 3351 "parse.y" { emit_line_note (input_filename, lineno); expand_computed_goto (yyvsp[-1].ttype); ; break;} -case 627: -#line 3356 "parse.y" +case 626: +#line 3354 "parse.y" { tree decl; emit_line_note (input_filename, lineno); decl = lookup_label (yyvsp[-1].ttype); TREE_USED (decl) = 1; expand_goto (decl); ; break;} -case 628: -#line 3362 "parse.y" +case 627: +#line 3360 "parse.y" { finish_stmt (); ; break;} -case 629: -#line 3364 "parse.y" +case 628: +#line 3362 "parse.y" { error ("label must be followed by statement"); yyungetc ('}', 0); finish_stmt (); ; break;} -case 630: -#line 3368 "parse.y" +case 629: +#line 3366 "parse.y" { finish_stmt (); ; break;} -case 632: -#line 3374 "parse.y" +case 631: +#line 3372 "parse.y" { expand_start_try_stmts (); ; break;} -case 633: -#line 3376 "parse.y" +case 632: +#line 3374 "parse.y" { expand_end_try_stmts (); expand_start_all_catch (); ; break;} -case 634: -#line 3379 "parse.y" +case 633: +#line 3377 "parse.y" { expand_end_all_catch (); ; break;} -case 635: -#line 3387 "parse.y" +case 634: +#line 3385 "parse.y" { expand_end_bindings (0,1,1); poplevel (2,0,0); ; break;} -case 636: -#line 3391 "parse.y" +case 635: +#line 3389 "parse.y" { expand_end_bindings (0,1,1); poplevel (2,0,0); ; break;} -case 637: -#line 3395 "parse.y" +case 636: +#line 3393 "parse.y" { expand_end_bindings (0,1,1); poplevel (2,0,0); ; break;} -case 639: -#line 3403 "parse.y" +case 638: +#line 3401 "parse.y" { emit_line_note (input_filename, lineno); ; break;} -case 640: -#line 3405 "parse.y" +case 639: +#line 3403 "parse.y" { expand_end_catch_block (); ; break;} -case 643: -#line 3415 "parse.y" +case 642: +#line 3413 "parse.y" { expand_start_catch_block (NULL_TREE, NULL_TREE); ; break;} -case 644: -#line 3427 "parse.y" +case 643: +#line 3425 "parse.y" { expand_start_catch_block (TREE_PURPOSE (yyvsp[-1].ttype), TREE_VALUE (yyvsp[-1].ttype)); ; break;} -case 645: -#line 3433 "parse.y" +case 644: +#line 3431 "parse.y" { tree label; do_label: label = define_label (input_filename, lineno, yyvsp[-1].ttype); @@ -7064,25 +7010,29 @@ expand_label (label); ; break;} +case 645: +#line 3438 "parse.y" +{ goto do_label; ; + break;} case 646: #line 3440 "parse.y" { goto do_label; ; break;} case 647: -#line 3442 "parse.y" -{ goto do_label; ; +#line 3445 "parse.y" +{ yyval.ttype = NULL_TREE; ; break;} case 648: #line 3447 "parse.y" -{ yyval.ttype = NULL_TREE; ; +{ yyval.ttype = yyvsp[-1].ttype; ; break;} case 649: #line 3449 "parse.y" -{ yyval.ttype = yyvsp[-1].ttype; ; +{ yyval.ttype = NULL_TREE; ; break;} case 650: -#line 3451 "parse.y" -{ yyval.ttype = NULL_TREE; ; +#line 3454 "parse.y" +{ yyval.itype = 0; ; break;} case 651: #line 3456 "parse.y" @@ -7090,55 +7040,51 @@ break;} case 652: #line 3458 "parse.y" -{ yyval.itype = 0; ; +{ yyval.itype = 1; ; break;} case 653: #line 3460 "parse.y" -{ yyval.itype = 1; ; - break;} -case 654: -#line 3462 "parse.y" { yyval.itype = -1; ; break;} -case 655: -#line 3469 "parse.y" +case 654: +#line 3467 "parse.y" { emit_line_note (input_filename, lineno); yyval.ttype = NULL_TREE; ; break;} -case 656: -#line 3472 "parse.y" +case 655: +#line 3470 "parse.y" { emit_line_note (input_filename, lineno); ; break;} -case 657: -#line 3477 "parse.y" +case 656: +#line 3475 "parse.y" { yyval.ttype = NULL_TREE; ; break;} -case 659: -#line 3480 "parse.y" +case 658: +#line 3478 "parse.y" { yyval.ttype = NULL_TREE; ; break;} -case 660: -#line 3486 "parse.y" +case 659: +#line 3484 "parse.y" { yyval.ttype = NULL_TREE; ; break;} -case 663: -#line 3493 "parse.y" +case 662: +#line 3491 "parse.y" { yyval.ttype = chainon (yyval.ttype, yyvsp[0].ttype); ; break;} -case 664: -#line 3498 "parse.y" +case 663: +#line 3496 "parse.y" { yyval.ttype = build_tree_list (yyval.ttype, yyvsp[-1].ttype); ; break;} -case 665: -#line 3503 "parse.y" +case 664: +#line 3501 "parse.y" { yyval.ttype = tree_cons (NULL_TREE, yyval.ttype, NULL_TREE); ; break;} -case 666: -#line 3505 "parse.y" +case 665: +#line 3503 "parse.y" { yyval.ttype = tree_cons (NULL_TREE, yyvsp[0].ttype, yyval.ttype); ; break;} -case 667: -#line 3515 "parse.y" +case 666: +#line 3513 "parse.y" { if (strict_prototype) yyval.ttype = void_list_node; @@ -7146,39 +7092,39 @@ yyval.ttype = NULL_TREE; ; break;} -case 669: -#line 3523 "parse.y" +case 668: +#line 3521 "parse.y" { yyval.ttype = tree_cons (NULL_TREE, yyval.ttype, void_list_node); TREE_PARMLIST (yyval.ttype) = 1; ; break;} -case 670: -#line 3531 "parse.y" +case 669: +#line 3529 "parse.y" { yyval.ttype = chainon (yyval.ttype, void_list_node); TREE_PARMLIST (yyval.ttype) = 1; ; break;} -case 671: -#line 3536 "parse.y" +case 670: +#line 3534 "parse.y" { TREE_PARMLIST (yyval.ttype) = 1; ; break;} -case 672: -#line 3541 "parse.y" +case 671: +#line 3539 "parse.y" { TREE_PARMLIST (yyval.ttype) = 1; ; break;} -case 673: -#line 3545 "parse.y" +case 672: +#line 3543 "parse.y" { yyval.ttype = build_tree_list (NULL_TREE, yyval.ttype); TREE_PARMLIST (yyval.ttype) = 1; ; break;} -case 674: -#line 3550 "parse.y" +case 673: +#line 3548 "parse.y" { /* ARM $8.2.5 has this as a boxed-off comment. */ if (pedantic) @@ -7186,27 +7132,27 @@ yyval.ttype = NULL_TREE; ; break;} -case 675: -#line 3557 "parse.y" +case 674: +#line 3555 "parse.y" { TREE_PARMLIST (yyval.ttype) = 1; ; break;} -case 676: -#line 3561 "parse.y" +case 675: +#line 3559 "parse.y" { TREE_PARMLIST (yyval.ttype) = 1; ; break;} -case 677: -#line 3565 "parse.y" +case 676: +#line 3563 "parse.y" { yyval.ttype = build_tree_list (NULL_TREE, yyval.ttype); TREE_PARMLIST (yyval.ttype) = 1; ; break;} -case 678: -#line 3570 "parse.y" +case 677: +#line 3568 "parse.y" { /* This helps us recover from really nasty parse errors, for example, a missing right @@ -7218,8 +7164,8 @@ yychar = ')'; ; break;} -case 679: -#line 3581 "parse.y" +case 678: +#line 3579 "parse.y" { /* This helps us recover from really nasty parse errors, for example, a missing right @@ -7231,184 +7177,188 @@ yychar = ')'; ; break;} +case 679: +#line 3594 "parse.y" +{ yyval.ttype = build_tree_list (NULL_TREE, yyval.ttype); ; + break;} case 680: #line 3596 "parse.y" -{ yyval.ttype = build_tree_list (NULL_TREE, yyval.ttype); ; +{ yyval.ttype = build_tree_list (yyvsp[0].ttype, yyval.ttype); ; break;} case 681: #line 3598 "parse.y" -{ yyval.ttype = build_tree_list (yyvsp[0].ttype, yyval.ttype); ; +{ yyval.ttype = chainon (yyval.ttype, yyvsp[0].ttype); ; break;} case 682: #line 3600 "parse.y" -{ yyval.ttype = chainon (yyval.ttype, yyvsp[0].ttype); ; +{ yyval.ttype = chainon (yyval.ttype, build_tree_list (NULL_TREE, yyvsp[0].ttype)); ; break;} case 683: #line 3602 "parse.y" -{ yyval.ttype = chainon (yyval.ttype, build_tree_list (NULL_TREE, yyvsp[0].ttype)); ; - break;} -case 684: -#line 3604 "parse.y" { yyval.ttype = chainon (yyval.ttype, build_tree_list (yyvsp[0].ttype, yyvsp[-2].ttype)); ; break;} -case 686: -#line 3610 "parse.y" +case 685: +#line 3608 "parse.y" { yyval.ttype = build_tree_list (NULL_TREE, yyval.ttype); ; break;} +case 686: +#line 3631 "parse.y" +{ yyval.ttype = build_tree_list (yyval.ttype, yyvsp[0].ttype); ; + break;} case 687: #line 3633 "parse.y" { yyval.ttype = build_tree_list (yyval.ttype, yyvsp[0].ttype); ; break;} case 688: #line 3635 "parse.y" -{ yyval.ttype = build_tree_list (yyval.ttype, yyvsp[0].ttype); ; +{ yyval.ttype = build_tree_list (get_decl_list (yyval.ttype), yyvsp[0].ttype); ; break;} case 689: #line 3637 "parse.y" -{ yyval.ttype = build_tree_list (get_decl_list (yyval.ttype), yyvsp[0].ttype); ; +{ yyval.ttype = build_tree_list (yyval.ttype, yyvsp[0].ttype); ; break;} case 690: #line 3639 "parse.y" -{ yyval.ttype = build_tree_list (yyval.ttype, yyvsp[0].ttype); ; +{ yyval.ttype = build_tree_list (yyval.ttype, NULL_TREE); ; break;} case 691: #line 3641 "parse.y" -{ yyval.ttype = build_tree_list (yyval.ttype, NULL_TREE); ; +{ yyval.ttype = build_tree_list (yyval.ttype, yyvsp[0].ttype); ; break;} case 692: -#line 3643 "parse.y" -{ yyval.ttype = build_tree_list (yyval.ttype, yyvsp[0].ttype); ; +#line 3646 "parse.y" +{ yyval.ttype = build_tree_list (NULL_TREE, yyval.ttype); ; break;} case 693: #line 3648 "parse.y" -{ yyval.ttype = build_tree_list (NULL_TREE, yyval.ttype); ; - break;} -case 694: -#line 3650 "parse.y" { yyval.ttype = build_tree_list (yyvsp[0].ttype, yyval.ttype); ; break;} -case 697: -#line 3659 "parse.y" +case 696: +#line 3657 "parse.y" { see_typename (); ; break;} -case 698: -#line 3682 "parse.y" +case 697: +#line 3680 "parse.y" { warning ("type specifier omitted for parameter"); yyval.ttype = build_tree_list (TREE_PURPOSE (TREE_VALUE (yyvsp[-1].ttype)), NULL_TREE); ; break;} -case 699: -#line 3687 "parse.y" +case 698: +#line 3685 "parse.y" { warning ("type specifier omitted for parameter"); yyval.ttype = build_tree_list (TREE_PURPOSE (TREE_VALUE (yyvsp[-2].ttype)), yyval.ttype); ; break;} -case 700: -#line 3695 "parse.y" +case 699: +#line 3693 "parse.y" { yyval.ttype = NULL_TREE; ; break;} -case 701: -#line 3697 "parse.y" +case 700: +#line 3695 "parse.y" { yyval.ttype = yyvsp[-1].ttype; ; break;} -case 702: -#line 3702 "parse.y" +case 701: +#line 3700 "parse.y" { yyval.ttype = build_decl_list (NULL_TREE, yyval.ttype); ; break;} -case 704: -#line 3708 "parse.y" +case 703: +#line 3706 "parse.y" { TREE_CHAIN (yyvsp[0].ttype) = yyval.ttype; yyval.ttype = yyvsp[0].ttype; ; break;} +case 704: +#line 3714 "parse.y" +{ yyval.ttype = NULL_TREE; ; + break;} case 705: #line 3716 "parse.y" -{ yyval.ttype = NULL_TREE; ; +{ yyval.ttype = make_pointer_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ; break;} case 706: #line 3718 "parse.y" -{ yyval.ttype = make_pointer_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ; +{ yyval.ttype = make_reference_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ; break;} case 707: #line 3720 "parse.y" -{ yyval.ttype = make_reference_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); ; - break;} -case 708: -#line 3722 "parse.y" { tree arg = make_pointer_declarator (yyvsp[-1].ttype, yyvsp[0].ttype); yyval.ttype = build_parse_node (SCOPE_REF, yyvsp[-2].ttype, arg); ; break;} -case 709: -#line 3728 "parse.y" +case 708: +#line 3726 "parse.y" { got_scope = NULL_TREE; ; break;} +case 709: +#line 3731 "parse.y" +{ yyval.ttype = ansi_opname[MULT_EXPR]; ; + break;} case 710: #line 3733 "parse.y" -{ yyval.ttype = ansi_opname[MULT_EXPR]; ; +{ yyval.ttype = ansi_opname[TRUNC_DIV_EXPR]; ; break;} case 711: #line 3735 "parse.y" -{ yyval.ttype = ansi_opname[TRUNC_DIV_EXPR]; ; +{ yyval.ttype = ansi_opname[TRUNC_MOD_EXPR]; ; break;} case 712: #line 3737 "parse.y" -{ yyval.ttype = ansi_opname[TRUNC_MOD_EXPR]; ; +{ yyval.ttype = ansi_opname[PLUS_EXPR]; ; break;} case 713: #line 3739 "parse.y" -{ yyval.ttype = ansi_opname[PLUS_EXPR]; ; +{ yyval.ttype = ansi_opname[MINUS_EXPR]; ; break;} case 714: #line 3741 "parse.y" -{ yyval.ttype = ansi_opname[MINUS_EXPR]; ; +{ yyval.ttype = ansi_opname[BIT_AND_EXPR]; ; break;} case 715: #line 3743 "parse.y" -{ yyval.ttype = ansi_opname[BIT_AND_EXPR]; ; +{ yyval.ttype = ansi_opname[BIT_IOR_EXPR]; ; break;} case 716: #line 3745 "parse.y" -{ yyval.ttype = ansi_opname[BIT_IOR_EXPR]; ; +{ yyval.ttype = ansi_opname[BIT_XOR_EXPR]; ; break;} case 717: #line 3747 "parse.y" -{ yyval.ttype = ansi_opname[BIT_XOR_EXPR]; ; +{ yyval.ttype = ansi_opname[BIT_NOT_EXPR]; ; break;} case 718: #line 3749 "parse.y" -{ yyval.ttype = ansi_opname[BIT_NOT_EXPR]; ; +{ yyval.ttype = ansi_opname[COMPOUND_EXPR]; ; break;} case 719: #line 3751 "parse.y" -{ yyval.ttype = ansi_opname[COMPOUND_EXPR]; ; +{ yyval.ttype = ansi_opname[yyvsp[0].code]; ; break;} case 720: #line 3753 "parse.y" -{ yyval.ttype = ansi_opname[yyvsp[0].code]; ; +{ yyval.ttype = ansi_opname[LT_EXPR]; ; break;} case 721: #line 3755 "parse.y" -{ yyval.ttype = ansi_opname[LT_EXPR]; ; +{ yyval.ttype = ansi_opname[GT_EXPR]; ; break;} case 722: #line 3757 "parse.y" -{ yyval.ttype = ansi_opname[GT_EXPR]; ; +{ yyval.ttype = ansi_opname[yyvsp[0].code]; ; break;} case 723: #line 3759 "parse.y" -{ yyval.ttype = ansi_opname[yyvsp[0].code]; ; +{ yyval.ttype = ansi_assopname[yyvsp[0].code]; ; break;} case 724: #line 3761 "parse.y" -{ yyval.ttype = ansi_assopname[yyvsp[0].code]; ; +{ yyval.ttype = ansi_opname [MODIFY_EXPR]; ; break;} case 725: #line 3763 "parse.y" -{ yyval.ttype = ansi_opname [MODIFY_EXPR]; ; +{ yyval.ttype = ansi_opname[yyvsp[0].code]; ; break;} case 726: #line 3765 "parse.y" @@ -7416,79 +7366,75 @@ break;} case 727: #line 3767 "parse.y" -{ yyval.ttype = ansi_opname[yyvsp[0].code]; ; +{ yyval.ttype = ansi_opname[POSTINCREMENT_EXPR]; ; break;} case 728: #line 3769 "parse.y" -{ yyval.ttype = ansi_opname[POSTINCREMENT_EXPR]; ; +{ yyval.ttype = ansi_opname[PREDECREMENT_EXPR]; ; break;} case 729: #line 3771 "parse.y" -{ yyval.ttype = ansi_opname[PREDECREMENT_EXPR]; ; +{ yyval.ttype = ansi_opname[TRUTH_ANDIF_EXPR]; ; break;} case 730: #line 3773 "parse.y" -{ yyval.ttype = ansi_opname[TRUTH_ANDIF_EXPR]; ; +{ yyval.ttype = ansi_opname[TRUTH_ORIF_EXPR]; ; break;} case 731: #line 3775 "parse.y" -{ yyval.ttype = ansi_opname[TRUTH_ORIF_EXPR]; ; +{ yyval.ttype = ansi_opname[TRUTH_NOT_EXPR]; ; break;} case 732: #line 3777 "parse.y" -{ yyval.ttype = ansi_opname[TRUTH_NOT_EXPR]; ; +{ yyval.ttype = ansi_opname[COND_EXPR]; ; break;} case 733: #line 3779 "parse.y" -{ yyval.ttype = ansi_opname[COND_EXPR]; ; +{ yyval.ttype = ansi_opname[yyvsp[0].code]; ; break;} case 734: #line 3781 "parse.y" -{ yyval.ttype = ansi_opname[yyvsp[0].code]; ; +{ yyval.ttype = ansi_opname[COMPONENT_REF]; ; break;} case 735: #line 3783 "parse.y" -{ yyval.ttype = ansi_opname[COMPONENT_REF]; ; +{ yyval.ttype = ansi_opname[MEMBER_REF]; ; break;} case 736: #line 3785 "parse.y" -{ yyval.ttype = ansi_opname[MEMBER_REF]; ; +{ yyval.ttype = ansi_opname[CALL_EXPR]; ; break;} case 737: #line 3787 "parse.y" -{ yyval.ttype = ansi_opname[CALL_EXPR]; ; +{ yyval.ttype = ansi_opname[ARRAY_REF]; ; break;} case 738: #line 3789 "parse.y" -{ yyval.ttype = ansi_opname[ARRAY_REF]; ; +{ yyval.ttype = ansi_opname[NEW_EXPR]; ; break;} case 739: #line 3791 "parse.y" -{ yyval.ttype = ansi_opname[NEW_EXPR]; ; +{ yyval.ttype = ansi_opname[DELETE_EXPR]; ; break;} case 740: #line 3793 "parse.y" -{ yyval.ttype = ansi_opname[DELETE_EXPR]; ; +{ yyval.ttype = ansi_opname[VEC_NEW_EXPR]; ; break;} case 741: #line 3795 "parse.y" -{ yyval.ttype = ansi_opname[VEC_NEW_EXPR]; ; +{ yyval.ttype = ansi_opname[VEC_DELETE_EXPR]; ; break;} case 742: -#line 3797 "parse.y" -{ yyval.ttype = ansi_opname[VEC_DELETE_EXPR]; ; +#line 3798 "parse.y" +{ yyval.ttype = grokoptypename (yyvsp[-1].ttype, yyvsp[0].ttype); ; break;} case 743: #line 3800 "parse.y" -{ yyval.ttype = grokoptypename (yyvsp[-1].ttype, yyvsp[0].ttype); ; - break;} -case 744: -#line 3802 "parse.y" { yyval.ttype = ansi_opname[ERROR_MARK]; ; break;} } /* the action file gets copied in in place of this dollarsign */ -#line 480 "/usr/local/lib/bison.simple" +#line 465 "/usr/local/lib/bison.simple" yyvsp -= yylen; yyssp -= yylen; @@ -7684,7 +7630,7 @@ yystate = yyn; goto yynewstate; } -#line 3805 "parse.y" +#line 3803 "parse.y" #ifdef SPEW_DEBUG diff -r -u -H -N gcc-2.6.3/cse.c gcc-i2.6.3/cse.c --- gcc-2.6.3/cse.c Tue Nov 1 18:38:40 1994 +++ gcc-i2.6.3/cse.c Thu Feb 16 11:58:55 1995 @@ -6007,6 +6007,29 @@ sets = (struct set *) alloca (sizeof (struct set)); sets[0].rtl = x; +/* intel1 */ +#ifdef STACK_REGS +#ifdef IS_STACK_MODE + if (IS_STACK_MODE (DFmode) && GET_CODE (SET_SRC (x)) == CONST_DOUBLE + && GET_CODE (SET_DEST (x)) == REG) + { + /* not worthwhile to hold on stack */ + rtx tem = find_reg_note (insn, REG_EQUAL, 0); + + /* Record the actual constant value in a REG_EQUAL note, making + a new one if one does not already exist. */ + if (tem) + XEXP (tem, 0) = SET_SRC(x); + else + REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUAL, + SET_SRC(x), REG_NOTES (insn)); + + invalidate (SET_DEST (x), GET_MODE(x) ); + } + else + +#endif +#endif /* Ignore SETs that are unconditional jumps. They never need cse processing, so this does not hurt. The reason is not efficiency but rather @@ -6625,6 +6648,32 @@ if (dest == pc_rtx && src_const && GET_CODE (src_const) == LABEL_REF) src_folded = src_const, src_folded_cost = -1; +#ifdef SAVE_ON_REGS + /* intel1 If src is of form (reg1 OP const) and src_folded + is of form (reg2 OP const) and the costs are the same + and reg1 != reg2, + then bump up the cost of src_folded so that src will be + preferred. The reason for this is that if reg2 is used + here it's life may be extended thereby increasing register + pressure and causing superfulous movs. */ + { + char * fmt; + if (src) + fmt = GET_RTX_FORMAT (GET_CODE (src)); + if (src && src_folded && src_cost == src_folded_cost + && GET_CODE (src) == GET_CODE (src_folded) + && GET_RTX_LENGTH (GET_CODE (src)) == 2 + && fmt[0] == 'e' && fmt[1] == 'e' + && GET_CODE (XEXP (src, 0)) == REG + && GET_CODE (XEXP (src, 1)) == CONST_INT + && GET_CODE (XEXP (src_folded, 0)) == REG + && GET_CODE (XEXP (src_folded, 1)) == CONST_INT + && !rtx_equal_p (XEXP (src, 0), XEXP (src_folded, 0))) + { + src_folded_cost++; + } + } +#endif /* Terminate loop when replacement made. This must terminate since the current contents will be tested and will always be valid. */ while (1) @@ -7068,6 +7117,16 @@ if (sets[i].src_elt == 0) { register struct table_elt *elt; + /* intel1 */ + int do_rehash=0; + + /* intel1 */ + if(GET_CODE(src)==REG && + !REGNO_QTY_VALID_P (REGNO(src))) + { /* we will want to rehash all expressions based of src since + reg_qty[REGNO(src)] is about to change */ + do_rehash = 1; + } /* Note that these insert_regs calls cannot remove any of the src_elt's, because they would have failed to diff -r -u -H -N gcc-2.6.3/expr.c gcc-i2.6.3/expr.c --- gcc-2.6.3/expr.c Wed Nov 30 19:08:49 1994 +++ gcc-i2.6.3/expr.c Wed Feb 15 23:19:22 1995 @@ -23,6 +23,8 @@ #include "rtl.h" #include "tree.h" #include "obstack.h" +/* intel1 */ +#include "c-tree.h" #include "flags.h" #include "regs.h" #include "function.h" @@ -8596,6 +8598,12 @@ && (i = floor_log2 (TREE_INT_CST_LOW (TREE_OPERAND (exp, 1)))) >= 0 && (mode = mode_for_size (i + 1, MODE_INT, 0)) != BLKmode && (type = type_for_mode (mode, 1)) != 0 + /* intel1 */ + && !(SLOW_SHORT_ACCESS + && (type == short_unsigned_type_node + || type == short_integer_type_node + || type == intHI_type_node + || type == unsigned_intHI_type_node)) && TYPE_PRECISION (type) < TYPE_PRECISION (TREE_TYPE (exp)) && (cmp_optab->handlers[(int) TYPE_MODE (type)].insn_code != CODE_FOR_nothing)) @@ -8751,6 +8759,12 @@ type = type_for_size (bitsize, unsignedp); if (! SLOW_BYTE_ACCESS && type != 0 && bitsize >= 0 + /* intel1 */ + && !(SLOW_SHORT_ACCESS + && (type == short_unsigned_type_node + || type == short_integer_type_node + || type == intHI_type_node + || type == unsigned_intHI_type_node)) && TYPE_PRECISION (type) < TYPE_PRECISION (TREE_TYPE (exp)) && (cmp_optab->handlers[(int) TYPE_MODE (type)].insn_code != CODE_FOR_nothing)) diff -r -u -H -N gcc-2.6.3/flags.h gcc-i2.6.3/flags.h --- gcc-2.6.3/flags.h Thu May 12 20:04:27 1994 +++ gcc-i2.6.3/flags.h Wed Feb 15 22:47:02 1995 @@ -357,3 +357,149 @@ function. */ extern int current_function_has_nonlocal_goto; + +/* intel1 our optimization controllers */ + +/* Optimize usage of registers for memory addresses */ + +extern int flag_opt_reg_use; + +/* Do reduce all the mem address givs */ + +extern int flag_all_mem_givs; + +/* Try to treat index terms of addresses as reducible mem givs */ + +extern int flag_reduce_index_givs; + +/* After reload try to replace spill slots with equivalent registers */ + +extern int flag_peep_spills; + +/* After reload try to optimize usage of spill slots in loops */ + +extern int flag_loop_after_global; + +/* In optimization of loops treats jumps backwards as not nullifying + optimization opportunities. */ + +extern int flag_jump_back; + +/* Do loop copy propogation */ + +extern int flag_copy_prop; + +/* Do compare elimination */ + +extern int flag_compare_elim; + +/* Do a mini software pipelining on stack registers */ + +extern int flag_sftwr_pipe; + +/* Try aggressive changing of jumps taken to jumps not taken */ + +extern int flag_opt_jumps_out; + +/* Try to replace memory operands with equivalent registers in first + pass of loop optimize */ + +extern int flag_replace_mem; + +/* Try to replace memory operands with equivalent stack registers in first + pass of loop optimize */ + +extern int flag_replace_stack_mem; + +/* After reload if a register is marked dead at a copy into another + register - see if the other register can be used in the first place. + Thereby eleiminating the copy. */ + +extern int flag_reg_reg_copy_opt; + +/* Move stack registers that will be compared for equality off, the + stack before the comparison. */ + +extern int flag_do_offload; + +/* Optimize usage of stack registers from the stack */ + +extern int flag_opt_reg_stack; + +/* cse is sometimes detrimental - see flow.c */ + +extern int flag_correct_cse_mistakes; + +/* Try to push loads back into loops if the loaded register has been spilled */ + +extern int flag_push_load_into_loop; + +/* After reload use available registers to load memory operands into + them and use the register instead of the memory operand. */ + +extern int flag_risc; + +/* After reload use available registers to load CONST_INTs into + them and then store the register instead of the CONST_INT. */ + +extern int flag_risc_const; + +/* Allow scheduler to try to swap two instructions when the + first increments a register by a constant and the second + uses that register as a base +*/ + +extern int flag_swap_for_agi; + +/* A destination that was riscified should stay that way. */ + +extern int flag_risc_mem_dest; + +/* Try to use available registers so that a memory operand that is + reloaded will be reloaded into the same register. This helps + loop_after_global. */ + +extern int flag_replace_reload_regs; + +/* If the riscified instruction has not changed it's place in + scheduling then recombine it into a cisc instruction. */ + +extern int flag_recombine; + +/* These negative flags needed to override optimization + levels which turn them on by default */ + +extern int flag_no_omit_frame_pointer; +extern int flag_no_risc; +extern int flag_no_risc_const; +extern int flag_no_risc_mem_dest; +extern int flag_no_recombine; +/* Use the first pass of the scheduler to rearrange between + insns that reference stack registers. */ + +extern int flag_schedule_stack_reg_insns; + +/* Use the first pass of the scheduler to rearrange between + insns that reference stack registers and those that don't + but not amongst themselves */ + +extern int flag_interleave_stack_non_stack; + +/* These negative flags needed to override optimization + levels which turn them on by default */ + +extern int flag_no_schedule_stack_reg_insns; +extern int flag_no_interleave_stack_non_stack; + +extern int flag_sign_extension_elim; + +/* Try to lift memory disambiguated memory operands that are stored + to in a loop into a register for the duration of the loop. */ + +extern int flag_lift_stores; + +/* As above but do the disambiguation at runtime. i.e. there + will be two copies of the loop, one disambiguated one not, + And the decision of which one to run will be made at runtime. */ + +extern int flag_runtime_lift_stores; diff -r -u -H -N gcc-2.6.3/flow.c gcc-i2.6.3/flow.c --- gcc-2.6.3/flow.c Thu Nov 17 12:46:04 1994 +++ gcc-i2.6.3/flow.c Thu Feb 16 12:14:28 1995 @@ -285,14 +285,14 @@ static HARD_REG_SET elim_reg_set; /* Forward declarations */ -static void find_basic_blocks PROTO((rtx, rtx)); +static void find_basic_blocks PROTO((rtx, rtx, int)); static int uses_reg_or_mem PROTO((rtx)); static void mark_label_ref PROTO((rtx, rtx, int)); -static void life_analysis PROTO((rtx, int)); +static void life_analysis PROTO((rtx, int, int)); void allocate_for_life_analysis PROTO((void)); -static void init_regset_vector PROTO((regset *, regset, int, int)); +/* intel2 static */ void init_regset_vector PROTO((regset *, regset, int, int)); static void propagate_block PROTO((regset, rtx, rtx, int, - regset, int)); + regset, int, int)); static int insn_dead_p PROTO((rtx, regset, int)); static int libcall_dead_p PROTO((rtx, regset, rtx, rtx)); static void mark_set_regs PROTO((regset, regset, rtx, @@ -305,16 +305,27 @@ static int try_pre_increment PROTO((rtx, rtx, HOST_WIDE_INT)); static rtx find_use_as_address PROTO((rtx, rtx, HOST_WIDE_INT)); void dump_flow_info PROTO((FILE *)); +/* intel1 */ +static void correct_cse_mistakes (); +static void count_reg_uses (); +static void do_correction (); /* Find basic blocks of the current function and perform data flow analysis. F is the first insn of the function and NREGS the number of register numbers in use. */ void +/* flow_analysis (f, nregs, file) +*/ +/* intel2 - added the change_f flag to disable changes to the insns, when called + * by memory_simplify. Don't apply any change to an insn if this flag == 0 + */ +flow_analysis (f, nregs, file, change_f) rtx f; int nregs; FILE *file; + int change_f; /* intel2 */ { register rtx insn; register int i; @@ -324,6 +335,14 @@ static struct {int from, to; } eliminables[] = ELIMINABLE_REGS; #endif + /* intel1 */ +#ifdef SPARE_REGS + if (change_f && flag_opt_reg_stack) + { + nregs += SPARE_REGS; + } +#endif + /* Record which registers will be eliminated. We use this in mark_used_regs. */ @@ -370,9 +389,13 @@ /* Allocate some tables that last till end of compiling this function and some needed only in find_basic_blocks and life_analysis. */ - n_basic_blocks = i; - basic_block_head = (rtx *) oballoc (n_basic_blocks * sizeof (rtx)); - basic_block_end = (rtx *) oballoc (n_basic_blocks * sizeof (rtx)); + if (change_f || (n_basic_blocks!=i)) + /* intel2 if change_f is 0 we may have already allocated basic blocks */ + { + n_basic_blocks = i; + basic_block_head = (rtx *) oballoc (n_basic_blocks * sizeof (rtx)); + basic_block_end = (rtx *) oballoc (n_basic_blocks * sizeof (rtx)); + } basic_block_drops_in = (char *) alloca (n_basic_blocks); basic_block_loop_depth = (short *) alloca (n_basic_blocks * sizeof (short)); uid_block_number @@ -380,11 +403,16 @@ uid_volatile = (char *) alloca (max_uid_for_flow + 1); bzero (uid_volatile, max_uid_for_flow + 1); - find_basic_blocks (f, nonlocal_label_list); - life_analysis (f, nregs); + find_basic_blocks (f, nonlocal_label_list /* intel2: */, change_f); + life_analysis (f, nregs /* intel2: */, change_f); if (file) dump_flow_info (file); + /* intel1 */ + if (flag_correct_cse_mistakes && change_f) + { + correct_cse_mistakes (f, nregs, file); + } basic_block_drops_in = 0; uid_block_number = 0; basic_block_loop_depth = 0; @@ -398,8 +426,9 @@ NONLOCAL_LABEL_LIST is the same local variable from flow_analysis. */ static void -find_basic_blocks (f, nonlocal_label_list) +find_basic_blocks (f, nonlocal_label_list /* intel2: */, change_f) rtx f, nonlocal_label_list; + int change_f;/* intel2 */ { register rtx insn; register int i; @@ -627,7 +656,7 @@ unreachable loops as unreachable. */ for (i = 0; i < n_basic_blocks; i++) - if (!block_live[i]) + if (!block_live[i] /* intel2: */ && change_f) { insn = basic_block_head[i]; while (1) @@ -790,9 +819,10 @@ regset_size and regset_bytes are also set here. */ static void -life_analysis (f, nregs) +life_analysis (f, nregs /* intel2: */, change_f) rtx f; int nregs; + int change_f; /* intel2 */ { register regset tem; int first_pass; @@ -820,8 +850,14 @@ max_regno = nregs; - bzero (regs_ever_live, sizeof regs_ever_live); + /* intel2 - begin */ + /* Dont reset the regs_ever_live array if called from memory_simplify */ + if (change_f) + { + /* intel2 - end */ + bzero (regs_ever_live, sizeof regs_ever_live); + } /* Allocate and zero out many data structures that will record the data from lifetime analysis. */ @@ -866,10 +902,32 @@ for (insn = f; insn; insn = NEXT_INSN (insn)) { enum rtx_code code1 = GET_CODE (insn); - if (code1 == CALL_INSN) + if (code1 == CALL_INSN /* intel2: */ && change_f) INSN_VOLATILE (insn) = 1; else if (code1 == INSN || code1 == JUMP_INSN) { + /* intel2 - begin */ + /* if change_f is reset, i.e. we are called from memory_simplify, and + * therefore we would like to update the insn's REG_DEAD notes. + * If we find a REG_DEAD note, we remove it here. + */ + if (!change_f) + { + register rtx note; + + + for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) + if (REG_NOTE_KIND (note) == REG_DEAD + || REG_NOTE_KIND (note) == REG_UNUSED) + remove_note(insn, note); + } + /* intel2 - end */ + + +/* intel2 - begin */ + if (change_f) + { +/* intel2 - end */ /* Delete (in effect) any obvious no-op moves. */ if (GET_CODE (PATTERN (insn)) == SET && GET_CODE (SET_DEST (PATTERN (insn))) == REG @@ -930,6 +988,9 @@ #endif && XEXP (SET_SRC (PATTERN (insn)), 0) == stack_pointer_rtx) INSN_VOLATILE (insn) = 1; + /* intel2 - begin */ + } /* if (change_f) */ + /* intel2 - end */ } } @@ -1070,7 +1131,7 @@ basic_block_head[i], basic_block_end[i], 0, first_pass ? basic_block_significant[i] : (regset) 0, - i); + i/* intel2: */, change_f); } { @@ -1135,7 +1196,7 @@ { propagate_block (basic_block_live_at_end[i], basic_block_head[i], basic_block_end[i], 1, - (regset) 0, i); + (regset) 0, i/* intel2: */, change_f); #ifdef USE_C_ALLOCA alloca (0); #endif @@ -1232,7 +1293,7 @@ SPACE is of type regset, but it is really as long as NELTS regsets. BYTES_PER_ELT is the number of bytes in one regset. */ -static void +/* intel2 static */ void init_regset_vector (vector, space, nelts, bytes_per_elt) regset *vector; regset space; @@ -1269,13 +1330,13 @@ BNUM is the number of the basic block. */ static void -propagate_block (old, first, last, final, significant, bnum) +propagate_block (old, first, last, final, significant, bnum /* intel2: */, change_f) register regset old; rtx first; rtx last; int final; regset significant; - int bnum; + int bnum /* intel2: */, change_f; { register rtx insn; rtx prev; @@ -1319,7 +1380,7 @@ loop_depth--; } - if (final) + if (final /* intel2: */ && change_f) { register int i, offset; REGSET_ELT_TYPE bit; @@ -1402,7 +1463,7 @@ "delete" it by turning it into a NOTE of type NOTE_INSN_DELETED. We could really delete it with delete_insn, but that can cause trouble for first or last insn in a basic block. */ - if (final && insn_is_dead) + if (final /* intel2: */ && change_f && insn_is_dead) { PUT_CODE (insn, NOTE); NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; @@ -1444,7 +1505,7 @@ { register rtx x = PATTERN (insn); /* Does this instruction increment or decrement a register? */ - if (final && GET_CODE (x) == SET + if (final /* intel2: */ && change_f && GET_CODE (x) == SET && GET_CODE (SET_DEST (x)) == REG && (GET_CODE (SET_SRC (x)) == PLUS || GET_CODE (SET_SRC (x)) == MINUS) @@ -1488,7 +1549,7 @@ live. */ mark_set_regs (old, dead, PATTERN (insn), - final ? insn : NULL_RTX, significant); + (final /* intel2: */ && change_f) ? insn : NULL_RTX, significant); /* If an insn doesn't use CC0, it becomes dead since we assume that every insn clobbers it. So show it dead here; @@ -1552,7 +1613,7 @@ old[i] |= live[i]; } - if (GET_CODE (insn) == CALL_INSN && final) + if (GET_CODE (insn) == CALL_INSN && final /* intel2: */ && change_f) { /* Any regs live at the time of a call instruction must not go in a register clobbered by calls. @@ -1570,7 +1631,7 @@ into MAXLIVE and REGS_SOMETIMES_LIVE. Also update counts of how many insns each reg is live at. */ - if (final) + if (final /* intel2: */ && change_f) { for (i = 0; i < regset_size; i++) { @@ -2776,6 +2837,11 @@ { register int i; static char *reg_class_names[] = REG_CLASS_NAMES; + /* intel1 */ +#ifdef SPARE_REGS + int max_regno; + max_regno = max_reg_num(); +#endif fprintf (file, "%d registers.\n", max_regno); @@ -2852,3 +2918,594 @@ } fprintf (file, "\n"); } + +/* intel1 */ +/* Information about registers */ +struct regopt_info +{ + rtx insn_set; /* If non NULL then the insn that loads the register + with it's current value */ + int num_uses_copied; /* To count if the reg setter has been copied to + each of the uses */ + char copied_for_src; /* Set per insn if the insn_set has been copied + as a result of analysis on the src */ +}; +static struct regopt_info *rinfo; + +/* Count the number of new sets of the register */ +static int *my_reg_n_sets; + +/* Count the number of times a register is used in an insn */ +static int *regs_in_body; + +/* Count the number of times a register is used in a function */ +static int *reg_n_uses; + +/* Copied from sched.c + Return the INSN_LIST containing INSN in LIST, or NULL + if LIST does not contain INSN. */ +#ifndef __GNUC__ +#define __inline +#endif + +__inline static rtx +find_insn_list (insn, list) + rtx insn; + rtx list; +{ + while (list) + { + if (XEXP (list, 0) == insn) + return list; + list = XEXP (list, 1); + } + return 0; +} + +/* + Sometimes cse is done where it is detremental. Consider register 23 + in the following insn stream: + +(insn 18 65 82 (set (reg/v:SI 23) + (plus:SI (reg/v:SI 22) + (const_int -4501))) 32 {movsi+1} (nil) + (nil)) + +(insn 82 18 83 (set (cc0) + (compare:CC (reg/v:SI 22) + (const_int 4500))) 6 {cmpsi_cc} (nil) + (nil)) + +(jump_insn 83 82 90 (set (pc) + (if_then_else (gt (cc0) + (const_int 0)) + (label_ref 63) + (pc))) 185 {bgt+1} (nil) + (nil)) + +(note 90 83 91 "" NOTE_INSN_DELETED) + +(insn 91 90 93 (set (reg:SI 32) + (ashift:SI (reg/v:SI 23) + (const_int 2))) 136 {ashlsi3} (nil) + (expr_list:REG_DEAD (reg/v:SI 23) + (nil))) + + reg 23 appears in insn 91 as a result of cse, before cse insn 90 + and 91 were: + +(insn 90 83 91 (set (reg:SI 33) + (plus:SI (reg/v:SI 22) + (const_int -4501))) -1 (nil) + (nil)) + +(insn 91 90 93 (set (reg:SI 34) + (ashift:SI (reg:SI 33) + (const_int 2))) -1 (nil) + (nil)) + + since reg 23 does not appear anywhere else in the rtl and it is dead + at insn 91 it would be better to move insn 18 to after insn 90, thus + allowing the combiner to combine insn 18 into 91. + +*/ +static void +correct_cse_mistakes (f, cur_max_reg, dump_file) + rtx f; + int cur_max_reg; + FILE *dump_file; +{ + rtx insn, src, dest, insn_set, note; + struct regs_mentioned *header, *a_reg_used; + int num_regs, recog_ok, i, regno; + char *storage1, *storage2; + + rinfo = + (struct regopt_info *) alloca ((cur_max_reg) * sizeof (struct regopt_info)); + bzero (rinfo, (cur_max_reg) * sizeof (struct regopt_info)); + reg_n_uses = (int *) alloca ((cur_max_reg) * sizeof (int)); + bzero (reg_n_uses, (cur_max_reg) * sizeof (int)); + regs_in_body = (int *) alloca ((cur_max_reg) * sizeof (int)); + bzero (regs_in_body, (cur_max_reg) * sizeof (int)); + my_reg_n_sets = (int *) alloca ((cur_max_reg) * sizeof (int)); + bzero (my_reg_n_sets, (cur_max_reg) * sizeof (int)); + + if (dump_file) + fprintf (dump_file, "\ndoing correct_cse_mistakes:\n\n"); + insn = f; + while (insn) + { + if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN + || GET_CODE (insn) == CALL_INSN) + { + count_reg_uses (PATTERN (insn), reg_n_uses); + } + insn = NEXT_INSN (insn); + } + insn = f; + while (insn) + { + switch (GET_CODE (insn)) + { + + case CALL_INSN: + /* Don't want to change reg_n_calls_crosses */ + bzero (rinfo, cur_max_reg * sizeof (struct regopt_info)); + break; + + case CODE_LABEL: + case BARRIER: + /* forget everything */ + bzero (rinfo, cur_max_reg * sizeof (struct regopt_info)); + break; + + case INSN: + if (GET_CODE (PATTERN (insn)) == CLOBBER) + { + if (GET_CODE (SET_DEST (PATTERN (insn))) == REG) + { + rinfo[ REGNO (SET_DEST (PATTERN (insn)))].insn_set = NULL; + for (i = 0; i < cur_max_reg; i++) + { + if (rinfo[i].insn_set + && reg_overlap_mentioned_p (SET_DEST (PATTERN (insn)), + SET_SRC (PATTERN (rinfo[i].insn_set))) + ) + { /* current value of reg dest overwritten */ + rinfo[i].insn_set = NULL; + } + } + } + } + else if (GET_CODE (PATTERN (insn)) == PARALLEL) + { + for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) + { + rtx cur_rtx; + cur_rtx = XVECEXP (PATTERN (insn), 0, i); + if ((GET_CODE (cur_rtx) == SET + || GET_CODE (cur_rtx) == CLOBBER) + && GET_CODE (SET_DEST (cur_rtx)) == REG) + { + rinfo[ REGNO (SET_DEST (cur_rtx))].insn_set = NULL; + for (i = 0; i < cur_max_reg; i++) + { + if (rinfo[i].insn_set + && reg_overlap_mentioned_p (SET_DEST (cur_rtx), + SET_SRC (PATTERN (rinfo[i].insn_set))) + ) + { /* current value of reg dest overwritten */ + rinfo[i].insn_set = NULL; + } + } + } + if (!(GET_CODE (cur_rtx) == SET + || GET_CODE (cur_rtx) == CLOBBER + || GET_CODE (cur_rtx) == USE)) + bzero (rinfo, cur_max_reg * sizeof (struct regopt_info)); + } + } + else if (GET_CODE (PATTERN (insn)) == SET) + { + dest = SET_DEST (PATTERN (insn)); + src = SET_SRC (PATTERN (insn)); + if (GET_CODE (src) == REG) + { + i = REGNO (src); + if (rinfo[i].insn_set + && BLOCK_NUM (insn) == BLOCK_NUM (rinfo[i].insn_set)) + { /* Since insn_set cannot be deleted stop optimization */ + rinfo[i].insn_set = NULL; + } + } + else /* (GET_CODE (src) != REG) */ + { + count_reg_uses (src, regs_in_body); + for (i = 0; i < cur_max_reg; i++) + { + if (rinfo[i].insn_set + && regs_in_body[i] + && BLOCK_NUM (insn) == BLOCK_NUM (rinfo[i].insn_set)) + { /* Since insn_set cannot be deleted stop optimization */ + rinfo[i].insn_set = NULL; + } + if (reg_n_sets[i] == 1 + && regs_in_body[i] + && rinfo[i].insn_set + && GET_CODE (rinfo[i].insn_set) == INSN) + { + if (find_regno_note (insn, REG_DEAD, i)) + { + /* copy insn_set just prior to insn */ + do_correction (i, insn, dump_file); + } + else + { /* A use that is not dead - stop. */ + rinfo[i].insn_set = NULL; + } + } + } + bzero (regs_in_body, cur_max_reg * sizeof (int)); + } + if (GET_CODE (dest) != REG) + { + count_reg_uses (dest, regs_in_body); + for (i = 0; i < cur_max_reg; i++) + { + if (rinfo[i].insn_set + && regs_in_body[i] + && BLOCK_NUM (insn) == BLOCK_NUM (rinfo[i].insn_set)) + { /* Since insn_set cannot be deleted stop optimization */ + rinfo[i].insn_set = NULL; + } + if (reg_n_sets[i] == 1 + && !rinfo[i].copied_for_src + && regs_in_body[i] + && rinfo[i].insn_set + && GET_CODE (rinfo[i].insn_set) == INSN) + { + if (find_regno_note (insn, REG_DEAD, i)) + { + /* copy insn_set just prior to insn */ + do_correction (i, insn, dump_file); + } + else + { /* A use that is not dead - stop. */ + rinfo[i].insn_set = NULL; + } + + } + } + bzero (regs_in_body, cur_max_reg * sizeof (int)); + } + for (i = 0; i < cur_max_reg; i++) + { + rinfo[i].copied_for_src = 0; + } + if (GET_CODE (dest) == REG) + { + for (i = 0; i < cur_max_reg; i++) + { + if (rinfo[i].insn_set + && reg_overlap_mentioned_p (dest, SET_SRC (PATTERN (rinfo[i].insn_set))) + ) + { /* current value of reg dest overwritten */ + rinfo[i].insn_set = NULL; + } + } + if (reg_overlap_mentioned_p (dest, SET_SRC (PATTERN (insn)))) + { + rinfo[REGNO (dest)].insn_set = NULL; + } + else + { + if ((GET_CODE (SET_SRC (PATTERN (insn))) == ASHIFT + && GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 0)) == REG + && GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == CONST_INT) + || (GET_CODE (SET_SRC (PATTERN (insn))) == PLUS + && GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 0)) == REG + && GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == SYMBOL_REF) + || (GET_CODE (SET_SRC (PATTERN (insn))) == PLUS + && GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 0)) == MULT + && GET_CODE (XEXP (XEXP (SET_SRC (PATTERN (insn)), 0), 0)) == REG + && GET_CODE (XEXP (XEXP (SET_SRC (PATTERN (insn)), 0), 1)) == CONST_INT + && GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == CONST_INT) + || (GET_CODE (SET_SRC (PATTERN (insn))) == PLUS + && GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 0)) == REG + && GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == CONST_INT) + ) + { /* these may be combinable */ + if (REG_NOTES (insn) == NULL) + { /* Don't want to mess around with + the REG_NOTES. */ + rinfo[REGNO (dest)].insn_set = insn; + } + } + else + { + rinfo[REGNO (dest)].insn_set = NULL; + } + } + } + } + else if (GET_CODE (PATTERN (insn)) == USE) + ; /* nothing */ + else + { + bzero (rinfo, cur_max_reg * sizeof (struct regopt_info)); + } + /* A register that dies cannot be used further in a substitution. */ + for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) + if (REG_NOTE_KIND (note) == REG_DEAD + && GET_CODE (XEXP (note, 0)) == REG) + { + for (i = 0; i < cur_max_reg; i++) + { + if (rinfo[i].insn_set + && reg_overlap_mentioned_p (XEXP (note, 0), + SET_SRC (PATTERN (rinfo[i].insn_set))) + ) + { + rinfo[i].insn_set = NULL; + } + } + } + + break; + + case JUMP_INSN: + case NOTE: + break; + + default: + bzero (rinfo, cur_max_reg * sizeof (struct regopt_info)); + break; + } + insn = NEXT_INSN (insn); + } + for (i = 0; i < cur_max_reg; i++) + reg_n_sets[i] += my_reg_n_sets[i]; +} + +/* + Increment the reg_n_uses element for each register mentioned in body + and for each time it is mentioned +*/ +static void +count_reg_uses (body, where_to_count) + rtx body; + int *where_to_count; +{ + int i, j, ret_val = 0; + char *fmt; + register RTX_CODE code = GET_CODE (body); + + if (code == CLOBBER) + return; + else if (code == REG) + where_to_count[REGNO (body)]++; + else if (code == SET) + { + if (GET_CODE (SET_DEST (body)) != REG) + { + count_reg_uses (SET_DEST (body), where_to_count); + } + count_reg_uses (SET_SRC (body), where_to_count); + } + else + { + fmt = GET_RTX_FORMAT (code); + for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) + if (fmt[i] == 'e') + count_reg_uses (XEXP (body, i), where_to_count); + else if (fmt[i] == 'E' || fmt[i] == 'V') + { + for (j = 0; j < XVECLEN (body, i); j++) + count_reg_uses (XVECEXP (body, i, j), where_to_count); + } + } +} + +/* + Copy the insn that sets regnum to just before insn. + If that insn has been copied to in front of each of + it's uses then delete it +*/ +static void +do_correction (regnum, insn, dump_file) + int regnum; + rtx insn; + FILE * dump_file; +{ + rtx insn_set; + int i; + + insn_set + = rinfo[regnum].insn_set; + if (BLOCK_NUM (insn) == BLOCK_NUM (insn_set)) + { /* Since insn_set cannot be deleted stop optimization */ + rinfo[regnum].insn_set = NULL; + return; + } + emit_insn_before ( + copy_rtx (PATTERN (insn_set)), + insn); + + if (REG_NOTES (insn_set)) + { + REG_NOTES (PREV_INSN (insn)) + = copy_rtx (REG_NOTES (insn_set)); + } + LOG_LINKS (insn) + = gen_rtx (INSN_LIST, VOIDmode, PREV_INSN (insn), + LOG_LINKS (insn)); + if (find_insn_list (insn_set, + LOG_LINKS (insn))) + remove_dependence (insn, insn_set); + rinfo[regnum].num_uses_copied += regs_in_body[regnum]; + my_reg_n_sets[regnum]++; + if (dump_file) + { + fprintf (dump_file, + " copy insn %d to before insn %d\n", + INSN_UID (insn_set), INSN_UID (insn)); + } + if (rinfo[regnum].num_uses_copied == reg_n_uses[regnum]) + { /* insn_set is no longer relevant - delete it */ + rinfo[regnum].insn_set = NULL; + PUT_CODE (insn_set, NOTE); + NOTE_LINE_NUMBER (insn_set) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (insn_set) = 0; + if (dump_file) + { + fprintf (dump_file, + " delete insn %d \n", + INSN_UID (insn_set)); + } + reg_n_sets[regnum]--; + } + /* If insn was a basic block head then now the copy is + the basic block head. */ + for (i = 0; i < n_basic_blocks; i++) + { + if (basic_block_head[i] == insn) + { + basic_block_head[i] = PREV_INSN (insn); + break; + } + } + +} + +/* intel2 */ +/* Call flow_analysis without changing insns, and if save_pseudo is set, saves + the basic_block_live_at_start information, concerning the pseudo registers, + and restores it after flow_analysis. */ + +void +hard_reg_flow_analysis (f, file, save_pseudo) + rtx f; + FILE *file; + int save_pseudo; +{ + int limit; + register int block, regno; + + /* Element N is a regset describing the registers live + at the start of basic block N, as was saved before the call to + flow_analysis. We use it to restore the contents of the pseudo registers, + needed by other phases. */ + + regset *basic_block_live_at_start_saved; + +#if 0 + register int j; +#endif + + if (save_pseudo) + { + int regset_size = ((max_regno + REGSET_ELT_BITS - 1) / REGSET_ELT_BITS); + int regset_bytes = regset_size * sizeof (*(regset)0); + basic_block_live_at_start_saved = + (regset *) alloca (n_basic_blocks * sizeof (regset)); + /* copy basic_block_live_at_start to basic_block_live_at_start_saved */ + for (block = 0; block < n_basic_blocks; block++) + { + basic_block_live_at_start_saved[block] = (regset) alloca (regset_bytes); + bcopy (basic_block_live_at_start[block], + basic_block_live_at_start_saved[block], + regset_bytes); + } + +#if 0 + /* Check if copy is o.k. */ + if (file) + { + fprintf (file, "Pseudo registers live at start:\n"); + + for (block = 0; block < n_basic_blocks; block++) + { + fprintf (file, "\nBlock no. %d original:", block); + + for (regno = FIRST_PSEUDO_REGISTER; regno < max_regno; regno++) + { + register int offset = regno / REGSET_ELT_BITS; + register REGSET_ELT_TYPE bit + = (REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS); + if ((basic_block_live_at_start_saved[block][offset] & bit) + ^ (basic_block_live_at_start[block][offset] & bit)) + { + fprintf (file, "\nERROR: differnt values in regsets!\n"); + fprintf (file, + "original: %d, saved: %d\n", + basic_block_live_at_start[block][offset], + basic_block_live_at_start_saved[block][offset]); + abort (); + } + if (basic_block_live_at_start[block][offset] & bit) + fprintf (file, " %d", regno); + } + fprintf (file, "\nSaved:"); + for (regno = FIRST_PSEUDO_REGISTER; regno < max_regno; regno++) + { + register int offset = regno / REGSET_ELT_BITS; + register REGSET_ELT_TYPE bit + = (REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS); + + if (basic_block_live_at_start_saved[block][offset] & bit) + fprintf (file, " %d", regno); + } + fprintf (file, "\n"); + } /* for (block = 0; block < n_basic_blocks; block++) */ + } /* if (file) */ +#endif + } /* if (save_pseudo) */ + + limit = max_reg_num (); + + /* Do control and data flow analysis, and write the results to the dump + * file, if dump wanted. + */ + flow_analysis (f, limit, file, 0 /* do not allow a change to the insns */ ); + + if (save_pseudo) + { + /* restore the contents of pseudo registers if basic_block_live_at_start */ + for (block = 0; block < n_basic_blocks; block++) + { + for (regno = FIRST_PSEUDO_REGISTER; regno < max_regno; regno++) + { + register int offset = regno / REGSET_ELT_BITS; + register REGSET_ELT_TYPE bit + = (REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS); + + if (basic_block_live_at_start_saved[block][offset] & bit) + basic_block_live_at_start[block][offset] |= bit; + else + basic_block_live_at_start[block][offset] &= ~bit; + } + } + +#if 0 + /* Check if copy is o.k. */ + if (file) + { + fprintf (file, "Pseudo registers live at start - restored :\n"); + + for (block = 0; block < n_basic_blocks; block++) + { + fprintf (file, "Block no. %d:", block); + for (regno = FIRST_PSEUDO_REGISTER; regno < max_regno; regno++) + { + register int offset = regno / REGSET_ELT_BITS; + register REGSET_ELT_TYPE bit + = (REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS); + if (basic_block_live_at_start[block][offset] & bit) + fprintf (file, " %d", regno); + } + fprintf (file, "\n"); + } + } +#endif + } /* if (save_pseudo) */ +} /* hard_reg_flow_analysis (f, file, save_pseudo) */ diff -r -u -H -N gcc-2.6.3/fold-const.c gcc-i2.6.3/fold-const.c --- gcc-2.6.3/fold-const.c Wed Nov 30 19:03:17 1994 +++ gcc-i2.6.3/fold-const.c Wed Feb 15 23:25:35 1995 @@ -3547,7 +3547,12 @@ return fold (build (MINUS_EXPR, type, arg0, TREE_OPERAND (arg1, 0))); else if (! FLOAT_TYPE_P (type)) { - if (integer_zerop (arg1)) + if (integer_zerop (arg1) + /* intel1 if it is pointer_type then removing the + 0 here + will cause references to array[0] not to be marked + as MEM_IN_STRUCT_P. So just leave the + 0 here - it + will be removed when the tree is made into rtl anyway. */ + && TREE_CODE (TREE_TYPE (arg0)) != POINTER_TYPE) return non_lvalue (convert (type, arg0)); /* If we are adding two BIT_AND_EXPR's, both of which are and'ing @@ -3914,6 +3919,31 @@ case FLOOR_DIV_EXPR: case CEIL_DIV_EXPR: case EXACT_DIV_EXPR: + /* intel1 - implemet x/C where c is floating point and a power of two + as x*(1/C) + */ +#ifndef REAL_IS_NOT_DOUBLE + if (HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT + && TREE_CODE (t) == RDIV_EXPR + && TREE_CODE (TREE_TYPE (t)) == REAL_TYPE + && TYPE_NAME (TREE_TYPE (t)) + && TREE_CODE (TYPE_NAME TREE_TYPE (t)) == TYPE_DECL + && TREE_CODE (TREE_OPERAND (t, 1)) == REAL_CST + && TREE_CODE (TREE_TYPE (TREE_OPERAND (t, 1))) == REAL_TYPE + && TYPE_NAME (TREE_TYPE (TREE_OPERAND (t, 1))) + && TREE_CODE (TYPE_NAME (TREE_TYPE (TREE_OPERAND(t, 1))))== TYPE_DE CL + && TREE_REAL_CST (TREE_OPERAND (t, 1)) >= 2.0 + && TREE_REAL_CST (TREE_OPERAND (t, 1)) + ==(double)(REAL_VALUE_UNSIGNED_FIX(TREE_REAL_CST(TREE_OPERAND(t, 1)))) + &&exact_log2(REAL_VALUE_UNSIGNED_FIX(TREE_REAL_CST(TREE_OPERAND(t,1)))) != -1 + ) + { + TREE_SET_CODE (t, MULT_EXPR); + code = TREE_CODE (t); + TREE_REAL_CST (TREE_OPERAND (t, 1)) + = 1.0 / TREE_REAL_CST (TREE_OPERAND (t, 1)); + } +#endif if (integer_onep (arg1)) return non_lvalue (convert (type, arg0)); if (integer_zerop (arg1)) diff -r -u -H -N gcc-2.6.3/gcc.aux gcc-i2.6.3/gcc.aux --- gcc-2.6.3/gcc.aux Fri Nov 11 18:51:12 1994 +++ gcc-i2.6.3/gcc.aux Thu Jul 14 22:14:35 1994 @@ -4,678 +4,672 @@ 'xrdef {Contributors-title}{Contributors to GNU CC} 'xrdef {Contributors-pg}{9} 'xrdef {Contributors-snt}{} -'xrdef {Funding-title}{Funding Free Software} -'xrdef {Funding-pg}{11} -'xrdef {Funding-snt}{Chapter'tie1} 'xrdef {Look and Feel-title}{Protect Your Freedom---Fight ``Look And Feel''} -'xrdef {Look and Feel-pg}{13} -'xrdef {Look and Feel-snt}{Chapter'tie2} +'xrdef {Look and Feel-pg}{11} +'xrdef {Look and Feel-snt}{Chapter'tie1} 'xrdef {G++ and GCC-title}{Compile C, C++, or Objective C} -'xrdef {G++ and GCC-pg}{17} -'xrdef {G++ and GCC-snt}{Chapter'tie3} +'xrdef {G++ and GCC-pg}{15} +'xrdef {G++ and GCC-snt}{Chapter'tie2} 'xrdef {Invoking GCC-title}{GNU CC Command Options} -'xrdef {Invoking GCC-pg}{19} -'xrdef {Invoking GCC-snt}{Chapter'tie4} +'xrdef {Invoking GCC-pg}{17} +'xrdef {Invoking GCC-snt}{Chapter'tie3} 'xrdef {Option Summary-title}{Option Summary} -'xrdef {Option Summary-pg}{19} -'xrdef {Option Summary-snt}{Section'tie4.1} +'xrdef {Option Summary-pg}{17} +'xrdef {Option Summary-snt}{Section'tie3.1} 'xrdef {Overall Options-title}{Options Controlling the Kind of Output} -'xrdef {Overall Options-pg}{24} -'xrdef {Overall Options-snt}{Section'tie4.2} +'xrdef {Overall Options-pg}{22} +'xrdef {Overall Options-snt}{Section'tie3.2} 'xrdef {Invoking G++-title}{Compiling C++ Programs} -'xrdef {Invoking G++-pg}{26} -'xrdef {Invoking G++-snt}{Section'tie4.3} +'xrdef {Invoking G++-pg}{24} +'xrdef {Invoking G++-snt}{Section'tie3.3} 'xrdef {C Dialect Options-title}{Options Controlling C Dialect} -'xrdef {C Dialect Options-pg}{27} -'xrdef {C Dialect Options-snt}{Section'tie4.4} +'xrdef {C Dialect Options-pg}{25} +'xrdef {C Dialect Options-snt}{Section'tie3.4} 'xrdef {C++ Dialect Options-title}{Options Controlling C++ Dialect} -'xrdef {C++ Dialect Options-pg}{30} -'xrdef {C++ Dialect Options-snt}{Section'tie4.5} +'xrdef {C++ Dialect Options-pg}{28} +'xrdef {C++ Dialect Options-snt}{Section'tie3.5} 'xrdef {Warning Options-title}{Options to Request or Suppress Warnings} -'xrdef {Warning Options-pg}{34} -'xrdef {Warning Options-snt}{Section'tie4.6} +'xrdef {Warning Options-pg}{32} +'xrdef {Warning Options-snt}{Section'tie3.6} 'xrdef {Debugging Options-title}{Options for Debugging Your Program or GNU CC} -'xrdef {Debugging Options-pg}{41} -'xrdef {Debugging Options-snt}{Section'tie4.7} +'xrdef {Debugging Options-pg}{37} +'xrdef {Debugging Options-snt}{Section'tie3.7} 'xrdef {Optimize Options-title}{Options That Control Optimization} -'xrdef {Optimize Options-pg}{44} -'xrdef {Optimize Options-snt}{Section'tie4.8} +'xrdef {Optimize Options-pg}{41} +'xrdef {Optimize Options-snt}{Section'tie3.8} 'xrdef {Preprocessor Options-title}{Options Controlling the Preprocessor} -'xrdef {Preprocessor Options-pg}{48} -'xrdef {Preprocessor Options-snt}{Section'tie4.9} +'xrdef {Preprocessor Options-pg}{45} +'xrdef {Preprocessor Options-snt}{Section'tie3.9} 'xrdef {Assembler Options-title}{Passing Options to the Assembler} -'xrdef {Assembler Options-pg}{51} -'xrdef {Assembler Options-snt}{Section'tie4.10} +'xrdef {Assembler Options-pg}{48} +'xrdef {Assembler Options-snt}{Section'tie3.10} 'xrdef {Link Options-title}{Options for Linking} -'xrdef {Link Options-pg}{51} -'xrdef {Link Options-snt}{Section'tie4.11} +'xrdef {Link Options-pg}{48} +'xrdef {Link Options-snt}{Section'tie3.11} 'xrdef {Directory Options-title}{Options for Directory Search} -'xrdef {Directory Options-pg}{53} -'xrdef {Directory Options-snt}{Section'tie4.12} +'xrdef {Directory Options-pg}{50} +'xrdef {Directory Options-snt}{Section'tie3.12} 'xrdef {Target Options-title}{Specifying Target Machine and Compiler Version} -'xrdef {Target Options-pg}{54} -'xrdef {Target Options-snt}{Section'tie4.13} +'xrdef {Target Options-pg}{51} +'xrdef {Target Options-snt}{Section'tie3.13} 'xrdef {Submodel Options-title}{Hardware Models and Configurations} -'xrdef {Submodel Options-pg}{56} -'xrdef {Submodel Options-snt}{Section'tie4.14} +'xrdef {Submodel Options-pg}{52} +'xrdef {Submodel Options-snt}{Section'tie3.14} 'xrdef {M680x0 Options-title}{M680x0 Options} -'xrdef {M680x0 Options-pg}{56} -'xrdef {M680x0 Options-snt}{Section'tie4.14.1} +'xrdef {M680x0 Options-pg}{53} +'xrdef {M680x0 Options-snt}{Section'tie3.14.1} 'xrdef {VAX Options-title}{VAX Options} -'xrdef {VAX Options-pg}{57} -'xrdef {VAX Options-snt}{Section'tie4.14.2} +'xrdef {VAX Options-pg}{54} +'xrdef {VAX Options-snt}{Section'tie3.14.2} 'xrdef {SPARC Options-title}{SPARC Options} -'xrdef {SPARC Options-pg}{58} -'xrdef {SPARC Options-snt}{Section'tie4.14.3} +'xrdef {SPARC Options-pg}{54} +'xrdef {SPARC Options-snt}{Section'tie3.14.3} 'xrdef {Convex Options-title}{Convex Options} -'xrdef {Convex Options-pg}{60} -'xrdef {Convex Options-snt}{Section'tie4.14.4} +'xrdef {Convex Options-pg}{57} +'xrdef {Convex Options-snt}{Section'tie3.14.4} 'xrdef {AMD29K Options-title}{AMD29K Options} -'xrdef {AMD29K Options-pg}{61} -'xrdef {AMD29K Options-snt}{Section'tie4.14.5} +'xrdef {AMD29K Options-pg}{58} +'xrdef {AMD29K Options-snt}{Section'tie3.14.5} 'xrdef {ARM Options-title}{ARM Options} -'xrdef {ARM Options-pg}{63} -'xrdef {ARM Options-snt}{Section'tie4.14.6} +'xrdef {ARM Options-pg}{60} +'xrdef {ARM Options-snt}{Section'tie3.14.6} 'xrdef {M88K Options-title}{M88K Options} -'xrdef {M88K Options-pg}{63} -'xrdef {M88K Options-snt}{Section'tie4.14.7} +'xrdef {M88K Options-pg}{60} +'xrdef {M88K Options-snt}{Section'tie3.14.7} 'xrdef {RS/6000 and PowerPC Options-title}{IBM RS/6000 and PowerPC Options} -'xrdef {RS/6000 and PowerPC Options-pg}{67} -'xrdef {RS/6000 and PowerPC Options-snt}{Section'tie4.14.8} +'xrdef {RS/6000 and PowerPC Options-pg}{63} +'xrdef {RS/6000 and PowerPC Options-snt}{Section'tie3.14.8} 'xrdef {RT Options-title}{IBM RT Options} -'xrdef {RT Options-pg}{69} -'xrdef {RT Options-snt}{Section'tie4.14.9} +'xrdef {RT Options-pg}{65} +'xrdef {RT Options-snt}{Section'tie3.14.9} 'xrdef {MIPS Options-title}{MIPS Options} -'xrdef {MIPS Options-pg}{70} -'xrdef {MIPS Options-snt}{Section'tie4.14.10} +'xrdef {MIPS Options-pg}{66} +'xrdef {MIPS Options-snt}{Section'tie3.14.10} 'xrdef {i386 Options-title}{Intel 386 Options} -'xrdef {i386 Options-pg}{73} -'xrdef {i386 Options-snt}{Section'tie4.14.11} +'xrdef {i386 Options-pg}{69} +'xrdef {i386 Options-snt}{Section'tie3.14.11} 'xrdef {HPPA Options-title}{HPPA Options} -'xrdef {HPPA Options-pg}{74} -'xrdef {HPPA Options-snt}{Section'tie4.14.12} +'xrdef {HPPA Options-pg}{70} +'xrdef {HPPA Options-snt}{Section'tie3.14.12} 'xrdef {Intel 960 Options-title}{Intel 960 Options} -'xrdef {Intel 960 Options-pg}{75} -'xrdef {Intel 960 Options-snt}{Section'tie4.14.13} +'xrdef {Intel 960 Options-pg}{71} +'xrdef {Intel 960 Options-snt}{Section'tie3.14.13} 'xrdef {DEC Alpha Options-title}{DEC Alpha Options} -'xrdef {DEC Alpha Options-pg}{76} -'xrdef {DEC Alpha Options-snt}{Section'tie4.14.14} +'xrdef {DEC Alpha Options-pg}{72} +'xrdef {DEC Alpha Options-snt}{Section'tie3.14.14} 'xrdef {Clipper Options-title}{Clipper Options} -'xrdef {Clipper Options-pg}{77} -'xrdef {Clipper Options-snt}{Section'tie4.14.15} +'xrdef {Clipper Options-pg}{73} +'xrdef {Clipper Options-snt}{Section'tie3.14.15} 'xrdef {H8/300 Options-title}{H8/300 Options} -'xrdef {H8/300 Options-pg}{77} -'xrdef {H8/300 Options-snt}{Section'tie4.14.16} +'xrdef {H8/300 Options-pg}{73} +'xrdef {H8/300 Options-snt}{Section'tie3.14.16} 'xrdef {System V Options-title}{Options for System V} -'xrdef {System V Options-pg}{78} -'xrdef {System V Options-snt}{Section'tie4.14.17} +'xrdef {System V Options-pg}{73} +'xrdef {System V Options-snt}{Section'tie3.14.17} 'xrdef {Code Gen Options-title}{Options for Code Generation Conventions} -'xrdef {Code Gen Options-pg}{78} -'xrdef {Code Gen Options-snt}{Section'tie4.15} +'xrdef {Code Gen Options-pg}{74} +'xrdef {Code Gen Options-snt}{Section'tie3.15} 'xrdef {Environment Variables-title}{Environment Variables Affecting GNU CC} -'xrdef {Environment Variables-pg}{81} -'xrdef {Environment Variables-snt}{Section'tie4.16} +'xrdef {Environment Variables-pg}{77} +'xrdef {Environment Variables-snt}{Section'tie3.16} 'xrdef {Running Protoize-title}{Running Protoize} -'xrdef {Running Protoize-pg}{83} -'xrdef {Running Protoize-snt}{Section'tie4.17} +'xrdef {Running Protoize-pg}{78} +'xrdef {Running Protoize-snt}{Section'tie3.17} 'xrdef {Installation-title}{Installing GNU CC} -'xrdef {Installation-pg}{87} -'xrdef {Installation-snt}{Chapter'tie5} +'xrdef {Installation-pg}{83} +'xrdef {Installation-snt}{Chapter'tie4} 'xrdef {Configurations-title}{Configurations Supported by GNU CC} -'xrdef {Configurations-pg}{93} -'xrdef {Configurations-snt}{Section'tie5.1} +'xrdef {Configurations-pg}{89} +'xrdef {Configurations-snt}{Section'tie4.1} 'xrdef {Other Dir-title}{Compilation in a Separate Directory} -'xrdef {Other Dir-pg}{106} -'xrdef {Other Dir-snt}{Section'tie5.2} +'xrdef {Other Dir-pg}{101} +'xrdef {Other Dir-snt}{Section'tie4.2} 'xrdef {Cross-Compiler-title}{Building and Installing a Cross-Compiler} -'xrdef {Cross-Compiler-pg}{106} -'xrdef {Cross-Compiler-snt}{Section'tie5.3} +'xrdef {Cross-Compiler-pg}{102} +'xrdef {Cross-Compiler-snt}{Section'tie4.3} 'xrdef {Steps of Cross-title}{Steps of Cross-Compilation} -'xrdef {Steps of Cross-pg}{107} -'xrdef {Steps of Cross-snt}{Section'tie5.3.1} +'xrdef {Steps of Cross-pg}{102} +'xrdef {Steps of Cross-snt}{Section'tie4.3.1} 'xrdef {Configure Cross-title}{Configuring a Cross-Compiler} -'xrdef {Configure Cross-pg}{107} -'xrdef {Configure Cross-snt}{Section'tie5.3.2} +'xrdef {Configure Cross-pg}{103} +'xrdef {Configure Cross-snt}{Section'tie4.3.2} 'xrdef {Tools and Libraries-title}{Tools and Libraries for a Cross-Compiler} -'xrdef {Tools and Libraries-pg}{108} -'xrdef {Tools and Libraries-snt}{Section'tie5.3.3} +'xrdef {Tools and Libraries-pg}{103} +'xrdef {Tools and Libraries-snt}{Section'tie4.3.3} 'xrdef {Cross Runtime-title}{\file {libgcc.a} and Cross-Compilers} -'xrdef {Cross Runtime-pg}{109} -'xrdef {Cross Runtime-snt}{Section'tie5.3.4} +'xrdef {Cross Runtime-pg}{104} +'xrdef {Cross Runtime-snt}{Section'tie4.3.4} 'xrdef {Cross Headers-title}{Cross-Compilers and Header Files} -'xrdef {Cross Headers-pg}{111} -'xrdef {Cross Headers-snt}{Section'tie5.3.5} +'xrdef {Cross Headers-pg}{106} +'xrdef {Cross Headers-snt}{Section'tie4.3.5} 'xrdef {Build Cross-title}{Actually Building the Cross-Compiler} -'xrdef {Build Cross-pg}{112} -'xrdef {Build Cross-snt}{Section'tie5.3.6} +'xrdef {Build Cross-pg}{107} +'xrdef {Build Cross-snt}{Section'tie4.3.6} 'xrdef {Sun Install-title}{Installing GNU CC on the Sun} -'xrdef {Sun Install-pg}{112} -'xrdef {Sun Install-snt}{Section'tie5.4} +'xrdef {Sun Install-pg}{107} +'xrdef {Sun Install-snt}{Section'tie4.4} 'xrdef {VMS Install-title}{Installing GNU CC on VMS} -'xrdef {VMS Install-pg}{113} -'xrdef {VMS Install-snt}{Section'tie5.5} +'xrdef {VMS Install-pg}{108} +'xrdef {VMS Install-snt}{Section'tie4.5} 'xrdef {Collect2-title}{\code {collect2}} -'xrdef {Collect2-pg}{117} -'xrdef {Collect2-snt}{Section'tie5.6} +'xrdef {Collect2-pg}{112} +'xrdef {Collect2-snt}{Section'tie4.6} 'xrdef {Header Dirs-title}{Standard Header File Directories} -'xrdef {Header Dirs-pg}{118} -'xrdef {Header Dirs-snt}{Section'tie5.7} +'xrdef {Header Dirs-pg}{113} +'xrdef {Header Dirs-snt}{Section'tie4.7} 'xrdef {C Extensions-title}{Extensions to the C Language Family} -'xrdef {C Extensions-pg}{119} -'xrdef {C Extensions-snt}{Chapter'tie6} +'xrdef {C Extensions-pg}{115} +'xrdef {C Extensions-snt}{Chapter'tie5} 'xrdef {Statement Exprs-title}{Statements and Declarations in Expressions} -'xrdef {Statement Exprs-pg}{119} -'xrdef {Statement Exprs-snt}{Section'tie6.1} +'xrdef {Statement Exprs-pg}{115} +'xrdef {Statement Exprs-snt}{Section'tie5.1} 'xrdef {Local Labels-title}{Locally Declared Labels} -'xrdef {Local Labels-pg}{120} -'xrdef {Local Labels-snt}{Section'tie6.2} +'xrdef {Local Labels-pg}{116} +'xrdef {Local Labels-snt}{Section'tie5.2} 'xrdef {Labels as Values-title}{Labels as Values} -'xrdef {Labels as Values-pg}{121} -'xrdef {Labels as Values-snt}{Section'tie6.3} +'xrdef {Labels as Values-pg}{117} +'xrdef {Labels as Values-snt}{Section'tie5.3} 'xrdef {Nested Functions-title}{Nested Functions} -'xrdef {Nested Functions-pg}{122} -'xrdef {Nested Functions-snt}{Section'tie6.4} +'xrdef {Nested Functions-pg}{118} +'xrdef {Nested Functions-snt}{Section'tie5.4} 'xrdef {Constructing Calls-title}{Constructing Function Calls} -'xrdef {Constructing Calls-pg}{125} -'xrdef {Constructing Calls-snt}{Section'tie6.5} +'xrdef {Constructing Calls-pg}{121} +'xrdef {Constructing Calls-snt}{Section'tie5.5} 'xrdef {Naming Types-title}{Naming an Expression's Type} -'xrdef {Naming Types-pg}{125} -'xrdef {Naming Types-snt}{Section'tie6.6} +'xrdef {Naming Types-pg}{121} +'xrdef {Naming Types-snt}{Section'tie5.6} 'xrdef {Typeof-title}{Referring to a Type with \code {typeof}} -'xrdef {Typeof-pg}{126} -'xrdef {Typeof-snt}{Section'tie6.7} +'xrdef {Typeof-pg}{122} +'xrdef {Typeof-snt}{Section'tie5.7} 'xrdef {Lvalues-title}{Generalized Lvalues} -'xrdef {Lvalues-pg}{127} -'xrdef {Lvalues-snt}{Section'tie6.8} +'xrdef {Lvalues-pg}{123} +'xrdef {Lvalues-snt}{Section'tie5.8} 'xrdef {Conditionals-title}{Conditionals with Omitted Operands} -'xrdef {Conditionals-pg}{128} -'xrdef {Conditionals-snt}{Section'tie6.9} +'xrdef {Conditionals-pg}{124} +'xrdef {Conditionals-snt}{Section'tie5.9} 'xrdef {Long Long-title}{Double-Word Integers} -'xrdef {Long Long-pg}{129} -'xrdef {Long Long-snt}{Section'tie6.10} +'xrdef {Long Long-pg}{125} +'xrdef {Long Long-snt}{Section'tie5.10} 'xrdef {Complex-title}{Complex Numbers} -'xrdef {Complex-pg}{129} -'xrdef {Complex-snt}{Section'tie6.11} +'xrdef {Complex-pg}{125} +'xrdef {Complex-snt}{Section'tie5.11} 'xrdef {Zero Length-title}{Arrays of Length Zero} -'xrdef {Zero Length-pg}{130} -'xrdef {Zero Length-snt}{Section'tie6.12} +'xrdef {Zero Length-pg}{126} +'xrdef {Zero Length-snt}{Section'tie5.12} 'xrdef {Variable Length-title}{Arrays of Variable Length} -'xrdef {Variable Length-pg}{131} -'xrdef {Variable Length-snt}{Section'tie6.13} +'xrdef {Variable Length-pg}{127} +'xrdef {Variable Length-snt}{Section'tie5.13} 'xrdef {Macro Varargs-title}{Macros with Variable Numbers of Arguments} -'xrdef {Macro Varargs-pg}{132} -'xrdef {Macro Varargs-snt}{Section'tie6.14} +'xrdef {Macro Varargs-pg}{128} +'xrdef {Macro Varargs-snt}{Section'tie5.14} 'xrdef {Subscripting-title}{Non-Lvalue Arrays May Have Subscripts} -'xrdef {Subscripting-pg}{133} -'xrdef {Subscripting-snt}{Section'tie6.15} +'xrdef {Subscripting-pg}{129} +'xrdef {Subscripting-snt}{Section'tie5.15} 'xrdef {Pointer Arith-title}{Arithmetic on \code {void}- and Function-Pointers} -'xrdef {Pointer Arith-pg}{133} -'xrdef {Pointer Arith-snt}{Section'tie6.16} +'xrdef {Pointer Arith-pg}{129} +'xrdef {Pointer Arith-snt}{Section'tie5.16} 'xrdef {Initializers-title}{Non-Constant Initializers} -'xrdef {Initializers-pg}{134} -'xrdef {Initializers-snt}{Section'tie6.17} +'xrdef {Initializers-pg}{130} +'xrdef {Initializers-snt}{Section'tie5.17} 'xrdef {Constructors-title}{Constructor Expressions} -'xrdef {Constructors-pg}{134} -'xrdef {Constructors-snt}{Section'tie6.18} +'xrdef {Constructors-pg}{130} +'xrdef {Constructors-snt}{Section'tie5.18} 'xrdef {Labeled Elements-title}{Labeled Elements in Initializers} -'xrdef {Labeled Elements-pg}{135} -'xrdef {Labeled Elements-snt}{Section'tie6.19} +'xrdef {Labeled Elements-pg}{131} +'xrdef {Labeled Elements-snt}{Section'tie5.19} 'xrdef {Case Ranges-title}{Case Ranges} -'xrdef {Case Ranges-pg}{137} -'xrdef {Case Ranges-snt}{Section'tie6.20} +'xrdef {Case Ranges-pg}{133} +'xrdef {Case Ranges-snt}{Section'tie5.20} 'xrdef {Cast to Union-title}{Cast to a Union Type} -'xrdef {Cast to Union-pg}{137} -'xrdef {Cast to Union-snt}{Section'tie6.21} +'xrdef {Cast to Union-pg}{133} +'xrdef {Cast to Union-snt}{Section'tie5.21} 'xrdef {Function Attributes-title}{Declaring Attributes of Functions} -'xrdef {Function Attributes-pg}{138} -'xrdef {Function Attributes-snt}{Section'tie6.22} +'xrdef {Function Attributes-pg}{134} +'xrdef {Function Attributes-snt}{Section'tie5.22} 'xrdef {Function Prototypes-title}{Prototypes and Old-Style Function Definitions} -'xrdef {Function Prototypes-pg}{141} -'xrdef {Function Prototypes-snt}{Section'tie6.23} +'xrdef {Function Prototypes-pg}{137} +'xrdef {Function Prototypes-snt}{Section'tie5.23} 'xrdef {Dollar Signs-title}{Dollar Signs in Identifier Names} -'xrdef {Dollar Signs-pg}{142} -'xrdef {Dollar Signs-snt}{Section'tie6.24} +'xrdef {Dollar Signs-pg}{138} +'xrdef {Dollar Signs-snt}{Section'tie5.24} 'xrdef {Character Escapes-title}{The Character \key {ESC} in Constants} -'xrdef {Character Escapes-pg}{142} -'xrdef {Character Escapes-snt}{Section'tie6.25} +'xrdef {Character Escapes-pg}{138} +'xrdef {Character Escapes-snt}{Section'tie5.25} 'xrdef {Alignment-title}{Inquiring on Alignment of Types or Variables} -'xrdef {Alignment-pg}{143} -'xrdef {Alignment-snt}{Section'tie6.26} +'xrdef {Alignment-pg}{139} +'xrdef {Alignment-snt}{Section'tie5.26} 'xrdef {Variable Attributes-title}{Specifying Attributes of Variables} -'xrdef {Variable Attributes-pg}{143} -'xrdef {Variable Attributes-snt}{Section'tie6.27} +'xrdef {Variable Attributes-pg}{139} +'xrdef {Variable Attributes-snt}{Section'tie5.27} 'xrdef {Inline-title}{An Inline Function is As Fast As a Macro} -'xrdef {Inline-pg}{146} -'xrdef {Inline-snt}{Section'tie6.28} +'xrdef {Inline-pg}{141} +'xrdef {Inline-snt}{Section'tie5.28} 'xrdef {Extended Asm-title}{Assembler Instructions with C Expression Operands} -'xrdef {Extended Asm-pg}{147} -'xrdef {Extended Asm-snt}{Section'tie6.29} +'xrdef {Extended Asm-pg}{143} +'xrdef {Extended Asm-snt}{Section'tie5.29} 'xrdef {Asm Labels-title}{Controlling Names Used in Assembler Code} -'xrdef {Asm Labels-pg}{151} -'xrdef {Asm Labels-snt}{Section'tie6.30} +'xrdef {Asm Labels-pg}{147} +'xrdef {Asm Labels-snt}{Section'tie5.30} 'xrdef {Explicit Reg Vars-title}{Variables in Specified Registers} -'xrdef {Explicit Reg Vars-pg}{152} -'xrdef {Explicit Reg Vars-snt}{Section'tie6.31} +'xrdef {Explicit Reg Vars-pg}{148} +'xrdef {Explicit Reg Vars-snt}{Section'tie5.31} 'xrdef {Global Reg Vars-title}{Defining Global Register Variables} -'xrdef {Global Reg Vars-pg}{153} -'xrdef {Global Reg Vars-snt}{Section'tie6.31.1} +'xrdef {Global Reg Vars-pg}{148} +'xrdef {Global Reg Vars-snt}{Section'tie5.31.1} 'xrdef {Local Reg Vars-title}{Specifying Registers for Local Variables} -'xrdef {Local Reg Vars-pg}{154} -'xrdef {Local Reg Vars-snt}{Section'tie6.31.2} +'xrdef {Local Reg Vars-pg}{150} +'xrdef {Local Reg Vars-snt}{Section'tie5.31.2} 'xrdef {Alternate Keywords-title}{Alternate Keywords} -'xrdef {Alternate Keywords-pg}{155} -'xrdef {Alternate Keywords-snt}{Section'tie6.32} +'xrdef {Alternate Keywords-pg}{151} +'xrdef {Alternate Keywords-snt}{Section'tie5.32} 'xrdef {Incomplete Enums-title}{Incomplete \code {enum} Types} -'xrdef {Incomplete Enums-pg}{156} -'xrdef {Incomplete Enums-snt}{Section'tie6.33} +'xrdef {Incomplete Enums-pg}{152} +'xrdef {Incomplete Enums-snt}{Section'tie5.33} 'xrdef {Function Names-title}{Function Names as Strings} -'xrdef {Function Names-pg}{156} -'xrdef {Function Names-snt}{Section'tie6.34} +'xrdef {Function Names-pg}{152} +'xrdef {Function Names-snt}{Section'tie5.34} 'xrdef {C++ Extensions-title}{Extensions to the C++ Language} -'xrdef {C++ Extensions-pg}{159} -'xrdef {C++ Extensions-snt}{Chapter'tie7} +'xrdef {C++ Extensions-pg}{155} +'xrdef {C++ Extensions-snt}{Chapter'tie6} 'xrdef {Naming Results-title}{Named Return Values in C++} -'xrdef {Naming Results-pg}{159} -'xrdef {Naming Results-snt}{Section'tie7.1} +'xrdef {Naming Results-pg}{155} +'xrdef {Naming Results-snt}{Section'tie6.1} 'xrdef {Min and Max-title}{Minimum and Maximum Operators in C++} -'xrdef {Min and Max-pg}{161} -'xrdef {Min and Max-snt}{Section'tie7.2} +'xrdef {Min and Max-pg}{157} +'xrdef {Min and Max-snt}{Section'tie6.2} 'xrdef {Destructors and Goto-title}{\code {goto} and Destructors in GNU C++} -'xrdef {Destructors and Goto-pg}{162} -'xrdef {Destructors and Goto-snt}{Section'tie7.3} +'xrdef {Destructors and Goto-pg}{158} +'xrdef {Destructors and Goto-snt}{Section'tie6.3} 'xrdef {C++ Interface-title}{Declarations and Definitions in One Header} -'xrdef {C++ Interface-pg}{162} -'xrdef {C++ Interface-snt}{Section'tie7.4} -'xrdef {Template Instantiation-title}{Where's the Template?} -'xrdef {Template Instantiation-pg}{164} -'xrdef {Template Instantiation-snt}{Section'tie7.5} +'xrdef {C++ Interface-pg}{158} +'xrdef {C++ Interface-snt}{Section'tie6.4} 'xrdef {C++ Signatures-title}{Type Abstraction using Signatures} -'xrdef {C++ Signatures-pg}{166} -'xrdef {C++ Signatures-snt}{Section'tie7.6} +'xrdef {C++ Signatures-pg}{160} +'xrdef {C++ Signatures-snt}{Section'tie6.5} 'xrdef {Trouble-title}{Known Causes of Trouble with GNU CC} -'xrdef {Trouble-pg}{169} -'xrdef {Trouble-snt}{Chapter'tie8} +'xrdef {Trouble-pg}{163} +'xrdef {Trouble-snt}{Chapter'tie7} 'xrdef {Actual Bugs-title}{Actual Bugs We Haven't Fixed Yet} -'xrdef {Actual Bugs-pg}{169} -'xrdef {Actual Bugs-snt}{Section'tie8.1} +'xrdef {Actual Bugs-pg}{163} +'xrdef {Actual Bugs-snt}{Section'tie7.1} 'xrdef {Installation Problems-title}{Installation Problems} -'xrdef {Installation Problems-pg}{169} -'xrdef {Installation Problems-snt}{Section'tie8.2} +'xrdef {Installation Problems-pg}{163} +'xrdef {Installation Problems-snt}{Section'tie7.2} 'xrdef {Cross-Compiler Problems-title}{Cross-Compiler Problems} -'xrdef {Cross-Compiler Problems-pg}{174} -'xrdef {Cross-Compiler Problems-snt}{Section'tie8.3} +'xrdef {Cross-Compiler Problems-pg}{168} +'xrdef {Cross-Compiler Problems-snt}{Section'tie7.3} 'xrdef {Interoperation-title}{Interoperation} -'xrdef {Interoperation-pg}{175} -'xrdef {Interoperation-snt}{Section'tie8.4} +'xrdef {Interoperation-pg}{168} +'xrdef {Interoperation-snt}{Section'tie7.4} 'xrdef {External Bugs-title}{Problems Compiling Certain Programs} -'xrdef {External Bugs-pg}{179} -'xrdef {External Bugs-snt}{Section'tie8.5} +'xrdef {External Bugs-pg}{173} +'xrdef {External Bugs-snt}{Section'tie7.5} 'xrdef {Incompatibilities-title}{Incompatibilities of GNU CC} -'xrdef {Incompatibilities-pg}{180} -'xrdef {Incompatibilities-snt}{Section'tie8.6} +'xrdef {Incompatibilities-pg}{174} +'xrdef {Incompatibilities-snt}{Section'tie7.6} 'xrdef {Fixed Headers-title}{Fixed Header Files} -'xrdef {Fixed Headers-pg}{183} -'xrdef {Fixed Headers-snt}{Section'tie8.7} +'xrdef {Fixed Headers-pg}{177} +'xrdef {Fixed Headers-snt}{Section'tie7.7} 'xrdef {Disappointments-title}{Disappointments and Misunderstandings} -'xrdef {Disappointments-pg}{184} -'xrdef {Disappointments-snt}{Section'tie8.8} +'xrdef {Disappointments-pg}{178} +'xrdef {Disappointments-snt}{Section'tie7.8} 'xrdef {C++ Misunderstandings-title}{Common Misunderstandings with GNU C++} -'xrdef {C++ Misunderstandings-pg}{185} -'xrdef {C++ Misunderstandings-snt}{Section'tie8.9} +'xrdef {C++ Misunderstandings-pg}{179} +'xrdef {C++ Misunderstandings-snt}{Section'tie7.9} 'xrdef {Static Definitions-title}{Declare \emph {and} Define Static Members} -'xrdef {Static Definitions-pg}{186} -'xrdef {Static Definitions-snt}{Section'tie8.9.1} +'xrdef {Static Definitions-pg}{180} +'xrdef {Static Definitions-snt}{Section'tie7.9.1} 'xrdef {Temporaries-title}{Temporaries May Vanish Before You Expect} -'xrdef {Temporaries-pg}{186} -'xrdef {Temporaries-snt}{Section'tie8.9.2} +'xrdef {Temporaries-pg}{180} +'xrdef {Temporaries-snt}{Section'tie7.9.2} 'xrdef {Protoize Caveats-title}{Caveats of using \code {protoize}} -'xrdef {Protoize Caveats-pg}{187} -'xrdef {Protoize Caveats-snt}{Section'tie8.10} +'xrdef {Protoize Caveats-pg}{181} +'xrdef {Protoize Caveats-snt}{Section'tie7.10} 'xrdef {Non-bugs-title}{Certain Changes We Don't Want to Make} -'xrdef {Non-bugs-pg}{188} -'xrdef {Non-bugs-snt}{Section'tie8.11} +'xrdef {Non-bugs-pg}{182} +'xrdef {Non-bugs-snt}{Section'tie7.11} 'xrdef {Warnings and Errors-title}{Warning Messages and Error Messages} -'xrdef {Warnings and Errors-pg}{191} -'xrdef {Warnings and Errors-snt}{Section'tie8.12} +'xrdef {Warnings and Errors-pg}{186} +'xrdef {Warnings and Errors-snt}{Section'tie7.12} 'xrdef {Bugs-title}{Reporting Bugs} -'xrdef {Bugs-pg}{193} -'xrdef {Bugs-snt}{Chapter'tie9} +'xrdef {Bugs-pg}{187} +'xrdef {Bugs-snt}{Chapter'tie8} 'xrdef {Bug Criteria-title}{Have You Found a Bug?} -'xrdef {Bug Criteria-pg}{193} -'xrdef {Bug Criteria-snt}{Section'tie9.1} +'xrdef {Bug Criteria-pg}{187} +'xrdef {Bug Criteria-snt}{Section'tie8.1} 'xrdef {Bug Lists-title}{Where to Report Bugs} -'xrdef {Bug Lists-pg}{194} -'xrdef {Bug Lists-snt}{Section'tie9.2} +'xrdef {Bug Lists-pg}{188} +'xrdef {Bug Lists-snt}{Section'tie8.2} 'xrdef {Bug Reporting-title}{How to Report Bugs} -'xrdef {Bug Reporting-pg}{195} -'xrdef {Bug Reporting-snt}{Section'tie9.3} +'xrdef {Bug Reporting-pg}{189} +'xrdef {Bug Reporting-snt}{Section'tie8.3} 'xrdef {Sending Patches-title}{Sending Patches for GNU CC} -'xrdef {Sending Patches-pg}{199} -'xrdef {Sending Patches-snt}{Section'tie9.4} +'xrdef {Sending Patches-pg}{193} +'xrdef {Sending Patches-snt}{Section'tie8.4} 'xrdef {Service-title}{How To Get Help with GNU CC} -'xrdef {Service-pg}{203} -'xrdef {Service-snt}{Chapter'tie10} +'xrdef {Service-pg}{197} +'xrdef {Service-snt}{Chapter'tie9} 'xrdef {VMS-title}{Using GNU CC on VMS} -'xrdef {VMS-pg}{205} -'xrdef {VMS-snt}{Chapter'tie11} +'xrdef {VMS-pg}{199} +'xrdef {VMS-snt}{Chapter'tie10} 'xrdef {Include Files and VMS-title}{Include Files and VMS} -'xrdef {Include Files and VMS-pg}{205} -'xrdef {Include Files and VMS-snt}{Section'tie11.1} +'xrdef {Include Files and VMS-pg}{199} +'xrdef {Include Files and VMS-snt}{Section'tie10.1} 'xrdef {Global Declarations-title}{Global Declarations and VMS} -'xrdef {Global Declarations-pg}{206} -'xrdef {Global Declarations-snt}{Section'tie11.2} +'xrdef {Global Declarations-pg}{200} +'xrdef {Global Declarations-snt}{Section'tie10.2} 'xrdef {VMS Misc-title}{Other VMS Issues} -'xrdef {VMS Misc-pg}{209} -'xrdef {VMS Misc-snt}{Section'tie11.3} +'xrdef {VMS Misc-pg}{203} +'xrdef {VMS Misc-snt}{Section'tie10.3} 'xrdef {Portability-title}{GNU CC and Portability} -'xrdef {Portability-pg}{211} -'xrdef {Portability-snt}{Chapter'tie12} +'xrdef {Portability-pg}{205} +'xrdef {Portability-snt}{Chapter'tie11} 'xrdef {Interface-title}{Interfacing to GNU CC Output} -'xrdef {Interface-pg}{213} -'xrdef {Interface-snt}{Chapter'tie13} +'xrdef {Interface-pg}{207} +'xrdef {Interface-snt}{Chapter'tie12} 'xrdef {Passes-title}{Passes and Files of the Compiler} -'xrdef {Passes-pg}{215} -'xrdef {Passes-snt}{Chapter'tie14} +'xrdef {Passes-pg}{209} +'xrdef {Passes-snt}{Chapter'tie13} 'xrdef {RTL-title}{RTL Representation} -'xrdef {RTL-pg}{221} -'xrdef {RTL-snt}{Chapter'tie15} +'xrdef {RTL-pg}{215} +'xrdef {RTL-snt}{Chapter'tie14} 'xrdef {RTL Objects-title}{RTL Object Types} -'xrdef {RTL Objects-pg}{221} -'xrdef {RTL Objects-snt}{Section'tie15.1} +'xrdef {RTL Objects-pg}{215} +'xrdef {RTL Objects-snt}{Section'tie14.1} 'xrdef {Accessors-title}{Access to Operands} -'xrdef {Accessors-pg}{222} -'xrdef {Accessors-snt}{Section'tie15.2} +'xrdef {Accessors-pg}{216} +'xrdef {Accessors-snt}{Section'tie14.2} 'xrdef {Flags-title}{Flags in an RTL Expression} -'xrdef {Flags-pg}{225} -'xrdef {Flags-snt}{Section'tie15.3} +'xrdef {Flags-pg}{219} +'xrdef {Flags-snt}{Section'tie14.3} 'xrdef {Machine Modes-title}{Machine Modes} -'xrdef {Machine Modes-pg}{228} -'xrdef {Machine Modes-snt}{Section'tie15.4} +'xrdef {Machine Modes-pg}{222} +'xrdef {Machine Modes-snt}{Section'tie14.4} 'xrdef {Constants-title}{Constant Expression Types} -'xrdef {Constants-pg}{232} -'xrdef {Constants-snt}{Section'tie15.5} +'xrdef {Constants-pg}{226} +'xrdef {Constants-snt}{Section'tie14.5} 'xrdef {Regs and Memory-title}{Registers and Memory} -'xrdef {Regs and Memory-pg}{234} -'xrdef {Regs and Memory-snt}{Section'tie15.6} +'xrdef {Regs and Memory-pg}{228} +'xrdef {Regs and Memory-snt}{Section'tie14.6} 'xrdef {Arithmetic-title}{RTL Expressions for Arithmetic} -'xrdef {Arithmetic-pg}{238} -'xrdef {Arithmetic-snt}{Section'tie15.7} +'xrdef {Arithmetic-pg}{232} +'xrdef {Arithmetic-snt}{Section'tie14.7} 'xrdef {Comparisons-title}{Comparison Operations} -'xrdef {Comparisons-pg}{241} -'xrdef {Comparisons-snt}{Section'tie15.8} +'xrdef {Comparisons-pg}{235} +'xrdef {Comparisons-snt}{Section'tie14.8} 'xrdef {Bit Fields-title}{Bit Fields} -'xrdef {Bit Fields-pg}{243} -'xrdef {Bit Fields-snt}{Section'tie15.9} +'xrdef {Bit Fields-pg}{237} +'xrdef {Bit Fields-snt}{Section'tie14.9} 'xrdef {Conversions-title}{Conversions} -'xrdef {Conversions-pg}{243} -'xrdef {Conversions-snt}{Section'tie15.10} +'xrdef {Conversions-pg}{237} +'xrdef {Conversions-snt}{Section'tie14.10} 'xrdef {RTL Declarations-title}{Declarations} -'xrdef {RTL Declarations-pg}{244} -'xrdef {RTL Declarations-snt}{Section'tie15.11} +'xrdef {RTL Declarations-pg}{238} +'xrdef {RTL Declarations-snt}{Section'tie14.11} 'xrdef {Side Effects-title}{Side Effect Expressions} -'xrdef {Side Effects-pg}{245} -'xrdef {Side Effects-snt}{Section'tie15.12} +'xrdef {Side Effects-pg}{239} +'xrdef {Side Effects-snt}{Section'tie14.12} 'xrdef {Incdec-title}{Embedded Side-Effects on Addresses} -'xrdef {Incdec-pg}{249} -'xrdef {Incdec-snt}{Section'tie15.13} +'xrdef {Incdec-pg}{243} +'xrdef {Incdec-snt}{Section'tie14.13} 'xrdef {Assembler-title}{Assembler Instructions as Expressions} -'xrdef {Assembler-pg}{250} -'xrdef {Assembler-snt}{Section'tie15.14} +'xrdef {Assembler-pg}{244} +'xrdef {Assembler-snt}{Section'tie14.14} 'xrdef {Insns-title}{Insns} -'xrdef {Insns-pg}{251} -'xrdef {Insns-snt}{Section'tie15.15} +'xrdef {Insns-pg}{245} +'xrdef {Insns-snt}{Section'tie14.15} 'xrdef {Calls-title}{RTL Representation of Function-Call Insns} -'xrdef {Calls-pg}{259} -'xrdef {Calls-snt}{Section'tie15.16} +'xrdef {Calls-pg}{253} +'xrdef {Calls-snt}{Section'tie14.16} 'xrdef {Sharing-title}{Structure Sharing Assumptions} -'xrdef {Sharing-pg}{261} -'xrdef {Sharing-snt}{Section'tie15.17} +'xrdef {Sharing-pg}{255} +'xrdef {Sharing-snt}{Section'tie14.17} 'xrdef {Reading RTL-title}{Reading RTL} -'xrdef {Reading RTL-pg}{262} -'xrdef {Reading RTL-snt}{Section'tie15.18} +'xrdef {Reading RTL-pg}{256} +'xrdef {Reading RTL-snt}{Section'tie14.18} 'xrdef {Machine Desc-title}{Machine Descriptions} -'xrdef {Machine Desc-pg}{263} -'xrdef {Machine Desc-snt}{Chapter'tie16} +'xrdef {Machine Desc-pg}{257} +'xrdef {Machine Desc-snt}{Chapter'tie15} 'xrdef {Patterns-title}{Everything about Instruction Patterns} -'xrdef {Patterns-pg}{263} -'xrdef {Patterns-snt}{Section'tie16.1} +'xrdef {Patterns-pg}{257} +'xrdef {Patterns-snt}{Section'tie15.1} 'xrdef {Example-title}{Example of \code {define_insn}} -'xrdef {Example-pg}{264} -'xrdef {Example-snt}{Section'tie16.2} +'xrdef {Example-pg}{258} +'xrdef {Example-snt}{Section'tie15.2} 'xrdef {RTL Template-title}{RTL Template} -'xrdef {RTL Template-pg}{265} -'xrdef {RTL Template-snt}{Section'tie16.3} +'xrdef {RTL Template-pg}{259} +'xrdef {RTL Template-snt}{Section'tie15.3} 'xrdef {Output Template-title}{Output Templates and Operand Substitution} -'xrdef {Output Template-pg}{269} -'xrdef {Output Template-snt}{Section'tie16.4} +'xrdef {Output Template-pg}{263} +'xrdef {Output Template-snt}{Section'tie15.4} 'xrdef {Output Statement-title}{C Statements for Assembler Output} -'xrdef {Output Statement-pg}{271} -'xrdef {Output Statement-snt}{Section'tie16.5} +'xrdef {Output Statement-pg}{265} +'xrdef {Output Statement-snt}{Section'tie15.5} 'xrdef {Constraints-title}{Operand Constraints} -'xrdef {Constraints-pg}{273} -'xrdef {Constraints-snt}{Section'tie16.6} +'xrdef {Constraints-pg}{267} +'xrdef {Constraints-snt}{Section'tie15.6} 'xrdef {Simple Constraints-title}{Simple Constraints} -'xrdef {Simple Constraints-pg}{273} -'xrdef {Simple Constraints-snt}{Section'tie16.6.1} +'xrdef {Simple Constraints-pg}{267} +'xrdef {Simple Constraints-snt}{Section'tie15.6.1} 'xrdef {Multi-Alternative-title}{Multiple Alternative Constraints} -'xrdef {Multi-Alternative-pg}{277} -'xrdef {Multi-Alternative-snt}{Section'tie16.6.2} +'xrdef {Multi-Alternative-pg}{271} +'xrdef {Multi-Alternative-snt}{Section'tie15.6.2} 'xrdef {Class Preferences-title}{Register Class Preferences} -'xrdef {Class Preferences-pg}{278} -'xrdef {Class Preferences-snt}{Section'tie16.6.3} +'xrdef {Class Preferences-pg}{272} +'xrdef {Class Preferences-snt}{Section'tie15.6.3} 'xrdef {Modifiers-title}{Constraint Modifier Characters} -'xrdef {Modifiers-pg}{279} -'xrdef {Modifiers-snt}{Section'tie16.6.4} +'xrdef {Modifiers-pg}{273} +'xrdef {Modifiers-snt}{Section'tie15.6.4} 'xrdef {Machine Constraints-title}{Constraints for Particular Machines} -'xrdef {Machine Constraints-pg}{280} -'xrdef {Machine Constraints-snt}{Section'tie16.6.5} +'xrdef {Machine Constraints-pg}{274} +'xrdef {Machine Constraints-snt}{Section'tie15.6.5} 'xrdef {No Constraints-title}{Not Using Constraints} -'xrdef {No Constraints-pg}{285} -'xrdef {No Constraints-snt}{Section'tie16.6.6} +'xrdef {No Constraints-pg}{279} +'xrdef {No Constraints-snt}{Section'tie15.6.6} 'xrdef {Standard Names-title}{Standard Pattern Names For Generation} -'xrdef {Standard Names-pg}{286} -'xrdef {Standard Names-snt}{Section'tie16.7} +'xrdef {Standard Names-pg}{280} +'xrdef {Standard Names-snt}{Section'tie15.7} 'xrdef {Pattern Ordering-title}{When the Order of Patterns Matters} -'xrdef {Pattern Ordering-pg}{296} -'xrdef {Pattern Ordering-snt}{Section'tie16.8} +'xrdef {Pattern Ordering-pg}{290} +'xrdef {Pattern Ordering-snt}{Section'tie15.8} 'xrdef {Dependent Patterns-title}{Interdependence of Patterns} -'xrdef {Dependent Patterns-pg}{296} -'xrdef {Dependent Patterns-snt}{Section'tie16.9} +'xrdef {Dependent Patterns-pg}{290} +'xrdef {Dependent Patterns-snt}{Section'tie15.9} 'xrdef {Jump Patterns-title}{Defining Jump Instruction Patterns} -'xrdef {Jump Patterns-pg}{298} -'xrdef {Jump Patterns-snt}{Section'tie16.10} +'xrdef {Jump Patterns-pg}{292} +'xrdef {Jump Patterns-snt}{Section'tie15.10} 'xrdef {Insn Canonicalizations-title}{Canonicalization of Instructions} -'xrdef {Insn Canonicalizations-pg}{300} -'xrdef {Insn Canonicalizations-snt}{Section'tie16.11} +'xrdef {Insn Canonicalizations-pg}{294} +'xrdef {Insn Canonicalizations-snt}{Section'tie15.11} 'xrdef {Peephole Definitions-title}{Machine-Specific Peephole Optimizers} -'xrdef {Peephole Definitions-pg}{301} -'xrdef {Peephole Definitions-snt}{Section'tie16.12} +'xrdef {Peephole Definitions-pg}{295} +'xrdef {Peephole Definitions-snt}{Section'tie15.12} 'xrdef {Expander Definitions-title}{Defining RTL Sequences for Code Generation} -'xrdef {Expander Definitions-pg}{305} -'xrdef {Expander Definitions-snt}{Section'tie16.13} +'xrdef {Expander Definitions-pg}{299} +'xrdef {Expander Definitions-snt}{Section'tie15.13} 'xrdef {Insn Splitting-title}{Defining How to Split Instructions} -'xrdef {Insn Splitting-pg}{308} -'xrdef {Insn Splitting-snt}{Section'tie16.14} +'xrdef {Insn Splitting-pg}{302} +'xrdef {Insn Splitting-snt}{Section'tie15.14} 'xrdef {Insn Attributes-title}{Instruction Attributes} -'xrdef {Insn Attributes-pg}{311} -'xrdef {Insn Attributes-snt}{Section'tie16.15} +'xrdef {Insn Attributes-pg}{305} +'xrdef {Insn Attributes-snt}{Section'tie15.15} 'xrdef {Defining Attributes-title}{Defining Attributes and their Values} -'xrdef {Defining Attributes-pg}{311} -'xrdef {Defining Attributes-snt}{Section'tie16.15.1} +'xrdef {Defining Attributes-pg}{305} +'xrdef {Defining Attributes-snt}{Section'tie15.15.1} 'xrdef {Expressions-title}{Attribute Expressions} -'xrdef {Expressions-pg}{312} -'xrdef {Expressions-snt}{Section'tie16.15.2} +'xrdef {Expressions-pg}{306} +'xrdef {Expressions-snt}{Section'tie15.15.2} 'xrdef {Tagging Insns-title}{Assigning Attribute Values to Insns} -'xrdef {Tagging Insns-pg}{315} -'xrdef {Tagging Insns-snt}{Section'tie16.15.3} +'xrdef {Tagging Insns-pg}{309} +'xrdef {Tagging Insns-snt}{Section'tie15.15.3} 'xrdef {Attr Example-title}{Example of Attribute Specifications} -'xrdef {Attr Example-pg}{317} -'xrdef {Attr Example-snt}{Section'tie16.15.4} +'xrdef {Attr Example-pg}{311} +'xrdef {Attr Example-snt}{Section'tie15.15.4} 'xrdef {Insn Lengths-title}{Computing the Length of an Insn} -'xrdef {Insn Lengths-pg}{318} -'xrdef {Insn Lengths-snt}{Section'tie16.15.5} +'xrdef {Insn Lengths-pg}{312} +'xrdef {Insn Lengths-snt}{Section'tie15.15.5} 'xrdef {Constant Attributes-title}{Constant Attributes} -'xrdef {Constant Attributes-pg}{320} -'xrdef {Constant Attributes-snt}{Section'tie16.15.6} +'xrdef {Constant Attributes-pg}{314} +'xrdef {Constant Attributes-snt}{Section'tie15.15.6} 'xrdef {Delay Slots-title}{Delay Slot Scheduling} -'xrdef {Delay Slots-pg}{320} -'xrdef {Delay Slots-snt}{Section'tie16.15.7} +'xrdef {Delay Slots-pg}{314} +'xrdef {Delay Slots-snt}{Section'tie15.15.7} 'xrdef {Function Units-title}{Specifying Function Units} -'xrdef {Function Units-pg}{322} -'xrdef {Function Units-snt}{Section'tie16.15.8} +'xrdef {Function Units-pg}{316} +'xrdef {Function Units-snt}{Section'tie15.15.8} 'xrdef {Target Macros-title}{Target Description Macros} -'xrdef {Target Macros-pg}{325} -'xrdef {Target Macros-snt}{Chapter'tie17} +'xrdef {Target Macros-pg}{319} +'xrdef {Target Macros-snt}{Chapter'tie16} 'xrdef {Driver-title}{Controlling the Compilation Driver, \file {gcc}} -'xrdef {Driver-pg}{325} -'xrdef {Driver-snt}{Section'tie17.1} +'xrdef {Driver-pg}{319} +'xrdef {Driver-snt}{Section'tie16.1} 'xrdef {Run-time Target-title}{Run-time Target Specification} -'xrdef {Run-time Target-pg}{329} -'xrdef {Run-time Target-snt}{Section'tie17.2} +'xrdef {Run-time Target-pg}{323} +'xrdef {Run-time Target-snt}{Section'tie16.2} 'xrdef {Storage Layout-title}{Storage Layout} -'xrdef {Storage Layout-pg}{332} -'xrdef {Storage Layout-snt}{Section'tie17.3} +'xrdef {Storage Layout-pg}{326} +'xrdef {Storage Layout-snt}{Section'tie16.3} 'xrdef {Type Layout-title}{Layout of Source Language Data Types} -'xrdef {Type Layout-pg}{337} -'xrdef {Type Layout-snt}{Section'tie17.4} +'xrdef {Type Layout-pg}{331} +'xrdef {Type Layout-snt}{Section'tie16.4} 'xrdef {Registers-title}{Register Usage} -'xrdef {Registers-pg}{340} -'xrdef {Registers-snt}{Section'tie17.5} +'xrdef {Registers-pg}{334} +'xrdef {Registers-snt}{Section'tie16.5} 'xrdef {Register Basics-title}{Basic Characteristics of Registers} -'xrdef {Register Basics-pg}{340} -'xrdef {Register Basics-snt}{Section'tie17.5.1} +'xrdef {Register Basics-pg}{334} +'xrdef {Register Basics-snt}{Section'tie16.5.1} 'xrdef {Allocation Order-title}{Order of Allocation of Registers} -'xrdef {Allocation Order-pg}{342} -'xrdef {Allocation Order-snt}{Section'tie17.5.2} +'xrdef {Allocation Order-pg}{336} +'xrdef {Allocation Order-snt}{Section'tie16.5.2} 'xrdef {Values in Registers-title}{How Values Fit in Registers} -'xrdef {Values in Registers-pg}{343} -'xrdef {Values in Registers-snt}{Section'tie17.5.3} +'xrdef {Values in Registers-pg}{336} +'xrdef {Values in Registers-snt}{Section'tie16.5.3} 'xrdef {Leaf Functions-title}{Handling Leaf Functions} -'xrdef {Leaf Functions-pg}{344} -'xrdef {Leaf Functions-snt}{Section'tie17.5.4} +'xrdef {Leaf Functions-pg}{338} +'xrdef {Leaf Functions-snt}{Section'tie16.5.4} 'xrdef {Stack Registers-title}{Registers That Form a Stack} -'xrdef {Stack Registers-pg}{345} -'xrdef {Stack Registers-snt}{Section'tie17.5.5} +'xrdef {Stack Registers-pg}{339} +'xrdef {Stack Registers-snt}{Section'tie16.5.5} 'xrdef {Obsolete Register Macros-title}{Obsolete Macros for Controlling Register Usage} -'xrdef {Obsolete Register Macros-pg}{346} -'xrdef {Obsolete Register Macros-snt}{Section'tie17.5.6} +'xrdef {Obsolete Register Macros-pg}{339} +'xrdef {Obsolete Register Macros-snt}{Section'tie16.5.6} 'xrdef {Register Classes-title}{Register Classes} -'xrdef {Register Classes-pg}{347} -'xrdef {Register Classes-snt}{Section'tie17.6} +'xrdef {Register Classes-pg}{340} +'xrdef {Register Classes-snt}{Section'tie16.6} 'xrdef {Stack and Calling-title}{Stack Layout and Calling Conventions} -'xrdef {Stack and Calling-pg}{353} -'xrdef {Stack and Calling-snt}{Section'tie17.7} +'xrdef {Stack and Calling-pg}{347} +'xrdef {Stack and Calling-snt}{Section'tie16.7} 'xrdef {Frame Layout-title}{Basic Stack Layout} -'xrdef {Frame Layout-pg}{353} -'xrdef {Frame Layout-snt}{Section'tie17.7.1} +'xrdef {Frame Layout-pg}{347} +'xrdef {Frame Layout-snt}{Section'tie16.7.1} 'xrdef {Frame Registers-title}{Registers That Address the Stack Frame} -'xrdef {Frame Registers-pg}{355} -'xrdef {Frame Registers-snt}{Section'tie17.7.2} +'xrdef {Frame Registers-pg}{349} +'xrdef {Frame Registers-snt}{Section'tie16.7.2} 'xrdef {Elimination-title}{Eliminating Frame Pointer and Arg Pointer} -'xrdef {Elimination-pg}{357} -'xrdef {Elimination-snt}{Section'tie17.7.3} +'xrdef {Elimination-pg}{350} +'xrdef {Elimination-snt}{Section'tie16.7.3} 'xrdef {Stack Arguments-title}{Passing Function Arguments on the Stack} -'xrdef {Stack Arguments-pg}{358} -'xrdef {Stack Arguments-snt}{Section'tie17.7.4} +'xrdef {Stack Arguments-pg}{352} +'xrdef {Stack Arguments-snt}{Section'tie16.7.4} 'xrdef {Register Arguments-title}{Passing Arguments in Registers} -'xrdef {Register Arguments-pg}{360} -'xrdef {Register Arguments-snt}{Section'tie17.7.5} +'xrdef {Register Arguments-pg}{354} +'xrdef {Register Arguments-snt}{Section'tie16.7.5} 'xrdef {Scalar Return-title}{How Scalar Function Values Are Returned} -'xrdef {Scalar Return-pg}{363} -'xrdef {Scalar Return-snt}{Section'tie17.7.6} +'xrdef {Scalar Return-pg}{357} +'xrdef {Scalar Return-snt}{Section'tie16.7.6} 'xrdef {Aggregate Return-title}{How Large Values Are Returned} -'xrdef {Aggregate Return-pg}{365} -'xrdef {Aggregate Return-snt}{Section'tie17.7.7} +'xrdef {Aggregate Return-pg}{359} +'xrdef {Aggregate Return-snt}{Section'tie16.7.7} 'xrdef {Caller Saves-title}{Caller-Saves Register Allocation} -'xrdef {Caller Saves-pg}{366} -'xrdef {Caller Saves-snt}{Section'tie17.7.8} +'xrdef {Caller Saves-pg}{360} +'xrdef {Caller Saves-snt}{Section'tie16.7.8} 'xrdef {Function Entry-title}{Function Entry and Exit} -'xrdef {Function Entry-pg}{367} -'xrdef {Function Entry-snt}{Section'tie17.7.9} +'xrdef {Function Entry-pg}{361} +'xrdef {Function Entry-snt}{Section'tie16.7.9} 'xrdef {Profiling-title}{Generating Code for Profiling} -'xrdef {Profiling-pg}{370} -'xrdef {Profiling-snt}{Section'tie17.7.10} +'xrdef {Profiling-pg}{364} +'xrdef {Profiling-snt}{Section'tie16.7.10} 'xrdef {Varargs-title}{Implementing the Varargs Macros} -'xrdef {Varargs-pg}{371} -'xrdef {Varargs-snt}{Section'tie17.8} +'xrdef {Varargs-pg}{365} +'xrdef {Varargs-snt}{Section'tie16.8} 'xrdef {Trampolines-title}{Trampolines for Nested Functions} -'xrdef {Trampolines-pg}{373} -'xrdef {Trampolines-snt}{Section'tie17.9} +'xrdef {Trampolines-pg}{367} +'xrdef {Trampolines-snt}{Section'tie16.9} 'xrdef {Library Calls-title}{Implicit Calls to Library Routines} -'xrdef {Library Calls-pg}{376} -'xrdef {Library Calls-snt}{Section'tie17.10} +'xrdef {Library Calls-pg}{370} +'xrdef {Library Calls-snt}{Section'tie16.10} 'xrdef {Addressing Modes-title}{Addressing Modes} -'xrdef {Addressing Modes-pg}{379} -'xrdef {Addressing Modes-snt}{Section'tie17.11} +'xrdef {Addressing Modes-pg}{373} +'xrdef {Addressing Modes-snt}{Section'tie16.11} 'xrdef {Condition Code-title}{Condition Code Status} -'xrdef {Condition Code-pg}{382} -'xrdef {Condition Code-snt}{Section'tie17.12} +'xrdef {Condition Code-pg}{376} +'xrdef {Condition Code-snt}{Section'tie16.12} 'xrdef {Costs-title}{Describing Relative Costs of Operations} -'xrdef {Costs-pg}{385} -'xrdef {Costs-snt}{Section'tie17.13} +'xrdef {Costs-pg}{378} +'xrdef {Costs-snt}{Section'tie16.13} 'xrdef {Sections-title}{Dividing the Output into Sections (Texts, Data, \dots{})} -'xrdef {Sections-pg}{388} -'xrdef {Sections-snt}{Section'tie17.14} +'xrdef {Sections-pg}{382} +'xrdef {Sections-snt}{Section'tie16.14} 'xrdef {PIC-title}{Position Independent Code} -'xrdef {PIC-pg}{390} -'xrdef {PIC-snt}{Section'tie17.15} +'xrdef {PIC-pg}{383} +'xrdef {PIC-snt}{Section'tie16.15} 'xrdef {Assembler Format-title}{Defining the Output Assembler Language} -'xrdef {Assembler Format-pg}{391} -'xrdef {Assembler Format-snt}{Section'tie17.16} +'xrdef {Assembler Format-pg}{384} +'xrdef {Assembler Format-snt}{Section'tie16.16} 'xrdef {File Framework-title}{The Overall Framework of an Assembler File} -'xrdef {File Framework-pg}{391} -'xrdef {File Framework-snt}{Section'tie17.16.1} +'xrdef {File Framework-pg}{385} +'xrdef {File Framework-snt}{Section'tie16.16.1} 'xrdef {Data Output-title}{Output of Data} -'xrdef {Data Output-pg}{393} -'xrdef {Data Output-snt}{Section'tie17.16.2} +'xrdef {Data Output-pg}{386} +'xrdef {Data Output-snt}{Section'tie16.16.2} 'xrdef {Uninitialized Data-title}{Output of Uninitialized Variables} -'xrdef {Uninitialized Data-pg}{395} -'xrdef {Uninitialized Data-snt}{Section'tie17.16.3} +'xrdef {Uninitialized Data-pg}{389} +'xrdef {Uninitialized Data-snt}{Section'tie16.16.3} 'xrdef {Label Output-title}{Output and Generation of Labels} -'xrdef {Label Output-pg}{396} -'xrdef {Label Output-snt}{Section'tie17.16.4} +'xrdef {Label Output-pg}{390} +'xrdef {Label Output-snt}{Section'tie16.16.4} 'xrdef {Initialization-title}{How Initialization Functions Are Handled} -'xrdef {Initialization-pg}{399} -'xrdef {Initialization-snt}{Section'tie17.16.5} +'xrdef {Initialization-pg}{393} +'xrdef {Initialization-snt}{Section'tie16.16.5} 'xrdef {Macros for Initialization-title}{Macros Controlling Initialization Routines} -'xrdef {Macros for Initialization-pg}{402} -'xrdef {Macros for Initialization-snt}{Section'tie17.16.6} +'xrdef {Macros for Initialization-pg}{395} +'xrdef {Macros for Initialization-snt}{Section'tie16.16.6} 'xrdef {Instruction Output-title}{Output of Assembler Instructions} -'xrdef {Instruction Output-pg}{403} -'xrdef {Instruction Output-snt}{Section'tie17.16.7} +'xrdef {Instruction Output-pg}{397} +'xrdef {Instruction Output-snt}{Section'tie16.16.7} 'xrdef {Dispatch Tables-title}{Output of Dispatch Tables} -'xrdef {Dispatch Tables-pg}{406} -'xrdef {Dispatch Tables-snt}{Section'tie17.16.8} +'xrdef {Dispatch Tables-pg}{400} +'xrdef {Dispatch Tables-snt}{Section'tie16.16.8} 'xrdef {Alignment Output-title}{Assembler Commands for Alignment} -'xrdef {Alignment Output-pg}{407} -'xrdef {Alignment Output-snt}{Section'tie17.16.9} +'xrdef {Alignment Output-pg}{401} +'xrdef {Alignment Output-snt}{Section'tie16.16.9} 'xrdef {Debugging Info-title}{Controlling Debugging Information Format} -'xrdef {Debugging Info-pg}{408} -'xrdef {Debugging Info-snt}{Section'tie17.17} +'xrdef {Debugging Info-pg}{402} +'xrdef {Debugging Info-snt}{Section'tie16.17} 'xrdef {All Debuggers-title}{Macros Affecting All Debugging Formats} -'xrdef {All Debuggers-pg}{408} -'xrdef {All Debuggers-snt}{Section'tie17.17.1} +'xrdef {All Debuggers-pg}{402} +'xrdef {All Debuggers-snt}{Section'tie16.17.1} 'xrdef {DBX Options-title}{Specific Options for DBX Output} -'xrdef {DBX Options-pg}{409} -'xrdef {DBX Options-snt}{Section'tie17.17.2} +'xrdef {DBX Options-pg}{403} +'xrdef {DBX Options-snt}{Section'tie16.17.2} 'xrdef {DBX Hooks-title}{Open-Ended Hooks for DBX Format} -'xrdef {DBX Hooks-pg}{411} -'xrdef {DBX Hooks-snt}{Section'tie17.17.3} +'xrdef {DBX Hooks-pg}{404} +'xrdef {DBX Hooks-snt}{Section'tie16.17.3} 'xrdef {File Names and DBX-title}{File Names in DBX Format} -'xrdef {File Names and DBX-pg}{413} -'xrdef {File Names and DBX-snt}{Section'tie17.17.4} +'xrdef {File Names and DBX-pg}{406} +'xrdef {File Names and DBX-snt}{Section'tie16.17.4} 'xrdef {SDB and DWARF-title}{Macros for SDB and DWARF Output} -'xrdef {SDB and DWARF-pg}{414} -'xrdef {SDB and DWARF-snt}{Section'tie17.17.5} +'xrdef {SDB and DWARF-pg}{407} +'xrdef {SDB and DWARF-snt}{Section'tie16.17.5} 'xrdef {Cross-compilation-title}{Cross Compilation and Floating Point} -'xrdef {Cross-compilation-pg}{415} -'xrdef {Cross-compilation-snt}{Section'tie17.18} +'xrdef {Cross-compilation-pg}{408} +'xrdef {Cross-compilation-snt}{Section'tie16.18} 'xrdef {Misc-title}{Miscellaneous Parameters} -'xrdef {Misc-pg}{417} -'xrdef {Misc-snt}{Section'tie17.19} +'xrdef {Misc-pg}{410} +'xrdef {Misc-snt}{Section'tie16.19} 'xrdef {Config-title}{The Configuration File} -'xrdef {Config-pg}{425} -'xrdef {Config-snt}{Chapter'tie18} +'xrdef {Config-pg}{417} +'xrdef {Config-snt}{Chapter'tie17} 'xrdef {Index-title}{Index} -'xrdef {Index-pg}{429} +'xrdef {Index-pg}{421} 'xrdef {Index-snt}{} diff -r -u -H -N gcc-2.6.3/gcc.cps gcc-i2.6.3/gcc.cps --- gcc-2.6.3/gcc.cps Fri Nov 11 18:44:28 1994 +++ gcc-i2.6.3/gcc.cps Thu Jul 14 22:07:29 1994 @@ -1,1866 +1,1856 @@ \initial {!} -\entry {\samp {!} in constraint}{278} +\entry {\samp {!} in constraint}{272} \initial {#} -\entry {\samp {#} in constraint}{279} -\entry {\code {#} in template}{270} -\entry {\code {#pragma}}{422} -\entry {\code {#pragma implementation}, implied}{163} -\entry {\code {#pragma}, reason for not using}{141} +\entry {\samp {#} in constraint}{273} +\entry {\code {#} in template}{264} +\entry {\code {#pragma}}{414} +\entry {\code {#pragma implementation}, implied}{159} +\entry {\code {#pragma}, reason for not using}{136} \initial {$} -\entry {$}{142} +\entry {$}{138} \initial {%} -\entry {\samp {%} in constraint}{279} -\entry {\samp {%} in template}{269} +\entry {\samp {%} in constraint}{273} +\entry {\samp {%} in template}{263} \initial {&} -\entry {\samp {&} in constraint}{279} +\entry {\samp {&} in constraint}{273} \initial {'} -\entry {'}{182} +\entry {'}{176} \initial {(} -\entry {(nil)}{222} +\entry {(nil)}{216} \initial {*} -\entry {\samp {*} in constraint}{279} -\entry {\code {*} in template}{271} +\entry {\samp {*} in constraint}{273} +\entry {\code {*} in template}{265} \initial {-} -\entry {\code {-lgcc}, use with \code {-nostdlib}}{52} -\entry {\code {-nostdlib} and unresolved references}{52} +\entry {\code {-lgcc}, use with \code {-nostdlib}}{49} +\entry {\code {-nostdlib} and unresolved references}{49} \initial {/} -\entry {\samp {/i} in RTL dump}{225} -\entry {\samp {/s} in RTL dump}{225, 226} -\entry {\samp {/u} in RTL dump}{225} -\entry {\samp {/v} in RTL dump}{225} +\entry {\samp {/i} in RTL dump}{219} +\entry {\samp {/s} in RTL dump}{219, 220} +\entry {\samp {/u} in RTL dump}{219} +\entry {\samp {/v} in RTL dump}{219} \initial {=} -\entry {\samp {=} in constraint}{279} +\entry {\samp {=} in constraint}{273} \initial {?} -\entry {\samp {?} in constraint}{278} -\entry {\code {?:} extensions}{127, 128} -\entry {?: side effect}{129} +\entry {\samp {?} in constraint}{272} +\entry {\code {?:} extensions}{123, 124} +\entry {?: side effect}{125} \initial {{\_}} -\entry {\samp {{\_}} in variables in macros}{126} -\entry {\code {{\_}{\_}bb{\_}init{\_}func}}{370} -\entry {\code {{\_}{\_}builtin{\_}apply}}{125} -\entry {\code {{\_}{\_}builtin{\_}apply{\_}args}}{125} -\entry {\code {{\_}{\_}builtin{\_}args{\_}info}}{372} -\entry {\code {{\_}{\_}builtin{\_}classify{\_}type}}{372} -\entry {\code {{\_}{\_}builtin{\_}next{\_}arg}}{372} -\entry {\code {{\_}{\_}builtin{\_}return}}{125} -\entry {\code {{\_}{\_}builtin{\_}saveregs}}{371} -\entry {\code {{\_}{\_}CTOR{\_}LIST{\_}{\_}}}{400} -\entry {\code {{\_}{\_}DTOR{\_}LIST{\_}{\_}}}{400} -\entry {\code {{\_}{\_}main}}{117} +\entry {\samp {{\_}} in variables in macros}{122} +\entry {\code {{\_}{\_}bb{\_}init{\_}func}}{364} +\entry {\code {{\_}{\_}builtin{\_}apply}}{121} +\entry {\code {{\_}{\_}builtin{\_}apply{\_}args}}{121} +\entry {\code {{\_}{\_}builtin{\_}args{\_}info}}{366} +\entry {\code {{\_}{\_}builtin{\_}classify{\_}type}}{366} +\entry {\code {{\_}{\_}builtin{\_}next{\_}arg}}{366} +\entry {\code {{\_}{\_}builtin{\_}return}}{121} +\entry {\code {{\_}{\_}builtin{\_}saveregs}}{365} +\entry {\code {{\_}{\_}CTOR{\_}LIST{\_}{\_}}}{393} +\entry {\code {{\_}{\_}DTOR{\_}LIST{\_}{\_}}}{393} +\entry {\code {{\_}{\_}main}}{112} \initial {{\tt\char43}} -\entry {\samp {{\tt\char43}} in constraint}{279} +\entry {\samp {{\tt\char43}} in constraint}{273} \initial {{\tt\gtr}} -\entry {\samp {{\tt\gtr}} in constraint}{273} -\entry {\code {{\tt\gtr}?}}{161} +\entry {\samp {{\tt\gtr}} in constraint}{267} +\entry {\code {{\tt\gtr}?}}{157} \initial {{\tt\indexbackslash }} -\entry {{\tt\indexbackslash }}{270} +\entry {{\tt\indexbackslash }}{264} \initial {{\tt\less}} -\entry {\samp {{\tt\less}} in constraint}{273} -\entry {\code {{\tt\less}?}}{161} +\entry {\samp {{\tt\less}} in constraint}{267} +\entry {\code {{\tt\less}?}}{157} \initial {0} -\entry {\samp {0} in constraint}{274} +\entry {\samp {0} in constraint}{268} \initial {A} -\entry {\code {abort}}{27, 211} -\entry {\code {abs}}{27, 240} -\entry {\code {abs} and attributes}{313} -\entry {\code {abs\var {m}2} instruction pattern}{289} -\entry {absolute value}{240} -\entry {access to operands}{222} -\entry {accessors}{222} -\entry {\code {ACCUMULATE{\_}OUTGOING{\_}ARGS}}{359} -\entry {\code {ACCUMULATE{\_}OUTGOING{\_}ARGS} and stack frames}{368} -\entry {\code {ADDITIONAL{\_}REGISTER{\_}NAMES}}{403} -\entry {\code {add\var {m}3} instruction pattern}{288} -\entry {\code {addr{\_}diff{\_}vec}}{249} -\entry {\code {addr{\_}diff{\_}vec}, length of}{319} -\entry {\code {addr{\_}vec}}{249} -\entry {\code {addr{\_}vec}, length of}{319} -\entry {\code {address}}{269} -\entry {address constraints}{275} -\entry {address of a label}{121} -\entry {\code {ADDRESS{\_}COST}}{385} -\entry {\code {address{\_}operand}}{275} -\entry {addressing modes}{379} -\entry {\code {ADJUST{\_}COST}}{387} -\entry {\code {ADJUST{\_}INSN{\_}LENGTH}}{319} -\entry {aggregates as return values}{365} -\entry {\code {aligned} attribute}{143} -\entry {alignment}{143} -\entry {\code {ALL{\_}REGS}}{347} -\entry {Alliant}{178} -\entry {\code {alloca}}{27} -\entry {\code {alloca} and SunOs}{93} -\entry {\code {alloca} vs variable-length arrays}{131} -\entry {\code {alloca}, for SunOs}{113} -\entry {\code {alloca}, for Unos}{101} -\entry {\code {allocate{\_}stack} instruction pattern}{295} -\entry {\code {ALLOCATE{\_}TRAMPOLINE}}{374} -\entry {alternate keywords}{155} -\entry {AMD29K options}{61} -\entry {analysis, data flow}{217} -\entry {\code {and}}{240} -\entry {\code {and} and attributes}{313} -\entry {\code {and}, canonicalization of}{300} -\entry {\code {and\var {m}3} instruction pattern}{288} -\entry {ANSI support}{27} -\entry {apostrophes}{182} -\entry {\code {APPLY{\_}RESULT{\_}SIZE}}{365} -\entry {\code {ARG{\_}POINTER{\_}REGNUM}}{356} -\entry {\code {ARG{\_}POINTER{\_}REGNUM} and virtual registers}{235} -\entry {\code {arg{\_}pointer{\_}rtx}}{356} -\entry {\code {ARGS{\_}GROW{\_}DOWNWARD}}{354} -\entry {argument passing}{213} -\entry {arguments in frame (88k)}{64} -\entry {arguments in registers}{360} -\entry {arguments on stack}{358} -\entry {arithmetic libraries}{214} -\entry {arithmetic shift}{240} -\entry {arithmetic simplifications}{215} -\entry {arithmetic, in RTL}{238} -\entry {ARM options}{63} -\entry {arrays of length zero}{130} -\entry {arrays of variable length}{131} -\entry {arrays, non-lvalue}{133} -\entry {\code {ashift}}{240} -\entry {\code {ashift} and attributes}{313} -\entry {\code {ashiftrt}}{240} -\entry {\code {ashiftrt} and attributes}{313} -\entry {\code {ashl\var {m}3} instruction pattern}{288} -\entry {\code {ashr\var {m}3} instruction pattern}{289} -\entry {\code {asm} expressions}{147} -\entry {\code {ASM{\_}APP{\_}OFF}}{392} -\entry {\code {ASM{\_}APP{\_}ON}}{392} -\entry {\code {ASM{\_}BYTE{\_}OP}}{393} -\entry {\code {ASM{\_}CLOSE{\_}PAREN}}{394} -\entry {\code {ASM{\_}COMMENT{\_}START}}{392} -\entry {\code {ASM{\_}DECLARE{\_}FUNCTION{\_}NAME}}{396} -\entry {\code {ASM{\_}DECLARE{\_}FUNCTION{\_}SIZE}}{397} -\entry {\code {ASM{\_}DECLARE{\_}OBJECT{\_}NAME}}{397} -\entry {\code {ASM{\_}FILE{\_}END}}{391} -\entry {\code {ASM{\_}FILE{\_}START}}{391} -\entry {\code {ASM{\_}FINAL{\_}SPEC}}{326} -\entry {\code {ASM{\_}FINISH{\_}DECLARE{\_}OBJECT}}{397} -\entry {\code {ASM{\_}FORMAT{\_}PRIVATE{\_}NAME}}{398} -\entry {\code {asm{\_}fprintf}}{405} -\entry {\code {ASM{\_}GENERATE{\_}INTERNAL{\_}LABEL}}{398} -\entry {\code {ASM{\_}GLOBALIZE{\_}LABEL}}{397} -\entry {\code {ASM{\_}IDENTIFY{\_}GCC}}{391} -\entry {\code {asm{\_}input}}{249} -\entry {\code {ASM{\_}NO{\_}SKIP{\_}IN{\_}TEXT}}{408} -\entry {\code {asm{\_}noperands}}{255} -\entry {\code {ASM{\_}OPEN{\_}PAREN}}{394} -\entry {\code {asm{\_}operands}, RTL sharing}{261} -\entry {\code {asm{\_}operands}, usage}{250} -\entry {\code {ASM{\_}OUTPUT{\_}ADDR{\_}DIFF{\_}ELT}}{406} -\entry {\code {ASM{\_}OUTPUT{\_}ADDR{\_}VEC{\_}ELT}}{407} -\entry {\code {ASM{\_}OUTPUT{\_}ALIGN}}{408} -\entry {\code {ASM{\_}OUTPUT{\_}ALIGN{\_}CODE}}{407} -\entry {\code {ASM{\_}OUTPUT{\_}ALIGNED{\_}COMMON}}{395} -\entry {\code {ASM{\_}OUTPUT{\_}ALIGNED{\_}LOCAL}}{396} -\entry {\code {ASM{\_}OUTPUT{\_}ASCII}}{393} -\entry {\code {ASM{\_}OUTPUT{\_}BYTE}}{393} -\entry {\code {ASM{\_}OUTPUT{\_}CASE{\_}END}}{407} -\entry {\code {ASM{\_}OUTPUT{\_}CASE{\_}LABEL}}{407} -\entry {\code {ASM{\_}OUTPUT{\_}CHAR}}{393} -\entry {\code {ASM{\_}OUTPUT{\_}COMMON}}{395} -\entry {\code {ASM{\_}OUTPUT{\_}CONSTRUCTOR}}{402} -\entry {\code {ASM{\_}OUTPUT{\_}DEF}}{399} -\entry {\code {ASM{\_}OUTPUT{\_}DESTRUCTOR}}{403} -\entry {\code {ASM{\_}OUTPUT{\_}DOUBLE}}{393} -\entry {\code {ASM{\_}OUTPUT{\_}DOUBLE{\_}INT}}{393} -\entry {\code {ASM{\_}OUTPUT{\_}EXTERNAL}}{397} -\entry {\code {ASM{\_}OUTPUT{\_}EXTERNAL{\_}LIBCALL}}{397} -\entry {\code {ASM{\_}OUTPUT{\_}FLOAT}}{393} -\entry {\code {ASM{\_}OUTPUT{\_}IDENT}}{392} -\entry {\code {ASM{\_}OUTPUT{\_}INT}}{393} -\entry {\code {ASM{\_}OUTPUT{\_}INTERNAL{\_}LABEL}}{398} -\entry {\code {ASM{\_}OUTPUT{\_}LABEL}}{396} -\entry {\code {ASM{\_}OUTPUT{\_}LABELREF}}{398} -\entry {\code {ASM{\_}OUTPUT{\_}LOCAL}}{396} -\entry {\code {ASM{\_}OUTPUT{\_}LONG{\_}DOUBLE}}{393} -\entry {\code {ASM{\_}OUTPUT{\_}LOOP{\_}ALIGN}}{407} -\entry {\code {ASM{\_}OUTPUT{\_}OPCODE}}{404} -\entry {\code {ASM{\_}OUTPUT{\_}POOL{\_}PROLOGUE}}{394} -\entry {\code {ASM{\_}OUTPUT{\_}QUADRUPLE{\_}INT}}{393} -\entry {\code {ASM{\_}OUTPUT{\_}REG{\_}POP}}{406} -\entry {\code {ASM{\_}OUTPUT{\_}REG{\_}PUSH}}{406} -\entry {\code {ASM{\_}OUTPUT{\_}SECTION{\_}NAME}}{392} -\entry {\code {ASM{\_}OUTPUT{\_}SHARED{\_}COMMON}}{396} -\entry {\code {ASM{\_}OUTPUT{\_}SHARED{\_}LOCAL}}{396} -\entry {\code {ASM{\_}OUTPUT{\_}SHORT}}{393} -\entry {\code {ASM{\_}OUTPUT{\_}SKIP}}{408} -\entry {\code {ASM{\_}OUTPUT{\_}SOURCE{\_}FILENAME}}{392} -\entry {\code {ASM{\_}OUTPUT{\_}SOURCE{\_}LINE}}{392} -\entry {\code {ASM{\_}OUTPUT{\_}SPECIAL{\_}POOL{\_}ENTRY}}{394} -\entry {\code {ASM{\_}SPEC}}{326} -\entry {\code {ASM{\_}STABD{\_}OP}}{410} -\entry {\code {ASM{\_}STABN{\_}OP}}{410} -\entry {\code {ASM{\_}STABS{\_}OP}}{410} -\entry {\code {assemble{\_}name}}{396} -\entry {assembler format}{391} -\entry {assembler instructions}{147} -\entry {assembler instructions in RTL}{250} -\entry {assembler names for identifiers}{151} -\entry {assembler syntax, 88k}{65} -\entry {\code {ASSEMBLER{\_}DIALECT}}{406} -\entry {assembly code, invalid}{193} -\entry {assigning attribute values to insns}{315} -\entry {asterisk in template}{271} -\entry {\code {atof}}{415} -\entry {\code {attr}}{316} -\entry {\code {attr{\_}flag}}{314} -\entry {attribute expressions}{312} -\entry {attribute of variables}{143} -\entry {attribute specifications}{317} -\entry {attribute specifications example}{317} -\entry {attributes, defining}{311} -\entry {autoincrement addressing, availability}{211} -\entry {autoincrement/decrement addressing}{273} -\entry {autoincrement/decrement analysis}{217} -\entry {automatic \code {inline} for C{\tt\char43}{\tt\char43} member fns}{146} +\entry {\code {abort}}{25, 205} +\entry {\code {abs}}{25, 234} +\entry {\code {abs} and attributes}{307} +\entry {\code {abs\var {m}2} instruction pattern}{283} +\entry {absolute value}{234} +\entry {access to operands}{216} +\entry {accessors}{216} +\entry {\code {ACCUMULATE{\_}OUTGOING{\_}ARGS}}{352} +\entry {\code {ACCUMULATE{\_}OUTGOING{\_}ARGS} and stack frames}{362} +\entry {\code {ADDITIONAL{\_}REGISTER{\_}NAMES}}{397} +\entry {\code {add\var {m}3} instruction pattern}{282} +\entry {\code {addr{\_}diff{\_}vec}}{243} +\entry {\code {addr{\_}diff{\_}vec}, length of}{313} +\entry {\code {addr{\_}vec}}{243} +\entry {\code {addr{\_}vec}, length of}{313} +\entry {\code {address}}{263} +\entry {address constraints}{269} +\entry {address of a label}{117} +\entry {\code {ADDRESS{\_}COST}}{379} +\entry {\code {address{\_}operand}}{269} +\entry {addressing modes}{373} +\entry {\code {ADJUST{\_}COST}}{381} +\entry {\code {ADJUST{\_}INSN{\_}LENGTH}}{313} +\entry {aggregates as return values}{359} +\entry {\code {aligned} attribute}{139} +\entry {alignment}{139} +\entry {\code {ALL{\_}REGS}}{341} +\entry {Alliant}{172} +\entry {\code {alloca}}{25} +\entry {\code {alloca} and SunOs}{89} +\entry {\code {alloca} vs variable-length arrays}{127} +\entry {\code {alloca}, for SunOs}{108} +\entry {\code {alloca}, for Unos}{96} +\entry {\code {allocate{\_}stack} instruction pattern}{289} +\entry {\code {ALLOCATE{\_}TRAMPOLINE}}{368} +\entry {alternate keywords}{151} +\entry {AMD29K options}{58} +\entry {analysis, data flow}{211} +\entry {\code {and}}{234} +\entry {\code {and} and attributes}{307} +\entry {\code {and}, canonicalization of}{294} +\entry {\code {and\var {m}3} instruction pattern}{282} +\entry {ANSI support}{25} +\entry {apostrophes}{176} +\entry {\code {APPLY{\_}RESULT{\_}SIZE}}{358} +\entry {\code {ARG{\_}POINTER{\_}REGNUM}}{349} +\entry {\code {ARG{\_}POINTER{\_}REGNUM} and virtual registers}{229} +\entry {\code {arg{\_}pointer{\_}rtx}}{350} +\entry {\code {ARGS{\_}GROW{\_}DOWNWARD}}{347} +\entry {argument passing}{207} +\entry {arguments in frame (88k)}{61} +\entry {arguments in registers}{354} +\entry {arguments on stack}{352} +\entry {arithmetic libraries}{208} +\entry {arithmetic shift}{234} +\entry {arithmetic simplifications}{209} +\entry {arithmetic, in RTL}{232} +\entry {ARM options}{60} +\entry {arrays of length zero}{126} +\entry {arrays of variable length}{127} +\entry {arrays, non-lvalue}{129} +\entry {\code {ashift}}{234} +\entry {\code {ashift} and attributes}{307} +\entry {\code {ashiftrt}}{234} +\entry {\code {ashiftrt} and attributes}{307} +\entry {\code {ashl\var {m}3} instruction pattern}{282} +\entry {\code {ashr\var {m}3} instruction pattern}{283} +\entry {\code {asm} expressions}{143} +\entry {\code {ASM{\_}APP{\_}OFF}}{385} +\entry {\code {ASM{\_}APP{\_}ON}}{385} +\entry {\code {ASM{\_}BYTE{\_}OP}}{387} +\entry {\code {ASM{\_}CLOSE{\_}PAREN}}{388} +\entry {\code {ASM{\_}COMMENT{\_}START}}{385} +\entry {\code {ASM{\_}DECLARE{\_}FUNCTION{\_}NAME}}{390} +\entry {\code {ASM{\_}DECLARE{\_}FUNCTION{\_}SIZE}}{390} +\entry {\code {ASM{\_}DECLARE{\_}OBJECT{\_}NAME}}{390} +\entry {\code {ASM{\_}FILE{\_}END}}{385} +\entry {\code {ASM{\_}FILE{\_}START}}{385} +\entry {\code {ASM{\_}FINAL{\_}SPEC}}{320} +\entry {\code {ASM{\_}FINISH{\_}DECLARE{\_}OBJECT}}{391} +\entry {\code {ASM{\_}FORMAT{\_}PRIVATE{\_}NAME}}{392} +\entry {\code {asm{\_}fprintf}}{399} +\entry {\code {ASM{\_}GENERATE{\_}INTERNAL{\_}LABEL}}{392} +\entry {\code {ASM{\_}GLOBALIZE{\_}LABEL}}{391} +\entry {\code {ASM{\_}IDENTIFY{\_}GCC}}{385} +\entry {\code {asm{\_}input}}{243} +\entry {\code {ASM{\_}NO{\_}SKIP{\_}IN{\_}TEXT}}{401} +\entry {\code {asm{\_}noperands}}{249} +\entry {\code {ASM{\_}OPEN{\_}PAREN}}{388} +\entry {\code {asm{\_}operands}, RTL sharing}{255} +\entry {\code {asm{\_}operands}, usage}{244} +\entry {\code {ASM{\_}OUTPUT{\_}ADDR{\_}DIFF{\_}ELT}}{400} +\entry {\code {ASM{\_}OUTPUT{\_}ADDR{\_}VEC{\_}ELT}}{400} +\entry {\code {ASM{\_}OUTPUT{\_}ALIGN}}{401} +\entry {\code {ASM{\_}OUTPUT{\_}ALIGN{\_}CODE}}{401} +\entry {\code {ASM{\_}OUTPUT{\_}ALIGNED{\_}COMMON}}{389} +\entry {\code {ASM{\_}OUTPUT{\_}ALIGNED{\_}LOCAL}}{390} +\entry {\code {ASM{\_}OUTPUT{\_}ASCII}}{387} +\entry {\code {ASM{\_}OUTPUT{\_}BYTE}}{387} +\entry {\code {ASM{\_}OUTPUT{\_}CASE{\_}END}}{400} +\entry {\code {ASM{\_}OUTPUT{\_}CASE{\_}LABEL}}{400} +\entry {\code {ASM{\_}OUTPUT{\_}CHAR}}{387} +\entry {\code {ASM{\_}OUTPUT{\_}COMMON}}{389} +\entry {\code {ASM{\_}OUTPUT{\_}CONSTRUCTOR}}{396} +\entry {\code {ASM{\_}OUTPUT{\_}DEF}}{392} +\entry {\code {ASM{\_}OUTPUT{\_}DESTRUCTOR}}{396} +\entry {\code {ASM{\_}OUTPUT{\_}DOUBLE}}{386} +\entry {\code {ASM{\_}OUTPUT{\_}DOUBLE{\_}INT}}{387} +\entry {\code {ASM{\_}OUTPUT{\_}EXTERNAL}}{391} +\entry {\code {ASM{\_}OUTPUT{\_}EXTERNAL{\_}LIBCALL}}{391} +\entry {\code {ASM{\_}OUTPUT{\_}FLOAT}}{386} +\entry {\code {ASM{\_}OUTPUT{\_}IDENT}}{386} +\entry {\code {ASM{\_}OUTPUT{\_}INT}}{387} +\entry {\code {ASM{\_}OUTPUT{\_}INTERNAL{\_}LABEL}}{391} +\entry {\code {ASM{\_}OUTPUT{\_}LABEL}}{390} +\entry {\code {ASM{\_}OUTPUT{\_}LABELREF}}{391} +\entry {\code {ASM{\_}OUTPUT{\_}LOCAL}}{389} +\entry {\code {ASM{\_}OUTPUT{\_}LONG{\_}DOUBLE}}{386} +\entry {\code {ASM{\_}OUTPUT{\_}LOOP{\_}ALIGN}}{401} +\entry {\code {ASM{\_}OUTPUT{\_}OPCODE}}{397} +\entry {\code {ASM{\_}OUTPUT{\_}POOL{\_}PROLOGUE}}{387} +\entry {\code {ASM{\_}OUTPUT{\_}QUADRUPLE{\_}INT}}{387} +\entry {\code {ASM{\_}OUTPUT{\_}REG{\_}POP}}{399} +\entry {\code {ASM{\_}OUTPUT{\_}REG{\_}PUSH}}{399} +\entry {\code {ASM{\_}OUTPUT{\_}SECTION{\_}NAME}}{386} +\entry {\code {ASM{\_}OUTPUT{\_}SHARED{\_}COMMON}}{389} +\entry {\code {ASM{\_}OUTPUT{\_}SHARED{\_}LOCAL}}{390} +\entry {\code {ASM{\_}OUTPUT{\_}SHORT}}{387} +\entry {\code {ASM{\_}OUTPUT{\_}SKIP}}{401} +\entry {\code {ASM{\_}OUTPUT{\_}SOURCE{\_}FILENAME}}{385} +\entry {\code {ASM{\_}OUTPUT{\_}SOURCE{\_}LINE}}{386} +\entry {\code {ASM{\_}OUTPUT{\_}SPECIAL{\_}POOL{\_}ENTRY}}{387} +\entry {\code {ASM{\_}SPEC}}{320} +\entry {\code {ASM{\_}STABD{\_}OP}}{403} +\entry {\code {ASM{\_}STABN{\_}OP}}{403} +\entry {\code {ASM{\_}STABS{\_}OP}}{403} +\entry {\code {assemble{\_}name}}{390} +\entry {assembler format}{385} +\entry {assembler instructions}{143} +\entry {assembler instructions in RTL}{244} +\entry {assembler names for identifiers}{147} +\entry {assembler syntax, 88k}{62} +\entry {\code {ASSEMBLER{\_}DIALECT}}{399} +\entry {assembly code, invalid}{187} +\entry {assigning attribute values to insns}{309} +\entry {asterisk in template}{265} +\entry {\code {atof}}{408} +\entry {\code {attr}}{310} +\entry {\code {attr{\_}flag}}{308} +\entry {attribute expressions}{306} +\entry {attribute of variables}{139} +\entry {attribute specifications}{311} +\entry {attribute specifications example}{311} +\entry {attributes, defining}{305} +\entry {autoincrement addressing, availability}{205} +\entry {autoincrement/decrement addressing}{267} +\entry {autoincrement/decrement analysis}{211} +\entry {automatic \code {inline} for C{\tt\char43}{\tt\char43} member fns}{142} \initial {B} -\entry {backslash}{270} -\entry {backtrace for bug reports}{197} -\entry {\code {barrier}}{253} -\entry {\code {BASE{\_}REG{\_}CLASS}}{348} -\entry {basic blocks}{217} -\entry {\code {bcmp}}{427} -\entry {\code {b\var {cond}} instruction pattern}{292} -\entry {\code {bcopy}, implicit usage}{378} -\entry {\code {BIGGEST{\_}ALIGNMENT}}{334} -\entry {\code {BIGGEST{\_}FIELD{\_}ALIGNMENT}}{334} -\entry {Bison parser generator}{90} -\entry {bit fields}{243} -\entry {bit shift overflow (88k)}{66} -\entry {\code {BITFIELD{\_}NBYTES{\_}LIMITED}}{336} -\entry {\code {BITS{\_}BIG{\_}ENDIAN}}{332} -\entry {\code {BITS{\_}BIG{\_}ENDIAN}, effect on \code {sign{\_}extract}}{243} -\entry {\code {BITS{\_}PER{\_}UNIT}}{332} -\entry {\code {BITS{\_}PER{\_}WORD}}{333} -\entry {bitwise complement}{240} -\entry {bitwise exclusive-or}{240} -\entry {bitwise inclusive-or}{240} -\entry {bitwise logical-and}{240} -\entry {\code {BLKmode}}{229} -\entry {\code {BLKmode}, and function return values}{260} -\entry {\code {BLOCK{\_}PROFILER}}{371} -\entry {\code {BLOCK{\_}PROFILER{\_}CODE}}{371} -\entry {\code {BRANCH{\_}COST}}{386} -\entry {\code {break{\_}out{\_}memory{\_}refs}}{382} -\entry {bug criteria}{193} -\entry {bug report mailing lists}{194} -\entry {bugs}{193} -\entry {bugs, known}{169} -\entry {builtin functions}{27} -\entry {byte writes (29k)}{62} -\entry {\code {byte{\_}mode}}{232} -\entry {\code {BYTES{\_}BIG{\_}ENDIAN}}{332} -\entry {\code {bzero}}{427} -\entry {\code {bzero}, implicit usage}{378} +\entry {backslash}{264} +\entry {backtrace for bug reports}{191} +\entry {\code {barrier}}{247} +\entry {\code {BASE{\_}REG{\_}CLASS}}{342} +\entry {basic blocks}{211} +\entry {\code {bcmp}}{419} +\entry {\code {b\var {cond}} instruction pattern}{286} +\entry {\code {bcopy}, implicit usage}{372} +\entry {\code {BIGGEST{\_}ALIGNMENT}}{328} +\entry {\code {BIGGEST{\_}FIELD{\_}ALIGNMENT}}{328} +\entry {Bison parser generator}{86} +\entry {bit fields}{237} +\entry {bit shift overflow (88k)}{63} +\entry {\code {BITFIELD{\_}NBYTES{\_}LIMITED}}{330} +\entry {\code {BITS{\_}BIG{\_}ENDIAN}}{326} +\entry {\code {BITS{\_}BIG{\_}ENDIAN}, effect on \code {sign{\_}extract}}{237} +\entry {\code {BITS{\_}PER{\_}UNIT}}{326} +\entry {\code {BITS{\_}PER{\_}WORD}}{326} +\entry {bitwise complement}{234} +\entry {bitwise exclusive-or}{234} +\entry {bitwise inclusive-or}{234} +\entry {bitwise logical-and}{234} +\entry {\code {BLKmode}}{223} +\entry {\code {BLKmode}, and function return values}{254} +\entry {\code {BLOCK{\_}PROFILER}}{364} +\entry {\code {BLOCK{\_}PROFILER{\_}CODE}}{365} +\entry {\code {BRANCH{\_}COST}}{380} +\entry {\code {break{\_}out{\_}memory{\_}refs}}{375} +\entry {bug criteria}{187} +\entry {bug report mailing lists}{188} +\entry {bugs}{187} +\entry {bugs, known}{163} +\entry {builtin functions}{25} +\entry {byte writes (29k)}{58} +\entry {\code {byte{\_}mode}}{226} +\entry {\code {BYTES{\_}BIG{\_}ENDIAN}}{326} +\entry {\code {bzero}}{419} +\entry {\code {bzero}, implicit usage}{372} \initial {C} -\entry {C compilation options}{19} -\entry {C intermediate output, nonexistent}{17} -\entry {C language extensions}{119} -\entry {C language, traditional}{28} -\entry {C statements for assembler output}{271} -\entry {\code {C{\_}INCLUDE{\_}PATH}}{82} -\entry {\code {c{\tt\char43}{\tt\char43}}}{26} -\entry {C{\tt\char43}{\tt\char43}}{17} -\entry {C{\tt\char43}{\tt\char43} compilation options}{19} -\entry {C{\tt\char43}{\tt\char43} interface and implementation headers}{162} -\entry {C{\tt\char43}{\tt\char43} language extensions}{159} -\entry {C{\tt\char43}{\tt\char43} member fns, automatically \code {inline}}{146} -\entry {C{\tt\char43}{\tt\char43} misunderstandings}{185} -\entry {C{\tt\char43}{\tt\char43} named return value}{159} -\entry {C{\tt\char43}{\tt\char43} options, command line}{30} -\entry {C{\tt\char43}{\tt\char43} pragmas, effect on inlining}{163} -\entry {C{\tt\char43}{\tt\char43} signatures}{166} -\entry {C{\tt\char43}{\tt\char43} source file suffixes}{26} -\entry {C{\tt\char43}{\tt\char43} static data, declaring and defining}{186} -\entry {C{\tt\char43}{\tt\char43} subtype polymorphism}{166} -\entry {C{\tt\char43}{\tt\char43} type abstraction}{166} -\entry {\code {call}}{246} -\entry {\code {call} instruction pattern}{292} -\entry {\code {call} usage}{259} -\entry {call-clobbered register}{341} -\entry {call-saved register}{341} -\entry {call-used register}{341} -\entry {\code {call{\_}insn}}{253} -\entry {\code {call{\_}insn} and \samp {/u}}{226} -\entry {\code {CALL{\_}INSN{\_}FUNCTION{\_}USAGE}}{253} -\entry {\code {call{\_}pop} instruction pattern}{292} -\entry {\code {CALL{\_}USED{\_}REGISTERS}}{341} -\entry {\code {call{\_}used{\_}regs}}{341} -\entry {\code {call{\_}value} instruction pattern}{292} -\entry {\code {call{\_}value{\_}pop} instruction pattern}{292} -\entry {\code {CALLER{\_}SAVE{\_}PROFITABLE}}{367} -\entry {calling conventions}{353} -\entry {calling functions in RTL}{259} -\entry {\code {CAN{\_}DEBUG{\_}WITHOUT{\_}FP}}{332} -\entry {\code {CAN{\_}ELIMINATE}}{358} -\entry {canonicalization of instructions}{300} -\entry {\code {CANONICALIZE{\_}COMPARISON}}{384} -\entry {case labels in initializers}{135} -\entry {case ranges}{137} -\entry {case sensitivity and VMS}{209} -\entry {\code {CASE{\_}DROPS{\_}THROUGH}}{418} -\entry {\code {CASE{\_}VALUES{\_}THRESHOLD}}{418} -\entry {\code {CASE{\_}VECTOR{\_}MODE}}{418} -\entry {\code {CASE{\_}VECTOR{\_}PC{\_}RELATIVE}}{418} -\entry {\code {casesi} instruction pattern}{294} -\entry {cast to a union}{137} -\entry {casts as lvalues}{127} -\entry {\code {cc{\_}status}}{382} -\entry {\code {CC{\_}STATUS{\_}MDEP}}{383} -\entry {\code {CC{\_}STATUS{\_}MDEP{\_}INIT}}{383} -\entry {\code {cc0}}{237} -\entry {\code {cc0}, RTL sharing}{261} -\entry {\code {cc0{\_}rtx}}{237} -\entry {\code {CC1{\_}SPEC}}{326} -\entry {\code {CC1PLUS{\_}SPEC}}{326} -\entry {\code {CCmode}}{229} -\entry {\code {CDImode}}{230} -\entry {\code {change{\_}address}}{286} -\entry {\code {CHAR{\_}TYPE{\_}SIZE}}{338} -\entry {\code {CHECK{\_}FLOAT{\_}VALUE}}{337} -\entry {\code {CHImode}}{230} -\entry {class definitions, register}{347} -\entry {class preference constraints}{278} -\entry {\code {CLASS{\_}LIKELY{\_}SPILLED{\_}P}}{352} -\entry {\code {CLASS{\_}MAX{\_}NREGS}}{352} -\entry {classes of RTX codes}{223} -\entry {\code {CLEAR{\_}INSN{\_}CACHE}}{375} -\entry {\code {clobber}}{246} -\entry {\code {cmp\var {m}} instruction pattern}{289} -\entry {\code {cmpstr\var {m}} instruction pattern}{289} -\entry {code generation conventions}{78} -\entry {code generation RTL sequences}{305} -\entry {code motion}{217} -\entry {\code {code{\_}label}}{253} -\entry {\code {code{\_}label} and \samp {/i}}{227} -\entry {\code {CODE{\_}LABEL{\_}NUMBER}}{253} -\entry {codes, RTL expression}{221} -\entry {\code {COImode}}{230} -\entry {combiner pass}{236} -\entry {command options}{19} -\entry {common subexpression elimination}{217} -\entry {\code {COMP{\_}TYPE{\_}ATTRIBUTES}}{422} -\entry {\code {compare}}{238} -\entry {\code {compare}, canonicalization of}{300} -\entry {compilation in a separate directory}{106} -\entry {compiler bugs, reporting}{195} -\entry {compiler compared to C{\tt\char43}{\tt\char43} preprocessor}{17} -\entry {compiler options, C{\tt\char43}{\tt\char43}}{30} -\entry {compiler passes and files}{215} -\entry {compiler version, specifying}{54} -\entry {\code {COMPILER{\_}PATH}}{82} -\entry {complement, bitwise}{240} -\entry {complex numbers}{129} -\entry {compound expressions as lvalues}{127} -\entry {computed gotos}{121} -\entry {computing the length of an insn}{318} -\entry {\code {cond}}{242} -\entry {\code {cond} and attributes}{313} -\entry {condition code register}{237} -\entry {condition code status}{382} -\entry {condition codes}{241} -\entry {conditional expressions as lvalues}{127} -\entry {conditional expressions, extensions}{128} -\entry {\code {CONDITIONAL{\_}REGISTER{\_}USAGE}}{341} -\entry {conditions, in patterns}{264} -\entry {configuration file}{425} -\entry {configurations supported by GNU CC}{93} -\entry {conflicting types}{184} -\entry {\code {const} applied to function}{138} -\entry {\code {const} function attribute}{139} -\entry {\code {CONST{\_}CALL{\_}P}}{226} -\entry {\code {CONST{\_}COSTS}}{385} -\entry {\code {const{\_}double}}{232} -\entry {\code {const{\_}double}, RTL sharing}{261} -\entry {\code {CONST{\_}DOUBLE{\_}CHAIN}}{232} -\entry {\code {CONST{\_}DOUBLE{\_}LOW}}{233} -\entry {\code {CONST{\_}DOUBLE{\_}MEM}}{232} -\entry {\code {CONST{\_}DOUBLE{\_}OK{\_}FOR{\_}LETTER{\_}P}}{353} -\entry {\code {const{\_}int}}{232} -\entry {\code {const{\_}int} and attribute tests}{313} -\entry {\code {const{\_}int} and attributes}{312} -\entry {\code {const{\_}int}, RTL sharing}{261} -\entry {\code {CONST{\_}OK{\_}FOR{\_}LETTER{\_}P}}{353} -\entry {\code {const{\_}string}}{233} -\entry {\code {const{\_}string} and attributes}{313} -\entry {\code {const{\_}true{\_}rtx}}{232} -\entry {\code {const0{\_}rtx}}{232} -\entry {\code {CONST0{\_}RTX}}{233} -\entry {\code {const1{\_}rtx}}{232} -\entry {\code {CONST1{\_}RTX}}{233} -\entry {\code {const2{\_}rtx}}{232} -\entry {\code {CONST2{\_}RTX}}{233} -\entry {constant attributes}{320} -\entry {constant folding}{215} -\entry {constant folding and floating point}{416} -\entry {constant propagation}{217} -\entry {\code {CONSTANT{\_}ADDRESS{\_}P}}{380} -\entry {\code {CONSTANT{\_}ALIGNMENT}}{334} -\entry {\code {CONSTANT{\_}P}}{380} -\entry {\code {CONSTANT{\_}POOL{\_}ADDRESS{\_}P}}{226} -\entry {constants in constraints}{274} -\entry {\code {constm1{\_}rtx}}{232} -\entry {constraint modifier characters}{279} -\entry {constraint, matching}{274} -\entry {constraints}{273} -\entry {constraints, machine specific}{280} -\entry {constructing calls}{125} -\entry {constructor expressions}{134} -\entry {constructors vs \code {goto}}{162} -\entry {constructors, automatic calls}{117} -\entry {constructors, output of}{399} +\entry {C compilation options}{17} +\entry {C intermediate output, nonexistent}{15} +\entry {C language extensions}{115} +\entry {C language, traditional}{26} +\entry {C statements for assembler output}{265} +\entry {\code {C{\_}INCLUDE{\_}PATH}}{78} +\entry {\code {c{\tt\char43}{\tt\char43}}}{24} +\entry {C{\tt\char43}{\tt\char43}}{15} +\entry {C{\tt\char43}{\tt\char43} compilation options}{17} +\entry {C{\tt\char43}{\tt\char43} interface and implementation headers}{158} +\entry {C{\tt\char43}{\tt\char43} language extensions}{155} +\entry {C{\tt\char43}{\tt\char43} member fns, automatically \code {inline}}{142} +\entry {C{\tt\char43}{\tt\char43} misunderstandings}{179} +\entry {C{\tt\char43}{\tt\char43} named return value}{155} +\entry {C{\tt\char43}{\tt\char43} options, command line}{28} +\entry {C{\tt\char43}{\tt\char43} pragmas, effect on inlining}{159} +\entry {C{\tt\char43}{\tt\char43} signatures}{160} +\entry {C{\tt\char43}{\tt\char43} source file suffixes}{24} +\entry {C{\tt\char43}{\tt\char43} static data, declaring and defining}{180} +\entry {C{\tt\char43}{\tt\char43} subtype polymorphism}{160} +\entry {C{\tt\char43}{\tt\char43} type abstraction}{160} +\entry {\code {call}}{240} +\entry {\code {call} instruction pattern}{286} +\entry {\code {call} usage}{253} +\entry {call-clobbered register}{335} +\entry {call-saved register}{335} +\entry {call-used register}{335} +\entry {\code {call{\_}insn}}{247} +\entry {\code {call{\_}insn} and \samp {/u}}{220} +\entry {\code {CALL{\_}INSN{\_}FUNCTION{\_}USAGE}}{247} +\entry {\code {call{\_}pop} instruction pattern}{286} +\entry {\code {CALL{\_}USED{\_}REGISTERS}}{335} +\entry {\code {call{\_}used{\_}regs}}{335} +\entry {\code {call{\_}value} instruction pattern}{286} +\entry {\code {call{\_}value{\_}pop} instruction pattern}{286} +\entry {\code {CALLER{\_}SAVE{\_}PROFITABLE}}{360} +\entry {calling conventions}{347} +\entry {calling functions in RTL}{253} +\entry {\code {CAN{\_}DEBUG{\_}WITHOUT{\_}FP}}{325} +\entry {\code {CAN{\_}ELIMINATE}}{351} +\entry {canonicalization of instructions}{294} +\entry {\code {CANONICALIZE{\_}COMPARISON}}{378} +\entry {case labels in initializers}{131} +\entry {case ranges}{133} +\entry {case sensitivity and VMS}{203} +\entry {\code {CASE{\_}DROPS{\_}THROUGH}}{411} +\entry {\code {CASE{\_}VALUES{\_}THRESHOLD}}{411} +\entry {\code {CASE{\_}VECTOR{\_}MODE}}{411} +\entry {\code {CASE{\_}VECTOR{\_}PC{\_}RELATIVE}}{411} +\entry {\code {casesi} instruction pattern}{288} +\entry {cast to a union}{133} +\entry {casts as lvalues}{123} +\entry {\code {cc{\_}status}}{376} +\entry {\code {CC{\_}STATUS{\_}MDEP}}{376} +\entry {\code {CC{\_}STATUS{\_}MDEP{\_}INIT}}{376} +\entry {\code {cc0}}{231} +\entry {\code {cc0}, RTL sharing}{255} +\entry {\code {cc0{\_}rtx}}{231} +\entry {\code {CC1{\_}SPEC}}{320} +\entry {\code {CC1PLUS{\_}SPEC}}{320} +\entry {\code {CCmode}}{223} +\entry {\code {CDImode}}{224} +\entry {\code {change{\_}address}}{280} +\entry {\code {CHAR{\_}TYPE{\_}SIZE}}{332} +\entry {\code {CHECK{\_}FLOAT{\_}VALUE}}{330} +\entry {\code {CHImode}}{224} +\entry {class definitions, register}{340} +\entry {class preference constraints}{272} +\entry {\code {CLASS{\_}LIKELY{\_}SPILLED{\_}P}}{346} +\entry {\code {CLASS{\_}MAX{\_}NREGS}}{346} +\entry {classes of RTX codes}{217} +\entry {\code {CLEAR{\_}INSN{\_}CACHE}}{369} +\entry {\code {clobber}}{240} +\entry {\code {cmp\var {m}} instruction pattern}{283} +\entry {\code {cmpstr\var {m}} instruction pattern}{283} +\entry {code generation conventions}{74} +\entry {code generation RTL sequences}{299} +\entry {code motion}{211} +\entry {\code {code{\_}label}}{247} +\entry {\code {code{\_}label} and \samp {/i}}{221} +\entry {\code {CODE{\_}LABEL{\_}NUMBER}}{247} +\entry {codes, RTL expression}{215} +\entry {\code {COImode}}{224} +\entry {combiner pass}{230} +\entry {command options}{17} +\entry {common subexpression elimination}{211} +\entry {\code {COMP{\_}TYPE{\_}ATTRIBUTES}}{415} +\entry {\code {compare}}{232} +\entry {\code {compare}, canonicalization of}{294} +\entry {compilation in a separate directory}{101} +\entry {compiler bugs, reporting}{189} +\entry {compiler compared to C{\tt\char43}{\tt\char43} preprocessor}{15} +\entry {compiler options, C{\tt\char43}{\tt\char43}}{28} +\entry {compiler passes and files}{209} +\entry {compiler version, specifying}{51} +\entry {\code {COMPILER{\_}PATH}}{78} +\entry {complement, bitwise}{234} +\entry {complex numbers}{125} +\entry {compound expressions as lvalues}{123} +\entry {computed gotos}{117} +\entry {computing the length of an insn}{312} +\entry {\code {cond}}{236} +\entry {\code {cond} and attributes}{307} +\entry {condition code register}{231} +\entry {condition code status}{376} +\entry {condition codes}{235} +\entry {conditional expressions as lvalues}{123} +\entry {conditional expressions, extensions}{124} +\entry {\code {CONDITIONAL{\_}REGISTER{\_}USAGE}}{335} +\entry {conditions, in patterns}{258} +\entry {configuration file}{417} +\entry {configurations supported by GNU CC}{89} +\entry {conflicting types}{178} +\entry {\code {const} applied to function}{134} +\entry {\code {const} function attribute}{135} +\entry {\code {CONST{\_}CALL{\_}P}}{220} +\entry {\code {CONST{\_}COSTS}}{378} +\entry {\code {const{\_}double}}{226} +\entry {\code {const{\_}double}, RTL sharing}{255} +\entry {\code {CONST{\_}DOUBLE{\_}CHAIN}}{226} +\entry {\code {CONST{\_}DOUBLE{\_}LOW}}{227} +\entry {\code {CONST{\_}DOUBLE{\_}MEM}}{226} +\entry {\code {CONST{\_}DOUBLE{\_}OK{\_}FOR{\_}LETTER{\_}P}}{346} +\entry {\code {const{\_}int}}{226} +\entry {\code {const{\_}int} and attribute tests}{307} +\entry {\code {const{\_}int} and attributes}{306} +\entry {\code {const{\_}int}, RTL sharing}{255} +\entry {\code {CONST{\_}OK{\_}FOR{\_}LETTER{\_}P}}{346} +\entry {\code {const{\_}string}}{227} +\entry {\code {const{\_}string} and attributes}{307} +\entry {\code {const{\_}true{\_}rtx}}{226} +\entry {\code {const0{\_}rtx}}{226} +\entry {\code {CONST0{\_}RTX}}{227} +\entry {\code {const1{\_}rtx}}{226} +\entry {\code {CONST1{\_}RTX}}{227} +\entry {\code {const2{\_}rtx}}{226} +\entry {\code {CONST2{\_}RTX}}{227} +\entry {constant attributes}{314} +\entry {constant folding}{209} +\entry {constant folding and floating point}{409} +\entry {constant propagation}{211} +\entry {\code {CONSTANT{\_}ADDRESS{\_}P}}{373} +\entry {\code {CONSTANT{\_}ALIGNMENT}}{328} +\entry {\code {CONSTANT{\_}P}}{374} +\entry {\code {CONSTANT{\_}POOL{\_}ADDRESS{\_}P}}{220} +\entry {constants in constraints}{268} +\entry {\code {constm1{\_}rtx}}{226} +\entry {constraint modifier characters}{273} +\entry {constraint, matching}{268} +\entry {constraints}{267} +\entry {constraints, machine specific}{274} +\entry {constructing calls}{121} +\entry {constructor expressions}{130} +\entry {constructors vs \code {goto}}{158} +\entry {constructors, automatic calls}{112} +\entry {constructors, output of}{393} \entry {contributors}{9} -\entry {controlling register usage}{341} -\entry {controlling the compilation driver}{325} -\entry {conventions, run-time}{213} -\entry {conversions}{243} -\entry {Convex options}{60} -\entry {\code {copy{\_}rtx{\_}if{\_}shared}}{261} -\entry {core dump}{193} -\entry {\code {cos}}{27} -\entry {costs of instructions}{385} -\entry {\code {COSTS{\_}N{\_}INSNS}}{385} -\entry {\code {CPLUS{\_}INCLUDE{\_}PATH}}{82} -\entry {\code {CPP{\_}PREDEFINES}}{329} -\entry {\code {CPP{\_}SPEC}}{325} -\entry {\code {CQImode}}{230} -\entry {cross compilation and floating point}{415} -\entry {cross compiling}{54} -\entry {cross-compiler, installation}{106} -\entry {cross-jumping}{219} -\entry {\code {CSImode}}{230} -\entry {\code {CTImode}}{230} -\entry {\code {CUMULATIVE{\_}ARGS}}{362} -\entry {\code {current{\_}function{\_}epilogue{\_}delay{\_}list}}{370} -\entry {\code {current{\_}function{\_}outgoing{\_}args{\_}size}}{359} -\entry {\code {current{\_}function{\_}pops{\_}args}}{369} -\entry {\code {current{\_}function{\_}pretend{\_}args{\_}size}}{368} +\entry {controlling register usage}{335} +\entry {controlling the compilation driver}{319} +\entry {conventions, run-time}{207} +\entry {conversions}{237} +\entry {Convex options}{57} +\entry {\code {copy{\_}rtx{\_}if{\_}shared}}{255} +\entry {core dump}{187} +\entry {\code {cos}}{25} +\entry {costs of instructions}{378} +\entry {\code {COSTS{\_}N{\_}INSNS}}{379} +\entry {\code {CPLUS{\_}INCLUDE{\_}PATH}}{78} +\entry {\code {CPP{\_}PREDEFINES}}{323} +\entry {\code {CPP{\_}SPEC}}{319} +\entry {\code {CQImode}}{224} +\entry {cross compilation and floating point}{408} +\entry {cross compiling}{51} +\entry {cross-compiler, installation}{102} +\entry {cross-jumping}{213} +\entry {\code {CSImode}}{224} +\entry {\code {CTImode}}{224} +\entry {\code {CUMULATIVE{\_}ARGS}}{356} +\entry {\code {current{\_}function{\_}epilogue{\_}delay{\_}list}}{363} +\entry {\code {current{\_}function{\_}outgoing{\_}args{\_}size}}{352} +\entry {\code {current{\_}function{\_}pops{\_}args}}{363} +\entry {\code {current{\_}function{\_}pretend{\_}args{\_}size}}{362} \initial {D} -\entry {\samp {d} in constraint}{273} -\entry {data flow analysis}{217} -\entry {\code {DATA{\_}ALIGNMENT}}{334} -\entry {\code {data{\_}section}}{388} -\entry {\code {DATA{\_}SECTION{\_}ASM{\_}OP}}{388} -\entry {\code {DBR{\_}OUTPUT{\_}SEQEND}}{405} -\entry {\code {dbr{\_}sequence{\_}length}}{405} -\entry {DBX}{175} -\entry {\code {DBX{\_}BLOCKS{\_}FUNCTION{\_}RELATIVE}}{411} -\entry {\code {DBX{\_}CONTIN{\_}CHAR}}{410} -\entry {\code {DBX{\_}CONTIN{\_}LENGTH}}{410} -\entry {\code {DBX{\_}DEBUGGING{\_}INFO}}{409} -\entry {\code {DBX{\_}FUNCTION{\_}FIRST}}{411} -\entry {\code {DBX{\_}LBRAC{\_}FIRST}}{411} -\entry {\code {DBX{\_}MEMPARM{\_}STABS{\_}LETTER}}{411} -\entry {\code {DBX{\_}NO{\_}XREFS}}{410} -\entry {\code {DBX{\_}OUTPUT{\_}ENUM}}{412} -\entry {\code {DBX{\_}OUTPUT{\_}FUNCTION{\_}END}}{412} -\entry {\code {DBX{\_}OUTPUT{\_}LBRAC}}{411} -\entry {\code {DBX{\_}OUTPUT{\_}MAIN{\_}SOURCE{\_}DIRECTORY}}{413} -\entry {\code {DBX{\_}OUTPUT{\_}MAIN{\_}SOURCE{\_}FILE{\_}END}}{413} -\entry {\code {DBX{\_}OUTPUT{\_}MAIN{\_}SOURCE{\_}FILENAME}}{413} -\entry {\code {DBX{\_}OUTPUT{\_}RBRAC}}{411} -\entry {\code {DBX{\_}OUTPUT{\_}SOURCE{\_}FILENAME}}{413} -\entry {\code {DBX{\_}OUTPUT{\_}STANDARD{\_}TYPES}}{412} -\entry {\code {DBX{\_}REGISTER{\_}NUMBER}}{408} -\entry {\code {DBX{\_}REGPARM{\_}STABS{\_}CODE}}{411} -\entry {\code {DBX{\_}REGPARM{\_}STABS{\_}LETTER}}{411} -\entry {\code {DBX{\_}STATIC{\_}CONST{\_}VAR{\_}CODE}}{410} -\entry {\code {DBX{\_}STATIC{\_}STAB{\_}DATA{\_}SECTION}}{410} -\entry {\code {DBX{\_}TYPE{\_}DECL{\_}STABS{\_}CODE}}{410} -\entry {\code {DBX{\_}WORKING{\_}DIRECTORY}}{413} -\entry {\code {DCmode}}{229} -\entry {De Morgan's law}{300} -\entry {dead code}{216} -\entry {\code {dead{\_}or{\_}set{\_}p}}{303} -\entry {deallocating variable length arrays}{131} -\entry {death notes}{346} -\entry {\code {debug{\_}rtx}}{198} -\entry {\code {DEBUG{\_}SYMS{\_}TEXT}}{409} -\entry {\code {DEBUGGER{\_}ARG{\_}OFFSET}}{409} -\entry {\code {DEBUGGER{\_}AUTO{\_}OFFSET}}{409} -\entry {debugging information generation}{219} -\entry {debugging information options}{41} -\entry {debugging, 88k OCS}{64} -\entry {declaration scope}{181} -\entry {declarations inside expressions}{119} -\entry {declarations, RTL}{244} -\entry {declaring attributes of functions}{138} -\entry {declaring static data in C{\tt\char43}{\tt\char43}}{186} -\entry {default implementation, signature member function}{167} -\entry {\code {DEFAULT{\_}CALLER{\_}SAVES}}{367} -\entry {\code {DEFAULT{\_}GDB{\_}EXTENSIONS}}{409} -\entry {\code {DEFAULT{\_}MAIN{\_}RETURN}}{422} -\entry {\code {DEFAULT{\_}PCC{\_}STRUCT{\_}RETURN}}{365} -\entry {\code {DEFAULT{\_}SHORT{\_}ENUMS}}{339} -\entry {\code {DEFAULT{\_}SIGNED{\_}CHAR}}{338} -\entry {\code {define{\_}asm{\_}attributes}}{317} -\entry {\code {define{\_}attr}}{311} -\entry {\code {define{\_}delay}}{321} -\entry {\code {define{\_}expand}}{305} -\entry {\code {define{\_}function{\_}unit}}{322} -\entry {\code {define{\_}insn}}{263} -\entry {\code {define{\_}insn} example}{264} -\entry {\code {define{\_}peephole}}{305} -\entry {define{\_}split}{308} -\entry {defining attributes and their values}{311} -\entry {defining jump instruction patterns}{298} -\entry {defining peephole optimizers}{301} -\entry {defining RTL sequences for code generation}{305} -\entry {defining static data in C{\tt\char43}{\tt\char43}}{186} -\entry {delay slots, defining}{320} -\entry {\code {DELAY{\_}SLOTS{\_}FOR{\_}EPILOGUE}}{369} -\entry {delayed branch scheduling}{219} -\entry {dependencies for make as output}{82} -\entry {dependencies, make}{50} -\entry {\code {DEPENDENCIES{\_}OUTPUT}}{82} -\entry {Dependent Patterns}{296} -\entry {destructors vs \code {goto}}{162} -\entry {destructors, output of}{399} -\entry {detecting \w {\samp {-traditional}}}{29} -\entry {\code {DFmode}}{229} -\entry {dialect options}{27} -\entry {digits in constraint}{274} -\entry {\code {DImode}}{229} -\entry {\code {DIR{\_}SEPARATOR}}{427} -\entry {directory options}{53} -\entry {disabling certain registers}{341} -\entry {dispatch table}{406} -\entry {\code {div}}{239} -\entry {\code {div} and attributes}{313} -\entry {\code {DIVDI3{\_}LIBCALL}}{377} -\entry {divide instruction, 88k}{66} -\entry {division}{239} -\entry {\code {div\var {m}3} instruction pattern}{288} -\entry {\code {divmod\var {m}4} instruction pattern}{288} -\entry {\code {DIVSI3{\_}LIBCALL}}{376} -\entry {dollar signs in identifier names}{142} -\entry {\code {DOLLARS{\_}IN{\_}IDENTIFIERS}}{422} -\entry {\code {DONE}}{306} -\entry {\code {DONT{\_}DECLARE{\_}SYS{\_}SIGLIST}}{427} -\entry {\code {DONT{\_}REDUCE{\_}ADDR}}{387} -\entry {double-word arithmetic}{129} -\entry {\code {DOUBLE{\_}TYPE{\_}SIZE}}{338} -\entry {downward funargs}{122} -\entry {driver}{325} -\entry {DW bit (29k)}{62} -\entry {\code {DWARF{\_}DEBUGGING{\_}INFO}}{414} -\entry {\code {DYNAMIC{\_}CHAIN{\_}ADDRESS}}{354} +\entry {\samp {d} in constraint}{267} +\entry {data flow analysis}{211} +\entry {\code {DATA{\_}ALIGNMENT}}{328} +\entry {\code {data{\_}section}}{382} +\entry {\code {DATA{\_}SECTION{\_}ASM{\_}OP}}{382} +\entry {\code {DBR{\_}OUTPUT{\_}SEQEND}}{398} +\entry {\code {dbr{\_}sequence{\_}length}}{398} +\entry {DBX}{169} +\entry {\code {DBX{\_}CONTIN{\_}CHAR}}{403} +\entry {\code {DBX{\_}CONTIN{\_}LENGTH}}{403} +\entry {\code {DBX{\_}DEBUGGING{\_}INFO}}{403} +\entry {\code {DBX{\_}FUNCTION{\_}FIRST}}{404} +\entry {\code {DBX{\_}LBRAC{\_}FIRST}}{404} +\entry {\code {DBX{\_}MEMPARM{\_}STABS{\_}LETTER}}{404} +\entry {\code {DBX{\_}NO{\_}XREFS}}{403} +\entry {\code {DBX{\_}OUTPUT{\_}ENUM}}{405} +\entry {\code {DBX{\_}OUTPUT{\_}FUNCTION{\_}END}}{405} +\entry {\code {DBX{\_}OUTPUT{\_}LBRAC}}{405} +\entry {\code {DBX{\_}OUTPUT{\_}MAIN{\_}SOURCE{\_}DIRECTORY}}{406} +\entry {\code {DBX{\_}OUTPUT{\_}MAIN{\_}SOURCE{\_}FILE{\_}END}}{406} +\entry {\code {DBX{\_}OUTPUT{\_}MAIN{\_}SOURCE{\_}FILENAME}}{406} +\entry {\code {DBX{\_}OUTPUT{\_}RBRAC}}{405} +\entry {\code {DBX{\_}OUTPUT{\_}SOURCE{\_}FILENAME}}{406} +\entry {\code {DBX{\_}OUTPUT{\_}STANDARD{\_}TYPES}}{405} +\entry {\code {DBX{\_}REGISTER{\_}NUMBER}}{402} +\entry {\code {DBX{\_}REGPARM{\_}STABS{\_}CODE}}{404} +\entry {\code {DBX{\_}REGPARM{\_}STABS{\_}LETTER}}{404} +\entry {\code {DBX{\_}STATIC{\_}CONST{\_}VAR{\_}CODE}}{404} +\entry {\code {DBX{\_}STATIC{\_}STAB{\_}DATA{\_}SECTION}}{404} +\entry {\code {DBX{\_}TYPE{\_}DECL{\_}STABS{\_}CODE}}{404} +\entry {\code {DBX{\_}WORKING{\_}DIRECTORY}}{406} +\entry {\code {DCmode}}{223} +\entry {De Morgan's law}{294} +\entry {dead code}{210} +\entry {\code {dead{\_}or{\_}set{\_}p}}{297} +\entry {deallocating variable length arrays}{127} +\entry {death notes}{340} +\entry {\code {debug{\_}rtx}}{192} +\entry {\code {DEBUG{\_}SYMS{\_}TEXT}}{403} +\entry {\code {DEBUGGER{\_}ARG{\_}OFFSET}}{402} +\entry {\code {DEBUGGER{\_}AUTO{\_}OFFSET}}{402} +\entry {debugging information generation}{213} +\entry {debugging information options}{37} +\entry {debugging, 88k OCS}{61} +\entry {declaration scope}{175} +\entry {declarations inside expressions}{115} +\entry {declarations, RTL}{238} +\entry {declaring attributes of functions}{134} +\entry {declaring static data in C{\tt\char43}{\tt\char43}}{180} +\entry {default implementation, signature member function}{161} +\entry {\code {DEFAULT{\_}CALLER{\_}SAVES}}{360} +\entry {\code {DEFAULT{\_}GDB{\_}EXTENSIONS}}{403} +\entry {\code {DEFAULT{\_}MAIN{\_}RETURN}}{415} +\entry {\code {DEFAULT{\_}PCC{\_}STRUCT{\_}RETURN}}{359} +\entry {\code {DEFAULT{\_}SHORT{\_}ENUMS}}{333} +\entry {\code {DEFAULT{\_}SIGNED{\_}CHAR}}{332} +\entry {\code {define{\_}asm{\_}attributes}}{311} +\entry {\code {define{\_}attr}}{305} +\entry {\code {define{\_}delay}}{315} +\entry {\code {define{\_}expand}}{299} +\entry {\code {define{\_}function{\_}unit}}{316} +\entry {\code {define{\_}insn}}{257} +\entry {\code {define{\_}insn} example}{258} +\entry {\code {define{\_}peephole}}{299} +\entry {define{\_}split}{302} +\entry {defining attributes and their values}{305} +\entry {defining jump instruction patterns}{292} +\entry {defining peephole optimizers}{295} +\entry {defining RTL sequences for code generation}{299} +\entry {defining static data in C{\tt\char43}{\tt\char43}}{180} +\entry {delay slots, defining}{314} +\entry {\code {DELAY{\_}SLOTS{\_}FOR{\_}EPILOGUE}}{363} +\entry {delayed branch scheduling}{213} +\entry {dependencies for make as output}{78} +\entry {dependencies, make}{47} +\entry {\code {DEPENDENCIES{\_}OUTPUT}}{78} +\entry {Dependent Patterns}{290} +\entry {destructors vs \code {goto}}{158} +\entry {destructors, output of}{393} +\entry {detecting \w {\samp {-traditional}}}{27} +\entry {\code {DFmode}}{223} +\entry {dialect options}{25} +\entry {digits in constraint}{268} +\entry {\code {DImode}}{223} +\entry {directory options}{50} +\entry {disabling certain registers}{335} +\entry {dispatch table}{400} +\entry {\code {div}}{233} +\entry {\code {div} and attributes}{307} +\entry {\code {DIVDI3{\_}LIBCALL}}{371} +\entry {divide instruction, 88k}{62} +\entry {division}{233} +\entry {\code {div\var {m}3} instruction pattern}{282} +\entry {\code {divmod\var {m}4} instruction pattern}{282} +\entry {\code {DIVSI3{\_}LIBCALL}}{370} +\entry {dollar signs in identifier names}{138} +\entry {\code {DOLLARS{\_}IN{\_}IDENTIFIERS}}{415} +\entry {\code {DONE}}{300} +\entry {\code {DONT{\_}DECLARE{\_}SYS{\_}SIGLIST}}{419} +\entry {\code {DONT{\_}REDUCE{\_}ADDR}}{381} +\entry {double-word arithmetic}{125} +\entry {\code {DOUBLE{\_}TYPE{\_}SIZE}}{332} +\entry {downward funargs}{118} +\entry {driver}{319} +\entry {DW bit (29k)}{58} +\entry {\code {DWARF{\_}DEBUGGING{\_}INFO}}{407} +\entry {\code {DYNAMIC{\_}CHAIN{\_}ADDRESS}}{348} \initial {E} -\entry {\samp {E} in constraint}{274} -\entry {\code {EASY{\_}DIV{\_}EXPR}}{419} -\entry {\code {EDOM}, implicit usage}{377} -\entry {\code {ELIGIBLE{\_}FOR{\_}EPILOGUE{\_}DELAY}}{369} -\entry {\code {ELIMINABLE{\_}REGS}}{357} -\entry {empty constraints}{285} -\entry {\code {EMPTY{\_}FIELD{\_}BOUNDARY}}{335} -\entry {\code {ENCODE{\_}SECTION{\_}INFO}}{389} -\entry {\code {ENCODE{\_}SECTION{\_}INFO} and address validation}{381} -\entry {\code {ENCODE{\_}SECTION{\_}INFO} usage}{405} -\entry {\code {ENDFILE{\_}SPEC}}{327} -\entry {endianness}{211} -\entry {\code {enum machine{\_}mode}}{228} -\entry {\code {enum reg{\_}class}}{348} -\entry {enumeration clash warnings}{38} -\entry {environment variables}{81} -\entry {epilogue}{367} -\entry {\code {eq}}{242} -\entry {\code {eq} and attributes}{313} -\entry {\code {eq{\_}attr}}{314} -\entry {equal}{242} -\entry {\code {errno}, implicit usage}{378} -\entry {error messages}{191} -\entry {escape sequences, traditional}{28} -\entry {exclamation point}{278} -\entry {exclusive-or, bitwise}{240} -\entry {\code {EXECUTABLE{\_}SUFFIX}}{426} -\entry {\code {exit}}{27} -\entry {exit status and VMS}{209} -\entry {\code {EXIT{\_}BODY}}{423} -\entry {\code {EXIT{\_}IGNORE{\_}STACK}}{368} -\entry {\code {EXPAND{\_}BUILTIN{\_}SAVEREGS}}{373} -\entry {expander definitions}{305} -\entry {explicit register variables}{152} -\entry {\code {expr{\_}list}}{259} -\entry {expression codes}{221} -\entry {expressions containing statements}{119} -\entry {expressions, compound, as lvalues}{127} -\entry {expressions, conditional, as lvalues}{127} -\entry {expressions, constructor}{134} -\entry {extended \code {asm}}{147} -\entry {\code {extend\var {mn}} instruction pattern}{290} -\entry {extensible constraints}{275} -\entry {extensions, \code {?:}}{127, 128} -\entry {extensions, C language}{119} -\entry {extensions, C{\tt\char43}{\tt\char43} language}{159} -\entry {\code {extern int target{\_}flags}}{330} -\entry {external declaration scope}{181} -\entry {\code {EXTRA{\_}CC{\_}MODES}}{383} -\entry {\code {EXTRA{\_}CC{\_}NAMES}}{384} -\entry {\code {EXTRA{\_}CONSTRAINT}}{353} -\entry {\code {EXTRA{\_}SECTION{\_}FUNCTIONS}}{388} -\entry {\code {EXTRA{\_}SECTIONS}}{388} -\entry {\code {extv} instruction pattern}{291} -\entry {\code {extzv} instruction pattern}{291} +\entry {\samp {E} in constraint}{268} +\entry {\code {EASY{\_}DIV{\_}EXPR}}{411} +\entry {\code {EDOM}, implicit usage}{371} +\entry {\code {ELIGIBLE{\_}FOR{\_}EPILOGUE{\_}DELAY}}{363} +\entry {\code {ELIMINABLE{\_}REGS}}{351} +\entry {empty constraints}{279} +\entry {\code {EMPTY{\_}FIELD{\_}BOUNDARY}}{328} +\entry {\code {ENCODE{\_}SECTION{\_}INFO}}{383} +\entry {\code {ENCODE{\_}SECTION{\_}INFO} and address validation}{374} +\entry {\code {ENCODE{\_}SECTION{\_}INFO} usage}{398} +\entry {\code {ENDFILE{\_}SPEC}}{321} +\entry {endianness}{205} +\entry {\code {enum machine{\_}mode}}{222} +\entry {\code {enum reg{\_}class}}{342} +\entry {enumeration clash warnings}{35} +\entry {environment variables}{77} +\entry {epilogue}{361} +\entry {\code {eq}}{236} +\entry {\code {eq} and attributes}{307} +\entry {\code {eq{\_}attr}}{308} +\entry {equal}{236} +\entry {\code {errno}, implicit usage}{371} +\entry {error messages}{186} +\entry {escape sequences, traditional}{26} +\entry {exclamation point}{272} +\entry {exclusive-or, bitwise}{234} +\entry {\code {EXECUTABLE{\_}SUFFIX}}{418} +\entry {\code {exit}}{25} +\entry {exit status and VMS}{203} +\entry {\code {EXIT{\_}BODY}}{416} +\entry {\code {EXIT{\_}IGNORE{\_}STACK}}{362} +\entry {\code {EXPAND{\_}BUILTIN{\_}SAVEREGS}}{366} +\entry {expander definitions}{299} +\entry {explicit register variables}{148} +\entry {\code {expr{\_}list}}{253} +\entry {expression codes}{215} +\entry {expressions containing statements}{115} +\entry {expressions, compound, as lvalues}{123} +\entry {expressions, conditional, as lvalues}{123} +\entry {expressions, constructor}{130} +\entry {extended \code {asm}}{143} +\entry {\code {extend\var {mn}} instruction pattern}{284} +\entry {extensible constraints}{269} +\entry {extensions, \code {?:}}{123, 124} +\entry {extensions, C language}{115} +\entry {extensions, C{\tt\char43}{\tt\char43} language}{155} +\entry {\code {extern int target{\_}flags}}{324} +\entry {external declaration scope}{175} +\entry {\code {EXTRA{\_}CC{\_}MODES}}{377} +\entry {\code {EXTRA{\_}CC{\_}NAMES}}{377} +\entry {\code {EXTRA{\_}CONSTRAINT}}{347} +\entry {\code {EXTRA{\_}SECTION{\_}FUNCTIONS}}{382} +\entry {\code {EXTRA{\_}SECTIONS}}{382} +\entry {\code {extv} instruction pattern}{285} +\entry {\code {extzv} instruction pattern}{285} \initial {F} -\entry {\samp {F} in constraint}{274} -\entry {\code {fabs}}{27} -\entry {\code {FAIL}}{306} -\entry {\code {FAILURE{\_}EXIT{\_}CODE}}{425} -\entry {fatal signal}{193} -\entry {features, optional, in system conventions}{330} -\entry {\code {ffs}}{27, 241} -\entry {\code {ffs\var {m}2} instruction pattern}{289} -\entry {file name suffix}{24} -\entry {file names}{51} -\entry {files and passes of the compiler}{215} -\entry {final pass}{219} -\entry {\code {FINAL{\_}PRESCAN{\_}INSN}}{404} -\entry {\code {FINAL{\_}REG{\_}PARM{\_}STACK{\_}SPACE}}{359} -\entry {\code {final{\_}scan{\_}insn}}{370} -\entry {\code {final{\_}sequence}}{405} -\entry {\code {FINALIZE{\_}PIC}}{390} -\entry {\code {FIRST{\_}INSN{\_}ADDRESS}}{319} -\entry {\code {FIRST{\_}PARM{\_}OFFSET}}{354} -\entry {\code {FIRST{\_}PARM{\_}OFFSET} and virtual registers}{235} -\entry {\code {FIRST{\_}PSEUDO{\_}REGISTER}}{340} -\entry {\code {FIRST{\_}STACK{\_}REG}}{345} -\entry {\code {FIRST{\_}VIRTUAL{\_}REGISTER}}{235} -\entry {\code {fix}}{244} -\entry {\code {fix{\_}trunc\var {mn}2} instruction pattern}{290} -\entry {fixed register}{341} -\entry {\code {FIXED{\_}REGISTERS}}{341} -\entry {\code {fixed{\_}regs}}{341} -\entry {\code {fix\var {mn}2} instruction pattern}{290} -\entry {\code {FIXUNS{\_}TRUNC{\_}LIKE{\_}FIX{\_}TRUNC}}{418} -\entry {\code {fixuns{\_}trunc\var {mn}2} instruction pattern}{290} -\entry {\code {fixuns\var {mn}2} instruction pattern}{290} -\entry {flags in RTL expression}{225} -\entry {\code {float}}{244} -\entry {\code {float} as function value type}{182} -\entry {\code {FLOAT{\_}ARG{\_}TYPE}}{378} -\entry {\code {float{\_}extend}}{244} -\entry {\code {FLOAT{\_}STORE{\_}FLAG{\_}VALUE}}{421} -\entry {\code {float{\_}truncate}}{244} -\entry {\code {FLOAT{\_}TYPE{\_}SIZE}}{338} -\entry {\code {FLOAT{\_}VALUE{\_}TYPE}}{378} -\entry {\code {FLOAT{\_}WORDS{\_}BIG{\_}ENDIAN}}{332} -\entry {\code {FLOATIFY}}{378} -\entry {floating point and cross compilation}{415} -\entry {\code {float\var {mn}2} instruction pattern}{290} -\entry {\code {floatuns\var {mn}2} instruction pattern}{290} -\entry {\code {force{\_}reg}}{286} -\entry {\code {format} function attribute}{140} -\entry {forwarding calls}{125} -\entry {frame layout}{353} -\entry {\code {FRAME{\_}GROWS{\_}DOWNWARD}}{354} -\entry {\code {FRAME{\_}GROWS{\_}DOWNWARD} and virtual registers}{235} -\entry {\code {frame{\_}pointer{\_}needed}}{367} -\entry {\code {FRAME{\_}POINTER{\_}REGNUM}}{355} -\entry {\code {FRAME{\_}POINTER{\_}REGNUM} and virtual registers}{235} -\entry {\code {FRAME{\_}POINTER{\_}REQUIRED}}{357} -\entry {\code {frame{\_}pointer{\_}rtx}}{356} -\entry {\code {fscanf}, and constant strings}{180} -\entry {\code {ftrunc\var {m}2} instruction pattern}{290} -\entry {function attributes}{138} -\entry {function call conventions}{213} -\entry {function entry and exit}{367} -\entry {function pointers, arithmetic}{