HAM Radio 1/HamRadio.cdr/tech/pll/readme

Text File | 1989-03-13 | 7.6 KB | 158 lines

      HCMOS PHASE-LOCKED LOOP DESIGN PROGRAM
      --------------------------------------
      Version 1.1


This file will give you some more information about the PLL
design program. It can be printed by typing :
      TYPE README>PRN
and then striking the <RETURN> key.

This diskette enables you to design a complete HCMOS-based PLL
including peripheral components. It's for use with Philips'
74HC/HCT4046A and 7046A HCMOS circuits, but it can also be used
to evaluate and modify existing designs, for example with the HEF4046.
Besides giving you an approximation of a loop's complete dynamic
behaviour, the program can generate a Bode plot to check loop stability.
All calculations are done with equations which are derived for high-
gain loops and most of them can be found in literature, e.g. in
'Phaselock techniques', Wiley, New York, 1979, Mr.Floyd Gardner and in
'Phase-locked loops', McGraw-Hill, New-York, 1984, Mr. Roland Best.
By eliminating much of the calculation drudgery of PLL design, the
program invites you to experiment but will still reduce design time.
This program is tailored to the Philips 74HC/HCT4046A and 74HC/HCT7046A
devices and does not garantee that other brands of '4046 will respond as
calculated by this program.

The program runs on every PC-DOS or MS-DOS compatible PC
with a colour or monochrome monitor. To benefit from all
the features of the program, a graphics card and/or an
EPSON or IBM compatible printer is needed, but these are
not essential.
The following graphic cards or compatibles are supported :
      - CGA
      - EGA
      - HERCULES
      - VGA
      - PC3270


STARTING THE PROGRAM
    To start the program, simply insert the diskette into
    drive A or B. No installation procedure is required.
    With the program on the logged drive, type :
        PLL
    and strike the <RETURN> key. Further instructions for using
    your PLL diskette are explained on-screen.
    If you have a hard disk you can copy all necessary files
    in a sub-directory C:\PLL by simply typing :
        DISK_C
    and then striking the <RETURN> key.

    To find out which graphics card is in your PC, type :
        DETECT
    and strike the <RETURN> key. If no information is generated,
    your graphics card is probably unsuitable for the program.

ABOUT THE PROGRAM
    After some introductory text when you start the program, you'll
    come to an elementary PLL block diagram and the pinning description.
    Then you are asked to enter some basic design parameters such as the
    input frequency, and whether you require a frequency divider in the
    feedback.
    Use the on-line 'help' facility if a question is unclear. In any
    case, you can always return to the previous question and alter data,
    should you make a mistake. When you have entered all the basic
    system parameters, calculation starts, after which the results are
    displayed. You can then optimize the loop and examine its stability.

MESSAGES
    During a calculation, three messages can appear on the screen ;
        - a message, this informs you about certain decisions
          or alterations made during a calculation.
        - a WARNING which informs you about possible problems
          that can arise with the current values of the parameters
          and how you can solve them, or how the program has solved them.
          A warning during optimizing will often result in an altered
          calculated parameter with respect to the input value.
        - an ERROR which informs you of an error during a calculation
          or that the loop will fail to operate with the current values
          of parameters.
          Unlike a warning which can be ignored, an error message must
          be obeyed.

RESULTS
    The results are presented in three groups on your screen :
      - the main system parameters you specified.
      - the calculated values of the external bias components for the
        VCO, and the values of the loop filter components and constants.
      - the calculated dynamic loop parameters.

OPTIMIZE
    An extremely useful feature of the program is the ability to tailor
    the loop parameters to your specification quickly. A somewhat
    tedious process when done manually, owing to the interdependency of
    the loop parameters. This is why PLLs were not always fully
    optimized in the past. With the program sixteen parameters can be
    altered individually, the new values of the dependent parameters
    being calculated automatically. Before optimizing starts the
    selected parameter is described and you can abort the optimizing
    before any alterations are made.

    In order to rearrange the loop such that the desired result is obtained,
    one of the two main loop parameters, Wn or zeta, is altered. This can
    often only be done by approximation. If the total loop is recalculated
    with the altered value of Wn or zeta, the desired result may not be obtained
    completely. Re-entering the original value will usually produce the desired
    result. If a WARNING message appears during the calculation, it is likely
    that the inserted value has also been changed. This can indicate that it is
    impossible to obtain the inserted value with the present configuration.
    However if the parameter being optimized depends on both Wn and zeta,
    only one of them is altered as indicated in the 'General information and
    warning' screen. Changing the other main loop parameter via optimize, will
    often help to get closer to the desired result.

    After optimization, you can print the results. The program will
    ask you for a title for your application and print this above
    the results together with the current date, assuming you've
    correctly set your system date.
    If your PC has a suitable graphics card, you can generate a Bode
    plot of the open loop to examine the loop stability. If the
    stability is inadequate, you can return to the optimization menu
    and make further alterations to the design.

    One option in the optimization menu can be used to evaluate
    existing designs. First, enter the system information in the
    usual way and let the program calculate its own values of filter
    components. Then select option 10 and enter the values of the
    components in your existing filter and start the calculations again
    to obtain a complete analysis of an existing loop.


WORLD-WIDE SALES ORGANIZATIONS
    At the end of the program is a complete list of the world-wide
    PHILIPS sales organizations which can supply more information on
    HCMOS products.
    For full design data, refer to :
      - PHILIPS High-speed CMOS Logic data handbook IC06.
      - PHILIPS Technical Publication, PHASE LOCKED LOOP CIRCUITS
        74HC/HCT4046A & 74HC/HCT7046A, ordering code 9398 649 90011.
        Besides providing an extensive description of the HCMOS PLL
        circuits, this publication explains the PLL theory behind the
        design program in detail.

    This PLL design-aid diskette is not copy protected and can be freely
    distributed. Duplicate the entire diskette using the DOS 'DISKCOPY'
    command or similar utility.

ACKNOWLEDGEMENT
    This program was created by Rob Volgers, Philips CMOS Logic dept. He
    is much indebted to Mr. Wim Rosink of the Philips Application Lab
    (PCALE) in Eindhoven for his stimulating discussions and his support
    with the mathematics.
    He also wants to thank Mr. R.C. den Dulk of the Technical University
    of Delft for reviewing the diskette.