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Assembly Source File  |  1995-06-06  |  4.3 KB  |  122 lines
  1. comment $
  2. ╒══════════════════════════════════════════════════════════════════════════╕
  3. │ "DMA_Setup"   PROGRAM A CHANNEL ON THE 8237 DMA CONTROLLER               │
  4. │             A general routine to program the DMA controler.              │
  5. │                                                                          │
  6. │ By Adam Seychell                                                         │
  7. │                                                                          │
  8. │                                                                          │
  9. │ INPUT:        AL    Mode Register  ( bits 0..1 ignored )                 │
  10. │               AH    channel   ( 0..7 )                                   │
  11. │               EBX   Physical Base Address ( 0..0ffffffh )                │
  12. │               ECX   Bytes to transfer     ( 1..10000h )                  │
  13. │                                                                          │
  14. │                                                                          │
  15. │Distroys:  EAX, EDX & ECX                                                 │
  16. │                                                                          │
  17. │        code has been optimized and fully tested.                         │
  18. └────────────────────────────────────────────────────────────────────────── $
  19. .386
  20. .Model flat
  21. .Code
  22.  
  23. DMA_Setup PROC
  24.         push    edi
  25.         push    ebx
  26.         xor     edx,edx
  27.         and     ah,7
  28.         mov     DMA_channel,ah
  29.         and     al,NOT 3
  30.         mov     mode,al
  31.  
  32.         ; -----  set channel mask register ------
  33.         movzx   edi,DMA_channel
  34.         mov     eax,edi
  35.         shr     edi,2
  36.         and     al,0011b
  37.         or      al,0100b
  38.         mov     dl,DMA_SNGL[edi]
  39.         out     dx,al
  40.  
  41.         ; ----- set mode register ------
  42.         and     al,03h
  43.         or      al,Mode
  44.         mov     dl,DMA_MODE[edi]
  45.         out     dx,al
  46.  
  47.         ; ------  clear MSB/LSB flip flop -----------
  48.         mov     dl,DMA_CLRFF[edi]
  49.         out     dx,al
  50.  
  51.  
  52.  
  53.         ;---- set byte count register ----
  54.         movzx   edi,DMA_channel
  55.         mov     eax,ecx
  56.         mov     ecx,edi
  57.         shr     ecx,2
  58.         shr     eax,cl                ; divide count address by 2 for DMA # 2
  59.         dec     eax                     ; count - 1
  60.         mov     dl,DMA_CNT[edi]         ; bits 0..7
  61.         out     dx,al
  62.         shr     eax,8
  63.         out     dx,al                   ; bits 8..15
  64.  
  65.  
  66.         ;---- set channel base address ---
  67.         shr     ebx,cl                ; divide base address by 2 for DMA # 2
  68.         mov     al,BL                       ; set bits 0..7
  69.         mov     dl,DMA_ADDR[edi]
  70.         out     dx,al
  71.         mov     al,BH                       ; set bits 8..15
  72.         out     dx,al
  73.  
  74.         shr     ebx,15           ; divide base address by 8000h for DMA # 2
  75.         xor     cl,1
  76.         shr     ebx,cl           ; divide base address by 10000h for DMA # 1
  77.         mov     al,BL            ; set bits 16..23 ( in LSB page register )
  78.         mov     dl,DMA_PAGE[edi]
  79.         out     dx,al
  80.  
  81.  
  82.         ; -----  clear channel (mask register) ------
  83.         mov     eax,edi
  84.         shr     edi,2
  85.         and     al,03h
  86.         mov     dl,DMA_SNGL[edi]
  87.         out     dx,al
  88.         pop     ebx
  89.         pop     edi
  90.         ret
  91.  
  92.  
  93. Mode            Db  ?
  94. DMA_Channel     Db  ?
  95.  
  96.  
  97. ;* 1st & 2nd DMA Controler's ports *;
  98.  
  99.   DMA_STAT   db 008h,0D0h        ;* read status register *;
  100.   DMA_CMD    db 008h,0D0h        ;* write command register *;
  101.   DMA_REQ    db 009h,0D2h        ;* write request register *;
  102.   DMA_SNGL   db 00Ah,0D4h        ;* write single bit register *;
  103.   DMA_MODE   db 00Bh,0D6h        ;* write mode register *;
  104.   DMA_CLRFF  db 00Ch,0D8h        ;* clear byte ptr flip;flop *;
  105.   DMA_MCLR   db 00Dh,0DAh        ;* master clear register *;
  106.   DMA_CLRM   db 00Eh,0DCh        ;* clear mask register *;
  107.   DMA_WRTALL db 00Fh,0DEh        ;* write all mask register *;
  108.  
  109. ; * ports for 8 channels *;
  110.  
  111. DMA_PAGE        db 087h,083h,081h,082h,08Fh,08Bh,089h,08Ah ; page register
  112. DMA_ADDR        db 000h,002h,004h,006h,0C0h,0C4h,0C8h,0CCh ; base adddress
  113. DMA_CNT         db 001h,003h,005h,007h,0C2h,0C6h,0CAh,0CEh ; base count
  114.  
  115. DMA_Setup   Endp
  116.  
  117.  
  118.             Public  DMA_Setup
  119.  
  120.  
  121.             End
  122.