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Text File  |  1995-04-10  |  5.9 KB  |  152 lines
  1. :PLDasm_LANGUAGE_SUMMARY
  2.  
  3. :SIGNAL_EXTENSIONS
  4. :Macrocell_Output_Signal_Extensions
  5.     ~.FB~    -  feedback multiplexer output
  6.     ~.IO~    -  I/O pin feedback
  7. :Macrocell_Output_Control_Signal_Extensions    
  8.     ~.TRST~  -  tristate enable/disable control input
  9. :Flip-Flop_Clock_Signal_Extensions    
  10.     ~.ACLK~  -  asynchronous clock input
  11.     ~.CLKF~  -  synchronous clock input
  12.     ~.ALE~   -  asynchronous latch enable input
  13.     ~.LE~    -  synchronous latch enable input
  14. :Flip-Flop_Data_Signal_Extensions    
  15.     ~.D~     -  D flip-flop data input
  16.     ~.J~     -  JK flip-flop data input
  17.     ~.K~     -  JK flip-flop data input
  18.     ~.R~     -  SR flip-flop data input
  19.     ~.S~     -  SR flip-flop data input
  20.     ~.T~     -  toggle flip-flop data input
  21. :Flip-Flop_Control_Signal_Extensions
  22.     ~.RSTF~  -  flip-flop reset control input
  23.     ~.SETF~  -  flip-flop set control input
  24. :State_Machine_Output_Signal_Extensions    
  25.     ~.OUTF~  -  Mealy/Moore machine output
  26. :RAM_Data_Signal_Extensions
  27.     ~.ADDR~  -  SRAM address line
  28.     ~.DATA~  -  SRAM data output
  29. :RAM_Control_Signal_Extensions    
  30.     ~.BE~    -  SRAM block enable
  31.     ~.WE~    -  SRAM write enable
  32. :Comparator_Signal_Extensions
  33.     ~.CMP~   -  12-bit comparator output
  34.  
  35. :PLDasm_KEYWORDS
  36. :Design_Header_Keywords
  37.     ~TITLE~       - specify design's title
  38.     ~AUTHOR~      - specify designer
  39.     ~COMPANY~     - specify designer's company
  40.     ~DATE~        - specify date of design
  41.     ~REVISION~    - specify design's revision #
  42.     ~PATTERN~     - specify identifying pattern
  43. :Design_Tracking_Keywords    
  44.     ~SIGNATURE~   - load identifying pattern
  45. :OPTIONS_Keywords
  46.     ~OPTIONS~     - chip options follow
  47.     ~TURBO~       - fast/slow enable/disable
  48.     ~SECURITY~    - config. readback enable/disable
  49. :CHIP_Declaration_Keywords
  50.     ~CHIP~        - specify type of FPGA or PLD
  51.     ~IFX780_84~   - EPX780 FPGA in 84-pin PLCC
  52.     ~IFX780_132~  - EPX780 FPGA in 132-pin PQFP
  53.     ~IFX8160_208~ - EPX8160 FPGA in 208-pin PQFP
  54.     ~INTEL_ARCH~  - device-independent architecture
  55. :Pin_Declaration_Keywords
  56.     ~PIN~         - pin declaration
  57.     ~NODE~        - buried macrocell declaration
  58.     ~INPUT~       - input-only pin
  59.     ~CMOS_LEVEL~  - CMOS input thresholds
  60.     ~TTL_LEVEL~   - TTL input thresholds
  61.     ~OUTPUT~      - output-only pin
  62.     ~3VOLT~       - 3.3V output signal range
  63.     ~5VOLT~       - 5V output signal range
  64.     ~OPEN_DRAIN~  - output pulls to ground only
  65.     ~HIGH~        - active high output
  66.     ~LOW~         - active low output
  67.     ~COMB~        - combinatorial output
  68.     ~COMBINATORIAL~
  69.     ~REG~         - registered output
  70.     ~REGISTERED~
  71.     ~LAT~         - latched output
  72.     ~LATCHED~
  73.     ~REGFBK~      - registered feedback
  74.     ~CMBFBK~      - combinatorial feedback
  75.     ~LATFBK~      - latched feedback
  76.     ~TREGFBK~     - toggle flip-flop feedback
  77.     ~PINFBK~      - feedback signal going to pin
  78.     ~DELAYCLK~    - dlyd. sync. clock to flip-flop
  79.     ~RAM~         - SRAM block input/output
  80. :RAM_Initialization_Keywords
  81.     ~DEFAULT_VALUE~ - entire RAM initial value
  82.     ~RAM_DEFAULTS~  - RAM location initial values
  83. :Design_Section_Keywords
  84.     ~EQUATIONS~   - start Boolean equations
  85.     ~T_TAB~       - start truth-table
  86.     ~STATE~       - start state machine description
  87. :Logic_Level_Keywords
  88.     ~GND~         - logic low
  89.     ~VCC~         - logic high
  90.     ~NC~          - no connection
  91. :Boolean_Equation_Keywords
  92.     ~/~           - NOT
  93.     ~*~           - AND
  94.     ~+~           - OR
  95.     ~:+:~         - XOR
  96.     ~= ~          - combinatorial assignment
  97.     ~:=~          - registered assignment
  98.     ~*=~          - latched assignment
  99. :State_Machine_Keywords
  100.     ~MOORE_MACHINE~  - Moore state machine
  101.     ~MEALY_MACHINE~  - Mealy state machine
  102.     ~CONDITIONS~     - state transition conditions
  103.     ~DEFAULT_BRANCH~ - default state transition
  104.     ~NEXT_STATE~     - go to next state on default
  105.     ~HOLD_STATE~     - hold state on default
  106.     ~DEFAULT_OUTPUT~ - specify default outputs
  107.     ~OUTPUT_HOLD~    - hold current outputs on default
  108. :Hierarchical_Module_Keywords
  109.     ~DEFMOD~      - begin module definition
  110.     ~ENDMOD~      - end module definition
  111.     ~FILE~        - specify file where module is defined
  112.     ~MODULE~      - specify module to instantiate in design
  113. :Simulation_Keywords
  114.     ~SIMULATION~  - start simulation section
  115.     ~VECTOR~      - group signals into a vector
  116.     ~TRACE_OFF~   - trace the listed signal values
  117.     ~TRACE_ON~    - stop tracing signal values
  118.     ~PRLDF~       - initialize flip-flop values
  119.     ~SETF~        - set signal values
  120.     ~CLOCKF~      - toggle signal value twice
  121.     ~IF~          - conditional execution
  122.     ~THEN~        - terminates IF condition
  123.     ~ELSE~        - alternate conditional action
  124.     ~FOR~         - iterative loop
  125.     ~TO~          - specify loop terminal value
  126.     ~DO~          - terminate FOR setup
  127.     ~WHILE~       - conditional loop
  128.     ~BEGIN~       - begin block of statements
  129.     ~END~         - end block of statements
  130.     ~CHECK~       - compare signal to its correct value
  131. :Simulation_Number_Representations
  132.     ~HEXADECIMAL~ - 0x17FC or #H3A6D (leading 0x or #H)
  133.     ~OCTAL~       - 0326 or #O174 (leading 0 or #O)
  134.     ~BINARY~      - #B11010001 (leading #B)
  135.     ~DECIMAL~     - 75 (no leading character sequence)
  136. :Simulation_Conditionals
  137.     ~=~           - equals    (lowest precedence)
  138.     ~/=~          - not equal
  139.     ~>=~          - greater than or equal
  140.     ~>~           - greater than
  141.     ~<=~          - less than or equal
  142.     ~<~           - less than (highest precedence)
  143.  
  144. **************************************
  145. * Copyright 1995 by XESS Corporation *
  146. *        2608 Sweetgum Drive         *
  147. *          Apex, NC 27502            *
  148. *               USA                  *
  149. *          (919) 387-0076            *
  150. *          (800) 549-9377            *
  151. **************************************
  152.