(***************************************************************************)
(*                                                                         *)
(*                         Copyright (C) 1987-1990                         *)
(*                      by Gogesch Micro Systems, INC.                     *)
(*                                                                         *)
(*                           All rights reserved.                          *)
(*                                                                         *)
(***************************************************************************)


%StartModel
%Manufacturer:Intel
%Type:EP320
%PartNumber:D5C032-30
%LastNode ? ?
%NumPins: 20
%FDF AND 0 ~P1 P1 ~P2 P2 ~P3 P3 ~P4 P4 ~P5 P5 ~P6 P6 ~P7 P7 ~P8 P8 ~P9 P9
     ~P11 P11 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 ~N7 N7 ~N8 N8*

%MACRO LOR8(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+36,%InFuse+72,%InFuse+108,%InFuse+144,%InFuse+180,
     %InFuse+216,%InFuse+252; OutLNode);
%MACEND;

%MACRO EP320(ArchFuse:%SF, EnableFuse:%SF, OrOutput:%TEXT, OutPin:%TEXT,
             TNode:%TEXT, InFuse:%FF, FeedBack:%TEXT, QOut:%TEXT);

%CASE %ArchFuse+3, %ArchFuse+2, %ArchFuse+1, %ArchFuse
   0:
    %IF %EnableFuse..%EnableFuse+35 = 1 %THEN
     INV(OrOutput; OutPin; 30,30,30,30);
    %ELSE
     INV(OrOutput; TNode; 30,30,30,30);
     TSB(TNode, %InFuse; OutPin; 30,30,30,30,30,30,30,30);
    %END;
    BUF(OutPin; FeedBack; 0,0,0,0);
  |3:
    %IF %EnableFuse..%EnableFuse+35 = 1 %THEN
     BUF(OrOutput; OutPin; 30,30,30,30);
    %ELSE
     BUF(OrOutput; TNode; 30,30,30,30);
     TSB(TNode, %InFuse; OutPin; 30,30,30,30,30,30,30,30);
    %END;
     BUF(OutPin; FeedBack; 0,0,0,0);
  |12:
     INV(OrOutput; TNode; 0,0,0,0);
     DQFF(TNode, P1; QOut; 1,1,1,1,1,1,1,1,1,1,1,1);
    %IF %EnableFuse..%EnableFuse+35 = 1 %THEN
     BUF(QOut; OutPin; 0,0,0,0);
    %ELSE
     TSB(QOut, %InFuse; OutPin; 1,1,1,1,1,1,1,1);
    %END;
    BUF(QOut; FeedBack; 0,0,0,0);
  |15:
     DQFF(OrOutput, P1; TNode; 17,17,23,0,11,11,17,17,23,0,11,11);
    %IF %EnableFuse..%EnableFuse+35 = 1 %THEN
     BUF(TNode; OutPin; 0,0,0,0);
    %ELSE
     TSB(TNode, %InFuse; OutPin; 30,30,30,30,30,30,30,30);
    %END;
    BUF(TNode; FeedBack; 0,0,0,0);
  %END;
%MACEND;

LOR8(%FF00, L1);
LOR8(%FF324, L2);
LOR8(%FF648, L3);
LOR8(%FF972, L4);
LOR8(%FF1296, L5);
LOR8(%FF1620, L6);
LOR8(%FF1944, L7);
LOR8(%FF2268, L8);

EP320(%SF2880, %SF288, L1, P19, N9, %FF288, N8, N17);
EP320(%SF2884, %SF612, L2, P18, N10, %FF612, N7, N18);
EP320(%SF2888, %SF936, L3, P17, N11, %FF936, N6, N19);
EP320(%SF2892, %SF1260, L4, P16, N12, %FF1260, N5, N20);
EP320(%SF2896, %SF1584, L5, P15, N13, %FF1584, N4, N21);
EP320(%SF2900, %SF1908, L6, P14, N14, %FF1908, N3, N22);
EP320(%SF2904, %SF2232, L7, P13, N15, %FF2232, N2, N23);
EP320(%SF2908, %SF2556, L8, P12, N16, %FF2556, N1, N24);
%EndModel

%StartModel
%Manufacturer:Intel
%Type:EP320
%PartNumber:D5C032-35
%LastNode ? ?
%NumPins: 20
%FDF AND 0 ~P1 P1 ~P2 P2 ~P3 P3 ~P4 P4 ~P5 P5 ~P6 P6 ~P7 P7 ~P8 P8 ~P9 P9
     ~P11 P11 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 ~N7 N7 ~N8 N8*

%MACRO LOR8(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+36,%InFuse+72,%InFuse+108,%InFuse+144,%InFuse+180,
     %InFuse+216,%InFuse+252; OutLNode);
%MACEND;

%MACRO EP320(ArchFuse:%SF, EnableFuse:%SF, OrOutput:%TEXT, OutPin:%TEXT,
             TNode:%TEXT, InFuse:%FF, FeedBack:%TEXT, QOut:%TEXT);
%CASE %ArchFuse+3, %ArchFuse+2, %ArchFuse+1, %ArchFuse
   0:
    %IF %EnableFuse..%EnableFuse+35 = 1 %THEN
     INV(OrOutput; OutPin; 35,35,35,35);
    %ELSE
     INV(OrOutput; TNode; 35,35,35,35);
     TSB(TNode, %InFuse; OutPin; 35,35,35,35,35,35,35,35);
    %END;
    BUF(OutPin; FeedBack; 0,0,0,0);
  |3:
    %IF %EnableFuse..%EnableFuse+35 = 1 %THEN
     BUF(OrOutput; OutPin; 35,35,35,35);
    %ELSE
     BUF(OrOutput; TNode; 35,35,35,35);
     TSB(TNode, %InFuse; OutPin; 35,35,35,35,35,35,35,35);
    %END;
     BUF(OutPin; FeedBack; 0,0,0,0);
  |12:
     INV(OrOutput; TNode; 0,0,0,0);
     DQFF(TNode, P1; QOut; 1,1,1,1,1,1,1,1,1,1,1,1);
    %IF %EnableFuse..%EnableFuse+35 = 1 %THEN
     BUF(QOut; OutPin; 0,0,0,0);
    %ELSE
     TSB(QOut, %InFuse; OutPin; 1,1,1,1,1,1,1,1);
    %END;
    BUF(QOut; FeedBack; 0,0,0,0);
  |15:
     DQFF(OrOutput, P1; TNode; 20,20,24,0,12,12,20,20,24,0,12,12);
    %IF %EnableFuse..%EnableFuse+35 = 1 %THEN
     BUF(TNode; OutPin; 0,0,0,0);
    %ELSE
     TSB(TNode, %InFuse; OutPin; 35,35,35,35,35,35,35,35);
    %END;
    BUF(TNode; FeedBack; 0,0,0,0);
  %END;
%MACEND;

LOR8(%FF00, L1);
LOR8(%FF324, L2);
LOR8(%FF648, L3);
LOR8(%FF972, L4);
LOR8(%FF1296, L5);
LOR8(%FF1620, L6);
LOR8(%FF1944, L7);
LOR8(%FF2268, L8);

EP320(%SF2880, %SF288, L1, P19, N9, %FF288, N8, N17);
EP320(%SF2884, %SF612, L2, P18, N10, %FF612, N7, N18);
EP320(%SF2888, %SF936, L3, P17, N11, %FF936, N6, N19);
EP320(%SF2892, %SF1260, L4, P16, N12, %FF1260, N5, N20);
EP320(%SF2896, %SF1584, L5, P15, N13, %FF1584, N4, N21);
EP320(%SF2900, %SF1908, L6, P14, N14, %FF1908, N3, N22);
EP320(%SF2904, %SF2232, L7, P13, N15, %FF2232, N2, N23);
EP320(%SF2908, %SF2556, L8, P12, N16, %FF2556, N1, N24);
%EndModel

%StartModel
%Manufacturer:Intel
%Type:EP320
%PartNumber:P5C032-30
%LastNode ? ?
%NumPins: 20
%FDF AND 0 ~P1 P1 ~P2 P2 ~P3 P3 ~P4 P4 ~P5 P5 ~P6 P6 ~P7 P7 ~P8 P8 ~P9 P9
     ~P11 P11 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 ~N7 N7 ~N8 N8*

%MACRO LOR8(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+36,%InFuse+72,%InFuse+108,%InFuse+144,%InFuse+180,
     %InFuse+216,%InFuse+252; OutLNode);
%MACEND;

%MACRO EP320(ArchFuse:%SF, EnableFuse:%SF, OrOutput:%TEXT, OutPin:%TEXT,
             TNode:%TEXT, InFuse:%FF, FeedBack:%TEXT, QOut:%TEXT);
%CASE %ArchFuse+3, %ArchFuse+2, %ArchFuse+1, %ArchFuse
   0:
    %IF %EnableFuse..%EnableFuse+35 = 1 %THEN
     INV(OrOutput; OutPin; 30,30,30,30);
    %ELSE
     INV(OrOutput; TNode; 30,30,30,30);
     TSB(TNode, %InFuse; OutPin; 30,30,30,30,30,30,30,30);
    %END;
    BUF(OutPin; FeedBack; 0,0,0,0);
  |3:
    %IF %EnableFuse..%EnableFuse+35 = 1 %THEN
     BUF(OrOutput; OutPin; 30,30,30,30);
    %ELSE
     BUF(OrOutput; TNode; 30,30,30,30);
     TSB(TNode, %InFuse; OutPin; 30,30,30,30,30,30,30,30);
    %END;
     BUF(OutPin; FeedBack; 0,0,0,0);
  |12:
     INV(OrOutput; TNode; 0,0,0,0);
     DQFF(TNode, P1; QOut; 1,1,1,1,1,1,1,1,1,1,1,1);
    %IF %EnableFuse..%EnableFuse+35 = 1 %THEN
     BUF(QOut; OutPin; 0,0,0,0);
    %ELSE
     TSB(QOut, %InFuse; OutPin; 1,1,1,1,1,1,1,1);
    %END;
    BUF(QOut; FeedBack; 0,0,0,0);
  |15:
     DQFF(OrOutput, P1; TNode; 17,17,23,0,11,11,17,17,23,0,11,11);
    %IF %EnableFuse..%EnableFuse+35 = 1 %THEN
     BUF(TNode; OutPin; 0,0,0,0);
    %ELSE
     TSB(TNode, %InFuse; OutPin; 30,30,30,30,30,30,30,30);
    %END;
    BUF(TNode; FeedBack; 0,0,0,0);
  %END;
%MACEND;

LOR8(%FF00, L1);
LOR8(%FF324, L2);
LOR8(%FF648, L3);
LOR8(%FF972, L4);
LOR8(%FF1296, L5);
LOR8(%FF1620, L6);
LOR8(%FF1944, L7);
LOR8(%FF2268, L8);

EP320(%SF2880, %SF288, L1, P19, N9, %FF288, N8, N17);
EP320(%SF2884, %SF612, L2, P18, N10, %FF612, N7, N18);
EP320(%SF2888, %SF936, L3, P17, N11, %FF936, N6, N19);
EP320(%SF2892, %SF1260, L4, P16, N12, %FF1260, N5, N20);
EP320(%SF2896, %SF1584, L5, P15, N13, %FF1584, N4, N21);
EP320(%SF2900, %SF1908, L6, P14, N14, %FF1908, N3, N22);
EP320(%SF2904, %SF2232, L7, P13, N15, %FF2232, N2, N23);
EP320(%SF2908, %SF2556, L8, P12, N16, %FF2556, N1, N24);
%EndModel

%StartModel
%Manufacturer:Intel
%Type:EP320
%PartNumber:P5C032-35
%LastNode ? ?
%NumPins: 20
%FDF AND 0 ~P1 P1 ~P2 P2 ~P3 P3 ~P4 P4 ~P5 P5 ~P6 P6 ~P7 P7 ~P8 P8 ~P9 P9
     ~P11 P11 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 ~N7 N7 ~N8 N8*

%MACRO LOR8(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+36,%InFuse+72,%InFuse+108,%InFuse+144,%InFuse+180,
     %InFuse+216,%InFuse+252; OutLNode);
%MACEND;

%MACRO EP320(ArchFuse:%SF, EnableFuse:%SF, OrOutput:%TEXT, OutPin:%TEXT,
             TNode:%TEXT, InFuse:%FF, FeedBack:%TEXT, QOut:%TEXT);
%CASE %ArchFuse+3, %ArchFuse+2, %ArchFuse+1, %ArchFuse
   0:
    %IF %EnableFuse..%EnableFuse+35 = 1 %THEN
     INV(OrOutput; OutPin; 35,35,35,35);
    %ELSE
     INV(OrOutput; TNode; 35,35,35,35);
     TSB(TNode, %InFuse; OutPin; 35,35,35,35,35,35,35,35);
    %END;
    BUF(OutPin; FeedBack; 0,0,0,0);
  |3:
    %IF %EnableFuse..%EnableFuse+35 = 1 %THEN
     BUF(OrOutput; OutPin; 35,35,35,35);
    %ELSE
     BUF(OrOutput; TNode; 35,35,35,35);
     TSB(TNode, %InFuse; OutPin; 35,35,35,35,35,35,35,35);
    %END;
     BUF(OutPin; FeedBack; 0,0,0,0);
  |12:
     INV(OrOutput; TNode; 0,0,0,0);
     DQFF(TNode, P1; QOut; 1,1,1,1,1,1,1,1,1,1,1,1);
    %IF %EnableFuse..%EnableFuse+35 = 1 %THEN
     BUF(QOut; OutPin; 0,0,0,0);
    %ELSE
     TSB(QOut, %InFuse; OutPin; 1,1,1,1,1,1,1,1);
    %END;
    BUF(QOut; FeedBack; 0,0,0,0);
  |15:
     DQFF(OrOutput, P1; TNode; 20,20,24,0,12,12,20,20,24,0,12,12);
    %IF %EnableFuse..%EnableFuse+35 = 1 %THEN
     BUF(TNode; OutPin; 0,0,0,0);
    %ELSE
     TSB(TNode, %InFuse; OutPin; 35,35,35,35,35,35,35,35);
    %END;
    BUF(TNode; FeedBack; 0,0,0,0);
  %END;
%MACEND;

LOR8(%FF00, L1);
LOR8(%FF324, L2);
LOR8(%FF648, L3);
LOR8(%FF972, L4);
LOR8(%FF1296, L5);
LOR8(%FF1620, L6);
LOR8(%FF1944, L7);
LOR8(%FF2268, L8);

EP320(%SF2880, %SF288, L1, P19, N9, %FF288, N8, N17);
EP320(%SF2884, %SF612, L2, P18, N10, %FF612, N7, N18);
EP320(%SF2888, %SF936, L3, P17, N11, %FF936, N6, N19);
EP320(%SF2892, %SF1260, L4, P16, N12, %FF1260, N5, N20);
EP320(%SF2896, %SF1584, L5, P15, N13, %FF1584, N4, N21);
EP320(%SF2900, %SF1908, L6, P14, N14, %FF1908, N3, N22);
EP320(%SF2904, %SF2232, L7, P13, N15, %FF2232, N2, N23);
EP320(%SF2908, %SF2556, L8, P12, N16, %FF2556, N1, N24);
%EndModel

%StartModel
%Manufacturer:Intel
%Type:EP600
%PartNumber:D5C060-45
%LastNode ? ?
%NumPins: 24
%FDF AND 0 ~P2 P2 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 ~N7 N7 ~N8 N8
         ~P11 P11 ~P14 P14 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~N13 N13
	 ~N14 N14 ~N15 N15 ~N16 N16 ~P23 P23 *

%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; LorOutput);
 %ELSE
  LNOR(%InFuse, %InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; LorOutput);
 %END;
%MACEND;

%MACRO EP600(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
      BUF(LorOutput; Outpin; 43,43,43,43);
   %ELSE
      BUF(LorOutput; TSBInput; 43,43,43,43);
      TSB(TSBInput, %InFuse; Outpin; 45,45,45,45,45,45,45,45);
   %END;
   BUF(OutPin; FeedBack; 2,2,2,2);
 |1,3:
   BUF(LorOutput; Outpin; 43,43,43,43);
   BUF(OutPin; FeedBack; 2,2,2,2);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 22,22,36,0,18,18,45,45,0,0,22,22,36,0,18,18,45,45,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(LorOutput; Outpin; 43,43,43,43);
    %ELSE
       BUF(LorOutput; TSBInput; 43,43,43,43);
       TSB(TSBInput, %InFuse; Outpin; 45,45,45,45,45,45,45,45);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 50,50,10,15,18,18,45,45,0,0,50,50,10,15,18,18,45,45,0,0);
   BUF(LorOutput; Outpin; 43,43,43,43);
   BUF(TNode; FeedBack; 0,0,0,0);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 22,22,36,0,18,18,45,45,0,0,22,22,36,0,18,18,45,45,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(LorOutput; Outpin; 43,43,43,43);
    %ELSE
       BUF(LorOutput; TSBInput; 43,43,43,43);
       TSB(TSBInput, %InFuse; Outpin; 45,45,45,45,45,45,45,45);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 50,50,10,15,18,18,45,45,0,0,50,50,10,15,18,18,45,45,0,0);
   BUF(LorOutput; Outpin; 43,43,43,43);
   BUF(TNode; FeedBack; 0,0,0,0);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 22,22,36,0,18,18,45,45,0,0,22,22,36,0,18,18,45,45,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 45,45,45,45,45,45,45,45);
    %END;
   BUF(OutPin; FeedBack; 2,2,2,2);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 50,50,10,15,18,18,45,45,0,0,50,50,10,15,18,18,45,45,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(OutPin; FeedBack; 2,2,2,2);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 22,22,36,0,18,18,45,45,0,0,22,22,36,0,18,18,45,45,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 45,45,45,45,45,45,45,45);
    %END;
   BUF(OutPin; FeedBack; 2,2,2,2);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 50,50,10,15,18,18,45,45,0,0,50,50,10,15,18,18,45,45,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(OutPin; FeedBack; 2,2,2,2);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 22,22,36,0,18,18,45,45,0,0,22,22,36,0,18,18,45,45,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 45,45,45,45,45,45,45,45);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 50,50,10,15,18,18,45,45,0,0,50,50,10,15,18,18,45,45,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 22,22,36,0,18,18,45,45,0,0,22,22,36,0,18,18,45,45,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 45,45,45,45,45,45,45,45);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 50,50,10,15,18,18,45,45,0,0,50,50,10,15,18,18,45,45,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 %END;
%MACEND;

LOR8(%SF6440, %FF3200, L1);
LOR8(%SF6445, %FF3600, L2);
LOR8(%SF6450, %FF4000, L3);
LOR8(%SF6455, %FF4400, L4);
LOR8(%SF6460, %FF4800, L5);
LOR8(%SF6465, %FF5200, L6);
LOR8(%SF6470, %FF5600, L7);
LOR8(%SF6475, %FF6000, L8);
LOR8(%SF6435, %FF2800, L9);
LOR8(%SF6430, %FF2400, L10);
LOR8(%SF6425, %FF2000, L11);
LOR8(%SF6420, %FF1600, L12);
LOR8(%SF6415, %FF1200, L13);
LOR8(%SF6410, %FF800, L14);
LOR8(%SF6405, %FF400, L15);
LOR8(%SF6400, %FF00, L16);

EP600(%SF6441, %SF3560, L1, P3, L17, %FF3560, N1, N17, N33, %FF3520, L33, N65, P1);
EP600(%SF6446, %SF3960, L2, P4, L18, %FF3960, N2, N18, N34, %FF3920, L34, N66, P1);
EP600(%SF6451, %SF4360, L3, P5, L19, %FF4360, N3, N19, N35, %FF4320, L35, N67, P1);
EP600(%SF6456, %SF4760, L4, P6, L20, %FF4760, N4, N20, N36, %FF4720, L36, N68, P1);
EP600(%SF6461, %SF5160, L5, P7, L21, %FF5160, N5, N21, N37, %FF5120, L37, N69, P1);
EP600(%SF6466, %SF5560, L6, P8, L22, %FF5560, N6, N22, N38, %FF5520, L38, N70, P1);
EP600(%SF6471, %SF5960, L7, P9, L23, %FF5960, N7, N23, N39, %FF5920, L39, N71, P1);
EP600(%SF6476, %SF6360, L8, P10, L24, %FF6360, N8, N24, N40, %FF6320, L40, N72, P1);
EP600(%SF6436, %SF3160, L9, P15, L25, %FF3160, N9, N25, N41, %FF3120, L41, N73, P13);
EP600(%SF6431, %SF2760, L10, P16, L26, %FF2760, N10, N26, N42, %FF2720, L42, N74, P13);
EP600(%SF6426, %SF2360, L11, P17, L27, %FF2360, N11, N27, N43, %FF2320, L43, N75, P13);
EP600(%SF6421, %SF1960, L12, P18, L28, %FF1960, N12, N28, N44, %FF1920, L44, N76, P13);
EP600(%SF6416, %SF1560, L13, P19, L29, %FF1560, N13, N29, N45, %FF1520, L45, N77, P13);
EP600(%SF6411, %SF1160, L14, P20, L30, %FF1160, N14, N30, N46, %FF1120, L46, N78, P13);
EP600(%SF6406, %SF760, L15, P21, L31, %FF760, N15, N31, N47, %FF720, L47, N79, P13);
EP600(%SF6401, %SF360, L16, P22, L32, %FF360, N16, N32, N48, %FF320, L48, N80, P13);
%EndModel

%StartModel
%Manufacturer:Intel
%Type:EP600
%PartNumber:D5C060-55
%LastNode ? ?
%NumPins: 24
%FDF AND 0 ~P2 P2 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 ~N7 N7 ~N8 N8
         ~P11 P11 ~P14 P14 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~N13 N13
	 ~N14 N14 ~N15 N15 ~N16 N16 ~P23 P23 *

%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; LorOutput);
 %ELSE
  LNOR(%InFuse, %InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; LorOutput);
 %END;
%MACEND;

%MACRO EP600(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
      BUF(LorOutput; Outpin; 53,53,53,53);
   %ELSE
      BUF(LorOutput; TSBInput; 53,53,53,53);
      TSB(TSBInput, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
   %END;
   BUF(OutPin; FeedBack; 2,2,2,2);
 |1,3:
   BUF(LorOutput; Outpin; 53,53,53,53);
   BUF(OutPin; FeedBack; 2,2,2,2);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,43,0,22,22,55,55,0,0,25,25,43,0,22,22,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(LorOutput; Outpin; 53,53,53,53);
    %ELSE
       BUF(LorOutput; TSBInput; 53,53,53,53);
       TSB(TSBInput, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 58,58,10,15,22,22,55,55,0,0,58,58,10,15,22,22,55,55,0,0);
   BUF(LorOutput; Outpin; 53,53,53,53);
   BUF(TNode; FeedBack; 0,0,0,0);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,43,0,22,22,55,55,0,0,25,25,43,0,22,22,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(LorOutput; Outpin; 53,53,53,53);
    %ELSE
       BUF(LorOutput; TSBInput; 53,53,53,53);
       TSB(TSBInput, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 58,58,10,15,22,22,55,55,0,0,58,58,10,15,22,22,55,55,0,0);
   BUF(LorOutput; Outpin; 53,53,53,53);
   BUF(TNode; FeedBack; 0,0,0,0);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,43,0,22,22,55,55,0,0,25,25,43,0,22,22,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(Outpin; FeedBack; 2,2,2,2);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 58,58,10,15,22,22,55,55,0,0,58,58,10,15,22,22,55,55,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 2,2,2,2);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,43,0,22,22,55,55,0,0,25,25,43,0,22,22,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(Outpin; FeedBack; 2,2,2,2);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 58,58,10,15,22,22,55,55,0,0,58,58,10,15,22,22,55,55,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 2,2,2,2);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,43,0,22,22,55,55,0,0,25,25,43,0,22,22,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 58,58,10,15,22,22,55,55,0,0,58,58,10,15,22,22,55,55,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 2,2,2,2);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,43,0,22,22,55,55,0,0,25,25,43,0,22,22,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 58,58,10,15,22,22,55,55,0,0,58,58,10,15,22,22,55,55,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 %END;
%MACEND;

LOR8(%SF6440, %FF3200, L1);
LOR8(%SF6445, %FF3600, L2);
LOR8(%SF6450, %FF4000, L3);
LOR8(%SF6455, %FF4400, L4);
LOR8(%SF6460, %FF4800, L5);
LOR8(%SF6465, %FF5200, L6);
LOR8(%SF6470, %FF5600, L7);
LOR8(%SF6475, %FF6000, L8);
LOR8(%SF6435, %FF2800, L9);
LOR8(%SF6430, %FF2400, L10);
LOR8(%SF6425, %FF2000, L11);
LOR8(%SF6420, %FF1600, L12);
LOR8(%SF6415, %FF1200, L13);
LOR8(%SF6410, %FF800, L14);
LOR8(%SF6405, %FF400, L15);
LOR8(%SF6400, %FF00, L16);

EP600(%SF6441, %SF3560, L1, P3, L17, %FF3560, N1, N17, N33, %FF3520, L33, N65, P1);
EP600(%SF6446, %SF3960, L2, P4, L18, %FF3960, N2, N18, N34, %FF3920, L34, N66, P1);
EP600(%SF6451, %SF4360, L3, P5, L19, %FF4360, N3, N19, N35, %FF4320, L35, N67, P1);
EP600(%SF6456, %SF4760, L4, P6, L20, %FF4760, N4, N20, N36, %FF4720, L36, N68, P1);
EP600(%SF6461, %SF5160, L5, P7, L21, %FF5160, N5, N21, N37, %FF5120, L37, N69, P1);
EP600(%SF6466, %SF5560, L6, P8, L22, %FF5560, N6, N22, N38, %FF5520, L38, N70, P1);
EP600(%SF6471, %SF5960, L7, P9, L23, %FF5960, N7, N23, N39, %FF5920, L39, N71, P1);
EP600(%SF6476, %SF6360, L8, P10, L24, %FF6360, N8, N24, N40, %FF6320, L40, N72, P1);
EP600(%SF6436, %SF3160, L9, P15, L25, %FF3160, N9, N25, N41, %FF3120, L41, N73, P13);
EP600(%SF6431, %SF2760, L10, P16, L26, %FF2760, N10, N26, N42, %FF2720, L42, N74, P13);
EP600(%SF6426, %SF2360, L11, P17, L27, %FF2360, N11, N27, N43, %FF2320, L43, N75, P13);
EP600(%SF6421, %SF1960, L12, P18, L28, %FF1960, N12, N28, N44, %FF1920, L44, N76, P13);
EP600(%SF6416, %SF1560, L13, P19, L29, %FF1560, N13, N29, N45, %FF1520, L45, N77, P13);
EP600(%SF6411, %SF1160, L14, P20, L30, %FF1160, N14, N30, N46, %FF1120, L46, N78, P13);
EP600(%SF6406, %SF760, L15, P21, L31, %FF760, N15, N31, N47, %FF720, L47, N79, P13);
EP600(%SF6401, %SF360, L16, P22, L32, %FF360, N16, N32, N48, %FF320, L48, N80, P13);
%EndModel

%StartModel
%Manufacturer:Intel
%Type:EP600
%PartNumber:P5C060-45
%LastNode ? ?
%NumPins: 24
%FDF AND 0 ~P2 P2 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 ~N7 N7 ~N8 N8
         ~P11 P11 ~P14 P14 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~N13 N13
	 ~N14 N14 ~N15 N15 ~N16 N16 ~P23 P23 *

%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; LorOutput);
 %ELSE
  LNOR(%InFuse, %InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; LorOutput);
 %END;
%MACEND;

%MACRO EP600(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
      BUF(LorOutput; Outpin; 43,43,43,43);
   %ELSE
      BUF(LorOutput; TSBInput; 43,43,43,43);
      TSB(TSBInput, %InFuse; Outpin; 45,45,45,45,45,45,45,45);
   %END;
   BUF(OutPin; FeedBack; 2,2,2,2);
 |1,3:
   BUF(LorOutput; Outpin; 43,43,43,43);
   BUF(OutPin; FeedBack; 2,2,2,2);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 22,22,36,0,18,18,45,45,0,0,22,22,36,0,18,18,45,45,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(LorOutput; Outpin; 43,43,43,43);
    %ELSE
       BUF(LorOutput; TSBInput; 43,43,43,43);
       TSB(TSBInput, %InFuse; Outpin; 45,45,45,45,45,45,45,45);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 50,50,10,15,18,18,45,45,0,0,50,50,10,15,18,18,45,45,0,0);
   BUF(LorOutput; Outpin; 43,43,43,43);
   BUF(TNode; FeedBack; 0,0,0,0);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 22,22,36,0,18,18,45,45,0,0,22,22,36,0,18,18,45,45,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(LorOutput; Outpin; 43,43,43,43);
    %ELSE
       BUF(LorOutput; TSBInput; 43,43,43,43);
       TSB(TSBInput, %InFuse; Outpin; 45,45,45,45,45,45,45,45);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 50,50,10,15,18,18,45,45,0,0,50,50,10,15,18,18,45,45,0,0);
   BUF(LorOutput; Outpin; 43,43,43,43);
   BUF(TNode; FeedBack; 0,0,0,0);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 22,22,36,0,18,18,45,45,0,0,22,22,36,0,18,18,45,45,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 45,45,45,45,45,45,45,45);
    %END;
   BUF(OutPin; FeedBack; 2,2,2,2);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 50,50,10,15,18,18,45,45,0,0,50,50,10,15,18,18,45,45,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(OutPin; FeedBack; 2,2,2,2);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 22,22,36,0,18,18,45,45,0,0,22,22,36,0,18,18,45,45,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 45,45,45,45,45,45,45,45);
    %END;
   BUF(OutPin; FeedBack; 2,2,2,2);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 50,50,10,15,18,18,45,45,0,0,50,50,10,15,18,18,45,45,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(OutPin; FeedBack; 2,2,2,2);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 22,22,36,0,18,18,45,45,0,0,22,22,36,0,18,18,45,45,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 45,45,45,45,45,45,45,45);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 50,50,10,15,18,18,45,45,0,0,50,50,10,15,18,18,45,45,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 22,22,36,0,18,18,45,45,0,0,22,22,36,0,18,18,45,45,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 45,45,45,45,45,45,45,45);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 50,50,10,15,18,18,45,45,0,0,50,50,10,15,18,18,45,45,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 %END;
%MACEND;

LOR8(%SF6440, %FF3200, L1);
LOR8(%SF6445, %FF3600, L2);
LOR8(%SF6450, %FF4000, L3);
LOR8(%SF6455, %FF4400, L4);
LOR8(%SF6460, %FF4800, L5);
LOR8(%SF6465, %FF5200, L6);
LOR8(%SF6470, %FF5600, L7);
LOR8(%SF6475, %FF6000, L8);
LOR8(%SF6435, %FF2800, L9);
LOR8(%SF6430, %FF2400, L10);
LOR8(%SF6425, %FF2000, L11);
LOR8(%SF6420, %FF1600, L12);
LOR8(%SF6415, %FF1200, L13);
LOR8(%SF6410, %FF800, L14);
LOR8(%SF6405, %FF400, L15);
LOR8(%SF6400, %FF00, L16);

EP600(%SF6441, %SF3560, L1, P3, L17, %FF3560, N1, N17, N33, %FF3520, L33, N65, P1);
EP600(%SF6446, %SF3960, L2, P4, L18, %FF3960, N2, N18, N34, %FF3920, L34, N66, P1);
EP600(%SF6451, %SF4360, L3, P5, L19, %FF4360, N3, N19, N35, %FF4320, L35, N67, P1);
EP600(%SF6456, %SF4760, L4, P6, L20, %FF4760, N4, N20, N36, %FF4720, L36, N68, P1);
EP600(%SF6461, %SF5160, L5, P7, L21, %FF5160, N5, N21, N37, %FF5120, L37, N69, P1);
EP600(%SF6466, %SF5560, L6, P8, L22, %FF5560, N6, N22, N38, %FF5520, L38, N70, P1);
EP600(%SF6471, %SF5960, L7, P9, L23, %FF5960, N7, N23, N39, %FF5920, L39, N71, P1);
EP600(%SF6476, %SF6360, L8, P10, L24, %FF6360, N8, N24, N40, %FF6320, L40, N72, P1);
EP600(%SF6436, %SF3160, L9, P15, L25, %FF3160, N9, N25, N41, %FF3120, L41, N73, P13);
EP600(%SF6431, %SF2760, L10, P16, L26, %FF2760, N10, N26, N42, %FF2720, L42, N74, P13);
EP600(%SF6426, %SF2360, L11, P17, L27, %FF2360, N11, N27, N43, %FF2320, L43, N75, P13);
EP600(%SF6421, %SF1960, L12, P18, L28, %FF1960, N12, N28, N44, %FF1920, L44, N76, P13);
EP600(%SF6416, %SF1560, L13, P19, L29, %FF1560, N13, N29, N45, %FF1520, L45, N77, P13);
EP600(%SF6411, %SF1160, L14, P20, L30, %FF1160, N14, N30, N46, %FF1120, L46, N78, P13);
EP600(%SF6406, %SF760, L15, P21, L31, %FF760, N15, N31, N47, %FF720, L47, N79, P13);
EP600(%SF6401, %SF360, L16, P22, L32, %FF360, N16, N32, N48, %FF320, L48, N80, P13);
%EndModel

%StartModel
%Manufacturer:Intel
%Type:EP600
%PartNumber:P5C060-55
%LastNode ? ?
%NumPins: 24
%FDF AND 0 ~P2 P2 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 ~N7 N7 ~N8 N8
         ~P11 P11 ~P14 P14 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~N13 N13
	 ~N14 N14 ~N15 N15 ~N16 N16 ~P23 P23 *

%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; LorOutput);
 %ELSE
  LNOR(%InFuse, %InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; LorOutput);
 %END;
%MACEND;

%MACRO EP600(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
      BUF(LorOutput; Outpin; 53,53,53,53);
   %ELSE
      BUF(LorOutput; TSBInput; 53,53,53,53);
      TSB(TSBInput, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
   %END;
   BUF(OutPin; FeedBack; 2,2,2,2);
 |1,3:
   BUF(LorOutput; Outpin; 53,53,53,53);
   BUF(OutPin; FeedBack; 2,2,2,2);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,43,0,22,22,55,55,0,0,25,25,43,0,22,22,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(LorOutput; Outpin; 53,53,53,53);
    %ELSE
       BUF(LorOutput; TSBInput; 53,53,53,53);
       TSB(TSBInput, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 58,58,10,15,22,22,55,55,0,0,58,58,10,15,22,22,55,55,0,0);
   BUF(LorOutput; Outpin; 53,53,53,53);
   BUF(TNode; FeedBack; 0,0,0,0);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,43,0,22,22,55,55,0,0,25,25,43,0,22,22,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(LorOutput; Outpin; 53,53,53,53);
    %ELSE
       BUF(LorOutput; TSBInput; 53,53,53,53);
       TSB(TSBInput, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 58,58,10,15,22,22,55,55,0,0,58,58,10,15,22,22,55,55,0,0);
   BUF(LorOutput; Outpin; 53,53,53,53);
   BUF(TNode; FeedBack; 0,0,0,0);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,43,0,22,22,55,55,0,0,25,25,43,0,22,22,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(Outpin; FeedBack; 2,2,2,2);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 58,58,10,15,22,22,55,55,0,0,58,58,10,15,22,22,55,55,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 2,2,2,2);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,43,0,22,22,55,55,0,0,25,25,43,0,22,22,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(Outpin; FeedBack; 2,2,2,2);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 58,58,10,15,22,22,55,55,0,0,58,58,10,15,22,22,55,55,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 2,2,2,2);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,43,0,22,22,55,55,0,0,25,25,43,0,22,22,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 58,58,10,15,22,22,55,55,0,0,58,58,10,15,22,22,55,55,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 2,2,2,2);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,43,0,22,22,55,55,0,0,25,25,43,0,22,22,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 58,58,10,15,22,22,55,55,0,0,58,58,10,15,22,22,55,55,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 %END;
%MACEND;

LOR8(%SF6440, %FF3200, L1);
LOR8(%SF6445, %FF3600, L2);
LOR8(%SF6450, %FF4000, L3);
LOR8(%SF6455, %FF4400, L4);
LOR8(%SF6460, %FF4800, L5);
LOR8(%SF6465, %FF5200, L6);
LOR8(%SF6470, %FF5600, L7);
LOR8(%SF6475, %FF6000, L8);
LOR8(%SF6435, %FF2800, L9);
LOR8(%SF6430, %FF2400, L10);
LOR8(%SF6425, %FF2000, L11);
LOR8(%SF6420, %FF1600, L12);
LOR8(%SF6415, %FF1200, L13);
LOR8(%SF6410, %FF800, L14);
LOR8(%SF6405, %FF400, L15);
LOR8(%SF6400, %FF00, L16);

EP600(%SF6441, %SF3560, L1, P3, L17, %FF3560, N1, N17, N33, %FF3520, L33, N65, P1);
EP600(%SF6446, %SF3960, L2, P4, L18, %FF3960, N2, N18, N34, %FF3920, L34, N66, P1);
EP600(%SF6451, %SF4360, L3, P5, L19, %FF4360, N3, N19, N35, %FF4320, L35, N67, P1);
EP600(%SF6456, %SF4760, L4, P6, L20, %FF4760, N4, N20, N36, %FF4720, L36, N68, P1);
EP600(%SF6461, %SF5160, L5, P7, L21, %FF5160, N5, N21, N37, %FF5120, L37, N69, P1);
EP600(%SF6466, %SF5560, L6, P8, L22, %FF5560, N6, N22, N38, %FF5520, L38, N70, P1);
EP600(%SF6471, %SF5960, L7, P9, L23, %FF5960, N7, N23, N39, %FF5920, L39, N71, P1);
EP600(%SF6476, %SF6360, L8, P10, L24, %FF6360, N8, N24, N40, %FF6320, L40, N72, P1);
EP600(%SF6436, %SF3160, L9, P15, L25, %FF3160, N9, N25, N41, %FF3120, L41, N73, P13);
EP600(%SF6431, %SF2760, L10, P16, L26, %FF2760, N10, N26, N42, %FF2720, L42, N74, P13);
EP600(%SF6426, %SF2360, L11, P17, L27, %FF2360, N11, N27, N43, %FF2320, L43, N75, P13);
EP600(%SF6421, %SF1960, L12, P18, L28, %FF1960, N12, N28, N44, %FF1920, L44, N76, P13);
EP600(%SF6416, %SF1560, L13, P19, L29, %FF1560, N13, N29, N45, %FF1520, L45, N77, P13);
EP600(%SF6411, %SF1160, L14, P20, L30, %FF1160, N14, N30, N46, %FF1120, L46, N78, P13);
EP600(%SF6406, %SF760, L15, P21, L31, %FF760, N15, N31, N47, %FF720, L47, N79, P13);
EP600(%SF6401, %SF360, L16, P22, L32, %FF360, N16, N32, N48, %FF320, L48, N80, P13);
%EndModel

%StartModel
%Manufacturer:Intel
%Type:EP600L
%PartNumber:N5C060-45
%LastNode ? ?
%NumPins: 28
%FDF AND 0 ~P3 P3 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 ~N7 N7 ~N8 N8
         ~P13 P13 ~P17 P17 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~N13 N13
	 ~N14 N14 ~N15 N15 ~N16 N16 ~P27 P27 *

%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; LorOutput);
 %ELSE
  LNOR(%InFuse, %InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; LorOutput);
 %END;
%MACEND;

%MACRO EP600(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
      BUF(LorOutput; Outpin; 43,43,43,43);
   %ELSE
      BUF(LorOutput; TSBInput; 43,43,43,43);
      TSB(TSBInput, %InFuse; Outpin; 45,45,45,45,45,45,45,45);
   %END;
   BUF(OutPin; FeedBack; 0,0,0,0);
 |1,3:
   BUF(LorOutput; Outpin; 43,43,43,43);
   BUF(OutPin; FeedBack; 0,0,0,0);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 22,22,38,0,18,18,45,45,0,0,22,22,38,0,18,18,45,45,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(LorOutput; Outpin; 43,43,43,43);
    %ELSE
       BUF(LorOutput; TSBInput; 43,43,43,43);
       TSB(TSBInput, %InFuse; Outpin; 45,45,45,45,45,45,45,45);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 50,50,10,15,18,18,45,45,0,0,50,50,10,15,18,18,45,45,0,0);
   BUF(LorOutput; Outpin; 43,43,43,43);
   BUF(TNode; FeedBack; 0,0,0,0);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 22,22,38,0,18,18,45,45,0,0,22,22,38,0,18,18,45,45,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(LorOutput; Outpin; 43,43,43,43);
    %ELSE
       BUF(LorOutput; TSBInput; 43,43,43,43);
       TSB(TSBInput, %InFuse; Outpin; 45,45,45,45,45,45,45,45);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 50,50,10,15,18,18,45,45,0,0,50,50,10,15,18,18,45,45,0,0);
   BUF(LorOutput; Outpin; 43,43,43,43);
   BUF(TNode; FeedBack; 0,0,0,0);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 22,22,38,0,18,18,45,45,0,0,22,22,38,0,18,18,45,45,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 45,45,45,45,45,45,45,45);
    %END;
   BUF(Outpin; FeedBack; 0,0,0,0);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 50,50,10,15,18,18,45,45,0,0,50,50,10,15,18,18,45,45,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 0,0,0,0);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 22,22,38,0,18,18,45,45,0,0,22,22,38,0,18,18,45,45,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 45,45,45,45,45,45,45,45);
    %END;
   BUF(Outpin; FeedBack; 0,0,0,0);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 50,50,10,15,18,18,45,45,0,0,50,50,10,15,18,18,45,45,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 0,0,0,0);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 22,22,38,0,18,18,45,45,0,0,22,22,38,0,18,18,45,45,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 45,45,45,45,45,45,45,45);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 50,50,10,15,18,18,45,45,0,0,50,50,10,15,18,18,45,45,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 22,22,38,0,18,18,45,45,0,0,22,22,38,0,18,18,45,45,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 45,45,45,45,45,45,45,45);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 50,50,10,15,18,18,45,45,0,0,50,50,10,15,18,18,45,45,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 %END;
%MACEND;

LOR8(%SF6440, %FF3200, L1);
LOR8(%SF6445, %FF3600, L2);
LOR8(%SF6450, %FF4000, L3);
LOR8(%SF6455, %FF4400, L4);
LOR8(%SF6460, %FF4800, L5);
LOR8(%SF6465, %FF5200, L6);
LOR8(%SF6470, %FF5600, L7);
LOR8(%SF6475, %FF6000, L8);
LOR8(%SF6435, %FF2800, L9);
LOR8(%SF6430, %FF2400, L10);
LOR8(%SF6425, %FF2000, L11);
LOR8(%SF6420, %FF1600, L12);
LOR8(%SF6415, %FF1200, L13);
LOR8(%SF6410, %FF800, L14);
LOR8(%SF6405, %FF400, L15);
LOR8(%SF6400, %FF00, L16);

EP600(%SF6441, %SF3560, L1, P4, L17, %FF3560, N1, N17, N33, %FF3520, L33, N65, P2);
EP600(%SF6446, %SF3960, L2, P5, L18, %FF3960, N2, N18, N34, %FF3920, L34, N66, P2);
EP600(%SF6451, %SF4360, L3, P6, L19, %FF4360, N3, N19, N35, %FF4320, L35, N67, P2);
EP600(%SF6456, %SF4760, L4, P7, L20, %FF4760, N4, N20, N36, %FF4720, L36, N68, P2);
EP600(%SF6461, %SF5160, L5, P8, L21, %FF5160, N5, N21, N37, %FF5120, L37, N69, P2);
EP600(%SF6466, %SF5560, L6, P9, L22, %FF5560, N6, N22, N38, %FF5520, L38, N70, P2);
EP600(%SF6471, %SF5960, L7, P10, L23, %FF5960, N7, N23, N39, %FF5920, L39, N71, P2);
EP600(%SF6476, %SF6360, L8, P12, L24, %FF6360, N8, N24, N40, %FF6320, L40, N72, P2);
EP600(%SF6436, %SF3160, L9, P18, L25, %FF3160, N9, N25, N41, %FF3120, L41, N73, P16);
EP600(%SF6431, %SF2760, L10, P20, L26, %FF2760, N10, N26, N42, %FF2720, L42, N74, P16);
EP600(%SF6426, %SF2360, L11, P21, L27, %FF2360, N11, N27, N43, %FF2320, L43, N75, P16);
EP600(%SF6421, %SF1960, L12, P22, L28, %FF1960, N12, N28, N44, %FF1920, L44, N76, P16);
EP600(%SF6416, %SF1560, L13, P23, L29, %FF1560, N13, N29, N45, %FF1520, L45, N77, P16);
EP600(%SF6411, %SF1160, L14, P24, L30, %FF1160, N14, N30, N46, %FF1120, L46, N78, P16);
EP600(%SF6406, %SF760, L15, P25, L31, %FF760, N15, N31, N47, %FF720, L47, N79, P16);
EP600(%SF6401, %SF360, L16, P26, L32, %FF360, N16, N32, N48, %FF320, L48, N80, P16);
%EndModel

%StartModel
%Manufacturer:Intel
%Type:EP600L
%PartNumber:N5C060-55
%LastNode ? ?
%NumPins: 28
%FDF AND 0 ~P3 P3 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 ~N7 N7 ~N8 N8
         ~P13 P13 ~P17 P17 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~N13 N13
	 ~N14 N14 ~N15 N15 ~N16 N16 ~P27 P27 *

%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; LorOutput);
 %ELSE
  LNOR(%InFuse, %InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; LorOutput);
 %END;
%MACEND;

%MACRO EP600(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
      BUF(LorOutput; Outpin; 53,53,53,53);
   %ELSE
      BUF(LorOutput; TSBInput; 53,53,53,53);
      TSB(TSBInput, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
   %END;
   BUF(OutPin; FeedBack; 0,0,0,0);
 |1,3:
   BUF(LorOutput; Outpin; 53,53,53,53);
   BUF(OutPin; FeedBack; 0,0,0,0);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,43,0,22,22,55,55,0,0,25,25,43,0,22,22,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(LorOutput; Outpin; 53,53,53,53);
    %ELSE
       BUF(LorOutput; TSBInput; 53,53,53,53);
       TSB(TSBInput, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 58,58,10,15,22,22,55,55,0,0,58,58,10,15,22,22,55,55,0,0);
   BUF(LorOutput; Outpin; 53,53,53,53);
   BUF(TNode; FeedBack; 0,0,0,0);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,43,0,22,22,55,55,0,0,25,25,43,0,22,22,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(LorOutput; Outpin; 53,53,53,53);
    %ELSE
       BUF(LorOutput; TSBInput; 53,53,53,53);
       TSB(TSBInput, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 58,58,10,15,22,22,55,55,0,0,58,58,10,15,22,22,55,55,0,0);
   BUF(LorOutput; Outpin; 53,53,53,53);
   BUF(TNode; FeedBack; 0,0,0,0);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,43,0,22,22,55,55,0,0,25,25,43,0,22,22,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(Outpin; FeedBack; 0,0,0,0);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 58,58,10,15,22,22,55,55,0,0,58,58,10,15,22,22,55,55,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 0,0,0,0);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,43,0,22,22,55,55,0,0,25,25,43,0,22,22,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(Outpin; FeedBack; 0,0,0,0);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 58,58,10,15,22,22,55,55,0,0,58,58,10,15,22,22,55,55,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 0,0,0,0);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,43,0,22,22,55,55,0,0,25,25,43,0,22,22,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 58,58,10,15,22,22,55,55,0,0,58,58,10,15,22,22,55,55,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,43,0,22,22,55,55,0,0,25,25,43,0,22,22,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 58,58,10,15,22,22,55,55,0,0,58,58,10,15,22,22,55,55,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 %END;
%MACEND;

LOR8(%SF6440, %FF3200, L1);
LOR8(%SF6445, %FF3600, L2);
LOR8(%SF6450, %FF4000, L3);
LOR8(%SF6455, %FF4400, L4);
LOR8(%SF6460, %FF4800, L5);
LOR8(%SF6465, %FF5200, L6);
LOR8(%SF6470, %FF5600, L7);
LOR8(%SF6475, %FF6000, L8);
LOR8(%SF6435, %FF2800, L9);
LOR8(%SF6430, %FF2400, L10);
LOR8(%SF6425, %FF2000, L11);
LOR8(%SF6420, %FF1600, L12);
LOR8(%SF6415, %FF1200, L13);
LOR8(%SF6410, %FF800, L14);
LOR8(%SF6405, %FF400, L15);
LOR8(%SF6400, %FF00, L16);

EP600(%SF6441, %SF3560, L1, P4, L17, %FF3560, N1, N17, N33, %FF3520, L33, N65, P2);
EP600(%SF6446, %SF3960, L2, P5, L18, %FF3960, N2, N18, N34, %FF3920, L34, N66, P2);
EP600(%SF6451, %SF4360, L3, P6, L19, %FF4360, N3, N19, N35, %FF4320, L35, N67, P2);
EP600(%SF6456, %SF4760, L4, P7, L20, %FF4760, N4, N20, N36, %FF4720, L36, N68, P2);
EP600(%SF6461, %SF5160, L5, P8, L21, %FF5160, N5, N21, N37, %FF5120, L37, N69, P2);
EP600(%SF6466, %SF5560, L6, P9, L22, %FF5560, N6, N22, N38, %FF5520, L38, N70, P2);
EP600(%SF6471, %SF5960, L7, P10, L23, %FF5960, N7, N23, N39, %FF5920, L39, N71, P2);
EP600(%SF6476, %SF6360, L8, P12, L24, %FF6360, N8, N24, N40, %FF6320, L40, N72, P2);
EP600(%SF6436, %SF3160, L9, P18, L25, %FF3160, N9, N25, N41, %FF3120, L41, N73, P16);
EP600(%SF6431, %SF2760, L10, P20, L26, %FF2760, N10, N26, N42, %FF2720, L42, N74, P16);
EP600(%SF6426, %SF2360, L11, P21, L27, %FF2360, N11, N27, N43, %FF2320, L43, N75, P16);
EP600(%SF6421, %SF1960, L12, P22, L28, %FF1960, N12, N28, N44, %FF1920, L44, N76, P16);
EP600(%SF6416, %SF1560, L13, P23, L29, %FF1560, N13, N29, N45, %FF1520, L45, N77, P16);
EP600(%SF6411, %SF1160, L14, P24, L30, %FF1160, N14, N30, N46, %FF1120, L46, N78, P16);
EP600(%SF6406, %SF760, L15, P25, L31, %FF760, N15, N31, N47, %FF720, L47, N79, P16);
EP600(%SF6401, %SF360, L16, P26, L32, %FF360, N16, N32, N48, %FF320, L48, N80, P16);
%EndModel

%StartModel
%Manufacturer:Intel
%Type:EP900
%PartNumber:D5C090-50
%LastNode ? ?
%NumPins: 40
%FDF AND 0 ~P2 P2 ~P3 P3 ~P4 P4 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P17 P17 ~P18 P18
	 ~P19 P19 ~P22 P22 ~P23 P23 ~P24 P24 ~N13 N13 ~N14 N14 ~N15 N15
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22
	 ~N23 N23 ~N24 N24 ~P37 P37 ~P38 P38 ~P39 P39 *

%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;
%MACEND;

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 45,45,45,45);
   %ELSE
      BUF(LorOutput; TSBInput; 45,45,45,45);
      TSB(TSBInput, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
   %END;
   BUF(OutPin; FeedBack; 5,5,5,5);
 |1,3:
   BUF(LorOutput; Outpin; 45,45,45,45);
   BUF(OutPin; FeedBack; 5,5,5,5);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 45,45,45,45);
    %ELSE
       BUF(LorOutput; TSBInput; 45,45,45,45);
       TSB(TSBInput, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(LorOutput; Outpin; 45,45,45,45);
   BUF(TNode; FeedBack; 0,0,0,0);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 45,45,45,45);
    %ELSE
       BUF(LorOutput; TSBInput; 45,45,45,45);
       TSB(TSBInput, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(LorOutput; Outpin; 45,45,45,45);
   BUF(TNode; FeedBack; 0,0,0,0);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 %END;
%MACEND;

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P5, L25, %FF9288, N1, N25, N49, %FF9216, L49,
      N73, P1);
EP900(%SF17346, %SF10008, L2, P6, L26, %FF10008, N2, N26, N50, %FF9936, L50,
      N74, P1);
EP900(%SF17351, %SF10728, L3, P7, L27, %FF10728, N3, N27, N51, %FF10656, L51,
      N75, P1);
EP900(%SF17356, %SF11448, L4, P8, L28, %FF11448, N4, N28, N52, %FF11376, L52,
      N76, P1);
EP900(%SF17361, %SF12168, L5, P9, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P1);
EP900(%SF17366, %SF12888, L6, P10, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P1);
EP900(%SF17371, %SF13608, L7, P11, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P1);
EP900(%SF17376, %SF14328, L8, P12, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P1);
EP900(%SF17381, %SF15048, L9, P13, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P1);
EP900(%SF17386, %SF15768, L10, P14, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P1);
EP900(%SF17391, %SF16488, L11, P15, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P1);
EP900(%SF17396, %SF17208, L12, P16, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P1);
EP900(%SF17336, %SF8568, L13, P25, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P21);
EP900(%SF17331, %SF7848, L14, P26, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P21);
EP900(%SF17326, %SF7128, L15, P27, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P21);
EP900(%SF17321, %SF6408, L16, P28, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P21);
EP900(%SF17316, %SF5688, L17, P29, L41, %FF5688, N17, N41, N65, %FF5616, L65,
      N89, P21);
EP900(%SF17311, %SF4968, L18, P30, L42, %FF4968, N18, N42, N66, %FF4896, L66,
      N90, P21);
EP900(%SF17306, %SF4248, L19, P31, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P21);
EP900(%SF17301, %SF3528, L20, P32, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P21);
EP900(%SF17296, %SF2808, L21, P33, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P21);
EP900(%SF17291, %SF2088, L22, P34, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P21);
EP900(%SF17286, %SF1368, L23, P35, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P21);
EP900(%SF17281, %SF648, L24, P36, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P21);
%EndModel

%StartModel
%Manufacturer:Intel
%Type:EP900
%PartNumber:D5C090-60
%LastNode ? ?
%NumPins: 40
%FDF AND 0 ~P2 P2 ~P3 P3 ~P4 P4 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P17 P17 ~P18 P18
	 ~P19 P19 ~P22 P22 ~P23 P23 ~P24 P24 ~N13 N13 ~N14 N14 ~N15 N15
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22
	 ~N23 N23 ~N24 N24 ~P37 P37 ~P38 P38 ~P39 P39 *

%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;
%MACEND;

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 55,55,55,55);
   %ELSE
      BUF(LorOutput; TSBInput; 55,55,55,55);
      TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
   %END;
   BUF(OutPin; FeedBack; 5,5,5,5);
 |1,3:
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(OutPin; FeedBack; 5,5,5,5);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,43,0,23,23,60,60,0,0,25,25,43,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 55,55,55,55);
    %ELSE
       BUF(LorOutput; TSBInput; 55,55,55,55);
       TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,10,15,23,23,60,60,0,0,59,59,10,15,23,23,60,60,0,0);
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(TNode; FeedBack; 0,0,0,0);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,43,0,23,23,60,60,0,0,25,25,43,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 55,55,55,55);
    %ELSE
       BUF(LorOutput; TSBInput; 55,55,55,55);
       TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,10,15,23,23,60,60,0,0,59,59,10,15,23,23,60,60,0,0);
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(TNode; FeedBack; 0,0,0,0);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,43,0,23,23,60,60,0,0,25,25,43,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,10,15,23,23,60,60,0,0,59,59,10,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,43,0,23,23,60,60,0,0,25,25,43,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,10,15,23,23,60,60,0,0,59,59,10,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,43,0,23,23,60,60,0,0,25,25,43,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,10,15,23,23,60,60,0,0,59,59,10,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,43,0,23,23,60,60,0,0,25,25,43,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,10,15,23,23,60,60,0,0,59,59,10,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 %END;
%MACEND;

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P5, L25, %FF9288, N1, N25, N49, %FF9216, L49,
      N73, P1);
EP900(%SF17346, %SF10008, L2, P6, L26, %FF10008, N2, N26, N50, %FF9936, L50,
      N74, P1);
EP900(%SF17351, %SF10728, L3, P7, L27, %FF10728, N3, N27, N51, %FF10656, L51,
      N75, P1);
EP900(%SF17356, %SF11448, L4, P8, L28, %FF11448, N4, N28, N52, %FF11376, L52,
      N76, P1);
EP900(%SF17361, %SF12168, L5, P9, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P1);
EP900(%SF17366, %SF12888, L6, P10, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P1);
EP900(%SF17371, %SF13608, L7, P11, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P1);
EP900(%SF17376, %SF14328, L8, P12, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P1);
EP900(%SF17381, %SF15048, L9, P13, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P1);
EP900(%SF17386, %SF15768, L10, P14, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P1);
EP900(%SF17391, %SF16488, L11, P15, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P1);
EP900(%SF17396, %SF17208, L12, P16, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P1);
EP900(%SF17336, %SF8568, L13, P25, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P21);
EP900(%SF17331, %SF7848, L14, P26, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P21);
EP900(%SF17326, %SF7128, L15, P27, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P21);
EP900(%SF17321, %SF6408, L16, P28, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P21);
EP900(%SF17316, %SF5688, L17, P29, L41, %FF5688, N17, N41, N65, %FF5616, L65,
      N89, P21);
EP900(%SF17311, %SF4968, L18, P30, L42, %FF4968, N18, N42, N66, %FF4896, L66,
      N90, P21);
EP900(%SF17306, %SF4248, L19, P31, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P21);
EP900(%SF17301, %SF3528, L20, P32, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P21);
EP900(%SF17296, %SF2808, L21, P33, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P21);
EP900(%SF17291, %SF2088, L22, P34, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P21);
EP900(%SF17286, %SF1368, L23, P35, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P21);
EP900(%SF17281, %SF648, L24, P36, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P21);
%EndModel

%StartModel
%Manufacturer:Intel
%Type:EP900
%PartNumber:P5C090-50
%LastNode ? ?
%NumPins: 40
%FDF AND 0 ~P2 P2 ~P3 P3 ~P4 P4 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P17 P17 ~P18 P18
	 ~P19 P19 ~P22 P22 ~P23 P23 ~P24 P24 ~N13 N13 ~N14 N14 ~N15 N15
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22
	 ~N23 N23 ~N24 N24 ~P37 P37 ~P38 P38 ~P39 P39 *

%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;
%MACEND;

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 45,45,45,45);
   %ELSE
      BUF(LorOutput; TSBInput; 45,45,45,45);
      TSB(TSBInput, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
   %END;
   BUF(OutPin; FeedBack; 5,5,5,5);
 |1,3:
   BUF(LorOutput; Outpin; 45,45,45,45);
   BUF(OutPin; FeedBack; 5,5,5,5);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 45,45,45,45);
    %ELSE
       BUF(LorOutput; TSBInput; 45,45,45,45);
       TSB(TSBInput, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(LorOutput; Outpin; 45,45,45,45);
   BUF(TNode; FeedBack; 0,0,0,0);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 45,45,45,45);
    %ELSE
       BUF(LorOutput; TSBInput; 45,45,45,45);
       TSB(TSBInput, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(LorOutput; Outpin; 45,45,45,45);
   BUF(TNode; FeedBack; 0,0,0,0);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 %END;
%MACEND;

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P5, L25, %FF9288, N1, N25, N49, %FF9216, L49,
      N73, P1);
EP900(%SF17346, %SF10008, L2, P6, L26, %FF10008, N2, N26, N50, %FF9936, L50,
      N74, P1);
EP900(%SF17351, %SF10728, L3, P7, L27, %FF10728, N3, N27, N51, %FF10656, L51,
      N75, P1);
EP900(%SF17356, %SF11448, L4, P8, L28, %FF11448, N4, N28, N52, %FF11376, L52,
      N76, P1);
EP900(%SF17361, %SF12168, L5, P9, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P1);
EP900(%SF17366, %SF12888, L6, P10, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P1);
EP900(%SF17371, %SF13608, L7, P11, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P1);
EP900(%SF17376, %SF14328, L8, P12, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P1);
EP900(%SF17381, %SF15048, L9, P13, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P1);
EP900(%SF17386, %SF15768, L10, P14, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P1);
EP900(%SF17391, %SF16488, L11, P15, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P1);
EP900(%SF17396, %SF17208, L12, P16, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P1);
EP900(%SF17336, %SF8568, L13, P25, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P21);
EP900(%SF17331, %SF7848, L14, P26, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P21);
EP900(%SF17326, %SF7128, L15, P27, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P21);
EP900(%SF17321, %SF6408, L16, P28, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P21);
EP900(%SF17316, %SF5688, L17, P29, L41, %FF5688, N17, N41, N65, %FF5616, L65,
      N89, P21);
EP900(%SF17311, %SF4968, L18, P30, L42, %FF4968, N18, N42, N66, %FF4896, L66,
      N90, P21);
EP900(%SF17306, %SF4248, L19, P31, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P21);
EP900(%SF17301, %SF3528, L20, P32, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P21);
EP900(%SF17296, %SF2808, L21, P33, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P21);
EP900(%SF17291, %SF2088, L22, P34, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P21);
EP900(%SF17286, %SF1368, L23, P35, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P21);
EP900(%SF17281, %SF648, L24, P36, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P21);
%EndModel

%StartModel
%Manufacturer:Intel
%Type:EP900
%PartNumber:P5C090-60
%LastNode ? ?
%NumPins: 40
%FDF AND 0 ~P2 P2 ~P3 P3 ~P4 P4 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P17 P17 ~P18 P18
	 ~P19 P19 ~P22 P22 ~P23 P23 ~P24 P24 ~N13 N13 ~N14 N14 ~N15 N15
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22
	 ~N23 N23 ~N24 N24 ~P37 P37 ~P38 P38 ~P39 P39 *

%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;
%MACEND;

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 55,55,55,55);
   %ELSE
      BUF(LorOutput; TSBInput; 55,55,55,55);
      TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
   %END;
   BUF(OutPin; FeedBack; 5,5,5,5);
 |1,3:
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(OutPin; FeedBack; 5,5,5,5);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,43,0,23,23,60,60,0,0,25,25,43,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 55,55,55,55);
    %ELSE
       BUF(LorOutput; TSBInput; 55,55,55,55);
       TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,10,15,23,23,60,60,0,0,59,59,10,15,23,23,60,60,0,0);
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(TNode; FeedBack; 0,0,0,0);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,43,0,23,23,60,60,0,0,25,25,43,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 55,55,55,55);
    %ELSE
       BUF(LorOutput; TSBInput; 55,55,55,55);
       TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,10,15,23,23,60,60,0,0,59,59,10,15,23,23,60,60,0,0);
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(TNode; FeedBack; 0,0,0,0);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,43,0,23,23,60,60,0,0,25,25,43,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,10,15,23,23,60,60,0,0,59,59,10,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,43,0,23,23,60,60,0,0,25,25,43,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,10,15,23,23,60,60,0,0,59,59,10,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,43,0,23,23,60,60,0,0,25,25,43,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,10,15,23,23,60,60,0,0,59,59,10,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,43,0,23,23,60,60,0,0,25,25,43,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,10,15,23,23,60,60,0,0,59,59,10,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 %END;
%MACEND;

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P5, L25, %FF9288, N1, N25, N49, %FF9216, L49,
      N73, P1);
EP900(%SF17346, %SF10008, L2, P6, L26, %FF10008, N2, N26, N50, %FF9936, L50,
      N74, P1);
EP900(%SF17351, %SF10728, L3, P7, L27, %FF10728, N3, N27, N51, %FF10656, L51,
      N75, P1);
EP900(%SF17356, %SF11448, L4, P8, L28, %FF11448, N4, N28, N52, %FF11376, L52,
      N76, P1);
EP900(%SF17361, %SF12168, L5, P9, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P1);
EP900(%SF17366, %SF12888, L6, P10, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P1);
EP900(%SF17371, %SF13608, L7, P11, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P1);
EP900(%SF17376, %SF14328, L8, P12, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P1);
EP900(%SF17381, %SF15048, L9, P13, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P1);
EP900(%SF17386, %SF15768, L10, P14, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P1);
EP900(%SF17391, %SF16488, L11, P15, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P1);
EP900(%SF17396, %SF17208, L12, P16, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P1);
EP900(%SF17336, %SF8568, L13, P25, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P21);
EP900(%SF17331, %SF7848, L14, P26, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P21);
EP900(%SF17326, %SF7128, L15, P27, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P21);
EP900(%SF17321, %SF6408, L16, P28, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P21);
EP900(%SF17316, %SF5688, L17, P29, L41, %FF5688, N17, N41, N65, %FF5616, L65,
      N89, P21);
EP900(%SF17311, %SF4968, L18, P30, L42, %FF4968, N18, N42, N66, %FF4896, L66,
      N90, P21);
EP900(%SF17306, %SF4248, L19, P31, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P21);
EP900(%SF17301, %SF3528, L20, P32, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P21);
EP900(%SF17296, %SF2808, L21, P33, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P21);
EP900(%SF17291, %SF2088, L22, P34, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P21);
EP900(%SF17286, %SF1368, L23, P35, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P21);
EP900(%SF17281, %SF648, L24, P36, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P21);
%EndModel

%StartModel
%Manufacturer:Intel
%Type:EP900
%PartNumber:N5C090-50
%LastNode ? ?
%NumPins: 44
%FDF AND 0 ~P3 P3 ~P4 P4 ~P5 P5 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P19 P19 ~P20 P20
	 ~P21 P21 ~P25 P25 ~P26 P26 ~P27 P27 ~N13 N13 ~N14 N14 ~N15 N15
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22
	 ~N23 N23 ~N24 N24 ~P41 P41 ~P42 P42 ~P43 P43 *

%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;
%MACEND;

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 45,45,45,45);
   %ELSE
      BUF(LorOutput; TSBInput; 45,45,45,45);
      TSB(TSBInput, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
   %END;
   BUF(OutPin; FeedBack; 5,5,5,5);
 |1,3:
   BUF(LorOutput; Outpin; 45,45,45,45);
   BUF(OutPin; FeedBack; 5,5,5,5);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 45,45,45,45);
    %ELSE
       BUF(LorOutput; TSBInput; 45,45,45,45);
       TSB(TSBInput, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(LorOutput; Outpin; 45,45,45,45);
   BUF(TNode; FeedBack; 0,0,0,0);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 45,45,45,45);
    %ELSE
       BUF(LorOutput; TSBInput; 45,45,45,45);
       TSB(TSBInput, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(LorOutput; Outpin; 45,45,45,45);
   BUF(TNode; FeedBack; 0,0,0,0);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 %END;
%MACEND;

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P6, L25, %FF9288, N1, N25, N49, %FF9216, L49,
      N73, P2);
EP900(%SF17346, %SF10008, L2, P7, L26, %FF10008, N2, N26, N50, %FF9936, L50,
      N74, P2);
EP900(%SF17351, %SF10728, L3, P8, L27, %FF10728, N3, N27, N51, %FF10656, L51,
      N75, P2);
EP900(%SF17356, %SF11448, L4, P9, L28, %FF11448, N4, N28, N52, %FF11376, L52,
      N76, P2);
EP900(%SF17361, %SF12168, L5, P10, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P2);
EP900(%SF17366, %SF12888, L6, P11, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P2);
EP900(%SF17371, %SF13608, L7, P12, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P2);
EP900(%SF17376, %SF14328, L8, P13, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P2);
EP900(%SF17381, %SF15048, L9, P14, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P2);
EP900(%SF17386, %SF15768, L10, P15, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P2);
EP900(%SF17391, %SF16488, L11, P16, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P2);
EP900(%SF17396, %SF17208, L12, P18, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P2);
EP900(%SF17336, %SF8568, L13, P28, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P24);
EP900(%SF17331, %SF7848, L14, P29, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P24);
EP900(%SF17326, %SF7128, L15, P30, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P24);
EP900(%SF17321, %SF6408, L16, P31, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P24);
EP900(%SF17316, %SF5688, L17, P32, L41, %FF5688, N17, N41, N65, %FF5616, L65,
      N89, P24);
EP900(%SF17311, %SF4968, L18, P33, L42, %FF4968, N18, N42, N66, %FF4896, L66,
      N90, P24);
EP900(%SF17306, %SF4248, L19, P34, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P24);
EP900(%SF17301, %SF3528, L20, P35, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P24);
EP900(%SF17296, %SF2808, L21, P36, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P24);
EP900(%SF17291, %SF2088, L22, P37, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P24);
EP900(%SF17286, %SF1368, L23, P38, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P24);
EP900(%SF17281, %SF648, L24, P40, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P24);
%EndModel

%StartModel
%Manufacturer:Intel
%Type:EP900
%PartNumber:N5C090-60
%LastNode ? ?
%NumPins: 44
%FDF AND 0 ~P3 P3 ~P4 P4 ~P5 P5 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P19 P19 ~P20 P20
	 ~P21 P21 ~P25 P25 ~P26 P26 ~P27 P27 ~N13 N13 ~N14 N14 ~N15 N15
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22
	 ~N23 N23 ~N24 N24 ~P41 P41 ~P42 P42 ~P43 P43 *

%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;
%MACEND;

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 55,55,55,55);
   %ELSE
      BUF(LorOutput; TSBInput; 55,55,55,55);
      TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
   %END;
   BUF(OutPin; FeedBack; 5,5,5,5);
 |1,3:
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(OutPin; FeedBack; 5,5,5,5);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,46,0,23,23,60,60,0,0,25,25,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 55,55,55,55);
    %ELSE
       BUF(LorOutput; TSBInput; 55,55,55,55);
       TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,10,15,23,23,60,60,0,0,59,59,10,15,23,23,60,60,0,0);
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(TNode; FeedBack; 0,0,0,0);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,46,0,23,23,60,60,0,0,25,25,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 55,55,55,55);
    %ELSE
       BUF(LorOutput; TSBInput; 55,55,55,55);
       TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,10,15,23,23,60,60,0,0,59,59,10,15,23,23,60,60,0,0);
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(TNode; FeedBack; 0,0,0,0);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,46,0,23,23,60,60,0,0,25,25,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,10,15,23,23,60,60,0,0,59,59,10,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,46,0,23,23,60,60,0,0,25,25,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,10,15,23,23,60,60,0,0,59,59,10,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,46,0,23,23,60,60,0,0,25,25,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,10,15,23,23,60,60,0,0,59,59,10,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,46,0,23,23,60,60,0,0,25,25,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,10,15,23,23,60,60,0,0,59,59,10,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 %END;
%MACEND;

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P6, L25, %FF9288, N1, N25, N49, %FF9216, L49,
      N73, P2);
EP900(%SF17346, %SF10008, L2, P7, L26, %FF10008, N2, N26, N50, %FF9936, L50,
      N74, P2);
EP900(%SF17351, %SF10728, L3, P8, L27, %FF10728, N3, N27, N51, %FF10656, L51,
      N75, P2);
EP900(%SF17356, %SF11448, L4, P9, L28, %FF11448, N4, N28, N52, %FF11376, L52,
      N76, P2);
EP900(%SF17361, %SF12168, L5, P10, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P2);
EP900(%SF17366, %SF12888, L6, P11, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P2);
EP900(%SF17371, %SF13608, L7, P12, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P2);
EP900(%SF17376, %SF14328, L8, P13, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P2);
EP900(%SF17381, %SF15048, L9, P14, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P2);
EP900(%SF17386, %SF15768, L10, P15, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P2);
EP900(%SF17391, %SF16488, L11, P16, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P2);
EP900(%SF17396, %SF17208, L12, P18, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P2);
EP900(%SF17336, %SF8568, L13, P28, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P24);
EP900(%SF17331, %SF7848, L14, P29, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P24);
EP900(%SF17326, %SF7128, L15, P30, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P24);
EP900(%SF17321, %SF6408, L16, P31, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P24);
EP900(%SF17316, %SF5688, L17, P32, L41, %FF5688, N17, N41, N65, %FF5616, L65,
      N89, P24);
EP900(%SF17311, %SF4968, L18, P33, L42, %FF4968, N18, N42, N66, %FF4896, L66,
      N90, P24);
EP900(%SF17306, %SF4248, L19, P34, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P24);
EP900(%SF17301, %SF3528, L20, P35, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P24);
EP900(%SF17296, %SF2808, L21, P36, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P24);
EP900(%SF17291, %SF2088, L22, P37, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P24);
EP900(%SF17286, %SF1368, L23, P38, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P24);
EP900(%SF17281, %SF648, L24, P40, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P24);
%EndModel


%StartModel
%Manufacturer:Intel
%Type:EP1800
%PartNumber:N5C180-70
%LastNode ? ?
%NumPins: 68
%FDF AND 0 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 ~N7 N7 ~N8 N8 ~N9 N9
	   ~N10 N10 ~N11 N11 ~N12 N12 ~N49 N49 ~N50 N50 ~N51 N51 ~N52 N52
	   ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57 ~N58 N58 ~N59 N59
	   ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64 ~P50 P50 ~P49 P49
	   ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16 ~P15 P15 ~P14 P14
	   ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19 ~P17 P17 ~P53 P53 *

%MACRO IODelay(OutPin:%TEXT, FDFNode:%TEXT);
    BUF(OutPin; FDFNode; 5,5,5,5);
%MACEND;

%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+88, %InFuse+176, %InFuse+264, %InFuse+352, %InFuse+440,
      %InFuse+528, %InFuse+616; LorOutput);
 %ELSE
  LNOR(%InFuse, %InFuse+88, %InFuse+176, %InFuse+264, %InFuse+352, %InFuse+440,
      %InFuse+528, %InFuse+616; LorOutput);
 %END;
%MACEND;

%MACRO EP1800GLOBAL(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
       XorInput:%TEXT, InFuse:%FF, TNode:%TEXT, CLK:%TEXT, ClrFuse:%FF,
       Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT, DInput:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   BUF(LorOutput; TNode; 50,50,50,50);
   %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
      BUF(LorOutput; OutPin; 65,65,65,65);
   %ELSE
      BUF(LorOutput; TSBInput; 65,65,65,65);
      TSB(TSBInput, %InFuse; Outpin; 15,15,15,15,15,15,15,15);
   %END;
 |1,3:
   BUF(LorOutput; TNode; 50,50,50,50);
   BUF(LorOutput; OutPin; 65,65,65,65);
 |4,5,6,7:
   BUF(LorOutput; TNode; 50,50,50,50);
   TSB(zero, ZERO; Outpin; 1,1,1,1,1,1,1,1);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 40,40,40,40);
   DQFFC(DInput, CLKPin, Clear; TNode; 29,29,12,0,24,24,55,55,1,1,29,29,12,0,24,24,55,55,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 15,15,15,15,15,15,15,15);
    %END;
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 40,40,40,40);
   DQFFC(DInput, CLK, Clear; TNode; 50,50,12,30,24,24,40,40,1,1,50,50,12,30,24,24,40,40,1,1);
   BUF(TNode; Outpin; 15,15,15,15);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 40,40,40,40);
   DQFFC(DInput, CLKPin, Clear; TNode; 29,29,12,0,24,24,55,55,1,1,29,29,12,0,24,24,55,55,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 15,15,15,15,15,15,15,15);
    %END;
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 40,40,40,40);
   DQFFC(DInput, CLK, Clear; TNode; 50,50,12,30,24,24,40,40,1,1,50,50,12,30,24,24,40,40,1,1);
   BUF(TNode; Outpin; 15,15,15,15);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 40,40,40,40);
   DQFFC(DInput, CLKPin, Clear; TNode; 14,14,12,0,24,24,40,40,1,1,14,14,12,0,24,24,40,40,1,1);
   TSB(zero, ZERO; Outpin; 1,1,1,1,1,1,1,1);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 40,40,40,40);
   DQFFC(DInput, CLK, Clear; TNode; 50,50,12,30,24,24,40,40,1,1,50,50,12,30,24,24,40,40,1,1);
   TSB(zero, ZERO; Outpin; 1,1,1,1,1,1,1,1);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 40,40,40,40);
   DQFFC(DInput, CLKPin, Clear; TNode; 14,14,12,0,24,24,40,40,1,1,14,14,12,0,24,24,40,40,1,1);
   TSB(zero, ZERO; Outpin; 1,1,1,1,1,1,1,1);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 40,40,40,40);
   DQFFC(DInput, CLK, Clear; TNode; 50,50,12,30,24,24,40,40,1,1,50,50,12,30,24,24,40,40,1,1);
   TSB(zero, ZERO; Outpin; 1,1,1,1,1,1,1,1);
 %END;
%MACEND;

%MACRO EP1800LOCAL(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT, DInput:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
      BUF(LorOutput; OutPin; 65,65,65,65);
   %ELSE
      BUF(LorOutput; TSBInput; 65,65,65,65);
      TSB(TSBInput, %InFuse; Outpin; 15,15,15,15,15,15,15,15);
   %END;
   BUF(OutPin; FeedBack; 10,10,10,10);
 |1,3:
   BUF(LorOutput; OutPin; 65,65,65,65);
   BUF(OutPin; FeedBack; 10,10,10,10);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 40,40,40,40);
   DQFFC(DInput, CLKPin, Clear; TNode; 14,14,12,0,24,24,40,40,1,1,14,14,12,0,24,24,40,40,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(LorOutput; OutPin; 65,65,65,65);
    %ELSE
       BUF(LorOutput; TSBInput; 65,65,65,65);
       TSB(TSBInput, %InFuse; Outpin; 15,15,15,15,15,15,15,15);
    %END;
   BUF(TNode; FeedBack; 10,10,10,10);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 40,40,40,40);
   DQFFC(DInput, CLK, Clear; TNode; 50,50,12,30,24,24,40,40,1,1,50,50,12,30,24,24,40,40,1,1);
   BUF(LorOutput; OutPin; 65,65,65,65);
   BUF(TNode; FeedBack; 10,10,10,10);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 40,40,40,40);
   DQFFC(DInput, CLKPin, Clear; TNode; 14,14,12,0,24,24,40,40,1,1,14,14,12,0,24,24,40,40,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(LorOutput; OutPin; 65,65,65,65);
    %ELSE
       BUF(LorOutput; TSBInput; 65,65,65,65);
       TSB(TSBInput, %InFuse; Outpin; 15,15,15,15,15,15,15,15);
    %END;
   BUF(TNode; FeedBack; 10,10,10,10);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 40,40,40,40);
   DQFFC(DInput, CLK, Clear; TNode; 50,50,12,30,24,24,40,40,1,1,50,50,12,30,24,24,40,40,1,1);
   BUF(LorOutput; OutPin; 65,65,65,65);
   BUF(TNode; FeedBack; 10,10,10,10);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 40,40,40,40);
   DQFFC(DInput, CLKPin, Clear; TNode; 29,29,12,0,24,24,55,55,1,1,29,29,12,0,24,24,55,55,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 15,15,15,15,15,15,15,15);
    %END;
   BUF(Outpin; FeedBack; 10,10,10,10);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 40,40,40,40);
   DQFFC(DInput, CLK, Clear; TNode; 14,14,12,0,24,24,40,40,1,1,14,14,12,0,24,24,40,40,1,1);
   BUF(TNode; Outpin; 15,15,15,15);
   BUF(Outpin; FeedBack; 10,10,10,10);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 40,40,40,40);
   DQFFC(DInput, CLKPin, Clear; TNode; 29,29,12,0,24,24,55,55,1,1,29,29,12,0,24,24,55,55,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 15,15,15,15,15,15,15,15);
    %END;
   BUF(Outpin; FeedBack; 10,10,10,10);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 40,40,40,40);
   DQFFC(DInput, CLK, Clear; TNode; 50,50,12,30,24,24,40,40,1,1,50,50,12,30,24,24,40,40,1,1);
   BUF(TNode; Outpin; 15,15,15,15);
   BUF(Outpin; FeedBack; 10,10,10,10);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 40,40,40,40);
   DQFFC(DInput, CLKPin, Clear; TNode; 29,29,12,0,24,24,55,55,1,1,29,29,12,0,24,24,55,55,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 15,15,15,15,15,15,15,15);
    %END;
   BUF(TNode; FeedBack; 10,10,10,10);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 40,40,40,40);
   DQFFC(DInput, CLK, Clear; TNode; 50,50,12,30,24,24,40,40,1,1,50,50,12,30,24,24,40,40,1,1);
   BUF(TNode; Outpin; 15,15,15,15);
   BUF(TNode; FeedBack; 10,10,10,10);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 40,40,40,40);
   DQFFC(DInput, CLKPin, Clear; TNode; 29,29,12,0,24,24,55,55,1,1,29,29,12,0,24,24,55,55,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 15,15,15,15,15,15,15,15);
    %END;
   BUF(TNode; FeedBack; 10,10,10,10);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 40,40,40,40);
   DQFFC(DInput, CLK, Clear; TNode; 50,50,12,30,24,24,40,40,1,1,50,50,12,30,24,24,40,40,1,1);
   BUF(TNode; Outpin; 15,15,15,15);
   BUF(TNode; FeedBack; 10,10,10,10);
 %END;
%MACEND;

%MACRO EP1800LOCALENHANCED(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT, DInput:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
      BUF(LorOutput; OutPin; 60,60,60,60);
   %ELSE
      BUF(LorOutput; TSBInput; 60,60,60,60);
      TSB(TSBInput, %InFuse; Outpin; 15,15,15,15,15,15,15,15);
   %END;
   BUF(OutPin; FeedBack; 10,10,10,10);
 |1,3:
   BUF(LorOutput; OutPin; 60,60,60,60);
   BUF(OutPin; FeedBack; 10,10,10,10);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 35,35,35,35);
   DQFFC(DInput, CLKPin, Clear; TNode; 14,14,12,0,24,24,35,35,1,1,14,14,12,0,24,24,35,35,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(LorOutput; OutPin; 60,60,60,60);
    %ELSE
       BUF(LorOutput; TSBInput; 60,60,60,60);
       TSB(TSBInput, %InFuse; Outpin; 15,15,15,15,15,15,15,15);
    %END;
   BUF(TNode; FeedBack; 10,10,10,10);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 35,35,35,35);
   DQFFC(DInput, CLK, Clear; TNode; 45,45,12,30,24,24,35,35,1,1,45,45,12,30,24,24,35,35,1,1);
   BUF(LorOutput; OutPin; 60,60,60,60);
   BUF(TNode; FeedBack; 10,10,10,10);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 35,35,35,35);
   DQFFC(DInput, CLKPin, Clear; TNode; 14,14,12,0,24,24,35,35,1,1,14,14,12,0,24,24,35,35,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(LorOutput; OutPin; 60,60,60,60);
    %ELSE
       BUF(LorOutput; TSBInput; 60,60,60,60);
       TSB(TSBInput, %InFuse; Outpin; 15,15,15,15,15,15,15,15);
    %END;
   BUF(TNode; FeedBack; 10,10,10,10);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 35,35,35,35);
   DQFFC(DInput, CLK, Clear; TNode; 45,45,12,30,24,24,35,35,1,1,45,45,12,30,24,24,35,35,1,1);
   BUF(LorOutput; OutPin; 60,60,60,60);
   BUF(TNode; FeedBack; 10,10,10,10);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 35,35,35,35);
   DQFFC(DInput, CLKPin, Clear; TNode; 29,29,12,0,24,24,55,55,1,1,29,29,12,0,24,24,55,55,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 15,15,15,15,15,15,15,15);
    %END;
   BUF(Outpin; FeedBack; 10,10,10,10);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 35,35,35,35);
   DQFFC(DInput, CLK, Clear; TNode; 14,14,12,0,24,24,35,35,1,1,14,14,12,0,24,24,35,35,1,1);
   BUF(TNode; Outpin; 15,15,15,15);
   BUF(Outpin; FeedBack; 10,10,10,10);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 35,35,35,35);
   DQFFC(DInput, CLKPin, Clear; TNode; 29,29,12,0,24,24,55,55,1,1,29,29,12,0,24,24,55,55,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 15,15,15,15,15,15,15,15);
    %END;
   BUF(Outpin; FeedBack; 10,10,10,10);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 35,35,35,35);
   DQFFC(DInput, CLK, Clear; TNode; 45,45,12,30,24,24,35,35,1,1,45,45,12,30,24,24,35,35,1,1);
   BUF(TNode; Outpin; 15,15,15,15);
   BUF(Outpin; FeedBack; 10,10,10,10);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 35,35,35,35);
   DQFFC(DInput, CLKPin, Clear; TNode; 29,29,12,0,24,24,55,55,1,1,29,29,12,0,24,24,55,55,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 15,15,15,15,15,15,15,15);
    %END;
   BUF(TNode; FeedBack; 10,10,10,10);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 35,35,35,35);
   DQFFC(DInput, CLK, Clear; TNode; 45,45,12,30,24,24,35,35,1,1,45,45,12,30,24,24,35,35,1,1);
   BUF(TNode; Outpin; 15,15,15,15);
   BUF(TNode; FeedBack; 10,10,10,10);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 35,35,35,35);
   DQFFC(DInput, CLKPin, Clear; TNode; 29,29,12,0,24,24,55,55,1,1,29,29,12,0,24,24,55,55,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 15,15,15,15,15,15,15,15);
    %END;
   BUF(TNode; FeedBack; 10,10,10,10);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 35,35,35,35);
   DQFFC(DInput, CLK, Clear; TNode; 45,45,12,30,24,24,35,35,1,1,45,45,12,30,24,24,35,35,1,1);
   BUF(TNode; Outpin; 15,15,15,15);
   BUF(TNode; FeedBack; 10,10,10,10);
 %END;
%MACEND;

SET(LARGEMODEL);

IODelay(P47, N49);
IODelay(P46, N50);
IODelay(P45, N51);
IODelay(P44, N52);
IODelay(P23, N53);
IODelay(P24, N54);
IODelay(P25, N55);
IODelay(P26, N56);
IODelay(P13, N57);
IODelay(P12, N58);
IODelay(P11, N59);
IODelay(P10, N60);
IODelay(P57, N61);
IODelay(P58, N62);
IODelay(P59, N63);
IODelay(P60, N64);

%FDF AND 0 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 ~N7 N7 ~N8 N8 ~N9 N9
	   ~N10 N10 ~N11 N11 ~N12 N12 ~N49 N49 ~N50 N50 ~N51 N51 ~N52 N52
	   ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57 ~N58 N58 ~N59 N59
	   ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64 ~P50 P50 ~P49 P49
	   ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16 ~P15 P15 ~P14 P14
	   ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19 ~P17 P17 ~P53 P53 *

LOR8(%SF42240, %FF00, L1);
LOR8(%SF42245, %FF880, L2);
LOR8(%SF42250, %FF1760, L3);
LOR8(%SF42255, %FF2640, L4);
LOR8(%SF42260, %FF3520, L5);
LOR8(%SF42265, %FF4400, L6);
LOR8(%SF42270, %FF5280, L7);
LOR8(%SF42275, %FF6160, L8);
LOR8(%SF42280, %FF7040, L9);
LOR8(%SF42285, %FF7920, L10);
LOR8(%SF42290, %FF8800, L11);
LOR8(%SF42295, %FF9680, L12);

%FDF AND 0 ~N13 N13 ~N14 N14 ~N15 N15 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19
           ~N20 N20 ~N21 N21 ~N22 N22 ~N23 N23 ~N24 N24 ~N49 N49 ~N50 N50
	   ~N51 N51 ~N52 N52 ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57
	   ~N58 N58 ~N59 N59 ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64
	   ~P50 P50 ~P49 P49 ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16
	   ~P15 P15 ~P14 P14 ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19
	   ~P17 P17 ~P53 P53 *

LOR8(%SF42300, %FF10560, L13);
LOR8(%SF42305, %FF11440, L14);
LOR8(%SF42310, %FF12320, L15);
LOR8(%SF42315, %FF13200, L16);
LOR8(%SF42320, %FF14080, L17);
LOR8(%SF42325, %FF14960, L18);
LOR8(%SF42330, %FF15840, L19);
LOR8(%SF42335, %FF16720, L20);
LOR8(%SF42340, %FF17600, L21);
LOR8(%SF42345, %FF18480, L22);
LOR8(%SF42350, %FF19360, L23);
LOR8(%SF42355, %FF20240, L24);

%FDF AND 0 ~N25 N25 ~N26 N26 ~N27 N27 ~N28 N28 ~N29 N29 ~N30 N30 ~N31 N31
           ~N32 N32 ~N33 N33 ~N34 N34 ~N35 N35 ~N36 N36 ~N49 N49 ~N50 N50
	   ~N51 N51 ~N52 N52 ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57
	   ~N58 N58 ~N59 N59 ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64
	   ~P50 P50 ~P49 P49 ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16
	   ~P15 P15 ~P14 P14 ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19
	   ~P17 P17 ~P53 P53 *

LOR8(%SF42360, %FF21120, L25);
LOR8(%SF42365, %FF22000, L26);
LOR8(%SF42370, %FF22880, L27);
LOR8(%SF42375, %FF23760, L28);
LOR8(%SF42380, %FF24640, L29);
LOR8(%SF42385, %FF25520, L30);
LOR8(%SF42390, %FF26400, L31);
LOR8(%SF42395, %FF27280, L32);
LOR8(%SF42400, %FF28160, L33);
LOR8(%SF42405, %FF29040, L34);
LOR8(%SF42410, %FF29920, L35);
LOR8(%SF42415, %FF30800, L36);

%FDF AND 0 ~N37 N37 ~N38 N38 ~N39 N39 ~N40 N40 ~N41 N41 ~N42 N42 ~N43 N43
           ~N44 N44 ~N45 N45 ~N46 N46 ~N47 N47 ~N48 N48 ~N49 N49 ~N50 N50
	   ~N51 N51 ~N52 N52 ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57
	   ~N58 N58 ~N59 N59 ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64
	   ~P50 P50 ~P49 P49 ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16
	   ~P15 P15 ~P14 P14 ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19
	   ~P17 P17 ~P53 P53 *

LOR8(%SF42420, %FF31680, L37);
LOR8(%SF42425, %FF32560, L38);
LOR8(%SF42430, %FF33440, L39);
LOR8(%SF42435, %FF34320, L40);
LOR8(%SF42440, %FF35200, L41);
LOR8(%SF42445, %FF36080, L42);
LOR8(%SF42450, %FF36960, L43);
LOR8(%SF42455, %FF37840, L44);
LOR8(%SF42460, %FF38720, L45);
LOR8(%SF42465, %FF39600, L46);
LOR8(%SF42470, %FF40480, L47);
LOR8(%SF42475, %FF41360, L48);

%FDF AND 0 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 ~N7 N7 ~N8 N8 ~N9 N9
	   ~N10 N10 ~N11 N11 ~N12 N12 ~N49 N49 ~N50 N50 ~N51 N51 ~N52 N52
	   ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57 ~N58 N58 ~N59 N59
	   ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64 ~P50 P50 ~P49 P49
	   ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16 ~P15 P15 ~P14 P14
	   ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19 ~P17 P17 ~P53 P53 *

EP1800GLOBAL(%SF42281, %SF7832, L9, P10, L49, %FF7832, N4, N113, %FF7744, L89, N177, P17, N193);
EP1800GLOBAL(%SF42286, %SF8712, L10, P11, L50, %FF8712, N3, N114, %FF8624, L90, N178, P17, N194);
EP1800GLOBAL(%SF42291, %SF9592, L11, P12, L51, %FF9592, N2, N115, %FF9504, L91, N179, P17, N195);
EP1800GLOBAL(%SF42296, %SF10472, L12, P13, L52, %FF10472, N1, N116, %FF10384, L92, N180, P17, N196);

%FDF AND 0 ~N13 N13 ~N14 N14 ~N15 N15 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19
           ~N20 N20 ~N21 N21 ~N22 N22 ~N23 N23 ~N24 N24 ~N49 N49 ~N50 N50
	   ~N51 N51 ~N52 N52 ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57
	   ~N58 N58 ~N59 N59 ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64
	   ~P50 P50 ~P49 P49 ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16
	   ~P15 P15 ~P14 P14 ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19
	   ~P17 P17 ~P53 P53 *

EP1800GLOBAL(%SF42301, %SF11352, L13, P23, L53, %FF11352, N13, N133, %FF11264, L93, N181, P19, N197);
EP1800GLOBAL(%SF42306, %SF12232, L14, P24, L54, %FF12232, N14, N134, %FF12144, L94, N182, P19, N198);
EP1800GLOBAL(%SF42311, %SF13112, L15, P25, L55, %FF13112, N15, N135, %FF13024, L95, N183, P19, N199);
EP1800GLOBAL(%SF42316, %SF13992, L16, P26, L56, %FF13992, N16, N136, %FF13904, L96, N184, P19, N200);

%FDF AND 0 ~N25 N25 ~N26 N26 ~N27 N27 ~N28 N28 ~N29 N29 ~N30 N30 ~N31 N31
           ~N32 N32 ~N33 N33 ~N34 N34 ~N35 N35 ~N36 N36 ~N49 N49 ~N50 N50
	   ~N51 N51 ~N52 N52 ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57
	   ~N58 N58 ~N59 N59 ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64
	   ~P50 P50 ~P49 P49 ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16
	   ~P15 P15 ~P14 P14 ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19
	   ~P17 P17 ~P53 P53 *

EP1800GLOBAL(%SF42401, %SF28952, L33, P44, L57, %FF28952, N28, N137, %FF28864, L97, N185, P51, N201);
EP1800GLOBAL(%SF42406, %SF29832, L34, P45, L58, %FF29832, N27, N138, %FF29744, L98, N186, P51, N202);
EP1800GLOBAL(%SF42411, %SF30712, L35, P46, L59, %FF30712, N26, N139, %FF30624, L99, N187, P51, N203);
EP1800GLOBAL(%SF42416, %SF31592, L36, P47, L60, %FF31592, N25, N140, %FF31504, L100, N188, P51, N204);

%FDF AND 0 ~N37 N37 ~N38 N38 ~N39 N39 ~N40 N40 ~N41 N41 ~N42 N42 ~N43 N43
           ~N44 N44 ~N45 N45 ~N46 N46 ~N47 N47 ~N48 N48 ~N49 N49 ~N50 N50
	   ~N51 N51 ~N52 N52 ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57
	   ~N58 N58 ~N59 N59 ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64
	   ~P50 P50 ~P49 P49 ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16
	   ~P15 P15 ~P14 P14 ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19
	   ~P17 P17 ~P53 P53 *

EP1800GLOBAL(%SF42421, %SF32472, L37, P57, L61, %FF32472, N37, N141, %FF32384, L101, N189, P53, N205);
EP1800GLOBAL(%SF42426, %SF33352, L38, P58, L62, %FF33352, N38, N142, %FF33264, L102, N190, P53, N206);
EP1800GLOBAL(%SF42431, %SF34232, L39, P59, L63, %FF34232, N39, N143, %FF34144, L103, N191, P53, N207);
EP1800GLOBAL(%SF42436, %SF35112, L40, P60, L64, %FF35112, N40, N144, %FF35024, L104, N192, P53, N208);

%FDF AND 0 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 ~N7 N7 ~N8 N8 ~N9 N9
	   ~N10 N10 ~N11 N11 ~N12 N12 ~N49 N49 ~N50 N50 ~N51 N51 ~N52 N52
	   ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57 ~N58 N58 ~N59 N59
	   ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64 ~P50 P50 ~P49 P49
	   ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16 ~P15 P15 ~P14 P14
	   ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19 ~P17 P17 ~P53 P53 *

EP1800LOCALENHANCED(%SF42241, %SF792, L1, P2, L65, %FF792, N12, N65, N97, %FF704, L105, N145, P17, N209);
EP1800LOCALENHANCED(%SF42246, %SF1672, L2, P3, L66, %FF1672, N11, N66, N98, %FF1584, L106, N146, P17, N210);
EP1800LOCALENHANCED(%SF42251, %SF2552, L3, P4, L67, %FF2552, N10, N67, N99, %FF2464, L107, N147, P17, N211);
EP1800LOCALENHANCED(%SF42256, %SF3432, L4, P5, L68, %FF3432, N9, N68, N100, %FF3344, L108, N148, P17, N212);
EP1800LOCAL(%SF42261, %SF4312, L5, P6, L69, %FF4312, N8, N69, N101, %FF4224, L109, N149, P17, N213);
EP1800LOCAL(%SF42266, %SF5192, L6, P7, L70, %FF5192, N7, N70, N102, %FF5104, L110, N150, P17, N214);
EP1800LOCAL(%SF42271, %SF6072, L7, P8, L71, %FF6072, N6, N71, N103, %FF5984, L111, N151, P17, N215);
EP1800LOCAL(%SF42276, %SF6952, L8, P9, L72, %FF6952, N5, N72, N104, %FF6864, L112, N152, P17, N216);

%FDF AND 0 ~N13 N13 ~N14 N14 ~N15 N15 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19
           ~N20 N20 ~N21 N21 ~N22 N22 ~N23 N23 ~N24 N24 ~N49 N49 ~N50 N50
	   ~N51 N51 ~N52 N52 ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57
	   ~N58 N58 ~N59 N59 ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64
	   ~P50 P50 ~P49 P49 ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16
	   ~P15 P15 ~P14 P14 ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19
	   ~P17 P17 ~P53 P53 *

EP1800LOCAL(%SF42321, %SF14872, L17, P27, L73, %FF14872, N17, N73, N105, %FF14784, L113, N153, P19, N217);
EP1800LOCAL(%SF42326, %SF15752, L18, P28, L74, %FF15752, N18, N74, N106, %FF15664, L114, N154, P19, N218);
EP1800LOCAL(%SF42331, %SF16632, L19, P29, L75, %FF16632, N19, N75, N107, %FF16544, L115, N155, P19, N219);
EP1800LOCAL(%SF42336, %SF17512, L20, P30, L76, %FF17512, N20, N76, N108, %FF17424, L116, N156, P19, N220);
EP1800LOCALENHANCED(%SF42341, %SF18392, L21, P31, L77, %FF18392, N21, N77, N109, %FF18304, L117, N157, P19, N221);
EP1800LOCALENHANCED(%SF42346, %SF19272, L22, P32, L78, %FF19272, N22, N78, N110, %FF19184, L118, N158, P19, N222);
EP1800LOCALENHANCED(%SF42351, %SF20152, L23, P33, L79, %FF20152, N23, N79, N111, %FF20064, L119, N159, P19, N223);
EP1800LOCALENHANCED(%SF42356, %SF21032, L24, P34, L80, %FF21032, N24, N80, N112, %FF20944, L120, N160, P19, N224);

%FDF AND 0 ~N25 N25 ~N26 N26 ~N27 N27 ~N28 N28 ~N29 N29 ~N30 N30 ~N31 N31
           ~N32 N32 ~N33 N33 ~N34 N34 ~N35 N35 ~N36 N36 ~N49 N49 ~N50 N50
	   ~N51 N51 ~N52 N52 ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57
	   ~N58 N58 ~N59 N59 ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64
	   ~P50 P50 ~P49 P49 ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16
	   ~P15 P15 ~P14 P14 ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19
	   ~P17 P17 ~P53 P53 *

EP1800LOCALENHANCED(%SF42361, %SF21912, L25, P36, L81, %FF21912, N36, N81, N113, %FF21824, L121, N161, P51, N225);
EP1800LOCALENHANCED(%SF42366, %SF22792, L26, P37, L82, %FF22792, N35, N82, N114, %FF22704, L122, N162, P51, N226);
EP1800LOCALENHANCED(%SF42371, %SF23672, L27, P38, L83, %FF23672, N34, N83, N115, %FF23584, L123, N163, P51, N227);
EP1800LOCALENHANCED(%SF42376, %SF24552, L28, P39, L84, %FF24552, N33, N84, N116, %FF24464, L124, N164, P51, N228);
EP1800LOCAL(%SF42381, %SF25432, L29, P40, L85, %FF25432, N32, N85, N117, %FF25344, L125, N165, P51, N229);
EP1800LOCAL(%SF42386, %SF26312, L30, P41, L86, %FF26312, N31, N86, N118, %FF26224, L126, N166, P51, N230);
EP1800LOCAL(%SF42391, %SF27192, L31, P42, L87, %FF27192, N30, N87, N119, %FF27104, L127, N167, P51, N231);
EP1800LOCAL(%SF42396, %SF28072, L32, P43, L88, %FF28072, N29, N88, N120, %FF27984, L128, N168, P51, N232);

%FDF AND 0 ~N37 N37 ~N38 N38 ~N39 N39 ~N40 N40 ~N41 N41 ~N42 N42 ~N43 N43
           ~N44 N44 ~N45 N45 ~N46 N46 ~N47 N47 ~N48 N48 ~N49 N49 ~N50 N50
	   ~N51 N51 ~N52 N52 ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57
	   ~N58 N58 ~N59 N59 ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64
	   ~P50 P50 ~P49 P49 ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16
	   ~P15 P15 ~P14 P14 ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19
	   ~P17 P17 ~P53 P53 *

EP1800LOCAL(%SF42441, %SF35992, L41, P61, L89, %FF35992, N41, N89, N121, %FF35904, L137, N169, P53, N233);
EP1800LOCAL(%SF42446, %SF36872, L42, P62, L90, %FF36872, N42, N90, N122, %FF36784, L138, N170, P53, N234);
EP1800LOCAL(%SF42451, %SF37752, L43, P63, L91, %FF37752, N43, N91, N123, %FF37664, L139, N171, P53, N235);
EP1800LOCAL(%SF42456, %SF38632, L44, P64, L92, %FF38632, N44, N92, N124, %FF38544, L140, N172, P53, N236);
EP1800LOCALENHANCED(%SF42461, %SF39512, L45, P65, L93, %FF39512, N45, N93, N125, %FF39424, L141, N173, P53, N237);
EP1800LOCALENHANCED(%SF42466, %SF40392, L46, P66, L94, %FF40392, N46, N94, N126, %FF40304, L142, N174, P53, N238);
EP1800LOCALENHANCED(%SF42471, %SF41272, L47, P67, L95, %FF41272, N47, N95, N127, %FF41184, L143, N175, P53, N239);
EP1800LOCALENHANCED(%SF42476, %SF42152, L48, P68, L96, %FF42152, N48, N96, N128, %FF42064, L144, N176, P53, N240);

%ENDMODEL

%StartModel
%Manufacturer:Intel
%Type:EP1800
%PartNumber:N5C180-75
%LastNode ? ?
%NumPins: 68
%FDF AND 0 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 ~N7 N7 ~N8 N8 ~N9 N9
	   ~N10 N10 ~N11 N11 ~N12 N12 ~N49 N49 ~N50 N50 ~N51 N51 ~N52 N52
	   ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57 ~N58 N58 ~N59 N59
	   ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64 ~P50 P50 ~P49 P49
	   ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16 ~P15 P15 ~P14 P14
	   ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19 ~P17 P17 ~P53 P53 *

%MACRO IODelay(OutPin:%TEXT, FDFNode:%TEXT);
    BUF(OutPin; FDFNode; 5,5,5,5);
%MACEND;

%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+88, %InFuse+176, %InFuse+264, %InFuse+352, %InFuse+440,
      %InFuse+528, %InFuse+616; LorOutput);
 %ELSE
  LNOR(%InFuse, %InFuse+88, %InFuse+176, %InFuse+264, %InFuse+352, %InFuse+440,
      %InFuse+528, %InFuse+616; LorOutput);
 %END;
%MACEND;

%MACRO EP1800GLOBAL(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
       XorInput:%TEXT, InFuse:%FF, TNode:%TEXT, CLK:%TEXT, ClrFuse:%FF,
       Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT, DInput:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   BUF(LorOutput; TNode; 53,53,53,53);
   %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
      BUF(LorOutput; OutPin; 70,70,70,70);
   %ELSE
      BUF(LorOutput; TSBInput; 70,70,70,70);
      TSB(TSBInput, %InFuse; Outpin; 17,17,17,17,17,17,17,17);
   %END;
 |1,3:
   BUF(LorOutput; TNode; 53,53,53,53);
   BUF(LorOutput; OutPin; 70,70,70,70);
 |4,5,6,7:
   BUF(LorOutput; TNode; 53,53,53,53);
   TSB(zero, ZERO; Outpin; 1,1,1,1,1,1,1,1);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 42,42,42,42);
   DQFFC(DInput, CLKPin, Clear; TNode; 32,32,13,0,25,25,59,59,1,1,32,32,13,0,25,25,59,59,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 17,17,17,17,17,17,17,17);
    %END;
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 42,42,42,42);
   DQFFC(DInput, CLK, Clear; TNode; 53,53,13,30,25,25,42,42,1,1,53,53,13,30,25,25,42,42,1,1);
   BUF(TNode; Outpin; 17,17,17,17);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 42,42,42,42);
   DQFFC(DInput, CLKPin, Clear; TNode; 32,32,13,0,25,25,59,59,1,1,32,32,13,0,25,25,59,59,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 17,17,17,17,17,17,17,17);
    %END;
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 42,42,42,42);
   DQFFC(DInput, CLK, Clear; TNode; 53,53,13,30,25,25,42,42,1,1,53,53,13,30,25,25,42,42,1,1);
   BUF(TNode; Outpin; 17,17,17,17);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 42,42,42,42);
   DQFFC(DInput, CLKPin, Clear; TNode; 15,15,13,0,25,25,42,42,1,1,15,15,13,0,25,25,42,42,1,1);
   TSB(zero, ZERO; Outpin; 1,1,1,1,1,1,1,1);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 42,42,42,42);
   DQFFC(DInput, CLK, Clear; TNode; 53,53,13,30,25,25,42,42,1,1,53,53,13,30,25,25,42,42,1,1);
   TSB(zero, ZERO; Outpin; 1,1,1,1,1,1,1,1);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 42,42,42,42);
   DQFFC(DInput, CLKPin, Clear; TNode; 15,15,13,0,25,25,42,42,1,1,15,15,13,0,25,25,42,42,1,1);
   TSB(zero, ZERO; Outpin; 1,1,1,1,1,1,1,1);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 42,42,42,42);
   DQFFC(DInput, CLK, Clear; TNode; 53,53,13,30,25,25,42,42,1,1,53,53,13,30,25,25,42,42,1,1);
   TSB(zero, ZERO; Outpin; 1,1,1,1,1,1,1,1);
 %END;
%MACEND;

%MACRO EP1800LOCAL(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT, DInput:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
      BUF(LorOutput; OutPin; 70,70,70,70);
   %ELSE
      BUF(LorOutput; TSBInput; 70,70,70,70);
      TSB(TSBInput, %InFuse; Outpin; 17,17,17,17,17,17,17,17);
   %END;
   BUF(OutPin; FeedBack; 11,11,11,11);
 |1,3:
   BUF(LorOutput; OutPin; 70,70,70,70);
   BUF(OutPin; FeedBack; 11,11,11,11);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 42,42,42,42);
   DQFFC(DInput, CLKPin, Clear; TNode; 15,15,13,0,25,25,42,42,1,1,15,15,13,0,25,25,42,42,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(LorOutput; OutPin; 70,70,70,70);
    %ELSE
       BUF(LorOutput; TSBInput; 70,70,70,70);
       TSB(TSBInput, %InFuse; Outpin; 17,17,17,17,17,17,17,17);
    %END;
   BUF(TNode; FeedBack; 11,11,11,11);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 42,42,42,42);
   DQFFC(DInput, CLK, Clear; TNode; 53,53,13,30,25,25,42,42,1,1,53,53,13,30,25,25,42,42,1,1);
   BUF(LorOutput; OutPin; 70,70,70,70);
   BUF(TNode; FeedBack; 11,11,11,11);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 42,42,42,42);
   DQFFC(DInput, CLKPin, Clear; TNode; 15,15,13,0,25,25,42,42,1,1,15,15,13,0,25,25,42,42,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(LorOutput; OutPin; 70,70,70,70);
    %ELSE
       BUF(LorOutput; TSBInput; 70,70,70,70);
       TSB(TSBInput, %InFuse; Outpin; 17,17,17,17,17,17,17,17);
    %END;
   BUF(TNode; FeedBack; 11,11,11,11);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 42,42,42,42);
   DQFFC(DInput, CLK, Clear; TNode; 53,53,13,30,25,25,42,42,1,1,53,53,13,30,25,25,42,42,1,1);
   BUF(LorOutput; OutPin; 70,70,70,70);
   BUF(TNode; FeedBack; 11,11,11,11);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 42,42,42,42);
   DQFFC(DInput, CLKPin, Clear; TNode; 32,32,13,0,25,25,59,59,1,1,32,32,13,0,25,25,59,59,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 17,17,17,17,17,17,17,17);
    %END;
   BUF(Outpin; FeedBack; 11,11,11,11);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 42,42,42,42);
   DQFFC(DInput, CLK, Clear; TNode; 53,53,13,30,25,25,42,42,1,1,53,53,13,30,25,25,42,42,1,1);
   BUF(TNode; Outpin; 17,17,17,17);
   BUF(Outpin; FeedBack; 11,11,11,11);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 42,42,42,42);
   DQFFC(DInput, CLKPin, Clear; TNode; 32,32,13,0,25,25,59,59,1,1,32,32,13,0,25,25,59,59,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 17,17,17,17,17,17,17,17);
    %END;
   BUF(Outpin; FeedBack; 11,11,11,11);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 42,42,42,42);
   DQFFC(DInput, CLK, Clear; TNode; 53,53,13,30,25,25,42,42,1,1,53,53,13,30,25,25,42,42,1,1);
   BUF(TNode; Outpin; 17,17,17,17);
   BUF(Outpin; FeedBack; 11,11,11,11);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 42,42,42,42);
   DQFFC(DInput, CLKPin, Clear; TNode; 32,32,13,0,25,25,59,59,1,1,32,32,13,0,25,25,59,59,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 17,17,17,17,17,17,17,17);
    %END;
   BUF(TNode; FeedBack; 11,11,11,11);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 42,42,42,42);
   DQFFC(DInput, CLK, Clear; TNode; 53,53,13,30,25,25,42,42,1,1,53,53,13,30,25,25,42,42,1,1);
   BUF(TNode; Outpin; 17,17,17,17);
   BUF(TNode; FeedBack; 11,11,11,11);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 42,42,42,42);
   DQFFC(DInput, CLKPin, Clear; TNode; 32,32,13,0,25,25,59,59,1,1,32,32,13,0,25,25,59,59,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 17,17,17,17,17,17,17,17);
    %END;
   BUF(TNode; FeedBack; 11,11,11,11);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 42,42,42,42);
   DQFFC(DInput, CLK, Clear; TNode; 53,53,13,30,25,25,42,42,1,1,53,53,13,30,25,25,42,42,1,1);
   BUF(TNode; Outpin; 17,17,17,17);
   BUF(TNode; FeedBack; 11,11,11,11);
 %END;
%MACEND;

%MACRO EP1800LOCALENHANCED(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT, DInput:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
      BUF(LorOutput; OutPin; 65,65,65,65);
   %ELSE
      BUF(LorOutput; TSBInput; 65,65,65,65);
      TSB(TSBInput, %InFuse; Outpin; 17,17,17,17,17,17,17,17);
   %END;
   BUF(OutPin; FeedBack; 11,11,11,11);
 |1,3:
   BUF(LorOutput; OutPin; 65,65,65,65);
   BUF(OutPin; FeedBack; 11,11,11,11);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 37,37,37,37);
   DQFFC(DInput, CLKPin, Clear; TNode; 15,15,13,0,25,25,37,37,1,1,15,15,13,0,25,25,37,37,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(LorOutput; OutPin; 65,65,65,65);
    %ELSE
       BUF(LorOutput; TSBInput; 65,65,65,65);
       TSB(TSBInput, %InFuse; Outpin; 17,17,17,17,17,17,17,17);
    %END;
   BUF(TNode; FeedBack; 11,11,11,11);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 37,37,37,37);
   DQFFC(DInput, CLK, Clear; TNode; 48,48,13,30,25,25,37,37,1,1,48,48,13,30,25,25,37,37,1,1);
   BUF(LorOutput; OutPin; 65,65,65,65);
   BUF(TNode; FeedBack; 11,11,11,11);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 37,37,37,37);
   DQFFC(DInput, CLKPin, Clear; TNode; 15,15,13,0,25,25,37,37,1,1,15,15,13,0,25,25,37,37,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(LorOutput; OutPin; 65,65,65,65);
    %ELSE
       BUF(LorOutput; TSBInput; 65,65,65,65);
       TSB(TSBInput, %InFuse; Outpin; 17,17,17,17,17,17,17,17);
    %END;
   BUF(TNode; FeedBack; 11,11,11,11);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 37,37,37,37);
   DQFFC(DInput, CLK, Clear; TNode; 48,48,13,30,25,25,37,37,1,1,48,48,13,30,25,25,37,37,1,1);
   BUF(LorOutput; OutPin; 65,65,65,65);
   BUF(TNode; FeedBack; 11,11,11,11);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 37,37,37,37);
   DQFFC(DInput, CLKPin, Clear; TNode; 32,32,13,0,25,25,54,54,1,1,32,32,13,0,25,25,54,54,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 17,17,17,17,17,17,17,17);
    %END;
   BUF(Outpin; FeedBack; 11,11,11,11);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 37,37,37,37);
   DQFFC(DInput, CLK, Clear; TNode; 48,48,13,30,25,25,37,37,1,1,48,48,13,30,25,25,37,37,1,1);
   BUF(TNode; Outpin; 17,17,17,17);
   BUF(Outpin; FeedBack; 11,11,11,11);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 37,37,37,37);
   DQFFC(DInput, CLKPin, Clear; TNode; 32,32,13,0,25,25,54,54,1,1,32,32,13,0,25,25,54,54,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 17,17,17,17,17,17,17,17);
    %END;
   BUF(Outpin; FeedBack; 11,11,11,11);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 37,37,37,37);
   DQFFC(DInput, CLK, Clear; TNode; 48,48,13,30,25,25,37,37,1,1,48,48,13,30,25,25,37,37,1,1);
   BUF(TNode; Outpin; 17,17,17,17);
   BUF(Outpin; FeedBack; 11,11,11,11);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 37,37,37,37);
   DQFFC(DInput, CLKPin, Clear; TNode; 32,32,13,0,25,25,54,54,1,1,32,32,13,0,25,25,54,54,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 17,17,17,17,17,17,17,17);
    %END;
   BUF(TNode; FeedBack; 11,11,11,11);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 37,37,37,37);
   DQFFC(DInput, CLK, Clear; TNode; 48,48,13,30,25,25,37,37,1,1,48,48,13,30,25,25,37,37,1,1);
   BUF(TNode; Outpin; 17,17,17,17);
   BUF(TNode; FeedBack; 11,11,11,11);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 37,37,37,37);
   DQFFC(DInput, CLKPin, Clear; TNode; 32,32,13,0,25,25,54,54,1,1,32,32,13,0,25,25,54,54,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 17,17,17,17,17,17,17,17);
    %END;
   BUF(TNode; FeedBack; 11,11,11,11);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 37,37,37,37);
   DQFFC(DInput, CLK, Clear; TNode; 48,48,13,30,25,25,37,37,1,1,48,48,13,30,25,25,37,37,1,1);
   BUF(TNode; Outpin; 17,17,17,17);
   BUF(TNode; FeedBack; 11,11,11,11);
 %END;
%MACEND;

SET(LARGEMODEL);

IODelay(P47, N49);
IODelay(P46, N50);
IODelay(P45, N51);
IODelay(P44, N52);
IODelay(P23, N53);
IODelay(P24, N54);
IODelay(P25, N55);
IODelay(P26, N56);
IODelay(P13, N57);
IODelay(P12, N58);
IODelay(P11, N59);
IODelay(P10, N60);
IODelay(P57, N61);
IODelay(P58, N62);
IODelay(P59, N63);
IODelay(P60, N64);

%FDF AND 0 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 ~N7 N7 ~N8 N8 ~N9 N9
	   ~N10 N10 ~N11 N11 ~N12 N12 ~N49 N49 ~N50 N50 ~N51 N51 ~N52 N52
	   ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57 ~N58 N58 ~N59 N59
	   ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64 ~P50 P50 ~P49 P49
	   ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16 ~P15 P15 ~P14 P14
	   ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19 ~P17 P17 ~P53 P53 *

LOR8(%SF42240, %FF00, L1);
LOR8(%SF42245, %FF880, L2);
LOR8(%SF42250, %FF1760, L3);
LOR8(%SF42255, %FF2640, L4);
LOR8(%SF42260, %FF3520, L5);
LOR8(%SF42265, %FF4400, L6);
LOR8(%SF42270, %FF5280, L7);
LOR8(%SF42275, %FF6160, L8);
LOR8(%SF42280, %FF7040, L9);
LOR8(%SF42285, %FF7920, L10);
LOR8(%SF42290, %FF8800, L11);
LOR8(%SF42295, %FF9680, L12);

%FDF AND 0 ~N13 N13 ~N14 N14 ~N15 N15 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19
           ~N20 N20 ~N21 N21 ~N22 N22 ~N23 N23 ~N24 N24 ~N49 N49 ~N50 N50
	   ~N51 N51 ~N52 N52 ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57
	   ~N58 N58 ~N59 N59 ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64
	   ~P50 P50 ~P49 P49 ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16
	   ~P15 P15 ~P14 P14 ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19
	   ~P17 P17 ~P53 P53 *

LOR8(%SF42300, %FF10560, L13);
LOR8(%SF42305, %FF11440, L14);
LOR8(%SF42310, %FF12320, L15);
LOR8(%SF42315, %FF13200, L16);
LOR8(%SF42320, %FF14080, L17);
LOR8(%SF42325, %FF14960, L18);
LOR8(%SF42330, %FF15840, L19);
LOR8(%SF42335, %FF16720, L20);
LOR8(%SF42340, %FF17600, L21);
LOR8(%SF42345, %FF18480, L22);
LOR8(%SF42350, %FF19360, L23);
LOR8(%SF42355, %FF20240, L24);

%FDF AND 0 ~N25 N25 ~N26 N26 ~N27 N27 ~N28 N28 ~N29 N29 ~N30 N30 ~N31 N31
           ~N32 N32 ~N33 N33 ~N34 N34 ~N35 N35 ~N36 N36 ~N49 N49 ~N50 N50
	   ~N51 N51 ~N52 N52 ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57
	   ~N58 N58 ~N59 N59 ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64
	   ~P50 P50 ~P49 P49 ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16
	   ~P15 P15 ~P14 P14 ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19
	   ~P17 P17 ~P53 P53 *

LOR8(%SF42360, %FF21120, L25);
LOR8(%SF42365, %FF22000, L26);
LOR8(%SF42370, %FF22880, L27);
LOR8(%SF42375, %FF23760, L28);
LOR8(%SF42380, %FF24640, L29);
LOR8(%SF42385, %FF25520, L30);
LOR8(%SF42390, %FF26400, L31);
LOR8(%SF42395, %FF27280, L32);
LOR8(%SF42400, %FF28160, L33);
LOR8(%SF42405, %FF29040, L34);
LOR8(%SF42410, %FF29920, L35);
LOR8(%SF42415, %FF30800, L36);

%FDF AND 0 ~N37 N37 ~N38 N38 ~N39 N39 ~N40 N40 ~N41 N41 ~N42 N42 ~N43 N43
           ~N44 N44 ~N45 N45 ~N46 N46 ~N47 N47 ~N48 N48 ~N49 N49 ~N50 N50
	   ~N51 N51 ~N52 N52 ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57
	   ~N58 N58 ~N59 N59 ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64
	   ~P50 P50 ~P49 P49 ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16
	   ~P15 P15 ~P14 P14 ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19
	   ~P17 P17 ~P53 P53 *

LOR8(%SF42420, %FF31680, L37);
LOR8(%SF42425, %FF32560, L38);
LOR8(%SF42430, %FF33440, L39);
LOR8(%SF42435, %FF34320, L40);
LOR8(%SF42440, %FF35200, L41);
LOR8(%SF42445, %FF36080, L42);
LOR8(%SF42450, %FF36960, L43);
LOR8(%SF42455, %FF37840, L44);
LOR8(%SF42460, %FF38720, L45);
LOR8(%SF42465, %FF39600, L46);
LOR8(%SF42470, %FF40480, L47);
LOR8(%SF42475, %FF41360, L48);

%FDF AND 0 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 ~N7 N7 ~N8 N8 ~N9 N9
	   ~N10 N10 ~N11 N11 ~N12 N12 ~N49 N49 ~N50 N50 ~N51 N51 ~N52 N52
	   ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57 ~N58 N58 ~N59 N59
	   ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64 ~P50 P50 ~P49 P49
	   ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16 ~P15 P15 ~P14 P14
	   ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19 ~P17 P17 ~P53 P53 *

EP1800GLOBAL(%SF42281, %SF7832, L9, P10, L49, %FF7832, N4, N113, %FF7744, L89, N177, P17, N193);
EP1800GLOBAL(%SF42286, %SF8712, L10, P11, L50, %FF8712, N3, N114, %FF8624, L90, N178, P17, N194);
EP1800GLOBAL(%SF42291, %SF9592, L11, P12, L51, %FF9592, N2, N115, %FF9504, L91, N179, P17, N195);
EP1800GLOBAL(%SF42296, %SF10472, L12, P13, L52, %FF10472, N1, N116, %FF10384, L92, N180, P17, N196);

%FDF AND 0 ~N13 N13 ~N14 N14 ~N15 N15 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19
           ~N20 N20 ~N21 N21 ~N22 N22 ~N23 N23 ~N24 N24 ~N49 N49 ~N50 N50
	   ~N51 N51 ~N52 N52 ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57
	   ~N58 N58 ~N59 N59 ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64
	   ~P50 P50 ~P49 P49 ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16
	   ~P15 P15 ~P14 P14 ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19
	   ~P17 P17 ~P53 P53 *

EP1800GLOBAL(%SF42301, %SF11352, L13, P23, L53, %FF11352, N13, N133, %FF11264, L93, N181, P19, N197);
EP1800GLOBAL(%SF42306, %SF12232, L14, P24, L54, %FF12232, N14, N134, %FF12144, L94, N182, P19, N198);
EP1800GLOBAL(%SF42311, %SF13112, L15, P25, L55, %FF13112, N15, N135, %FF13024, L95, N183, P19, N199);
EP1800GLOBAL(%SF42316, %SF13992, L16, P26, L56, %FF13992, N16, N136, %FF13904, L96, N184, P19, N200);

%FDF AND 0 ~N25 N25 ~N26 N26 ~N27 N27 ~N28 N28 ~N29 N29 ~N30 N30 ~N31 N31
           ~N32 N32 ~N33 N33 ~N34 N34 ~N35 N35 ~N36 N36 ~N49 N49 ~N50 N50
	   ~N51 N51 ~N52 N52 ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57
	   ~N58 N58 ~N59 N59 ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64
	   ~P50 P50 ~P49 P49 ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16
	   ~P15 P15 ~P14 P14 ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19
	   ~P17 P17 ~P53 P53 *

EP1800GLOBAL(%SF42401, %SF28952, L33, P44, L57, %FF28952, N28, N137, %FF28864, L97, N185, P51, N201);
EP1800GLOBAL(%SF42406, %SF29832, L34, P45, L58, %FF29832, N27, N138, %FF29744, L98, N186, P51, N202);
EP1800GLOBAL(%SF42411, %SF30712, L35, P46, L59, %FF30712, N26, N139, %FF30624, L99, N187, P51, N203);
EP1800GLOBAL(%SF42416, %SF31592, L36, P47, L60, %FF31592, N25, N140, %FF31504, L100, N188, P51, N204);

%FDF AND 0 ~N37 N37 ~N38 N38 ~N39 N39 ~N40 N40 ~N41 N41 ~N42 N42 ~N43 N43
           ~N44 N44 ~N45 N45 ~N46 N46 ~N47 N47 ~N48 N48 ~N49 N49 ~N50 N50
	   ~N51 N51 ~N52 N52 ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57
	   ~N58 N58 ~N59 N59 ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64
	   ~P50 P50 ~P49 P49 ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16
	   ~P15 P15 ~P14 P14 ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19
	   ~P17 P17 ~P53 P53 *

EP1800GLOBAL(%SF42421, %SF32472, L37, P57, L61, %FF32472, N37, N141, %FF32384, L101, N189, P53, N205);
EP1800GLOBAL(%SF42426, %SF33352, L38, P58, L62, %FF33352, N38, N142, %FF33264, L102, N190, P53, N206);
EP1800GLOBAL(%SF42431, %SF34232, L39, P59, L63, %FF34232, N39, N143, %FF34144, L103, N191, P53, N207);
EP1800GLOBAL(%SF42436, %SF35112, L40, P60, L64, %FF35112, N40, N144, %FF35024, L104, N192, P53, N208);

%FDF AND 0 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 ~N7 N7 ~N8 N8 ~N9 N9
	   ~N10 N10 ~N11 N11 ~N12 N12 ~N49 N49 ~N50 N50 ~N51 N51 ~N52 N52
	   ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57 ~N58 N58 ~N59 N59
	   ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64 ~P50 P50 ~P49 P49
	   ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16 ~P15 P15 ~P14 P14
	   ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19 ~P17 P17 ~P53 P53 *

EP1800LOCALENHANCED(%SF42241, %SF792, L1, P2, L65, %FF792, N12, N65, N97, %FF704, L105, N145, P17, N209);
EP1800LOCALENHANCED(%SF42246, %SF1672, L2, P3, L66, %FF1672, N11, N66, N98, %FF1584, L106, N146, P17, N210);
EP1800LOCALENHANCED(%SF42251, %SF2552, L3, P4, L67, %FF2552, N10, N67, N99, %FF2464, L107, N147, P17, N211);
EP1800LOCALENHANCED(%SF42256, %SF3432, L4, P5, L68, %FF3432, N9, N68, N100, %FF3344, L108, N148, P17, N212);
EP1800LOCAL(%SF42261, %SF4312, L5, P6, L69, %FF4312, N8, N69, N101, %FF4224, L109, N149, P17, N213);
EP1800LOCAL(%SF42266, %SF5192, L6, P7, L70, %FF5192, N7, N70, N102, %FF5104, L110, N150, P17, N214);
EP1800LOCAL(%SF42271, %SF6072, L7, P8, L71, %FF6072, N6, N71, N103, %FF5984, L111, N151, P17, N215);
EP1800LOCAL(%SF42276, %SF6952, L8, P9, L72, %FF6952, N5, N72, N104, %FF6864, L112, N152, P17, N216);

%FDF AND 0 ~N13 N13 ~N14 N14 ~N15 N15 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19
           ~N20 N20 ~N21 N21 ~N22 N22 ~N23 N23 ~N24 N24 ~N49 N49 ~N50 N50
	   ~N51 N51 ~N52 N52 ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57
	   ~N58 N58 ~N59 N59 ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64
	   ~P50 P50 ~P49 P49 ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16
	   ~P15 P15 ~P14 P14 ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19
	   ~P17 P17 ~P53 P53 *

EP1800LOCAL(%SF42321, %SF14872, L17, P27, L73, %FF14872, N17, N73, N105, %FF14784, L113, N153, P19, N217);
EP1800LOCAL(%SF42326, %SF15752, L18, P28, L74, %FF15752, N18, N74, N106, %FF15664, L114, N154, P19, N218);
EP1800LOCAL(%SF42331, %SF16632, L19, P29, L75, %FF16632, N19, N75, N107, %FF16544, L115, N155, P19, N219);
EP1800LOCAL(%SF42336, %SF17512, L20, P30, L76, %FF17512, N20, N76, N108, %FF17424, L116, N156, P19, N220);
EP1800LOCALENHANCED(%SF42341, %SF18392, L21, P31, L77, %FF18392, N21, N77, N109, %FF18304, L117, N157, P19, N221);
EP1800LOCALENHANCED(%SF42346, %SF19272, L22, P32, L78, %FF19272, N22, N78, N110, %FF19184, L118, N158, P19, N222);
EP1800LOCALENHANCED(%SF42351, %SF20152, L23, P33, L79, %FF20152, N23, N79, N111, %FF20064, L119, N159, P19, N223);
EP1800LOCALENHANCED(%SF42356, %SF21032, L24, P34, L80, %FF21032, N24, N80, N112, %FF20944, L120, N160, P19, N224);

%FDF AND 0 ~N25 N25 ~N26 N26 ~N27 N27 ~N28 N28 ~N29 N29 ~N30 N30 ~N31 N31
           ~N32 N32 ~N33 N33 ~N34 N34 ~N35 N35 ~N36 N36 ~N49 N49 ~N50 N50
	   ~N51 N51 ~N52 N52 ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57
	   ~N58 N58 ~N59 N59 ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64
	   ~P50 P50 ~P49 P49 ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16
	   ~P15 P15 ~P14 P14 ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19
	   ~P17 P17 ~P53 P53 *

EP1800LOCALENHANCED(%SF42361, %SF21912, L25, P36, L81, %FF21912, N36, N81, N113, %FF21824, L121, N161, P51, N225);
EP1800LOCALENHANCED(%SF42366, %SF22792, L26, P37, L82, %FF22792, N35, N82, N114, %FF22704, L122, N162, P51, N226);
EP1800LOCALENHANCED(%SF42371, %SF23672, L27, P38, L83, %FF23672, N34, N83, N115, %FF23584, L123, N163, P51, N227);
EP1800LOCALENHANCED(%SF42376, %SF24552, L28, P39, L84, %FF24552, N33, N84, N116, %FF24464, L124, N164, P51, N228);
EP1800LOCAL(%SF42381, %SF25432, L29, P40, L85, %FF25432, N32, N85, N117, %FF25344, L125, N165, P51, N229);
EP1800LOCAL(%SF42386, %SF26312, L30, P41, L86, %FF26312, N31, N86, N118, %FF26224, L126, N166, P51, N230);
EP1800LOCAL(%SF42391, %SF27192, L31, P42, L87, %FF27192, N30, N87, N119, %FF27104, L127, N167, P51, N231);
EP1800LOCAL(%SF42396, %SF28072, L32, P43, L88, %FF28072, N29, N88, N120, %FF27984, L128, N168, P51, N232);

%FDF AND 0 ~N37 N37 ~N38 N38 ~N39 N39 ~N40 N40 ~N41 N41 ~N42 N42 ~N43 N43
           ~N44 N44 ~N45 N45 ~N46 N46 ~N47 N47 ~N48 N48 ~N49 N49 ~N50 N50
	   ~N51 N51 ~N52 N52 ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57
	   ~N58 N58 ~N59 N59 ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64
	   ~P50 P50 ~P49 P49 ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16
	   ~P15 P15 ~P14 P14 ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19
	   ~P17 P17 ~P53 P53 *

EP1800LOCAL(%SF42441, %SF35992, L41, P61, L89, %FF35992, N41, N89, N121, %FF35904, L137, N169, P53, N233);
EP1800LOCAL(%SF42446, %SF36872, L42, P62, L90, %FF36872, N42, N90, N122, %FF36784, L138, N170, P53, N234);
EP1800LOCAL(%SF42451, %SF37752, L43, P63, L91, %FF37752, N43, N91, N123, %FF37664, L139, N171, P53, N235);
EP1800LOCAL(%SF42456, %SF38632, L44, P64, L92, %FF38632, N44, N92, N124, %FF38544, L140, N172, P53, N236);
EP1800LOCALENHANCED(%SF42461, %SF39512, L45, P65, L93, %FF39512, N45, N93, N125, %FF39424, L141, N173, P53, N237);
EP1800LOCALENHANCED(%SF42466, %SF40392, L46, P66, L94, %FF40392, N46, N94, N126, %FF40304, L142, N174, P53, N238);
EP1800LOCALENHANCED(%SF42471, %SF41272, L47, P67, L95, %FF41272, N47, N95, N127, %FF41184, L143, N175, P53, N239);
EP1800LOCALENHANCED(%SF42476, %SF42152, L48, P68, L96, %FF42152, N48, N96, N128, %FF42064, L144, N176, P53, N240);

%ENDMODEL

%StartModel
%Manufacturer:Intel
%Type:EP1800
%PartNumber:N5C180-90
%LastNode ? ?
%NumPins: 68
%FDF AND 0 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 ~N7 N7 ~N8 N8 ~N9 N9
	   ~N10 N10 ~N11 N11 ~N12 N12 ~N49 N49 ~N50 N50 ~N51 N51 ~N52 N52
	   ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57 ~N58 N58 ~N59 N59
	   ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64 ~P50 P50 ~P49 P49
	   ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16 ~P15 P15 ~P14 P14
	   ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19 ~P17 P17 ~P53 P53 *

%MACRO IODelay(OutPin:%TEXT, FDFNode:%TEXT);
    BUF(OutPin; FDFNode; 5,5,5,5);
%MACEND;

%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+88, %InFuse+176, %InFuse+264, %InFuse+352, %InFuse+440,
      %InFuse+528, %InFuse+616; LorOutput);
 %ELSE
  LNOR(%InFuse, %InFuse+88, %InFuse+176, %InFuse+264, %InFuse+352, %InFuse+440,
      %InFuse+528, %InFuse+616; LorOutput);
 %END;
%MACEND;

%MACRO EP1800GLOBAL(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
       XorInput:%TEXT, InFuse:%FF, TNode:%TEXT, CLK:%TEXT, ClrFuse:%FF,
       Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT, DInput:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   BUF(LorOutput; TNode; 71,71,71,71);
   %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
      BUF(LorOutput; Outpin; 85,85,85,85);
   %ELSE
      BUF(LorOutput; TSBInput; 85,85,85,85);
      TSB(TSBInput, %InFuse; Outpin; 23,23,23,23,23,23,23,23);
   %END;
 |1,3:
   BUF(LorOutput; TNode; 71,71,71,71);
   BUF(LorOutput; Outpin; 85,85,85,85);
 |4,5,6,7:
   BUF(LorOutput; TNode; 71,71,71,71);
   TSB(zero, ZERO; Outpin; 1,1,1,1,1,1,1,1);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 48,48,48,48);
   DQFFC(DInput, CLKPin, Clear; TNode; 41,41,18,0,30,30,71,71,1,1,41,41,18,0,30,30,71,71,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 23,23,23,23,23,23,23,23);
    %END;
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 48,48,48,48);
   DQFFC(DInput, CLK, Clear; TNode; 62,62,18,30,30,30,48,48,1,1,62,62,18,30,30,30,48,48,1,1);
   BUF(TNode; Outpin; 23,23,23,23);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 48,48,48,48);
   DQFFC(DInput, CLKPin, Clear; TNode; 41,41,18,0,30,30,71,71,1,1,41,41,18,0,30,30,71,71,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 23,23,23,23,23,23,23,23);
    %END;
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 48,48,48,48);
   DQFFC(DInput, CLK, Clear; TNode; 62,62,18,30,30,30,48,48,1,1,62,62,18,30,30,30,48,48,1,1);
   BUF(TNode; Outpin; 23,23,23,23);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 48,48,48,48);
   DQFFC(DInput, CLKPin, Clear; TNode; 18,18,18,0,30,30,48,48,1,1,18,18,18,0,30,30,48,48,1,1);
   TSB(zero, ZERO; Outpin; 1,1,1,1,1,1,1,1);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 48,48,48,48);
   DQFFC(DInput, CLK, Clear; TNode; 62,62,18,30,30,30,48,48,1,1,62,62,18,30,30,30,48,48,1,1);
   TSB(zero, ZERO; Outpin; 1,1,1,1,1,1,1,1);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 48,48,48,48);
   DQFFC(DInput, CLKPin, Clear; TNode; 18,18,18,0,30,30,48,48,1,1,18,18,18,0,30,30,48,48,1,1);
   TSB(zero, ZERO; Outpin; 1,1,1,1,1,1,1,1);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 48,48,48,48);
   DQFFC(DInput, CLK, Clear; TNode; 62,62,18,30,30,30,48,48,1,1,62,62,18,30,30,30,48,48,1,1);
   TSB(zero, ZERO; Outpin; 1,1,1,1,1,1,1,1);
 %END;
%MACEND;

%MACRO EP1800LOCAL(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT, DInput:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
      BUF(LorOutput; Outpin; 85,85,85,85);
   %ELSE
      BUF(LorOutput; TSBInput; 85,85,85,85);
      TSB(TSBInput, %InFuse; Outpin; 23,23,23,23,23,23,23,23);
   %END;
   BUF(OutPin; FeedBack; 16,16,16,16);
 |1,3:
   BUF(LorOutput; Outpin; 85,85,85,85);
   BUF(OutPin; FeedBack; 16,16,16,16);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 48,48,48,48);
   DQFFC(DInput, CLKPin, Clear; TNode; 41,41,18,0,30,30,71,71,1,1,41,41,18,0,30,30,71,71,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(LorOutput; Outpin; 85,85,85,85);
    %ELSE
       BUF(LorOutput; TSBInput; 85,85,85,85);
       TSB(TSBInput, %InFuse; Outpin; 23,23,23,23,23,23,23,23);
    %END;
   BUF(TNode; FeedBack; 16,16,16,16);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 48,48,48,48);
   DQFFC(DInput, CLK, Clear; TNode; 62,62,18,30,30,30,48,48,1,1,62,62,18,30,30,30,48,48,1,1);
   BUF(LorOutput; Outpin; 85,85,85,85);
   BUF(TNode; FeedBack; 16,16,16,16);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 48,48,48,48);
   DQFFC(DInput, CLKPin, Clear; TNode; 41,41,18,0,30,30,71,71,1,1,41,41,18,0,30,30,71,71,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(LorOutput; Outpin; 85,85,85,85);
    %ELSE
       BUF(LorOutput; TSBInput; 85,85,85,85);
       TSB(TSBInput, %InFuse; Outpin; 23,23,23,23,23,23,23,23);
    %END;
   BUF(TNode; FeedBack; 16,16,16,16);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 48,48,48,48);
   DQFFC(DInput, CLK, Clear; TNode; 62,62,18,30,30,30,48,48,1,1,62,62,18,30,30,30,48,48,1,1);
   BUF(LorOutput; Outpin; 85,85,85,85);
   BUF(TNode; FeedBack; 16,16,16,16);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 48,48,48,48);
   DQFFC(DInput, CLKPin, Clear; TNode; 41,41,18,0,30,30,71,71,1,1,41,41,18,0,30,30,71,71,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 23,23,23,23,23,23,23,23);
    %END;
   BUF(Outpin; FeedBack; 16,16,16,16);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 48,48,48,48);
   DQFFC(DInput, CLK, Clear; TNode; 62,62,18,30,30,30,48,48,1,1,62,62,18,30,30,30,48,48,1,1);
   BUF(TNode; Outpin; 23,23,23,23);
   BUF(Outpin; FeedBack; 16,16,16,16);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 48,48,48,48);
   DQFFC(DInput, CLKPin, Clear; TNode; 41,41,18,0,30,30,71,71,1,1,41,41,18,0,30,30,71,71,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 23,23,23,23,23,23,23,23);
    %END;
   BUF(Outpin; FeedBack; 16,16,16,16);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 48,48,48,48);
   DQFFC(DInput, CLK, Clear; TNode; 62,62,18,30,30,30,48,48,1,1,62,62,18,30,30,30,48,48,1,1);
   BUF(TNode; Outpin; 23,23,23,23);
   BUF(Outpin; FeedBack; 16,16,16,16);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 48,48,48,48);
   DQFFC(DInput, CLKPin, Clear; TNode; 41,41,18,0,30,30,71,71,1,1,41,41,18,0,30,30,71,71,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 23,23,23,23,23,23,23,23);
    %END;
   BUF(TNode; FeedBack; 16,16,16,16);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 48,48,48,48);
   DQFFC(DInput, CLK, Clear; TNode; 62,62,18,30,30,30,48,48,1,1,62,62,18,30,30,30,48,48,1,1);
   BUF(TNode; Outpin; 23,23,23,23);
   BUF(TNode; FeedBack; 16,16,16,16);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 48,48,48,48);
   DQFFC(DInput, CLKPin, Clear; TNode; 41,41,18,0,30,30,71,71,1,1,41,41,18,0,30,30,71,71,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 23,23,23,23,23,23,23,23);
    %END;
   BUF(TNode; FeedBack; 16,16,16,16);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 48,48,48,48);
   DQFFC(DInput, CLK, Clear; TNode; 62,62,18,30,30,30,48,48,1,1,62,62,18,30,30,30,48,48,1,1);
   BUF(TNode; Outpin; 23,23,23,23);
   BUF(TNode; FeedBack; 16,16,16,16);
 %END;
%MACEND;

%MACRO EP1800LOCALENHANCED(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT, DInput:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
      BUF(LorOutput; Outpin; 80,80,80,80);
   %ELSE
      BUF(LorOutput; TSBInput; 80,80,80,80);
      TSB(TSBInput, %InFuse; Outpin; 23,23,23,23,23,23,23,23);
   %END;
   BUF(OutPin; FeedBack; 16,16,16,16);
 |1,3:
   BUF(LorOutput; Outpin; 80,80,80,80);
   BUF(OutPin; FeedBack; 16,16,16,16);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 43,43,43,43);
   DQFFC(DInput, CLKPin, Clear; TNode; 41,41,18,0,30,30,66,66,1,1,41,41,18,0,30,30,66,66,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(LorOutput; Outpin; 80,80,80,80);
    %ELSE
       BUF(LorOutput; TSBInput; 80,80,80,80);
       TSB(TSBInput, %InFuse; Outpin; 23,23,23,23,23,23,23,23);
    %END;
   BUF(TNode; FeedBack; 16,16,16,16);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 43,43,43,43);
   DQFFC(DInput, CLK, Clear; TNode; 57,57,18,30,30,30,43,43,1,1,57,57,18,30,30,30,43,43,1,1);
   BUF(LorOutput; Outpin; 80,80,80,80);
   BUF(TNode; FeedBack; 16,16,16,16);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 43,43,43,43);
   DQFFC(DInput, CLKPin, Clear; TNode; 41,41,18,0,30,30,66,66,1,1,41,41,18,0,30,30,66,66,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(LorOutput; Outpin; 80,80,80,80);
    %ELSE
       BUF(LorOutput; TSBInput; 80,80,80,80);
       TSB(TSBInput, %InFuse; Outpin; 23,23,23,23,23,23,23,23);
    %END;
   BUF(TNode; FeedBack; 16,16,16,16);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 43,43,43,43);
   DQFFC(DInput, CLK, Clear; TNode; 57,57,18,30,30,30,43,43,1,1,57,57,18,30,30,30,43,43,1,1);
   BUF(LorOutput; Outpin; 80,80,80,80);
   BUF(TNode; FeedBack; 16,16,16,16);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 43,43,43,43);
   DQFFC(DInput, CLKPin, Clear; TNode; 41,41,18,0,30,30,66,66,1,1,41,41,18,0,30,30,66,66,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 23,23,23,23,23,23,23,23);
    %END;
   BUF(Outpin; FeedBack; 16,16,16,16);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 43,43,43,43);
   DQFFC(DInput, CLK, Clear; TNode; 57,57,18,30,30,30,43,43,1,1,57,57,18,30,30,30,43,43,1,1);
   BUF(TNode; Outpin; 23,23,23,23);
   BUF(Outpin; FeedBack; 16,16,16,16);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 43,43,43,43);
   DQFFC(DInput, CLKPin, Clear; TNode; 41,41,18,0,30,30,66,66,1,1,41,41,18,0,30,30,66,66,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 23,23,23,23,23,23,23,23);
    %END;
   BUF(Outpin; FeedBack; 16,16,16,16);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 43,43,43,43);
   DQFFC(DInput, CLK, Clear; TNode; 57,57,18,30,30,30,43,43,1,1,57,57,18,30,30,30,43,43,1,1);
   BUF(TNode; Outpin; 23,23,23,23);
   BUF(Outpin; FeedBack; 16,16,16,16);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 43,43,43,43);
   DQFFC(DInput, CLKPin, Clear; TNode; 41,41,18,0,30,30,66,66,1,1,41,41,18,0,30,30,66,66,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 23,23,23,23,23,23,23,23);
    %END;
   BUF(TNode; FeedBack; 16,16,16,16);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(LorOutput; DInput; 43,43,43,43);
   DQFFC(DInput, CLK, Clear; TNode; 57,57,18,30,30,30,43,43,1,1,57,57,18,30,30,30,43,43,1,1);
   BUF(TNode; Outpin; 23,23,23,23);
   BUF(TNode; FeedBack; 16,16,16,16);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 43,43,43,43);
   DQFFC(DInput, CLKPin, Clear; TNode; 41,41,18,0,30,30,66,66,1,1,41,41,18,0,30,30,66,66,1,1);
    %IF %EnableFuse..%EnableFuse+87 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 23,23,23,23,23,23,23,23);
    %END;
   BUF(TNode; FeedBack; 16,16,16,16);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   BUF(XorInput; DInput; 43,43,43,43);
   DQFFC(DInput, CLK, Clear; TNode; 57,57,18,30,30,30,43,43,1,1,57,57,18,30,30,30,43,43,1,1);
   BUF(TNode; Outpin; 23,23,23,23);
   BUF(TNode; FeedBack; 16,16,16,16);
 %END;
%MACEND;

SET(LARGEMODEL);

IODelay(P47, N49);
IODelay(P46, N50);
IODelay(P45, N51);
IODelay(P44, N52);
IODelay(P23, N53);
IODelay(P24, N54);
IODelay(P25, N55);
IODelay(P26, N56);
IODelay(P13, N57);
IODelay(P12, N58);
IODelay(P11, N59);
IODelay(P10, N60);
IODelay(P57, N61);
IODelay(P58, N62);
IODelay(P59, N63);
IODelay(P60, N64);

%FDF AND 0 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 ~N7 N7 ~N8 N8 ~N9 N9
	   ~N10 N10 ~N11 N11 ~N12 N12 ~N49 N49 ~N50 N50 ~N51 N51 ~N52 N52
	   ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57 ~N58 N58 ~N59 N59
	   ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64 ~P50 P50 ~P49 P49
	   ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16 ~P15 P15 ~P14 P14
	   ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19 ~P17 P17 ~P53 P53 *

LOR8(%SF42240, %FF00, L1);
LOR8(%SF42245, %FF880, L2);
LOR8(%SF42250, %FF1760, L3);
LOR8(%SF42255, %FF2640, L4);
LOR8(%SF42260, %FF3520, L5);
LOR8(%SF42265, %FF4400, L6);
LOR8(%SF42270, %FF5280, L7);
LOR8(%SF42275, %FF6160, L8);
LOR8(%SF42280, %FF7040, L9);
LOR8(%SF42285, %FF7920, L10);
LOR8(%SF42290, %FF8800, L11);
LOR8(%SF42295, %FF9680, L12);

%FDF AND 0 ~N13 N13 ~N14 N14 ~N15 N15 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19
           ~N20 N20 ~N21 N21 ~N22 N22 ~N23 N23 ~N24 N24 ~N49 N49 ~N50 N50
	   ~N51 N51 ~N52 N52 ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57
	   ~N58 N58 ~N59 N59 ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64
	   ~P50 P50 ~P49 P49 ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16
	   ~P15 P15 ~P14 P14 ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19
	   ~P17 P17 ~P53 P53 *

LOR8(%SF42300, %FF10560, L13);
LOR8(%SF42305, %FF11440, L14);
LOR8(%SF42310, %FF12320, L15);
LOR8(%SF42315, %FF13200, L16);
LOR8(%SF42320, %FF14080, L17);
LOR8(%SF42325, %FF14960, L18);
LOR8(%SF42330, %FF15840, L19);
LOR8(%SF42335, %FF16720, L20);
LOR8(%SF42340, %FF17600, L21);
LOR8(%SF42345, %FF18480, L22);
LOR8(%SF42350, %FF19360, L23);
LOR8(%SF42355, %FF20240, L24);

%FDF AND 0 ~N25 N25 ~N26 N26 ~N27 N27 ~N28 N28 ~N29 N29 ~N30 N30 ~N31 N31
           ~N32 N32 ~N33 N33 ~N34 N34 ~N35 N35 ~N36 N36 ~N49 N49 ~N50 N50
	   ~N51 N51 ~N52 N52 ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57
	   ~N58 N58 ~N59 N59 ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64
	   ~P50 P50 ~P49 P49 ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16
	   ~P15 P15 ~P14 P14 ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19
	   ~P17 P17 ~P53 P53 *

LOR8(%SF42360, %FF21120, L25);
LOR8(%SF42365, %FF22000, L26);
LOR8(%SF42370, %FF22880, L27);
LOR8(%SF42375, %FF23760, L28);
LOR8(%SF42380, %FF24640, L29);
LOR8(%SF42385, %FF25520, L30);
LOR8(%SF42390, %FF26400, L31);
LOR8(%SF42395, %FF27280, L32);
LOR8(%SF42400, %FF28160, L33);
LOR8(%SF42405, %FF29040, L34);
LOR8(%SF42410, %FF29920, L35);
LOR8(%SF42415, %FF30800, L36);

%FDF AND 0 ~N37 N37 ~N38 N38 ~N39 N39 ~N40 N40 ~N41 N41 ~N42 N42 ~N43 N43
           ~N44 N44 ~N45 N45 ~N46 N46 ~N47 N47 ~N48 N48 ~N49 N49 ~N50 N50
	   ~N51 N51 ~N52 N52 ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57
	   ~N58 N58 ~N59 N59 ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64
	   ~P50 P50 ~P49 P49 ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16
	   ~P15 P15 ~P14 P14 ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19
	   ~P17 P17 ~P53 P53 *

LOR8(%SF42420, %FF31680, L37);
LOR8(%SF42425, %FF32560, L38);
LOR8(%SF42430, %FF33440, L39);
LOR8(%SF42435, %FF34320, L40);
LOR8(%SF42440, %FF35200, L41);
LOR8(%SF42445, %FF36080, L42);
LOR8(%SF42450, %FF36960, L43);
LOR8(%SF42455, %FF37840, L44);
LOR8(%SF42460, %FF38720, L45);
LOR8(%SF42465, %FF39600, L46);
LOR8(%SF42470, %FF40480, L47);
LOR8(%SF42475, %FF41360, L48);

%FDF AND 0 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 ~N7 N7 ~N8 N8 ~N9 N9
	   ~N10 N10 ~N11 N11 ~N12 N12 ~N49 N49 ~N50 N50 ~N51 N51 ~N52 N52
	   ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57 ~N58 N58 ~N59 N59
	   ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64 ~P50 P50 ~P49 P49
	   ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16 ~P15 P15 ~P14 P14
	   ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19 ~P17 P17 ~P53 P53 *

EP1800GLOBAL(%SF42281, %SF7832, L9, P10, L49, %FF7832, N4, N113, %FF7744, L89, N177, P17, N193);
EP1800GLOBAL(%SF42286, %SF8712, L10, P11, L50, %FF8712, N3, N114, %FF8624, L90, N178, P17, N194);
EP1800GLOBAL(%SF42291, %SF9592, L11, P12, L51, %FF9592, N2, N115, %FF9504, L91, N179, P17, N195);
EP1800GLOBAL(%SF42296, %SF10472, L12, P13, L52, %FF10472, N1, N116, %FF10384, L92, N180, P17, N196);

%FDF AND 0 ~N13 N13 ~N14 N14 ~N15 N15 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19
           ~N20 N20 ~N21 N21 ~N22 N22 ~N23 N23 ~N24 N24 ~N49 N49 ~N50 N50
	   ~N51 N51 ~N52 N52 ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57
	   ~N58 N58 ~N59 N59 ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64
	   ~P50 P50 ~P49 P49 ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16
	   ~P15 P15 ~P14 P14 ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19
	   ~P17 P17 ~P53 P53 *

EP1800GLOBAL(%SF42301, %SF11352, L13, P23, L53, %FF11352, N13, N133, %FF11264, L93, N181, P19, N197);
EP1800GLOBAL(%SF42306, %SF12232, L14, P24, L54, %FF12232, N14, N134, %FF12144, L94, N182, P19, N198);
EP1800GLOBAL(%SF42311, %SF13112, L15, P25, L55, %FF13112, N15, N135, %FF13024, L95, N183, P19, N199);
EP1800GLOBAL(%SF42316, %SF13992, L16, P26, L56, %FF13992, N16, N136, %FF13904, L96, N184, P19, N200);

%FDF AND 0 ~N25 N25 ~N26 N26 ~N27 N27 ~N28 N28 ~N29 N29 ~N30 N30 ~N31 N31
           ~N32 N32 ~N33 N33 ~N34 N34 ~N35 N35 ~N36 N36 ~N49 N49 ~N50 N50
	   ~N51 N51 ~N52 N52 ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57
	   ~N58 N58 ~N59 N59 ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64
	   ~P50 P50 ~P49 P49 ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16
	   ~P15 P15 ~P14 P14 ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19
	   ~P17 P17 ~P53 P53 *

EP1800GLOBAL(%SF42401, %SF28952, L33, P44, L57, %FF28952, N28, N137, %FF28864, L97, N185, P51, N201);
EP1800GLOBAL(%SF42406, %SF29832, L34, P45, L58, %FF29832, N27, N138, %FF29744, L98, N186, P51, N202);
EP1800GLOBAL(%SF42411, %SF30712, L35, P46, L59, %FF30712, N26, N139, %FF30624, L99, N187, P51, N203);
EP1800GLOBAL(%SF42416, %SF31592, L36, P47, L60, %FF31592, N25, N140, %FF31504, L100, N188, P51, N204);

%FDF AND 0 ~N37 N37 ~N38 N38 ~N39 N39 ~N40 N40 ~N41 N41 ~N42 N42 ~N43 N43
           ~N44 N44 ~N45 N45 ~N46 N46 ~N47 N47 ~N48 N48 ~N49 N49 ~N50 N50
	   ~N51 N51 ~N52 N52 ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57
	   ~N58 N58 ~N59 N59 ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64
	   ~P50 P50 ~P49 P49 ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16
	   ~P15 P15 ~P14 P14 ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19
	   ~P17 P17 ~P53 P53 *

EP1800GLOBAL(%SF42421, %SF32472, L37, P57, L61, %FF32472, N37, N141, %FF32384, L101, N189, P53, N205);
EP1800GLOBAL(%SF42426, %SF33352, L38, P58, L62, %FF33352, N38, N142, %FF33264, L102, N190, P53, N206);
EP1800GLOBAL(%SF42431, %SF34232, L39, P59, L63, %FF34232, N39, N143, %FF34144, L103, N191, P53, N207);
EP1800GLOBAL(%SF42436, %SF35112, L40, P60, L64, %FF35112, N40, N144, %FF35024, L104, N192, P53, N208);

%FDF AND 0 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 ~N7 N7 ~N8 N8 ~N9 N9
	   ~N10 N10 ~N11 N11 ~N12 N12 ~N49 N49 ~N50 N50 ~N51 N51 ~N52 N52
	   ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57 ~N58 N58 ~N59 N59
	   ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64 ~P50 P50 ~P49 P49
	   ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16 ~P15 P15 ~P14 P14
	   ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19 ~P17 P17 ~P53 P53 *

EP1800LOCALENHANCED(%SF42241, %SF792, L1, P2, L65, %FF792, N12, N65, N97, %FF704, L105, N145, P17, N209);
EP1800LOCALENHANCED(%SF42246, %SF1672, L2, P3, L66, %FF1672, N11, N66, N98, %FF1584, L106, N146, P17, N210);
EP1800LOCALENHANCED(%SF42251, %SF2552, L3, P4, L67, %FF2552, N10, N67, N99, %FF2464, L107, N147, P17, N211);
EP1800LOCALENHANCED(%SF42256, %SF3432, L4, P5, L68, %FF3432, N9, N68, N100, %FF3344, L108, N148, P17, N212);
EP1800LOCAL(%SF42261, %SF4312, L5, P6, L69, %FF4312, N8, N69, N101, %FF4224, L109, N149, P17, N213);
EP1800LOCAL(%SF42266, %SF5192, L6, P7, L70, %FF5192, N7, N70, N102, %FF5104, L110, N150, P17, N214);
EP1800LOCAL(%SF42271, %SF6072, L7, P8, L71, %FF6072, N6, N71, N103, %FF5984, L111, N151, P17, N215);
EP1800LOCAL(%SF42276, %SF6952, L8, P9, L72, %FF6952, N5, N72, N104, %FF6864, L112, N152, P17, N216);

%FDF AND 0 ~N13 N13 ~N14 N14 ~N15 N15 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19
           ~N20 N20 ~N21 N21 ~N22 N22 ~N23 N23 ~N24 N24 ~N49 N49 ~N50 N50
	   ~N51 N51 ~N52 N52 ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57
	   ~N58 N58 ~N59 N59 ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64
	   ~P50 P50 ~P49 P49 ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16
	   ~P15 P15 ~P14 P14 ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19
	   ~P17 P17 ~P53 P53 *

EP1800LOCAL(%SF42321, %SF14872, L17, P27, L73, %FF14872, N17, N73, N105, %FF14784, L113, N153, P19, N217);
EP1800LOCAL(%SF42326, %SF15752, L18, P28, L74, %FF15752, N18, N74, N106, %FF15664, L114, N154, P19, N218);
EP1800LOCAL(%SF42331, %SF16632, L19, P29, L75, %FF16632, N19, N75, N107, %FF16544, L115, N155, P19, N219);
EP1800LOCAL(%SF42336, %SF17512, L20, P30, L76, %FF17512, N20, N76, N108, %FF17424, L116, N156, P19, N220);
EP1800LOCALENHANCED(%SF42341, %SF18392, L21, P31, L77, %FF18392, N21, N77, N109, %FF18304, L117, N157, P19, N221);
EP1800LOCALENHANCED(%SF42346, %SF19272, L22, P32, L78, %FF19272, N22, N78, N110, %FF19184, L118, N158, P19, N222);
EP1800LOCALENHANCED(%SF42351, %SF20152, L23, P33, L79, %FF20152, N23, N79, N111, %FF20064, L119, N159, P19, N223);
EP1800LOCALENHANCED(%SF42356, %SF21032, L24, P34, L80, %FF21032, N24, N80, N112, %FF20944, L120, N160, P19, N224);

%FDF AND 0 ~N25 N25 ~N26 N26 ~N27 N27 ~N28 N28 ~N29 N29 ~N30 N30 ~N31 N31
           ~N32 N32 ~N33 N33 ~N34 N34 ~N35 N35 ~N36 N36 ~N49 N49 ~N50 N50
	   ~N51 N51 ~N52 N52 ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57
	   ~N58 N58 ~N59 N59 ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64
	   ~P50 P50 ~P49 P49 ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16
	   ~P15 P15 ~P14 P14 ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19
	   ~P17 P17 ~P53 P53 *

EP1800LOCALENHANCED(%SF42361, %SF21912, L25, P36, L81, %FF21912, N36, N81, N113, %FF21824, L121, N161, P51, N225);
EP1800LOCALENHANCED(%SF42366, %SF22792, L26, P37, L82, %FF22792, N35, N82, N114, %FF22704, L122, N162, P51, N226);
EP1800LOCALENHANCED(%SF42371, %SF23672, L27, P38, L83, %FF23672, N34, N83, N115, %FF23584, L123, N163, P51, N227);
EP1800LOCALENHANCED(%SF42376, %SF24552, L28, P39, L84, %FF24552, N33, N84, N116, %FF24464, L124, N164, P51, N228);
EP1800LOCAL(%SF42381, %SF25432, L29, P40, L85, %FF25432, N32, N85, N117, %FF25344, L125, N165, P51, N229);
EP1800LOCAL(%SF42386, %SF26312, L30, P41, L86, %FF26312, N31, N86, N118, %FF26224, L126, N166, P51, N230);
EP1800LOCAL(%SF42391, %SF27192, L31, P42, L87, %FF27192, N30, N87, N119, %FF27104, L127, N167, P51, N231);
EP1800LOCAL(%SF42396, %SF28072, L32, P43, L88, %FF28072, N29, N88, N120, %FF27984, L128, N168, P51, N232);

%FDF AND 0 ~N37 N37 ~N38 N38 ~N39 N39 ~N40 N40 ~N41 N41 ~N42 N42 ~N43 N43
           ~N44 N44 ~N45 N45 ~N46 N46 ~N47 N47 ~N48 N48 ~N49 N49 ~N50 N50
	   ~N51 N51 ~N52 N52 ~N53 N53 ~N54 N54 ~N55 N55 ~N56 N56 ~N57 N57
	   ~N58 N58 ~N59 N59 ~N60 N60 ~N61 N61 ~N62 N62 ~N63 N63 ~N64 N64
	   ~P50 P50 ~P49 P49 ~P48 P48 ~P20 P20 ~P21 P21 ~P22 P22 ~P16 P16
	   ~P15 P15 ~P14 P14 ~P54 P54 ~P55 P55 ~P56 P56 ~P51 P51 ~P19 P19
	   ~P17 P17 ~P53 P53 *

EP1800LOCAL(%SF42441, %SF35992, L41, P61, L89, %FF35992, N41, N89, N121, %FF35904, L137, N169, P53, N233);
EP1800LOCAL(%SF42446, %SF36872, L42, P62, L90, %FF36872, N42, N90, N122, %FF36784, L138, N170, P53, N234);
EP1800LOCAL(%SF42451, %SF37752, L43, P63, L91, %FF37752, N43, N91, N123, %FF37664, L139, N171, P53, N235);
EP1800LOCAL(%SF42456, %SF38632, L44, P64, L92, %FF38632, N44, N92, N124, %FF38544, L140, N172, P53, N236);
EP1800LOCALENHANCED(%SF42461, %SF39512, L45, P65, L93, %FF39512, N45, N93, N125, %FF39424, L141, N173, P53, N237);
EP1800LOCALENHANCED(%SF42466, %SF40392, L46, P66, L94, %FF40392, N46, N94, N126, %FF40304, L142, N174, P53, N238);
EP1800LOCALENHANCED(%SF42471, %SF41272, L47, P67, L95, %FF41272, N47, N95, N127, %FF41184, L143, N175, P53, N239);
EP1800LOCALENHANCED(%SF42476, %SF42152, L48, P68, L96, %FF42152, N48, N96, N128, %FF42064, L144, N176, P53, N240);

%ENDMODEL