(***************************************************************************)
(*                                                                         *)
(*                         Copyright (C) 1987-1990                         *)
(*                      by Gogesch Micro Systems, INC.                     *)
(*                                                                         *)
(*                           All rights reserved.                          *)
(*                                                                         *)
(***************************************************************************)

;Delays for the ATMEL devices were taken from their 1987 data sheet for 22v10


;Delays for the following devices are given for 50pF only;
;subtracted 2ns for 15pF delays.
;Feedback Setup Time and Clk to Feedback delays could not be modeled.
%StartModel
%Manufacturer:ATMEL
%Type:22V10
%PartNumber:AT22V10-25
%LastNode ? ?
%NumPins: 24
%FDF AND 0 P1 ~P1 N1 ~N1 P2 ~P2 N2 ~N2 P3 ~P3 N3 ~N3 P4 ~P4 N4 ~N4 P5 ~P5
     N5 ~N5 P6 ~P6 N6 ~N6 P7 ~P7 N7 ~N7 P8 ~P8 N8 ~N8 P9 ~P9 N9 ~N9
     P10 ~P10 N10 ~N10 P11 ~P11 P13 ~P13 *

%MACRO LOR16(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308,%InFuse+352,%InFuse+396,%InFuse+440,%InFuse+484,
     %InFuse+528,%InFuse+572,%InFuse+616,%InFuse+660; OutLNode);
%MACEND;

%MACRO LOR14(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308,%InFuse+352,%InFuse+396,%InFuse+440,%InFuse+484,
     %InFuse+528,%InFuse+572; OutLNode);
%MACEND;

%MACRO LOR12(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308,%InFuse+352,%InFuse+396,%InFuse+440,
     %InFuse+484; OutLNode);
%MACEND;

%MACRO LOR10(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308,%InFuse+352,%InFuse+396; OutLNode);
%MACEND;

%MACRO LOR8(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308; OutLNode);
%MACEND;

%MACRO V10Mac(S1:%SF, S0:%SF, FeedBack:%TEXT, OrOutput:%TEXT, TNode:%TEXT,
              OutPin:%TEXT, InFuse:%FF, EnableFuse:%SF, TLNode:%TEXT);
 %CASE %S1,%S0
   0:
     LOR(OrOutput, L21; TLNode);
     DQFFC(TLNode, P1, L22; TNode; 13,13,18,0,12,12,23,23,25,25,15,15,18,0,12,12,25,25,25,25);
    %IF %EnableFuse..%EnableFuse+43 = 1 %THEN
     INV(TNode; OutPin; 0,0,0,0);
    %ELSE
     ITSB(TNode, %InFuse; OutPin; 23,23,23,23,25,25,25,25);
    %END;
    INV(TNode; FeedBack; 0,0,0,0);
  |1:
     LOR(OrOutput, L21; TLNode);
     DQFFC(TLNode, P1, L22; TNode; 13,13,18,0,12,12,23,23,25,25,15,15,18,0,12,12,25,25,25,25);
    %IF %EnableFuse..%EnableFuse+43 = 1 %THEN
     BUF(TNode; OutPin; 0,0,0,0);
    %ELSE
     TSB(TNode, %InFuse; OutPin; 23,23,23,23,25,25,25,25);
    %END;
    INV(TNode; FeedBack; 0,0,0,0);
  |2:
    %IF %EnableFuse..%EnableFuse+43 = 1 %THEN
     INV(OrOutput; OutPin; 23,23,25,25);
    %ELSE
     INV(OrOutput; TNode; 23,23,25,25);
     TSB(TNode, %InFuse; OutPin; 23,23,23,23,25,25,25,25);
    %END;
    BUF(OutPin; FeedBack; 0,0,0,0);
  |3:
    %IF %EnableFuse..%EnableFuse+43 = 1 %THEN
     BUF(OrOutput; OutPin; 23,23,25,25);
    %ELSE
     BUF(OrOutput; TNode; 23,23,25,25);
     TSB(TNode, %InFuse; OutPin; 23,23,23,23,25,25,25,25);
    %END;
    BUF(OutPin; FeedBack; 0,0,0,0);
  %END;
%MACEND;

LAND(%FF5764; L21);
LNOR(%FF00, IPH; L22);

LOR8(%FF88, L1);
LOR10(%FF484, L2);
LOR12(%FF968, L3);
LOR14(%FF1540, L4);
LOR16(%FF2200, L5);
LOR16(%FF2948, L6);
LOR14(%FF3696, L7);
LOR12(%FF4356, L8);
LOR10(%FF4928, L9);
LOR8(%FF5412, L10);

V10Mac(%SF5809, %SF5808, N1, L1, N11, P23, %FF44, %SF44, L11);
V10Mac(%SF5811, %SF5810, N2, L2, N12, P22, %FF440, %SF440, L12);
V10Mac(%SF5813, %SF5812, N3, L3, N13, P21, %FF924, %SF924, L13);
V10Mac(%SF5815, %SF5814, N4, L4, N14, P20, %FF1496, %SF1496, L14);
V10Mac(%SF5817, %SF5816, N5, L5, N15, P19, %FF2156, %SF2156, L15);
V10Mac(%SF5819, %SF5818, N6, L6, N16, P18, %FF2904, %SF2904, L16);
V10Mac(%SF5821, %SF5820, N7, L7, N17, P17, %FF3652, %SF3652, L17);
V10Mac(%SF5823, %SF5822, N8, L8, N18, P16, %FF4312, %SF4312, L18);
V10Mac(%SF5825, %SF5824, N9, L9, N19, P15, %FF4884, %SF4884, L19);
V10Mac(%SF5827, %SF5826, N10, L10, N20, P14, %FF5368, %SF5368, L20);
%EndModel

;Delays for the following devices are given for 50pF only;
;subtracted 2ns for 15pF delays.
;Feedback Setup Time and Clk to Feedback delays could not be modeled.
%StartModel
%Manufacturer:ATMEL
%Type:22V10
%PartNumber:AT22V10-35
%LastNode ? ?
%NumPins: 24
%FDF AND 0 P1 ~P1 N1 ~N1 P2 ~P2 N2 ~N2 P3 ~P3 N3 ~N3 P4 ~P4 N4 ~N4 P5 ~P5
     N5 ~N5 P6 ~P6 N6 ~N6 P7 ~P7 N7 ~N7 P8 ~P8 N8 ~N8 P9 ~P9 N9 ~N9
     P10 ~P10 N10 ~N10 P11 ~P11 P13 ~P13 *

%MACRO LOR16(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308,%InFuse+352,%InFuse+396,%InFuse+440,%InFuse+484,
     %InFuse+528,%InFuse+572,%InFuse+616,%InFuse+660; OutLNode);
%MACEND;

%MACRO LOR14(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308,%InFuse+352,%InFuse+396,%InFuse+440,%InFuse+484,
     %InFuse+528,%InFuse+572; OutLNode);
%MACEND;

%MACRO LOR12(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308,%InFuse+352,%InFuse+396,%InFuse+440,
     %InFuse+484; OutLNode);
%MACEND;

%MACRO LOR10(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308,%InFuse+352,%InFuse+396; OutLNode);
%MACEND;

%MACRO LOR8(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308; OutLNode);
%MACEND;

%MACRO V10Mac(S1:%SF, S0:%SF, FeedBack:%TEXT, OrOutput:%TEXT, TNode:%TEXT,
              OutPin:%TEXT, InFuse:%FF, EnableFuse:%SF, TLNode:%TEXT);
 %CASE %S1,%S0
   0:
     LOR(OrOutput, L21; TLNode);
     DQFFC(TLNode, P1, L22; TNode; 23,23,25,0,18,18,33,33,35,35,25,25,25,0,18,18,35,35,35,35);
    %IF %EnableFuse..%EnableFuse+43 = 1 %THEN
     INV(TNode; OutPin; 0,0,0,0);
    %ELSE
     ITSB(TNode, %InFuse; OutPin; 33,33,33,33,35,35,35,35);
    %END;
    INV(TNode; FeedBack; 0,0,0,0);
  |1:
     LOR(OrOutput, L21; TLNode);
     DQFFC(TLNode, P1, L22; TNode; 23,23,25,0,18,18,33,33,35,35,25,25,25,0,18,18,35,35,35,35);
    %IF %EnableFuse..%EnableFuse+43 = 1 %THEN
     BUF(TNode; OutPin; 0,0,0,0);
    %ELSE
     TSB(TNode, %InFuse; OutPin; 33,33,33,33,35,35,35,35);
    %END;
    INV(TNode; FeedBack; 0,0,0,0);
  |2:
    %IF %EnableFuse..%EnableFuse+43 = 1 %THEN
     INV(OrOutput; OutPin; 33,33,35,35);
    %ELSE
     INV(OrOutput; TNode; 33,33,35,35);
     TSB(TNode, %InFuse; OutPin; 33,33,33,33,35,35,35,35);
    %END;
    BUF(OutPin; FeedBack; 0,0,0,0);
  |3:
    %IF %EnableFuse..%EnableFuse+43 = 1 %THEN
     BUF(OrOutput; OutPin; 33,33,35,35);
    %ELSE
     BUF(OrOutput; TNode; 33,33,35,35);
     TSB(TNode, %InFuse; OutPin; 33,33,33,33,35,35,35,35);
    %END;
    BUF(OutPin; FeedBack; 0,0,0,0);
  %END;
%MACEND;

LAND(%FF5764; L21);
LNOR(%FF00, IPH; L22);

LOR8(%FF88, L1);
LOR10(%FF484, L2);
LOR12(%FF968, L3);
LOR14(%FF1540, L4);
LOR16(%FF2200, L5);
LOR16(%FF2948, L6);
LOR14(%FF3696, L7);
LOR12(%FF4356, L8);
LOR10(%FF4928, L9);
LOR8(%FF5412, L10);

V10Mac(%SF5809, %SF5808, N1, L1, N11, P23, %FF44, %SF44, L11);
V10Mac(%SF5811, %SF5810, N2, L2, N12, P22, %FF440, %SF440, L12);
V10Mac(%SF5813, %SF5812, N3, L3, N13, P21, %FF924, %SF924, L13);
V10Mac(%SF5815, %SF5814, N4, L4, N14, P20, %FF1496, %SF1496, L14);
V10Mac(%SF5817, %SF5816, N5, L5, N15, P19, %FF2156, %SF2156, L15);
V10Mac(%SF5819, %SF5818, N6, L6, N16, P18, %FF2904, %SF2904, L16);
V10Mac(%SF5821, %SF5820, N7, L7, N17, P17, %FF3652, %SF3652, L17);
V10Mac(%SF5823, %SF5822, N8, L8, N18, P16, %FF4312, %SF4312, L18);
V10Mac(%SF5825, %SF5824, N9, L9, N19, P15, %FF4884, %SF4884, L19);
V10Mac(%SF5827, %SF5826, N10, L10, N20, P14, %FF5368, %SF5368, L20);
%EndModel

%StartModel
%Manufacturer:Atmel
%Type:ATV750
%PartNumber:ATV750-30
%LastNode ? ?
%NumPins: 24
%FDF AND 0 ~P13 P13 ~P11 P11 N19 ~N19 N20 ~N20 ~P14 P14 ~P10 P10 N17 ~N17
     N18 ~N18 ~P15 P15 ~P9 P9 N15 ~N15 N16 ~N16 ~P16 P16 ~P8 P8 N13 ~N13
     N14 ~N14 ~P17 P17 ~P7 P7 N11 ~N11 N12 ~N12 ~P18 P18 ~P6 P6 N9 ~N9
     N10 ~N10 ~P19 P19 ~P5 P5 N7 ~N7 N8 ~N8 ~P20 P20 ~P4 P4 N5 ~N5 N6 ~N6
     ~P21 P21 ~P3 P3 N3 ~N3 N4 ~N4 ~P22 P22 ~P2 P2 N1 ~N1 N2 ~N2 ~P23 P23
     ~P1 P1*

%MACRO LOR8(InFuse:%FF, OrOutput1:%TEXT, OrOutput2:%TEXT);
 LOR(%InFuse,%InFuse+84,%InFuse+168,%InFuse+252,%InFuse+336,%InFuse+420,
     %InFuse+504,%InFuse+588; OrOutput1);
 LOR(%InFuse+672,%InFuse+756,%InFuse+840,%InFuse+924,%InFuse+1008,%InFuse+1092,
     %InFuse+1176,%InFuse+1260; OrOutput2);
%MACEND;

%MACRO LOR7(InFuse:%FF, OrOutput1:%TEXT, OrOutput2:%TEXT);
 LOR(%InFuse,%InFuse+84,%InFuse+168,%InFuse+252,%InFuse+336,%InFuse+420,
     %InFuse+504; OrOutput1);
 LOR(%InFuse+588,%InFuse+672,%InFuse+756,%InFuse+840,%InFuse+924,%InFuse+1008,
     %InFuse+1092; OrOutput2);
%MACEND;

%MACRO LOR6(InFuse:%FF, OrOutput1:%TEXT, OrOutput2:%TEXT);
 LOR(%InFuse,%InFuse+84,%InFuse+168,%InFuse+252,%InFuse+336,%InFuse+420;
     OrOutput1);
 LOR(%InFuse+504,%InFuse+588,%InFuse+672,%InFuse+756,%InFuse+840,%InFuse+924;
     OrOutput2);
%MACEND;

%MACRO LOR5(InFuse:%FF, OrOutput1:%TEXT, OrOutput2:%TEXT);
 LOR(%InFuse,%InFuse+84,%InFuse+168,%InFuse+252,%InFuse+336; OrOutput1);
 LOR(%InFuse+420,%InFuse+504,%InFuse+588,%InFuse+672,%InFuse+756; OrOutput2);
%MACEND;

%MACRO LOR4(InFuse:%FF, OrOutput1:%TEXT, OrOutput2:%TEXT);
 LOR(%InFuse,%InFuse+84,%InFuse+168,%InFuse+252; OrOutput1);
 LOR(%InFuse+336,%InFuse+420,%InFuse+504,%InFuse+588; OrOutput2);
%MACEND;

%MACRO RegisterFeedBack(Reg1Clock:%FF, Reg2Clock:%FF, Clock1:%TEXT,
       Clock2:%TEXT, ARFuse1:%FF, ARFuse2:%FF, Reset1:%TEXT, Reset2:%TEXT,
       OrNode:%TEXT, OrOutput2:%TEXT, TRegNode1:%TEXT, TRegNode2:%TEXT,
       FeedBack1:%TEXT, FeedBack2:%TEXT);

     AND(Reg1Clock; Clock1; 0,0,0,0);
     AND(Reg2Clock; Clock2; 0,0,0,0);
     LNOR(ARFuse1, IPH; Reset1);
     LNOR(ARFuse2, IPH; Reset2);

     DQFFC(OrNode, Clock1, Reset1; TRegNode1; 10,10,15,5,12,12,30,30,30,30,10,10,15,5,12,12,30,30,30,30);
     DQFFC(OrOutput2, Clock2, Reset2; TRegNode2; 10,10,15,5,12,12,30,30,30,30,10,10,15,5,12,12,30,30,30,30);
     BUF(TRegNode1; FeedBack1; 0,0,0,0);
     BUF(TRegNode2; FeedBack2; 0,0,0,0);
%MACEND;

%MACRO ATV750(OrOutput1:%TEXT, OrOutput2:%TEXT, OrNode:%TEXT, EnableFuse:%SF,
       TRegNode1:%TEXT, OutPin:%TEXT, InFuse:%FF, TNode:%TEXT, S0:%SF);
%CASE %S0+2, %S0+1, %S0
   0:
     OR(OrOutput1, OrOutput2, L41; OrNode; 15,15,15,15);
    %IF %EnableFuse..%EnableFuse+83 = 1 %THEN
     INV(TRegNode1; OutPin; 0,0,0,0);
    %ELSE
     ITSB(TRegNode1, %InFuse; OutPin; 30,30,30,30,30,30,30,30);
    %END;
  |1:
     OR(OrOutput1, OrOutput2, L41; OrNode; 15,15,15,15);
    %IF %EnableFuse..%EnableFuse+83 = 1 %THEN
     NOR(OrOutput1, OrOutput2; OutPin; 30,30,30,30);
    %ELSE
     NOR(OrOutput1, OrOutput2; TNode; 30,30,30,30);
     TSB(TNode, %InFuse; OutPin; 30,30,30,30,30,30,30,30);
    %END;
  |2:
    OR(OrOutput1, L41; OrNode; 15,15,15,15);
    %IF %EnableFuse..%EnableFuse+83 = 1 %THEN
     INV(TRegNode1; OutPin; 0,0,0,0);
    %ELSE
     ITSB(TRegNode1, %InFuse; OutPin; 30,30,30,30,30,30,30,30);
    %END;
  |3:
    OR(OrOutput1, L41; OrNode; 15,15,15,15);
    %IF %EnableFuse..%EnableFuse+83 = 1 %THEN
     INV(OrOutput1; OutPin; 30,30,30,30);
    %ELSE
     INV(OrOutput1; TNode; 30,30,30,30);
     TSB(TNode, %InFuse; OutPin; 30,30,30,30,30,30,30,30);
    %END;
  |4:
     OR(OrOutput1, OrOutput2, L41; OrNode; 15,15,15,15);
    %IF %EnableFuse..%EnableFuse+83 = 1 %THEN
     BUF(TRegNode1; OutPin; 0,0,0,0);
    %ELSE
     TSB(TRegNode1, %InFuse; OutPin; 30,30,30,30,30,30,30,30);
    %END;
  |5:
     OR(OrOutput1, OrOutput2, L41; OrNode; 15,15,15,15);
    %IF %EnableFuse..%EnableFuse+83 = 1 %THEN
     OR(OrOutput1, OrOutput2; OutPin; 30,30,30,30);
    %ELSE
     OR(OrOutput1, OrOutput2; TNode; 30,30,30,30);
     TSB(TNode, %InFuse; OutPin; 30,30,30,30,30,30,30,30);
    %END;
  |6:
    OR(OrOutput1, L41; OrNode; 15,15,15,15);
    %IF %EnableFuse..%EnableFuse+83 = 1 %THEN
     BUF(TRegNode1; OutPin; 0,0,0,0);
    %ELSE
     TSB(TRegNode1, %InFuse; OutPin; 30,30,30,30,30,30,30,30);
    %END;
  |7:
    OR(OrOutput1, L41; OrNode; 15,15,15,15);
    %IF %EnableFuse..%EnableFuse+83 = 1 %THEN
     BUF(OrOutput1; OutPin; 30,30,30,30);
    %ELSE
     BUF(OrOutput1; TNode; 30,30,30,30);
     TSB(TNode, %InFuse; OutPin; 30,30,30,30,30,30,30,30);
    %END;
  %END;
%MACEND;

LAND(%FF14280; L41);

LOR4(%FF00,L1, L11);
LOR5(%FF1092,L2, L12);
LOR6(%FF2352,L3, L13);
LOR7(%FF3780,L4, L14);
LOR8(%FF5376,L5, L15);
LOR8(%FF7140,L6, L16);
LOR7(%FF8904,L7, L17);
LOR6(%FF10500,L8, L18);
LOR5(%FF11928,L9, L19);
LOR4(%FF13188,L10, L20);

RegisterFeedBack(%FF756, %FF840, N21, N31, %FF672, %FF924, L21, L31, N41,
L11, N51, N61, N2, N1);
RegisterFeedBack(%FF2016, %FF2100, N22, N32, %FF1932, %FF2184, L22, L32, N42,
L12, N52, N62, N4, N3);
RegisterFeedBack(%FF3444, %FF3528, N23, N33, %FF3380, %FF3812, L23, L33, N43,
L13, N53, N63, N6, N5);
RegisterFeedBack(%FF5040, %FF5124, N24, N34, %FF4956, %FF5208, L24, L34, N44,
L14, N54, N64, N8, N7);
RegisterFeedBack(%FF6804, %FF6888, N25, N35, %FF6720, %FF6972, L25, L35, N45,
L15, N55, N65, N10, N9);
RegisterFeedBack(%FF8588, %FF8652, N26, N36, %FF8484, %FF8736, L26, L36, N46,
L16, N56, N66, N12, N11);
RegisterFeedBack(%FF10164, %FF10248, N27, N37, %FF10080, %FF10332, L27, L37, N47,
L17, N57, N67, N14, N13);
RegisterFeedBack(%FF11592, %FF11676, N28, N38, %FF11508, %FF11760, L28, L38, N48,
L18, N58, N68, N16, N15);
RegisterFeedBack(%FF12852, %FF12936, N29, N39, %FF12768, %FF13020, L29, L39, N49,
L19, N59, N69, N18, N17);
RegisterFeedBack(%FF13944, %FF14028, N30, N40, %FF13860, %FF14112, L30, L40, N50,
L20, N60, N70, N20, N19);

ATV750(L1, L11, N41, %SF1008, N51, P23, %FF1008, N71, %SF14364);
ATV750(L2, L12, N42, %SF2268, N52, P22, %FF2268, N72, %SF14367);
ATV750(L3, L13, N43, %SF3696, N53, P21, %FF3696, N73, %SF14370);
ATV750(L4, L14, N44, %SF5292, N54, P20, %FF5292, N74, %SF14373);
ATV750(L5, L15, N45, %SF7056, N55, P19, %FF7056, N75, %SF14376);
ATV750(L6, L16, N46, %SF8820, N56, P18, %FF8820, N76, %SF14379);
ATV750(L7, L17, N47, %SF10416, N57, P17, %FF10416, N77, %SF14382);
ATV750(L8, L18, N48, %SF11844, N58, P16, %FF11844, N78, %SF14385);
ATV750(L9, L19, N49, %SF13104, N59, P15, %FF13104, N79, %SF14388);
ATV750(L10, L20, N50, %SF14196, N60, P14, %FF14196, N80, %SF14391);

%EndModel

%StartModel
%Manufacturer:Atmel
%Type:ATV750
%PartNumber:ATV750-35
%LastNode ? ?
%NumPins: 24
%FDF AND 0 ~P13 P13 ~P11 P11 N19 ~N19 N20 ~N20 ~P14 P14 ~P10 P10 N17 ~N17
     N18 ~N18 ~P15 P15 ~P9 P9 N15 ~N15 N16 ~N16 ~P16 P16 ~P8 P8 N13 ~N13
     N14 ~N14 ~P17 P17 ~P7 P7 N11 ~N11 N12 ~N12 ~P18 P18 ~P6 P6 N9 ~N9
     N10 ~N10 ~P19 P19 ~P5 P5 N7 ~N7 N8 ~N8 ~P20 P20 ~P4 P4 N5 ~N5 N6 ~N6
     ~P21 P21 ~P3 P3 N3 ~N3 N4 ~N4 ~P22 P22 ~P2 P2 N1 ~N1 N2 ~N2 ~P23 P23
     ~P1 P1*

%MACRO LOR8(InFuse:%FF, OrOutput1:%TEXT, OrOutput2:%TEXT);
 LOR(%InFuse,%InFuse+84,%InFuse+168,%InFuse+252,%InFuse+336,%InFuse+420,
     %InFuse+504,%InFuse+588; OrOutput1);
 LOR(%InFuse+672,%InFuse+756,%InFuse+840,%InFuse+924,%InFuse+1008,%InFuse+1092,
     %InFuse+1176,%InFuse+1260; OrOutput2);
%MACEND;

%MACRO LOR7(InFuse:%FF, OrOutput1:%TEXT, OrOutput2:%TEXT);
 LOR(%InFuse,%InFuse+84,%InFuse+168,%InFuse+252,%InFuse+336,%InFuse+420,
     %InFuse+504; OrOutput1);
 LOR(%InFuse+588,%InFuse+672,%InFuse+756,%InFuse+840,%InFuse+924,%InFuse+1008,
     %InFuse+1092; OrOutput2);
%MACEND;

%MACRO LOR6(InFuse:%FF, OrOutput1:%TEXT, OrOutput2:%TEXT);
 LOR(%InFuse,%InFuse+84,%InFuse+168,%InFuse+252,%InFuse+336,%InFuse+420;
     OrOutput1);
 LOR(%InFuse+504,%InFuse+588,%InFuse+672,%InFuse+756,%InFuse+840,%InFuse+924;
     OrOutput2);
%MACEND;

%MACRO LOR5(InFuse:%FF, OrOutput1:%TEXT, OrOutput2:%TEXT);
 LOR(%InFuse,%InFuse+84,%InFuse+168,%InFuse+252,%InFuse+336; OrOutput1);
 LOR(%InFuse+420,%InFuse+504,%InFuse+588,%InFuse+672,%InFuse+756; OrOutput2);
%MACEND;

%MACRO LOR4(InFuse:%FF, OrOutput1:%TEXT, OrOutput2:%TEXT);
 LOR(%InFuse,%InFuse+84,%InFuse+168,%InFuse+252; OrOutput1);
 LOR(%InFuse+336,%InFuse+420,%InFuse+504,%InFuse+588; OrOutput2);
%MACEND;

%MACRO RegisterFeedBack(Reg1Clock:%FF, Reg2Clock:%FF, Clock1:%TEXT,
       Clock2:%TEXT, ARFuse1:%FF, ARFuse2:%FF, Reset1:%TEXT, Reset2:%TEXT,
       OrNode:%TEXT, OrOutput2:%TEXT, TRegNode1:%TEXT, TRegNode2:%TEXT,
       FeedBack1:%TEXT, FeedBack2:%TEXT);

     AND(Reg1Clock; Clock1; 0,0,0,0);
     AND(Reg2Clock; Clock2; 0,0,0,0);
     LNOR(ARFuse1, IPH; Reset1);
     LNOR(ARFuse2, IPH; Reset2);

     DQFFC(OrNode, Clock1, Reset1; TRegNode1; 12,12,18,10,15,15,35,35,35,35,12,12,18,10,15,15,35,35,35,35);
     DQFFC(OrOutput2, Clock2, Reset2; TRegNode2; 12,12,18,10,15,15,35,35,35,35,12,12,18,10,15,15,35,35,35,35);
     BUF(TRegNode1; FeedBack1; 0,0,0,0);
     BUF(TRegNode2; FeedBack2; 0,0,0,0);
%MACEND;

%MACRO ATV750(OrOutput1:%TEXT, OrOutput2:%TEXT, OrNode:%TEXT, EnableFuse:%SF,
       TRegNode1:%TEXT, OutPin:%TEXT, InFuse:%FF, TNode:%TEXT, S0:%SF);
%CASE %S0+2, %S0+1, %S0
   0:
     OR(OrOutput1, OrOutput2, L41; OrNode; 18,18,18,18);
    %IF %EnableFuse..%EnableFuse+83 = 1 %THEN
     INV(TRegNode1; OutPin; 0,0,0,0);
    %ELSE
     ITSB(TRegNode1, %InFuse; OutPin; 35,35,35,35,35,35,35,35);
    %END;
  |1:
     OR(OrOutput1, OrOutput2, L41; OrNode; 18,18,18,18);
    %IF %EnableFuse..%EnableFuse+83 = 1 %THEN
     NOR(OrOutput1, OrOutput2; OutPin; 35,35,35,35);
    %ELSE
     NOR(OrOutput1, OrOutput2; TNode; 35,35,35,35);
     TSB(TNode, %InFuse; OutPin; 35,35,35,35,35,35,35,35);
    %END;
  |2:
    OR(OrOutput1, L41; OrNode; 18,18,18,18);
    %IF %EnableFuse..%EnableFuse+83 = 1 %THEN
     INV(TRegNode1; OutPin; 0,0,0,0);
    %ELSE
     ITSB(TRegNode1, %InFuse; OutPin; 35,35,35,35,35,35,35,35);
    %END;
  |3:
    OR(OrOutput1, L41; OrNode; 18,18,18,18);
    %IF %EnableFuse..%EnableFuse+83 = 1 %THEN
     INV(OrOutput1; OutPin; 35,35,35,35);
    %ELSE
     INV(OrOutput1; TNode; 35,35,35,35);
     TSB(TNode, %InFuse; OutPin; 35,35,35,35,35,35,35,35);
    %END;
  |4:
     OR(OrOutput1, OrOutput2, L41; OrNode; 18,18,18,18);
    %IF %EnableFuse..%EnableFuse+83 = 1 %THEN
     BUF(TRegNode1; OutPin; 0,0,0,0);
    %ELSE
     TSB(TRegNode1, %InFuse; OutPin; 35,35,35,35,35,35,35,35);
    %END;
  |5:
     OR(OrOutput1, OrOutput2, L41; OrNode; 18,18,18,18);
    %IF %EnableFuse..%EnableFuse+83 = 1 %THEN
     OR(OrOutput1, OrOutput2; OutPin; 35,35,35,35);
    %ELSE
     OR(OrOutput1, OrOutput2; TNode; 35,35,35,35);
     TSB(TNode, %InFuse; OutPin; 35,35,35,35,35,35,35,35);
    %END;
  |6:
    OR(OrOutput1, L41; OrNode; 18,18,18,18);
    %IF %EnableFuse..%EnableFuse+83 = 1 %THEN
     BUF(TRegNode1; OutPin; 0,0,0,0);
    %ELSE
     TSB(TRegNode1, %InFuse; OutPin; 35,35,35,35,35,35,35,35);
    %END;
  |7:
    OR(OrOutput1, L41; OrNode; 18,18,18,18);
    %IF %EnableFuse..%EnableFuse+83 = 1 %THEN
     BUF(OrOutput1; OutPin; 35,35,35,35);
    %ELSE
     BUF(OrOutput1; TNode; 35,35,35,35);
     TSB(TNode, %InFuse; OutPin; 35,35,35,35,35,35,35,35);
    %END;
  %END;
%MACEND;

LAND(%FF14280; L41);

LOR4(%FF00,L1, L11);
LOR5(%FF1092,L2, L12);
LOR6(%FF2352,L3, L13);
LOR7(%FF3780,L4, L14);
LOR8(%FF5376,L5, L15);
LOR8(%FF7140,L6, L16);
LOR7(%FF8904,L7, L17);
LOR6(%FF10500,L8, L18);
LOR5(%FF11928,L9, L19);
LOR4(%FF13188,L10, L20);

RegisterFeedBack(%FF756, %FF840, N21, N31, %FF672, %FF924, L21, L31, N41,
L11, N51, N61, N2, N1);
RegisterFeedBack(%FF2016, %FF2100, N22, N32, %FF1932, %FF2184, L22, L32, N42,
L12, N52, N62, N4, N3);
RegisterFeedBack(%FF3444, %FF3528, N23, N33, %FF3380, %FF3812, L23, L33, N43,
L13, N53, N63, N6, N5);
RegisterFeedBack(%FF5040, %FF5124, N24, N34, %FF4956, %FF5208, L24, L34, N44,
L14, N54, N64, N8, N7);
RegisterFeedBack(%FF6804, %FF6888, N25, N35, %FF6720, %FF6972, L25, L35, N45,
L15, N55, N65, N10, N9);
RegisterFeedBack(%FF8588, %FF8652, N26, N36, %FF8484, %FF8736, L26, L36, N46,
L16, N56, N66, N12, N11);
RegisterFeedBack(%FF10164, %FF10248, N27, N37, %FF10080, %FF10332, L27, L37, N47,
L17, N57, N67, N14, N13);
RegisterFeedBack(%FF11592, %FF11676, N28, N38, %FF11508, %FF11760, L28, L38, N48,
L18, N58, N68, N16, N15);
RegisterFeedBack(%FF12852, %FF12936, N29, N39, %FF12768, %FF13020, L29, L39, N49,
L19, N59, N69, N18, N17);
RegisterFeedBack(%FF13944, %FF14028, N30, N40, %FF13860, %FF14112, L30, L40, N50,
L20, N60, N70, N20, N19);

ATV750(L1, L11, N41, %SF1008, N51, P23, %FF1008, N71, %SF14364);
ATV750(L2, L12, N42, %SF2268, N52, P22, %FF2268, N72, %SF14367);
ATV750(L3, L13, N43, %SF3696, N53, P21, %FF3696, N73, %SF14370);
ATV750(L4, L14, N44, %SF5292, N54, P20, %FF5292, N74, %SF14373);
ATV750(L5, L15, N45, %SF7056, N55, P19, %FF7056, N75, %SF14376);
ATV750(L6, L16, N46, %SF8820, N56, P18, %FF8820, N76, %SF14379);
ATV750(L7, L17, N47, %SF10416, N57, P17, %FF10416, N77, %SF14382);
ATV750(L8, L18, N48, %SF11844, N58, P16, %FF11844, N78, %SF14385);
ATV750(L9, L19, N49, %SF13104, N59, P15, %FF13104, N79, %SF14388);
ATV750(L10, L20, N50, %SF14196, N60, P14, %FF14196, N80, %SF14391);

%EndModel

%StartModel
%Manufacturer:Atmel
%Type:ATV750
%PartNumber:ATV750-40
%LastNode ? ?
%NumPins: 24
%FDF AND 0 ~P13 P13 ~P11 P11 N19 ~N19 N20 ~N20 ~P14 P14 ~P10 P10 N17 ~N17
     N18 ~N18 ~P15 P15 ~P9 P9 N15 ~N15 N16 ~N16 ~P16 P16 ~P8 P8 N13 ~N13
     N14 ~N14 ~P17 P17 ~P7 P7 N11 ~N11 N12 ~N12 ~P18 P18 ~P6 P6 N9 ~N9
     N10 ~N10 ~P19 P19 ~P5 P5 N7 ~N7 N8 ~N8 ~P20 P20 ~P4 P4 N5 ~N5 N6 ~N6
     ~P21 P21 ~P3 P3 N3 ~N3 N4 ~N4 ~P22 P22 ~P2 P2 N1 ~N1 N2 ~N2 ~P23 P23
     ~P1 P1*

%MACRO LOR8(InFuse:%FF, OrOutput1:%TEXT, OrOutput2:%TEXT);
 LOR(%InFuse,%InFuse+84,%InFuse+168,%InFuse+252,%InFuse+336,%InFuse+420,
     %InFuse+504,%InFuse+588; OrOutput1);
 LOR(%InFuse+672,%InFuse+756,%InFuse+840,%InFuse+924,%InFuse+1008,%InFuse+1092,
     %InFuse+1176,%InFuse+1260; OrOutput2);
%MACEND;

%MACRO LOR7(InFuse:%FF, OrOutput1:%TEXT, OrOutput2:%TEXT);
 LOR(%InFuse,%InFuse+84,%InFuse+168,%InFuse+252,%InFuse+336,%InFuse+420,
     %InFuse+504; OrOutput1);
 LOR(%InFuse+588,%InFuse+672,%InFuse+756,%InFuse+840,%InFuse+924,%InFuse+1008,
     %InFuse+1092; OrOutput2);
%MACEND;

%MACRO LOR6(InFuse:%FF, OrOutput1:%TEXT, OrOutput2:%TEXT);
 LOR(%InFuse,%InFuse+84,%InFuse+168,%InFuse+252,%InFuse+336,%InFuse+420;
     OrOutput1);
 LOR(%InFuse+504,%InFuse+588,%InFuse+672,%InFuse+756,%InFuse+840,%InFuse+924;
     OrOutput2);
%MACEND;

%MACRO LOR5(InFuse:%FF, OrOutput1:%TEXT, OrOutput2:%TEXT);
 LOR(%InFuse,%InFuse+84,%InFuse+168,%InFuse+252,%InFuse+336; OrOutput1);
 LOR(%InFuse+420,%InFuse+504,%InFuse+588,%InFuse+672,%InFuse+756; OrOutput2);
%MACEND;

%MACRO LOR4(InFuse:%FF, OrOutput1:%TEXT, OrOutput2:%TEXT);
 LOR(%InFuse,%InFuse+84,%InFuse+168,%InFuse+252; OrOutput1);
 LOR(%InFuse+336,%InFuse+420,%InFuse+504,%InFuse+588; OrOutput2);
%MACEND;

%MACRO RegisterFeedBack(Reg1Clock:%FF, Reg2Clock:%FF, Clock1:%TEXT,
       Clock2:%TEXT, ARFuse1:%FF, ARFuse2:%FF, Reset1:%TEXT, Reset2:%TEXT,
       OrNode:%TEXT, OrOutput2:%TEXT, TRegNode1:%TEXT, TRegNode2:%TEXT,
       FeedBack1:%TEXT, FeedBack2:%TEXT);

     AND(Reg1Clock; Clock1; 0,0,0,0);
     AND(Reg2Clock; Clock2; 0,0,0,0);
     LNOR(ARFuse1, IPH; Reset1);
     LNOR(ARFuse2, IPH; Reset2);

     DQFFC(OrNode, Clock1, Reset1; TRegNode1; 15,15,20,15,17,17,40,40,40,40,15,15,20,15,17,17,40,40,40,40);
     DQFFC(OrOutput2, Clock2, Reset2; TRegNode2; 15,15,20,15,17,17,40,40,40,40,15,15,20,15,17,17,40,40,40,40);
     BUF(TRegNode1; FeedBack1; 0,0,0,0);
     BUF(TRegNode2; FeedBack2; 0,0,0,0);
%MACEND;

%MACRO ATV750(OrOutput1:%TEXT, OrOutput2:%TEXT, OrNode:%TEXT, EnableFuse:%SF,
       TRegNode1:%TEXT, OutPin:%TEXT, InFuse:%FF, TNode:%TEXT, S0:%SF);
%CASE %S0+2, %S0+1, %S0
   0:
     OR(OrOutput1, OrOutput2, L41; OrNode; 20,20,20,20);
    %IF %EnableFuse..%EnableFuse+83 = 1 %THEN
     INV(TRegNode1; OutPin; 0,0,0,0);
    %ELSE
     ITSB(TRegNode1, %InFuse; OutPin; 40,40,40,40,40,40,40,40);
    %END;
  |1:
     OR(OrOutput1, OrOutput2, L41; OrNode; 20,20,20,20);
    %IF %EnableFuse..%EnableFuse+83 = 1 %THEN
     NOR(OrOutput1, OrOutput2; OutPin; 40,40,40,40);
    %ELSE
     NOR(OrOutput1, OrOutput2; TNode; 40,40,40,40);
     TSB(TNode, %InFuse; OutPin; 40,40,40,40,40,40,40,40);
    %END;
  |2:
    OR(OrOutput1, L41; OrNode; 20,20,20,20);
    %IF %EnableFuse..%EnableFuse+83 = 1 %THEN
     INV(TRegNode1; OutPin; 0,0,0,0);
    %ELSE
     ITSB(TRegNode1, %InFuse; OutPin; 40,40,40,40,40,40,40,40);
    %END;
  |3:
    OR(OrOutput1, L41; OrNode; 20,20,20,20);
    %IF %EnableFuse..%EnableFuse+83 = 1 %THEN
     INV(OrOutput1; OutPin; 40,40,40,40);
    %ELSE
     INV(OrOutput1; TNode; 40,40,40,40);
     TSB(TNode, %InFuse; OutPin; 40,40,40,40,40,40,40,40);
    %END;
  |4:
     OR(OrOutput1, OrOutput2, L41; OrNode; 20,20,20,20);
    %IF %EnableFuse..%EnableFuse+83 = 1 %THEN
     BUF(TRegNode1; OutPin; 0,0,0,0);
    %ELSE
     TSB(TRegNode1, %InFuse; OutPin; 40,40,40,40,40,40,40,40);
    %END;
  |5:
     OR(OrOutput1, OrOutput2, L41; OrNode; 20,20,20,20);
    %IF %EnableFuse..%EnableFuse+83 = 1 %THEN
     OR(OrOutput1, OrOutput2; OutPin; 40,40,40,40);
    %ELSE
     OR(OrOutput1, OrOutput2; TNode; 40,40,40,40);
     TSB(TNode, %InFuse; OutPin; 40,40,40,40,40,40,40,40);
    %END;
  |6:
    OR(OrOutput1, L41; OrNode; 20,20,20,20);
    %IF %EnableFuse..%EnableFuse+83 = 1 %THEN
     BUF(TRegNode1; OutPin; 0,0,0,0);
    %ELSE
     TSB(TRegNode1, %InFuse; OutPin; 40,40,40,40,40,40,40,40);
    %END;
  |7:
    OR(OrOutput1, L41; OrNode; 20,20,20,20);
    %IF %EnableFuse..%EnableFuse+83 = 1 %THEN
     BUF(OrOutput1; OutPin; 40,40,40,40);
    %ELSE
     BUF(OrOutput1; TNode; 40,40,40,40);
     TSB(TNode, %InFuse; OutPin; 40,40,40,40,40,40,40,40);
    %END;
  %END;
%MACEND;

LAND(%FF14280; L41);

LOR4(%FF00,L1, L11);
LOR5(%FF1092,L2, L12);
LOR6(%FF2352,L3, L13);
LOR7(%FF3780,L4, L14);
LOR8(%FF5376,L5, L15);
LOR8(%FF7140,L6, L16);
LOR7(%FF8904,L7, L17);
LOR6(%FF10500,L8, L18);
LOR5(%FF11928,L9, L19);
LOR4(%FF13188,L10, L20);

RegisterFeedBack(%FF756, %FF840, N21, N31, %FF672, %FF924, L21, L31, N41,
L11, N51, N61, N2, N1);
RegisterFeedBack(%FF2016, %FF2100, N22, N32, %FF1932, %FF2184, L22, L32, N42,
L12, N52, N62, N4, N3);
RegisterFeedBack(%FF3444, %FF3528, N23, N33, %FF3380, %FF3812, L23, L33, N43,
L13, N53, N63, N6, N5);
RegisterFeedBack(%FF5040, %FF5124, N24, N34, %FF4956, %FF5208, L24, L34, N44,
L14, N54, N64, N8, N7);
RegisterFeedBack(%FF6804, %FF6888, N25, N35, %FF6720, %FF6972, L25, L35, N45,
L15, N55, N65, N10, N9);
RegisterFeedBack(%FF8588, %FF8652, N26, N36, %FF8484, %FF8736, L26, L36, N46,
L16, N56, N66, N12, N11);
RegisterFeedBack(%FF10164, %FF10248, N27, N37, %FF10080, %FF10332, L27, L37, N47,
L17, N57, N67, N14, N13);
RegisterFeedBack(%FF11592, %FF11676, N28, N38, %FF11508, %FF11760, L28, L38, N48,
L18, N58, N68, N16, N15);
RegisterFeedBack(%FF12852, %FF12936, N29, N39, %FF12768, %FF13020, L29, L39, N49,
L19, N59, N69, N18, N17);
RegisterFeedBack(%FF13944, %FF14028, N30, N40, %FF13860, %FF14112, L30, L40, N50,
L20, N60, N70, N20, N19);

ATV750(L1, L11, N41, %SF1008, N51, P23, %FF1008, N71, %SF14364);
ATV750(L2, L12, N42, %SF2268, N52, P22, %FF2268, N72, %SF14367);
ATV750(L3, L13, N43, %SF3696, N53, P21, %FF3696, N73, %SF14370);
ATV750(L4, L14, N44, %SF5292, N54, P20, %FF5292, N74, %SF14373);
ATV750(L5, L15, N45, %SF7056, N55, P19, %FF7056, N75, %SF14376);
ATV750(L6, L16, N46, %SF8820, N56, P18, %FF8820, N76, %SF14379);
ATV750(L7, L17, N47, %SF10416, N57, P17, %FF10416, N77, %SF14382);
ATV750(L8, L18, N48, %SF11844, N58, P16, %FF11844, N78, %SF14385);
ATV750(L9, L19, N49, %SF13104, N59, P15, %FF13104, N79, %SF14388);
ATV750(L10, L20, N50, %SF14196, N60, P14, %FF14196, N80, %SF14391);

%EndModel
