(***************************************************************************)
(*                                                                         *)
(*                         Copyright (C) 1987-1990                         *)
(*                      by Gogesch Micro Systems, INC.                     *)
(*                                                                         *)
(*                           All rights reserved.                          *)
(*                                                                         *)
(***************************************************************************)


;DELAYS FOR THE FOLLOWING WERE TAKEN FROM THE 1988 AMD PAL DEVICE DATA BOOK.

%StartModel
%Manufacturer:AMD
%Type:10H8
%PartNumber:PAL10H8
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P4 ~P4 P5 ~P5 P6 ~P6 P7 ~P7 P8 ~P8 P9 ~P9
     P11 ~P11 *

OR(%FF00, %FF20; P19; 25,25,35,35);
OR(%FF40, %FF60; P18; 25,25,35,35);
OR(%FF80, %FF100; P17; 25,25,35,35);
OR(%FF120, %FF140; P16; 25,25,35,35);
OR(%FF160, %FF180; P15; 25,25,35,35);
OR(%FF200, %FF220; P14; 25,25,35,35);
OR(%FF240, %FF260; P13; 25,25,35,35);
OR(%FF280, %FF300; P12; 25,25,35,35);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:10L8
%PartNumber:PAL10L8
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P4 ~P4 P5 ~P5 P6 ~P6 P7 ~P7 P8 ~P8 P9 ~P9
     P11 ~P11 *

NOR(%FF00, %FF20; P19; 25,25,35,35);
NOR(%FF40, %FF60; P18; 25,25,35,35);
NOR(%FF80, %FF100; P17; 25,25,35,35);
NOR(%FF120, %FF140; P16; 25,25,35,35);
NOR(%FF160, %FF180; P15; 25,25,35,35);
NOR(%FF200, %FF220; P14; 25,25,35,35);
NOR(%FF240, %FF260; P13; 25,25,35,35);
NOR(%FF280, %FF300; P12; 25,25,35,35);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:12H6
%PartNumber:PAL12H6
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P19 ~P19 P4 ~P4 P5 ~P5 P6 ~P6 P7 ~P7
     P8 ~P8 P12 ~P12 P9 ~P9 P11 ~P11 *

OR(%FF00, %FF24, %FF48, %FF72; P18; 25,25,35,35);
OR(%FF96, %FF120; P17; 25,25,35,35);
OR(%FF144, %FF168; P16; 25,25,35,35);
OR(%FF192, %FF216; P15; 25,25,35,35);
OR(%FF240, %FF264; P14; 25,25,35,35);
OR(%FF288, %FF312, %FF336, %FF360; P13; 25,25,35,35);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:12L10
%PartNumber:PAL12L10
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P4 ~P4 P5 ~P5 P6 ~P6 P7 ~P7 P8 ~P8 P9 ~P9
     P10 ~P10 P11 ~P11 P13 ~P13 *

NOR(%FF00, %FF24; P23; 25,25,40,40);
NOR(%FF48, %FF72; P22; 25,25,40,40);
NOR(%FF96, %FF120; P21; 25,25,40,40);
NOR(%FF144, %FF168; P20; 25,25,40,40);
NOR(%FF192, %FF216; P19; 25,25,40,40);
NOR(%FF240, %FF264; P18; 25,25,40,40);
NOR(%FF288, %FF312; P17; 25,25,40,40);
NOR(%FF336, %FF360; P16; 25,25,40,40);
NOR(%FF384, %FF408; P15; 25,25,40,40);
NOR(%FF432, %FF456; P14; 25,25,40,40);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:12L6
%PartNumber:PAL12L6
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P19 ~P19 P4 ~P4 P5 ~P5 P6 ~P6 P7 ~P7
     P8 ~P8 P12 ~P12 P9 ~P9 P11 ~P11 *

NOR(%FF00, %FF24, %FF48, %FF72; P18; 25,25,35,35);
NOR(%FF96, %FF120; P17; 25,25,35,35);
NOR(%FF144, %FF168; P16; 25,25,35,35);
NOR(%FF192, %FF216; P15; 25,25,35,35);
NOR(%FF240, %FF264; P14; 25,25,35,35);
NOR(%FF288, %FF312, %FF336, %FF360; P13; 25,25,35,35);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:14H4
%PartNumber:PAL14H4
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P19 ~P19 P4 ~P4 P18 ~P18 P5 ~P5 P6 ~P6
     P7 ~P7 P13 ~P13 P8 ~P8 P12 ~P12 P9 ~P9 P11 ~P11 *

OR(%FF00, %FF28, %FF56, %FF84; P17; 25,25,35,35);
OR(%FF112, %FF140, %FF168, %FF196; P16; 25,25,35,35);
OR(%FF224, %FF252, %FF280, %FF308; P15; 25,25,35,35);
OR(%FF336, %FF364, %FF392, %FF420; P14; 25,25,35,35);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:14L4
%PartNumber:PAL14L4
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P19 ~P19 P4 ~P4 P18 ~P18 P5 ~P5 P6 ~P6
     P7 ~P7 P13 ~P13 P8 ~P8 P12 ~P12 P9 ~P9 P11 ~P11 *

NOR(%FF00, %FF28, %FF56, %FF84; P17; 25,25,35,35);
NOR(%FF112, %FF140, %FF168, %FF196; P16; 25,25,35,35);
NOR(%FF224, %FF252, %FF280, %FF308; P15; 25,25,35,35);
NOR(%FF336, %FF364, %FF392, %FF420; P14; 25,25,35,35);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:14L8
%PartNumber:PAL14L8
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P23 ~P23 P4 ~P4 P5 ~P5 P6 ~P6 P7 ~P7
     P8 ~P8 P9 ~P9 P10 ~P10 P14 ~P14 P11 ~P11 P13 ~P13 *

NOR(%FF00, %FF28, %FF56, %FF84; P22; 25,25,40,40);
NOR(%FF112, %FF140; P21; 25,25,40,40);
NOR(%FF168, %FF196; P20; 25,25,40,40);
NOR(%FF224, %FF252; P19; 25,25,40,40);
NOR(%FF280, %FF308; P18; 25,25,40,40);
NOR(%FF336, %FF364; P17; 25,25,40,40);
NOR(%FF392, %FF420; P16; 25,25,40,40);
NOR(%FF448, %FF476, %FF504, %FF532; P15; 25,25,40,40);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16C1
%PartNumber:PAL16C1
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P19 ~P19 P4 ~P4 P18 ~P18 P5 ~P5 P17 ~P17
     P6 ~P6 P14 ~P14 P7 ~P7 P13 ~P13 P8 ~P8 P12 ~P12 P9 ~P9 P11 ~P11 *

LOR(%FF00, %FF32, %FF64, %FF96, %FF128, %FF160, %FF192, %FF224, %FF256,
   %FF288, %FF320, %FF352, %FF384, %FF416, %FF448, %FF480; L1);
BUF(L1; P16; 25,25,40,40);
INV(L1; P15; 25,25,40,40);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16H2
%PartNumber:PAL16H2
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P19 ~P19 P4 ~P4 P18 ~P18 P5 ~P5 P17 ~P17
     P6 ~P6 P14 ~P14 P7 ~P7 P13 ~P13 P8 ~P8 P12 ~P12 P9 ~P9 P11 ~P11 *

OR(%FF00, %FF32, %FF64, %FF96, %FF128, %FF160, %FF192, %FF224; P16; 25,25,35,35);
OR(%FF256, %FF288, %FF320, %FF352, %FF384, %FF416, %FF448, %FF480; P15; 25,25,35,35);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16L2
%PartNumber:PAL16L2
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P19 ~P19 P4 ~P4 P18 ~P18 P5 ~P5 P17 ~P17
     P6 ~P6 P14 ~P14 P7 ~P7 P13 ~P13 P8 ~P8 P12 ~P12 P9 ~P9 P11 ~P11 *

NOR(%FF00, %FF32, %FF64, %FF96, %FF128, %FF160, %FF192, %FF224; P16; 25,25,35,35);
NOR(%FF256, %FF288, %FF320, %FF352, %FF384, %FF416, %FF448, %FF480; P15; 25,25,35,35);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16L6
%PartNumber:PAL16L6
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P23 ~P23 P4 ~P4 P22 ~P22 P5 ~P5 P6 ~P6
     P7 ~P7 P8 ~P8 P9 ~P9 P15 ~P15 P10 ~P10 P14 ~P14 P11 ~P11 P13 ~P13 *

NOR(%FF00, %FF32, %FF64, %FF96; P21; 25,25,40,40);
NOR(%FF128, %FF160, %FF192, %FF224; P20; 25,25,40,40);
NOR(%FF256, %FF288; P19; 25,25,40,40);
NOR(%FF320, %FF352; P18; 25,25,40,40);
NOR(%FF384, %FF416, %FF448, %FF480; P17; 25,25,40,40);
NOR(%FF512, %FF544, %FF576, %FF608; P16; 25,25,40,40);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16L8
%PartNumber:PAL16L8A
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P18 ~P18 P4 ~P4 P17 ~P17 P5 ~P5 P16 ~P16
     P6 ~P6 P15 ~P15 P7 ~P7 P14 ~P14 P8 ~P8 P13 ~P13 P9 ~P9 P11 ~P11 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 15,15,25,25);
 %ELSE
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 15,15,25,25);
  TSB(TNode, %InFuse; OutPin; 10,10,13,13,25,25,25,25);
 %END;
%MACEND;

NOR7ENABLE(%SF00, %FF00, P19, N1);
NOR7ENABLE(%SF256, %FF256, P18, N2);
NOR7ENABLE(%SF512, %FF512, P17, N3);
NOR7ENABLE(%SF768, %FF768, P16, N4);
NOR7ENABLE(%SF1024, %FF1024, P15, N5);
NOR7ENABLE(%SF1280, %FF1280, P14, N6);
NOR7ENABLE(%SF1536, %FF1536, P13, N7);
NOR7ENABLE(%SF1792, %FF1792, P12, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16L8
%PartNumber:PAL16L8A-2
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P18 ~P18 P4 ~P4 P17 ~P17 P5 ~P5 P16 ~P16
     P6 ~P6 P15 ~P15 P7 ~P7 P14 ~P14 P8 ~P8 P13 ~P13 P9 ~P9 P11 ~P11 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 25,25,35,35);
 %ELSE
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 25,25,35,35);
  TSB(TNode, %InFuse; OutPin; 25,25,25,25,35,35,35,35);
 %END;
%MACEND;

NOR7ENABLE(%SF00, %FF00, P19, N1);
NOR7ENABLE(%SF256, %FF256, P18, N2);
NOR7ENABLE(%SF512, %FF512, P17, N3);
NOR7ENABLE(%SF768, %FF768, P16, N4);
NOR7ENABLE(%SF1024, %FF1024, P15, N5);
NOR7ENABLE(%SF1280, %FF1280, P14, N6);
NOR7ENABLE(%SF1536, %FF1536, P13, N7);
NOR7ENABLE(%SF1792, %FF1792, P12, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16L8
%PartNumber:PAL16L8A-4
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P18 ~P18 P4 ~P4 P17 ~P17 P5 ~P5 P16 ~P16
     P6 ~P6 P15 ~P15 P7 ~P7 P14 ~P14 P8 ~P8 P13 ~P13 P9 ~P9 P11 ~P11 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 35,35,55,55);
 %ELSE
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 35,35,55,55);
  TSB(TNode, %InFuse; OutPin; 30,30,30,30,50,50,50,50);
 %END;
%MACEND;

NOR7ENABLE(%SF00, %FF00, P19, N1);
NOR7ENABLE(%SF256, %FF256, P18, N2);
NOR7ENABLE(%SF512, %FF512, P17, N3);
NOR7ENABLE(%SF768, %FF768, P16, N4);
NOR7ENABLE(%SF1024, %FF1024, P15, N5);
NOR7ENABLE(%SF1280, %FF1280, P14, N6);
NOR7ENABLE(%SF1536, %FF1536, P13, N7);
NOR7ENABLE(%SF1792, %FF1792, P12, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16L8
%PartNumber:PAL16L8B
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P18 ~P18 P4 ~P4 P17 ~P17 P5 ~P5 P16 ~P16
     P6 ~P6 P15 ~P15 P7 ~P7 P14 ~P14 P8 ~P8 P13 ~P13 P9 ~P9 P11 ~P11 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 12,12,15,15);
 %ELSE
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 12,12,15,15);
  TSB(TNode, %InFuse; OutPin; 12,12,12,12,22,22,15,15);
 %END;
%MACEND;

NOR7ENABLE(%SF00, %FF00, P19, N1);
NOR7ENABLE(%SF256, %FF256, P18, N2);
NOR7ENABLE(%SF512, %FF512, P17, N3);
NOR7ENABLE(%SF768, %FF768, P16, N4);
NOR7ENABLE(%SF1024, %FF1024, P15, N5);
NOR7ENABLE(%SF1280, %FF1280, P14, N6);
NOR7ENABLE(%SF1536, %FF1536, P13, N7);
NOR7ENABLE(%SF1792, %FF1792, P12, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16L8
%PartNumber:PAL16L8B-2
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P18 ~P18 P4 ~P4 P17 ~P17 P5 ~P5 P16 ~P16
     P6 ~P6 P15 ~P15 P7 ~P7 P14 ~P14 P8 ~P8 P13 ~P13 P9 ~P9 P11 ~P11 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 17,17,25,25);
 %ELSE
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 17,17,25,25);
  TSB(TNode, %InFuse; OutPin; 10,10,13,13,25,25,25,25);
 %END;
%MACEND;

NOR7ENABLE(%SF00, %FF00, P19, N1);
NOR7ENABLE(%SF256, %FF256, P18, N2);
NOR7ENABLE(%SF512, %FF512, P17, N3);
NOR7ENABLE(%SF768, %FF768, P16, N4);
NOR7ENABLE(%SF1024, %FF1024, P15, N5);
NOR7ENABLE(%SF1280, %FF1280, P14, N6);
NOR7ENABLE(%SF1536, %FF1536, P13, N7);
NOR7ENABLE(%SF1792, %FF1792, P12, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16L8
%PartNumber:PAL16L8B-4
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P18 ~P18 P4 ~P4 P17 ~P17 P5 ~P5 P16 ~P16
     P6 ~P6 P15 ~P15 P7 ~P7 P14 ~P14 P8 ~P8 P13 ~P13 P9 ~P9 P11 ~P11 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 25,25,35,35);
 %ELSE
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 25,25,35,35);
  TSB(TNode, %InFuse; OutPin; 25,25,25,25,35,35,35,35);
 %END;
%MACEND;

NOR7ENABLE(%SF00, %FF00, P19, N1);
NOR7ENABLE(%SF256, %FF256, P18, N2);
NOR7ENABLE(%SF512, %FF512, P17, N3);
NOR7ENABLE(%SF768, %FF768, P16, N4);
NOR7ENABLE(%SF1024, %FF1024, P15, N5);
NOR7ENABLE(%SF1280, %FF1280, P14, N6);
NOR7ENABLE(%SF1536, %FF1536, P13, N7);
NOR7ENABLE(%SF1792, %FF1792, P12, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16L8
%PartNumber:PAL16L8D
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P18 ~P18 P4 ~P4 P17 ~P17 P5 ~P5 P16 ~P16
     P6 ~P6 P15 ~P15 P7 ~P7 P14 ~P14 P8 ~P8 P13 ~P13 P9 ~P9 P11 ~P11 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 8,8,10,10);
 %ELSE
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 8,8,10,10);
  TSB(TNode, %InFuse; OutPin; 8,8,8,8,10,10,10,10);
 %END;
%MACEND;

NOR7ENABLE(%SF00, %FF00, P19, N1);
NOR7ENABLE(%SF256, %FF256, P18, N2);
NOR7ENABLE(%SF512, %FF512, P17, N3);
NOR7ENABLE(%SF768, %FF768, P16, N4);
NOR7ENABLE(%SF1024, %FF1024, P15, N5);
NOR7ENABLE(%SF1280, %FF1280, P14, N6);
NOR7ENABLE(%SF1536, %FF1536, P13, N7);
NOR7ENABLE(%SF1792, %FF1792, P12, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16L8
%PartNumber:PAL16L8Q-25
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P18 ~P18 P4 ~P4 P17 ~P17 P5 ~P5 P16 ~P16
     P6 ~P6 P15 ~P15 P7 ~P7 P14 ~P14 P8 ~P8 P13 ~P13 P9 ~P9 P11 ~P11 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 20,20,25,25);
 %ELSE
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 20,20,25,25);
  TSB(TNode, %InFuse; OutPin; 20,20,20,20,25,25,25,25);
 %END;
%MACEND;

NOR7ENABLE(%SF00, %FF00, P19, N1);
NOR7ENABLE(%SF256, %FF256, P18, N2);
NOR7ENABLE(%SF512, %FF512, P17, N3);
NOR7ENABLE(%SF768, %FF768, P16, N4);
NOR7ENABLE(%SF1024, %FF1024, P15, N5);
NOR7ENABLE(%SF1280, %FF1280, P14, N6);
NOR7ENABLE(%SF1536, %FF1536, P13, N7);
NOR7ENABLE(%SF1792, %FF1792, P12, N8);
%EndModel

;Delays are given for device with polarity fuse programmed.
%StartModel
%Manufacturer:AMD
%Type:16P8
%PartNumber:PAL16P8A
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P18 ~P18 P4 ~P4 P17 ~P17 P5 ~P5 P16 ~P16
     P6 ~P6 P15 ~P15 P7 ~P7 P14 ~P14 P8 ~P8 P13 ~P13 P9 ~P9 P11 ~P11 *

%MACRO POR7ENABLE(EnableFuse:%SF, InFuse:%FF, XorFuse:%SF, OutPin:%TEXT,
                 TNode:%TEXT);
%IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  %IF %XorFuse=0 %THEN
   NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
      %InFuse+192, %InFuse+224; OutPin; 20,20,30,30);
  %ELSE
   OR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
      %InFuse+192, %InFuse+224; OutPin; 20,20,30,30);
  %END;
%ELSE
  %IF %XorFuse=0 %THEN
   NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
      %InFuse+192, %InFuse+224; TNode; 20,20,30,30);
  %ELSE
   OR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
      %InFuse+192, %InFuse+224; TNode; 20,20,30,30);
  %END;
  TSB(TNode, %InFuse; OutPin; 10,10,13,13,25,25,25,25);
 %END;
%MACEND;

POR7ENABLE(%SF00, %FF00, %SF2048, P19, N1);
POR7ENABLE(%SF256, %FF256, %SF2049, P18, N2);
POR7ENABLE(%SF512, %FF512, %SF2050, P17, N3);
POR7ENABLE(%SF768, %FF768, %SF2051, P16, N4);
POR7ENABLE(%SF1024, %FF1024, %SF2052, P15, N5);
POR7ENABLE(%SF1280, %FF1280, %SF2053, P14, N6);
POR7ENABLE(%SF1536, %FF1536, %SF2054, P13, N7);
POR7ENABLE(%SF1792, %FF1792, %SF2055, P12, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16R4
%PartNumber:PAL16R4A
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P19 ~P19 P3 ~P3 P18 ~P18 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 P13 ~P13 P9 ~P9 P12 ~P12 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 15,15,25,25);
 %ELSE
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 15,15,25,25);
  TSB(TNode, %InFuse; OutPin; 10,10,13,13,25,25,25,25);
 %END;
%MACEND;

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 DQFF(TLNode,P1;NodeInp;10,10,15,0,10,10,15,15,25,0,15,15);
 TSB(NodeInp,L1;OutPin;10,10,11,11,20,20,20,20);
%MACEND;

LINV(P11;L1);
NOR7ENABLE(%SF00, %FF00, P19, N1);
NOR7ENABLE(%SF256, %FF256, P18, N2);
NOR8DFF(%FF512, N3, L2, P17);
NOR8DFF(%FF768, N4, L3, P16);
NOR8DFF(%FF1024, N5, L4, P15);
NOR8DFF(%FF1280, N6, L5, P14);
NOR7ENABLE(%SF1536, %FF1536, P13, N7);
NOR7ENABLE(%SF1792, %FF1792, P12, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16R4
%PartNumber:PAL16R4A-2
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P19 ~P19 P3 ~P3 P18 ~P18 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 P13 ~P13 P9 ~P9 P12 ~P12 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 25,25,35,35);
 %ELSE
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 25,25,35,35);
  TSB(TNode, %InFuse; OutPin; 25,25,25,25,35,35,35,35);
 %END;
%MACEND;

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 DQFF(TLNode,P1;NodeInp;15,15,25,0,10,10,25,25,35,0,25,25);
 TSB(NodeInp,L1;OutPin;15,15,15,15,25,25,25,25);
%MACEND;

LINV(P11;L1);
NOR7ENABLE(%SF00, %FF00, P19, N1);
NOR7ENABLE(%SF256, %FF256, P18, N2);
NOR8DFF(%FF512, N3, L2, P17);
NOR8DFF(%FF768, N4, L3, P16);
NOR8DFF(%FF1024, N5, L4, P15);
NOR8DFF(%FF1280, N6, L5, P14);
NOR7ENABLE(%SF1536, %FF1536, P13, N7);
NOR7ENABLE(%SF1792, %FF1792, P12, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16R4
%PartNumber:PAL16R4A-4
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P19 ~P19 P3 ~P3 P18 ~P18 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 P13 ~P13 P9 ~P9 P12 ~P12 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 35,35,55,55);
 %ELSE
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 35,35,55,55);
  TSB(TNode, %InFuse; OutPin; 30,30,30,30,50,50,50,50);
 %END;
%MACEND;

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 DQFF(TLNode,P1;NodeInp;20,20,45,0,20,20,35,35,60,0,30,30);
 TSB(NodeInp,L1;OutPin;15,15,15,15,30,30,30,30);
%MACEND;

LINV(P11;L1);
NOR7ENABLE(%SF00, %FF00, P19, N1);
NOR7ENABLE(%SF256, %FF256, P18, N2);
NOR8DFF(%FF512, N3, L2, P17);
NOR8DFF(%FF768, N4, L3, P16);
NOR8DFF(%FF1024, N5, L4, P15);
NOR8DFF(%FF1280, N6, L5, P14);
NOR7ENABLE(%SF1536, %FF1536, P13, N7);
NOR7ENABLE(%SF1792, %FF1792, P12, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16R4
%PartNumber:PAL16R4B
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P19 ~P19 P3 ~P3 P18 ~P18 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 P13 ~P13 P9 ~P9 P12 ~P12 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 12,12,15,15);
 %ELSE
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 12,12,15,15);
  TSB(TNode, %InFuse; OutPin; 12,12,12,12,22,22,15,15);
 %END;
%MACEND;

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 DQFF(TLNode,P1;NodeInp;8,8,10,0,5,6,12,12,15,0,10,10);
 TSB(NodeInp,L1;OutPin;10,10,10,10,15,15,15,15);
%MACEND;

LINV(P11;L1);
NOR7ENABLE(%SF00, %FF00, P19, N1);
NOR7ENABLE(%SF256, %FF256, P18, N2);
NOR8DFF(%FF512, N3, L2, P17);
NOR8DFF(%FF768, N4, L3, P16);
NOR8DFF(%FF1024, N5, L4, P15);
NOR8DFF(%FF1280, N6, L5, P14);
NOR7ENABLE(%SF1536, %FF1536, P13, N7);
NOR7ENABLE(%SF1792, %FF1792, P12, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16R4
%PartNumber:PAL16R4B-2
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P19 ~P19 P3 ~P3 P18 ~P18 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 P13 ~P13 P9 ~P9 P12 ~P12 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 17,17,25,25);
 %ELSE
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 17,17,25,25);
  TSB(TNode, %InFuse; OutPin; 10,10,13,13,25,25,25,25);
 %END;
%MACEND;

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 DQFF(TLNode,P1;NodeInp;10,10,15,0,10,10,15,15,25,0,15,15);
 TSB(NodeInp,L1;OutPin;10,10,11,11,20,20,20,20);
%MACEND;

LINV(P11;L1);
NOR7ENABLE(%SF00, %FF00, P19, N1);
NOR7ENABLE(%SF256, %FF256, P18, N2);
NOR8DFF(%FF512, N3, L2, P17);
NOR8DFF(%FF768, N4, L3, P16);
NOR8DFF(%FF1024, N5, L4, P15);
NOR8DFF(%FF1280, N6, L5, P14);
NOR7ENABLE(%SF1536, %FF1536, P13, N7);
NOR7ENABLE(%SF1792, %FF1792, P12, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16R4
%PartNumber:PAL16R4B-4
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P19 ~P19 P3 ~P3 P18 ~P18 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 P13 ~P13 P9 ~P9 P12 ~P12 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 25,25,35,35);
 %ELSE
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 25,25,35,35);
  TSB(TNode, %InFuse; OutPin; 25,25,25,25,35,35,35,35);
 %END;
%MACEND;

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 DQFF(TLNode,P1;NodeInp;15,15,25,0,10,10,25,25,35,0,25,25);
 TSB(NodeInp,L1;OutPin;15,15,15,15,25,25,25,25);
%MACEND;

LINV(P11;L1);
NOR7ENABLE(%SF00, %FF00, P19, N1);
NOR7ENABLE(%SF256, %FF256, P18, N2);
NOR8DFF(%FF512, N3, L2, P17);
NOR8DFF(%FF768, N4, L3, P16);
NOR8DFF(%FF1024, N5, L4, P15);
NOR8DFF(%FF1280, N6, L5, P14);
NOR7ENABLE(%SF1536, %FF1536, P13, N7);
NOR7ENABLE(%SF1792, %FF1792, P12, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16R4
%PartNumber:PAL16R4D
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P19 ~P19 P3 ~P3 P18 ~P18 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 P13 ~P13 P9 ~P9 P12 ~P12 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 8,8,10,10);
 %ELSE
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 8,8,10,10);
  TSB(TNode, %InFuse; OutPin; 8,8,8,8,10,10,10,10);
 %END;
%MACEND;

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 DQFF(TLNode,P1;NodeInp;6,6,8,0,5,6,7,7,10,0,8,8);
 TSB(NodeInp,L1;OutPin;8,8,8,8,10,10,10,10);
%MACEND;

LINV(P11;L1);
NOR7ENABLE(%SF00, %FF00, P19, N1);
NOR7ENABLE(%SF256, %FF256, P18, N2);
NOR8DFF(%FF512, N3, L2, P17);
NOR8DFF(%FF768, N4, L3, P16);
NOR8DFF(%FF1024, N5, L4, P15);
NOR8DFF(%FF1280, N6, L5, P14);
NOR7ENABLE(%SF1536, %FF1536, P13, N7);
NOR7ENABLE(%SF1792, %FF1792, P12, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16R4
%PartNumber:PAL16R4Q-25
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P19 ~P19 P3 ~P3 P18 ~P18 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 P13 ~P13 P9 ~P9 P12 ~P12 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 20,20,25,25);
 %ELSE
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 20,20,25,25);
  TSB(TNode, %InFuse; OutPin; 20,20,20,20,25,25,25,25);
 %END;
%MACEND;

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 DQFF(TLNode,P1;NodeInp;10,10,15,0,10,10,15,15,20,0,15,15);
 TSB(NodeInp,L1;OutPin;15,15,15,15,20,20,20,20);
%MACEND;

LINV(P11;L1);
NOR7ENABLE(%SF00, %FF00, P19, N1);
NOR7ENABLE(%SF256, %FF256, P18, N2);
NOR8DFF(%FF512, N3, L2, P17);
NOR8DFF(%FF768, N4, L3, P16);
NOR8DFF(%FF1024, N5, L4, P15);
NOR8DFF(%FF1280, N6, L5, P14);
NOR7ENABLE(%SF1536, %FF1536, P13, N7);
NOR7ENABLE(%SF1792, %FF1792, P12, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16R6
%PartNumber:PAL16R6A
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P19 ~P19 P3 ~P3 N2 ~N2 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 N7 ~N7 P9 ~P9 P12 ~P12 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 15,15,25,25);
 %ELSE
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 15,15,25,25);
  TSB(TNode, %InFuse; OutPin; 10,10,13,13,25,25,25,25);
 %END;
%MACEND;

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 DQFF(TLNode,P1;NodeInp;10,10,15,0,10,10,15,15,25,0,15,15);
 TSB(NodeInp,L1;OutPin;10,10,11,11,20,20,20,20);
%MACEND;

LINV(P11;L1);
NOR7ENABLE(%SF00, %FF00, P19, N1);
NOR8DFF(%FF256, N2, L2, P18);
NOR8DFF(%FF512, N3, L3, P17);
NOR8DFF(%FF768, N4, L4, P16);
NOR8DFF(%FF1024, N5, L5, P15);
NOR8DFF(%FF1280, N6, L6, P14);
NOR8DFF(%FF1536, N7, L7, P13);
NOR7ENABLE(%SF1792, %FF1792, P12, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16R6
%PartNumber:PAL16R6A-2
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P19 ~P19 P3 ~P3 N2 ~N2 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 N7 ~N7 P9 ~P9 P12 ~P12 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 25,25,35,35);
 %ELSE
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 25,25,35,35);
  TSB(TNode, %InFuse; OutPin; 25,25,25,25,35,35,35,35);
 %END;
%MACEND;

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 DQFF(TLNode,P1;NodeInp;15,15,25,0,10,10,25,25,35,0,25,25);
 TSB(NodeInp,L1;OutPin;15,15,15,15,25,25,25,25);
%MACEND;

LINV(P11;L1);
NOR7ENABLE(%SF00, %FF00, P19, N1);
NOR8DFF(%FF256, N2, L2, P18);
NOR8DFF(%FF512, N3, L3, P17);
NOR8DFF(%FF768, N4, L4, P16);
NOR8DFF(%FF1024, N5, L5, P15);
NOR8DFF(%FF1280, N6, L6, P14);
NOR8DFF(%FF1536, N7, L7, P13);
NOR7ENABLE(%SF1792, %FF1792, P12, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16R6
%PartNumber:PAL16R6A-4
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P19 ~P19 P3 ~P3 N2 ~N2 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 N7 ~N7 P9 ~P9 P12 ~P12 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 35,35,55,55);
 %ELSE
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 35,35,55,55);
  TSB(TNode, %InFuse; OutPin; 30,30,30,30,50,50,50,50);
 %END;
%MACEND;

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 DQFF(TLNode,P1;NodeInp;20,20,45,0,20,20,35,35,60,0,30,30);
 TSB(NodeInp,L1;OutPin;15,15,15,15,30,30,30,30);
%MACEND;

LINV(P11;L1);
NOR7ENABLE(%SF00, %FF00, P19, N1);
NOR8DFF(%FF256, N2, L2, P18);
NOR8DFF(%FF512, N3, L3, P17);
NOR8DFF(%FF768, N4, L4, P16);
NOR8DFF(%FF1024, N5, L5, P15);
NOR8DFF(%FF1280, N6, L6, P14);
NOR8DFF(%FF1536, N7, L7, P13);
NOR7ENABLE(%SF1792, %FF1792, P12, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16R6
%PartNumber:PAL16R6B
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P19 ~P19 P3 ~P3 N2 ~N2 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 N7 ~N7 P9 ~P9 P12 ~P12 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 12,12,15,15);
 %ELSE
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 12,12,15,15);
  TSB(TNode, %InFuse; OutPin; 12,12,12,12,22,22,15,15);
 %END;
%MACEND;

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 DQFF(TLNode,P1;NodeInp;8,8,10,0,5,6,12,12,15,0,10,10);
 TSB(NodeInp,L1;OutPin;10,10,10,10,15,15,15,15);
%MACEND;

LINV(P11;L1);
NOR7ENABLE(%SF00, %FF00, P19, N1);
NOR8DFF(%FF256, N2, L2, P18);
NOR8DFF(%FF512, N3, L3, P17);
NOR8DFF(%FF768, N4, L4, P16);
NOR8DFF(%FF1024, N5, L5, P15);
NOR8DFF(%FF1280, N6, L6, P14);
NOR8DFF(%FF1536, N7, L7, P13);
NOR7ENABLE(%SF1792, %FF1792, P12, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16R6
%PartNumber:PAL16R6B-2
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P19 ~P19 P3 ~P3 N2 ~N2 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 N7 ~N7 P9 ~P9 P12 ~P12 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 17,17,25,25);
 %ELSE
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 17,17,25,25);
  TSB(TNode, %InFuse; OutPin; 10,10,13,13,25,25,25,25);
 %END;
%MACEND;

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 DQFF(TLNode,P1;NodeInp;10,10,15,0,10,10,15,15,25,0,15,15);
 TSB(NodeInp,L1;OutPin;10,10,11,11,20,20,20,20);
%MACEND;

LINV(P11;L1);
NOR7ENABLE(%SF00, %FF00, P19, N1);
NOR8DFF(%FF256, N2, L2, P18);
NOR8DFF(%FF512, N3, L3, P17);
NOR8DFF(%FF768, N4, L4, P16);
NOR8DFF(%FF1024, N5, L5, P15);
NOR8DFF(%FF1280, N6, L6, P14);
NOR8DFF(%FF1536, N7, L7, P13);
NOR7ENABLE(%SF1792, %FF1792, P12, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16R6
%PartNumber:PAL16R6B-4
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P19 ~P19 P3 ~P3 N2 ~N2 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 N7 ~N7 P9 ~P9 P12 ~P12 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 25,25,35,35);
 %ELSE
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 25,25,35,35);
  TSB(TNode, %InFuse; OutPin; 25,25,25,25,35,35,35,35);
 %END;
%MACEND;

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 DQFF(TLNode,P1;NodeInp;15,15,25,0,10,10,25,25,35,0,25,25);
 TSB(NodeInp,L1;OutPin;15,15,15,15,25,25,25,25);
%MACEND;

LINV(P11;L1);
NOR7ENABLE(%SF00, %FF00, P19, N1);
NOR8DFF(%FF256, N2, L2, P18);
NOR8DFF(%FF512, N3, L3, P17);
NOR8DFF(%FF768, N4, L4, P16);
NOR8DFF(%FF1024, N5, L5, P15);
NOR8DFF(%FF1280, N6, L6, P14);
NOR8DFF(%FF1536, N7, L7, P13);
NOR7ENABLE(%SF1792, %FF1792, P12, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16R6
%PartNumber:PAL16R6D
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P19 ~P19 P3 ~P3 N2 ~N2 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 N7 ~N7 P9 ~P9 P12 ~P12 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 8,8,10,10);
 %ELSE
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 8,8,10,10);
  TSB(TNode, %InFuse; OutPin; 8,8,8,8,10,10,10,10);
 %END;
%MACEND;

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 DQFF(TLNode,P1;NodeInp;6,6,8,0,5,6,7,7,10,0,8,8);
 TSB(NodeInp,L1;OutPin;8,8,8,8,10,10,10,10);
%MACEND;

LINV(P11;L1);
NOR7ENABLE(%SF00, %FF00, P19, N1);
NOR8DFF(%FF256, N2, L2, P18);
NOR8DFF(%FF512, N3, L3, P17);
NOR8DFF(%FF768, N4, L4, P16);
NOR8DFF(%FF1024, N5, L5, P15);
NOR8DFF(%FF1280, N6, L6, P14);
NOR8DFF(%FF1536, N7, L7, P13);
NOR7ENABLE(%SF1792, %FF1792, P12, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16R6
%PartNumber:PAL16R6Q-25
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P19 ~P19 P3 ~P3 N2 ~N2 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 N7 ~N7 P9 ~P9 P12 ~P12 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 20,20,25,25);
 %ELSE
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 20,20,25,25);
  TSB(TNode, %InFuse; OutPin; 20,20,20,20,25,25,25,25);
 %END;
%MACEND;

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 DQFF(TLNode,P1;NodeInp;10,10,15,0,10,10,15,15,20,0,15,15);
 TSB(NodeInp,L1;OutPin;15,15,15,15,20,20,20,20);
%MACEND;

LINV(P11;L1);
NOR7ENABLE(%SF00, %FF00, P19, N1);
NOR8DFF(%FF256, N2, L2, P18);
NOR8DFF(%FF512, N3, L3, P17);
NOR8DFF(%FF768, N4, L4, P16);
NOR8DFF(%FF1024, N5, L5, P15);
NOR8DFF(%FF1280, N6, L6, P14);
NOR8DFF(%FF1536, N7, L7, P13);
NOR7ENABLE(%SF1792, %FF1792, P12, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16R8
%PartNumber:PAL16R8A
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 N1 ~N1 P3 ~P3 N2 ~N2 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 N7 ~N7 P9 ~P9 N8 ~N8 *

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 DQFFC(TLNode,P1,IPL;NodeInp;10,10,15,0,10,10,1,1,1,1,15,15,25,0,15,15,1,1,1,1);
 TSB(NodeInp,L1;OutPin;10,10,11,11,20,20,20,20);
%MACEND;

LINV(P11;L1);
NOR8DFF(%FF00, N1, L2, P19);
NOR8DFF(%FF256, N2, L3, P18);
NOR8DFF(%FF512, N3, L4, P17);
NOR8DFF(%FF768, N4, L5, P16);
NOR8DFF(%FF1024, N5, L6, P15);
NOR8DFF(%FF1280, N6, L7, P14);
NOR8DFF(%FF1536, N7, L8, P13);
NOR8DFF(%FF1792, N8, L9, P12);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16R8
%PartNumber:PAL16R8A-2
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 N1 ~N1 P3 ~P3 N2 ~N2 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 N7 ~N7 P9 ~P9 N8 ~N8 *

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 DQFFC(TLNode,P1,IPL;NodeInp;15,15,25,0,10,10,1,1,1,1,25,25,35,0,25,25,1,1,1,1);
 TSB(NodeInp,L1;OutPin;15,15,15,15,25,25,25,25);
%MACEND;

LINV(P11;L1);
NOR8DFF(%FF00, N1, L2, P19);
NOR8DFF(%FF256, N2, L3, P18);
NOR8DFF(%FF512, N3, L4, P17);
NOR8DFF(%FF768, N4, L5, P16);
NOR8DFF(%FF1024, N5, L6, P15);
NOR8DFF(%FF1280, N6, L7, P14);
NOR8DFF(%FF1536, N7, L8, P13);
NOR8DFF(%FF1792, N8, L9, P12);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16R8
%PartNumber:PAL16R8A-4
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 N1 ~N1 P3 ~P3 N2 ~N2 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 N7 ~N7 P9 ~P9 N8 ~N8 *

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 DQFF(TLNode,P1;NodeInp;20,20,45,0,20,20,35,35,60,0,30,30);
 TSB(NodeInp,L1;OutPin;15,15,15,15,30,30,30,30);
%MACEND;

LINV(P11;L1);
NOR8DFF(%FF00, N1, L2, P19);
NOR8DFF(%FF256, N2, L3, P18);
NOR8DFF(%FF512, N3, L4, P17);
NOR8DFF(%FF768, N4, L5, P16);
NOR8DFF(%FF1024, N5, L6, P15);
NOR8DFF(%FF1280, N6, L7, P14);
NOR8DFF(%FF1536, N7, L8, P13);
NOR8DFF(%FF1792, N8, L9, P12);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16R8
%PartNumber:PAL16R8B
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 N1 ~N1 P3 ~P3 N2 ~N2 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 N7 ~N7 P9 ~P9 N8 ~N8 *

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 DQFFC(TLNode,P1,IPL;NodeInp;8,8,10,0,5,6,1,1,1,1,12,12,15,0,10,10,1,1,1,1);
 TSB(NodeInp,L1;OutPin;10,10,10,10,15,15,15,15);
%MACEND;

LINV(P11;L1);
NOR8DFF(%FF00, N1, L2, P19);
NOR8DFF(%FF256, N2, L3, P18);
NOR8DFF(%FF512, N3, L4, P17);
NOR8DFF(%FF768, N4, L5, P16);
NOR8DFF(%FF1024, N5, L6, P15);
NOR8DFF(%FF1280, N6, L7, P14);
NOR8DFF(%FF1536, N7, L8, P13);
NOR8DFF(%FF1792, N8, L9, P12);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16R8
%PartNumber:PAL16R8B-2
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 N1 ~N1 P3 ~P3 N2 ~N2 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 N7 ~N7 P9 ~P9 N8 ~N8 *

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 DQFFC(TLNode,P1,IPL;NodeInp;10,10,15,0,10,10,1,1,1,1,15,15,25,0,15,15,1,1,1,1);
 TSB(NodeInp,L1;OutPin;10,10,11,11,20,20,20,20);
%MACEND;

LINV(P11;L1);
NOR8DFF(%FF00, N1, L2, P19);
NOR8DFF(%FF256, N2, L3, P18);
NOR8DFF(%FF512, N3, L4, P17);
NOR8DFF(%FF768, N4, L5, P16);
NOR8DFF(%FF1024, N5, L6, P15);
NOR8DFF(%FF1280, N6, L7, P14);
NOR8DFF(%FF1536, N7, L8, P13);
NOR8DFF(%FF1792, N8, L9, P12);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16R8
%PartNumber:PAL16R8B-4
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 N1 ~N1 P3 ~P3 N2 ~N2 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 N7 ~N7 P9 ~P9 N8 ~N8 *

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 DQFF(TLNode,P1;NodeInp;15,15,25,0,10,10,25,25,35,0,25,25);
 TSB(NodeInp,L1;OutPin;15,15,15,15,25,25,25,25);
%MACEND;

LINV(P11;L1);
NOR8DFF(%FF00, N1, L2, P19);
NOR8DFF(%FF256, N2, L3, P18);
NOR8DFF(%FF512, N3, L4, P17);
NOR8DFF(%FF768, N4, L5, P16);
NOR8DFF(%FF1024, N5, L6, P15);
NOR8DFF(%FF1280, N6, L7, P14);
NOR8DFF(%FF1536, N7, L8, P13);
NOR8DFF(%FF1792, N8, L9, P12);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16R8
%PartNumber:PAL16R8D
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 N1 ~N1 P3 ~P3 N2 ~N2 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 N7 ~N7 P9 ~P9 N8 ~N8 *

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 DQFF(TLNode,P1;NodeInp;6,6,8,0,5,6,7,7,10,0,8,8);
 TSB(NodeInp,L1;OutPin;8,8,8,8,10,10,10,10);
%MACEND;

LINV(P11;L1);
NOR8DFF(%FF00, N1, L2, P19);
NOR8DFF(%FF256, N2, L3, P18);
NOR8DFF(%FF512, N3, L4, P17);
NOR8DFF(%FF768, N4, L5, P16);
NOR8DFF(%FF1024, N5, L6, P15);
NOR8DFF(%FF1280, N6, L7, P14);
NOR8DFF(%FF1536, N7, L8, P13);
NOR8DFF(%FF1792, N8, L9, P12);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16R8
%PartNumber:PAL16R8Q-25
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 N1 ~N1 P3 ~P3 N2 ~N2 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 N7 ~N7 P9 ~P9 N8 ~N8 *

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 DQFF(TLNode,P1;NodeInp;10,10,15,0,10,10,15,15,20,0,15,15);
 TSB(NodeInp,L1;OutPin;15,15,15,15,20,20,20,20);
%MACEND;

LINV(P11;L1);
NOR8DFF(%FF00, N1, L2, P19);
NOR8DFF(%FF256, N2, L3, P18);
NOR8DFF(%FF512, N3, L4, P17);
NOR8DFF(%FF768, N4, L5, P16);
NOR8DFF(%FF1024, N5, L6, P15);
NOR8DFF(%FF1280, N6, L7, P14);
NOR8DFF(%FF1536, N7, L8, P13);
NOR8DFF(%FF1792, N8, L9, P12);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16RA8
%PartNumber:PAL16RA8
%LastNode ? ?
%NumPins: 20
%FDF AND 0 P2 ~P2 P19 ~P19 P3 ~P3 P18 ~P18 P4 ~P4 P17 ~P17 P5 ~P5 P16 ~P16
           P6 ~P6 P15 ~P15 P7 ~P7 P14 ~P14 P8 ~P8 P13 ~P13 P9 ~P9 P12 ~P12 *


%MACRO LOADMac(IO:%TEXT, IOBar:%TEXT, InFuse:%FF, TLNode1:%TEXT,
                   TLNode2:%TEXT, ResetLoadInput:%TEXT, TLNode3:%TEXT,
        	   SetLoadInput:%TEXT, XorFuse:%SF, TLNode:%TEXT, PClock:%TEXT,
                   RegOut:%TEXT, TLSet:%TEXT);

  LINV(IO; IOBar);
  LAND(P1, %InFuse+64; TLNode1);
  LAND(L1, IOBar; TLNode2);
  LNOR(TLNode1, TLNode2, IPH; ResetLoadInput);
  LINV(%InFuse+96; TLSet);
  LAND(P1, TLSet; TLNode3);
  LOR(TLNode2, TLNode3; SetLoadInput);

 %IF %XorFuse=1 %THEN
  LOR(%InFuse+128, %InFuse+160, %InFuse+192, %InFuse+224; TLNode);
 %ELSE
  LNOR(%InFuse+128, %InFuse+160, %InFuse+192, %InFuse+224; TLNode);
 %END;
  AND(%InFuse+32; PClock; 0,0,0,0);
  DQFFPC(TLNode, PClock, SetLoadInput, ResetLoadInput; RegOut; 17,17,10,0,13,13,22,27,15,0,30,30,20,10,20,20,35,40,35,0);
%MACEND;


%MACRO OUTPUTMac(InFuse:%FF, TLNode:%TEXT, RegOutput:%TEXT, Output:%TEXT,
                 TsbEnable:%TEXT, IO:%TEXT, EnableFuse:%SF, SETFuse:%SF,
		 RESETFuse:%SF);

%IF %SETFuse..%SETFuse+31 = 1 %THEN
 %IF %RESETFuse..%RESETFuse+31 = 1 %THEN

   %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
     ITSB(TLNode, L2; IO; 10,10,10,10,20,20,20,20);
   %ELSE
     AND(%InFuse, L2; TSBEnable; 18,18,30,30);
     ITSB(TLNode, TsbEnable; IO; 10,10,10,10,20,20,20,20);
   %END;

 %ELSE

   %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
     ITSB(RegOutput, L2; IO; 10,10,10,10,20,20,20,20);
   %ELSE
     AND(%InFuse, L2; TsbEnable; 18,18,30,30);
     ITSB(RegOutput, TsbEnable; IO; 10,10,10,10,20,20,20,20);
   %END;
 %END;
%ELSE
 %IF %RESETFuse..%RESETFuse+31 = 1 %THEN

   %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
     ITSB(RegOutput, L2; IO; 10,10,10,10,20,20,20,20);
   %ELSE
     AND(%InFuse, L2; TsbEnable; 18,18,30,30);
     ITSB(RegOutput, TsbEnable; IO; 10,10,10,10,20,20,20,20);
   %END;

 %ELSE

   %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
     ITSB(RegOutput, L2; IO; 10,10,10,10,20,20,20,20);
   %ELSE
     AND(%InFuse, L2; TsbEnable; 18,18,30,30);
     ITSB(RegOutput, TsbEnable; IO; 10,10,10,10,20,20,20,20);
   %END;
 %END;
%END;
%MACEND;

LINV(P1; L1);
LINV(P11; L2);

LOADMac(P19, L3, %FF00, L4, L5, L6, L7, L8, %SF2048, L9, N1, N2, L59);
LOADMac(P18, L10, %FF256, L11, L12, L13, L14, L15, %SF2049, L16, N3, N4, L60);
LOADMac(P17, L17, %FF512, L18, L19 ,L20, L21, L22, %SF2050, L23, N5, N6, L61);
LOADMac(P16, L24, %FF768, L25, L26, L27, L28, L29, %SF2051, L30, N7, N8, L62);
LOADMac(P15, L31, %FF1024, L32, L33, L34, L35, L36, %SF2052, L37, N9, N10, L63);
LOADMac(P14, L38, %FF1280, L39, L40, L41, L42, L43, %SF2053, L44, N11, N12, L64);
LOADMac(P13, L45, %FF1536, L46, L47, L48, L49, L50, %SF2054, L51, N13, N14, L65);
LOADMac(P12, L52, %FF1792, L53, L54, L55, L56, L57, %SF2055, L58, N15, N16, L66);

OUTPUTMac(%FF00, L9, N2, L67, N17, P19, %SF00, %SF96, %SF64);
OUTPUTMac(%FF256, L16, N4, L69, N18, P18, %SF256, %SF352, %SF320);
OUTPUTMac(%FF512, L23, N6, L71, N19, P17, %SF512, %SF608, %SF576);
OUTPUTMac(%FF768, L30, N8, L73, N20, P16, %SF768, %SF864, %SF832);
OUTPUTMac(%FF1024, L37, N10, L75, N21, P15, %SF1024, %SF1120, %SF1088);
OUTPUTMac(%FF1280, L44, N12, L77, N22, P14, %SF1280, %SF1376, %SF1344);
OUTPUTMac(%FF1536, L51, N14, L79, N23, P13, %SF1536, %SF1632, %SF1600);
OUTPUTMac(%FF1792, L58, N16, L81, N24, P12, %SF1792, %SF1888, %SF1856);
%EndModel

;The registers on the following device reset upon power-up, whereby the
;active-low outputs are set to a logic High.
;Delays for this device are given for polarity fuse programmed.
%StartModel
%Manufacturer:AMD
%Type:16RP4
%PartNumber:PAL16RP4A
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P19 ~P19 P3 ~P3 P18 ~P18 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 P13 ~P13 P9 ~P9 P12 ~P12 *

%MACRO POR7ENABLE(EnableFuse:%SF, XorFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  %IF %XorFuse = 0 %THEN
   NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
      %InFuse+192, %InFuse+224; OutPin; 20,20,30,30);
  %ELSE
   OR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 20,20,30,30);
  %END;
 %ELSE
  %IF %XorFuse = 0 %THEN
   NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
      %InFuse+192, %InFuse+224; TNode; 20,20,30,30);
  %ELSE
   OR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 20,20,30,30);
  %END;
  TSB(TNode, %InFuse; OutPin; 10,10,13,13,25,25,25,25);
 %END;
%MACEND;

%MACRO POR8DFF(InFuse:%FF, XorFuse:%SF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 %IF %XorFuse = 0 %THEN
  LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 %ELSE
  LOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 %END;
 DQFFC(TLNode,P1,IPL;NodeInp;10,10,20,0,6,14,1,1,1,1,15,15,30,0,10,20,1,1,1,1);
 TSB(NodeInp,L1;OutPin;10,10,11,11,20,20,20,20);
%MACEND;

LINV(P11;L1);
POR7ENABLE(%SF00, %SF2048, %FF00, P19, N1);
POR7ENABLE(%SF256, %SF2049, %FF256, P18, N2);
POR8DFF(%FF512, %SF2050, N3, L2, P17);
POR8DFF(%FF768, %SF2051, N4, L3, P16);
POR8DFF(%FF1024, %SF2052, N5, L4, P15);
POR8DFF(%FF1280, %SF2053, N6, L5, P14);
POR7ENABLE(%SF1536, %SF2054, %FF1536, P13, N7);
POR7ENABLE(%SF1792, %SF2055, %FF1792, P12, N8);
%EndModel

;The registers on the following device reset upon power-up, whereby the
;active-low outputs are set to a logic High.
;Delays for this device are given for polarity fuse programmed.
%StartModel
%Manufacturer:AMD
%Type:16RP6
%PartNumber:PAL16RP6A
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P19 ~P19 P3 ~P3 N2 ~N2 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 N7 ~N7 P9 ~P9 P12 ~P12 *

%MACRO POR7ENABLE(EnableFuse:%SF, XorFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  %IF %XorFuse = 0 %THEN
   NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
      %InFuse+192, %InFuse+224; OutPin; 20,20,30,30);
  %ELSE
   OR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 20,20,30,30);
  %END;
 %ELSE
  %IF %XorFuse = 0 %THEN
   NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
      %InFuse+192, %InFuse+224; TNode; 20,20,30,30);
  %ELSE
   OR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 20,20,30,30);
  %END;
    TSB(TNode, %InFuse; OutPin; 10,10,13,13,25,25,25,25);
 %END;
%MACEND;

%MACRO POR8DFF(InFuse:%FF, XorFuse:%SF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 %IF %XorFuse = 0 %THEN
  LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 %ELSE
  LOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 %END;
 DQFFC(TLNode,P1,IPL;NodeInp;10,10,20,0,6,14,1,1,1,1,15,15,30,0,10,20,1,1,1,1);
 TSB(NodeInp,L1;OutPin;10,10,11,11,20,20,20,20);
%MACEND;

LINV(P11;L1);
POR7ENABLE(%SF00, %SF2048, %FF00, P19, N1);
POR8DFF(%FF256, %SF2049, N2, L2, P18);
POR8DFF(%FF512, %SF2050, N3, L3, P17);
POR8DFF(%FF768, %SF2051, N4, L4, P16);
POR8DFF(%FF1024, %SF2052, N5, L5, P15);
POR8DFF(%FF1280, %SF2053, N6, L6, P14);
POR8DFF(%FF1536, %SF2054, N7, L7, P13);
POR7ENABLE(%SF1792, %SF2055, %FF1792, P12, N8);
%EndModel

;The registers on the following device reset upon power-up, whereby the
;active-low outputs are set to a logic High.
;Delays for this device are given for polarity fuse programmed.
%StartModel
%Manufacturer:AMD
%Type:16RP8
%PartNumber:PAL16RP8A
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 N1 ~N1 P3 ~P3 N2 ~N2 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 N7 ~N7 P9 ~P9 N8 ~N8 *

%MACRO POR8DFF(InFuse:%FF, XorFuse:%SF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 %IF %XorFuse = 0 %THEN
  LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 %ELSE
  LOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 %END;
 DQFFC(TLNode,P1,IPL;NodeInp;10,10,20,0,6,14,1,1,1,1,15,15,30,0,10,20,1,1,1,1);
 TSB(NodeInp,L1;OutPin;10,10,11,11,20,20,20,20);
%MACEND;

LINV(P11; L1);
POR8DFF(%FF00, %SF2048, N1, L2, P19);
POR8DFF(%FF256, %SF2049, N2, L3, P18);
POR8DFF(%FF512, %SF2050, N3, L4, P17);
POR8DFF(%FF768, %SF2051, N4, L5, P16);
POR8DFF(%FF1024, %SF2052, N5, L6, P15);
POR8DFF(%FF1280, %SF2053, N6, L7, P14);
POR8DFF(%FF1536, %SF2054, N7, L8, P13);
POR8DFF(%FF1792, %SF2055, N8, L9, P12);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:18L4
%PartNumber:PAL18L4
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P23 ~P23 P4 ~P4 P22 ~P22 P5 ~P5 P21 ~P21 P6 ~P6
   P7 ~P7 P8 ~P8 P16 ~P16 P9 ~P9 P15 ~P15 P10 ~P10 P14 ~P14 P11 ~P11 P13 ~P13 *

NOR(%FF00, %FF36, %FF72, %FF108, %FF144, %FF180; P20; 25,25,40,40);
NOR(%FF216, %FF252, %FF288, %FF324; P19; 25,25,40,40);
NOR(%FF360, %FF396, %FF432, %FF468; P18; 25,25,40,40);
NOR(%FF504, %FF540, %FF576, %FF612, %FF648, %FF684; P17; 25,25,40,40);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:20C1
%PartNumber:PAL20C1
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P23 ~P23 P4 ~P4 P22 ~P22 P5 ~P5 P21 ~P21
     P6 ~P6 P20 ~P20 P7 ~P7 P17 ~P17 P8 ~P8 P16 ~P16 P9 ~P9 P15 ~P15
     P10 ~P10 P14 ~P14 P11 ~P11 P13 ~P13 *

LOR(%FF00, %FF40, %FF80, %FF120, %FF160, %FF200, %FF240, %FF280, %FF320,
   %FF360, %FF400, %FF440, %FF480, %FF520, %FF560, %FF600; L1);
BUF(L1; P19; 25,25,40,40);
INV(L1; P18; 25,25,40,40);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:20L10
%PartNumber:PAL20L10A
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P22 ~P22 P4 ~P4 P21 ~P21 P5 ~P5 P20 ~P20
     P6 ~P6 P19 ~P19 P7 ~P7 P18 ~P18 P8 ~P8 P17 ~P17 P9 ~P9 P16 ~P16
     P10 ~P10 P15 ~P15 P11 ~P11 P13 ~P13 *

%MACRO NOR3ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
  NOR(%InFuse+40, %InFuse+80, %InFuse+120; OutPin; 23,23,30,30);
 %ELSE
  NOR(%InFuse+40, %InFuse+80, %InFuse+120; TNode; 23,23,30,30);
  TSB(TNode, %InFuse; OutPin; 19,19,15,15,30,30,30,30);
 %END;
%MACEND;

NOR3ENABLE(%SF00, %FF00, P23, N1);
NOR3ENABLE(%SF160, %FF160, P22, N2);
NOR3ENABLE(%SF320, %FF320, P21, N3);
NOR3ENABLE(%SF480, %FF480, P20, N4);
NOR3ENABLE(%SF640, %FF640, P19, N5);
NOR3ENABLE(%SF800, %FF800, P18, N6);
NOR3ENABLE(%SF960, %FF960, P17, N7);
NOR3ENABLE(%SF1120, %FF1120, P16, N8);
NOR3ENABLE(%SF1280, %FF1280, P15, N9);
NOR3ENABLE(%SF1440, %FF1440, P14, N10);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:20L2
%PartNumber:PAL20L2
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P23 ~P23 P4 ~P4 P22 ~P22 P5 ~P5 P21 ~P21
     P6 ~P6 P20 ~P20 P7 ~P7 P17 ~P17 P8 ~P8 P16 ~P16 P9 ~P9 P15 ~P15
     P10 ~P10 P14 ~P14 P11 ~P11 P13 ~P13 *

NOR(%FF00, %FF40, %FF80, %FF120, %FF160, %FF200, %FF240, %FF280; P19; 25,25,40,40);
NOR(%FF320, %FF360, %FF400, %FF440, %FF480, %FF520, %FF560, %FF600; P18; 25,25,40,40);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:20L8
%PartNumber:PAL20L8A
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P23 ~P23 P4 ~P4 P21 ~P21 P5 ~P5 P20 ~P20
     P6 ~P6 P19 ~P19 P7 ~P7 P18 ~P18 P8 ~P8 P17 ~P17 P9 ~P9 P16 ~P16
     P10 ~P10 P14 ~P14 P11 ~P11 P13 ~P13 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
  NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
     %InFuse+240, %InFuse+280; OutPin; 15,15,25,25);
 %ELSE
  NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; TNode; 15,15,25,25);
  TSB(TNode, %InFuse; OutPin; 10,10,13,13,25,25,25,25);
 %END;
%MACEND;

NOR7ENABLE(%SF00, %FF00, P22, N1);
NOR7ENABLE(%SF320, %FF320, P21, N2);
NOR7ENABLE(%SF640, %FF640, P20, N3);
NOR7ENABLE(%SF960, %FF960, P19, N4);
NOR7ENABLE(%SF1280, %FF1280, P18, N5);
NOR7ENABLE(%SF1600, %FF1600, P17, N6);
NOR7ENABLE(%SF1920, %FF1920, P16, N7);
NOR7ENABLE(%SF2240, %FF2240, P15, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:20L8
%PartNumber:PAL20L8A-2
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P23 ~P23 P4 ~P4 P21 ~P21 P5 ~P5 P20 ~P20
     P6 ~P6 P19 ~P19 P7 ~P7 P18 ~P18 P8 ~P8 P17 ~P17 P9 ~P9 P16 ~P16
     P10 ~P10 P14 ~P14 P11 ~P11 P13 ~P13 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
  NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
     %InFuse+240, %InFuse+280; OutPin; 25,25,35,35);
 %ELSE
  NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; TNode; 25,25,35,35);
  TSB(TNode, %InFuse; OutPin; 25,25,25,25,35,35,35,35);
 %END;
%MACEND;

NOR7ENABLE(%SF00, %FF00, P22, N1);
NOR7ENABLE(%SF320, %FF320, P21, N2);
NOR7ENABLE(%SF640, %FF640, P20, N3);
NOR7ENABLE(%SF960, %FF960, P19, N4);
NOR7ENABLE(%SF1280, %FF1280, P18, N5);
NOR7ENABLE(%SF1600, %FF1600, P17, N6);
NOR7ENABLE(%SF1920, %FF1920, P16, N7);
NOR7ENABLE(%SF2240, %FF2240, P15, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:20L8
%PartNumber:PAL20L8B
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P23 ~P23 P4 ~P4 P21 ~P21 P5 ~P5 P20 ~P20
     P6 ~P6 P19 ~P19 P7 ~P7 P18 ~P18 P8 ~P8 P17 ~P17 P9 ~P9 P16 ~P16
     P10 ~P10 P14 ~P14 P11 ~P11 P13 ~P13 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
  NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
     %InFuse+240, %InFuse+280; OutPin; 12,12,15,15);
 %ELSE
  NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; TNode; 12,12,15,15);
  TSB(TNode, %InFuse; OutPin; 12,12,12,12,18,18,15,15);
 %END;
%MACEND;

NOR7ENABLE(%SF00, %FF00, P22, N1);
NOR7ENABLE(%SF320, %FF320, P21, N2);
NOR7ENABLE(%SF640, %FF640, P20, N3);
NOR7ENABLE(%SF960, %FF960, P19, N4);
NOR7ENABLE(%SF1280, %FF1280, P18, N5);
NOR7ENABLE(%SF1600, %FF1600, P17, N6);
NOR7ENABLE(%SF1920, %FF1920, P16, N7);
NOR7ENABLE(%SF2240, %FF2240, P15, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:20L8
%PartNumber:PAL20L8B-2
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P23 ~P23 P4 ~P4 P21 ~P21 P5 ~P5 P20 ~P20
     P6 ~P6 P19 ~P19 P7 ~P7 P18 ~P18 P8 ~P8 P17 ~P17 P9 ~P9 P16 ~P16
     P10 ~P10 P14 ~P14 P11 ~P11 P13 ~P13 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
  NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
     %InFuse+240, %InFuse+280; OutPin; 15,15,25,25);
 %ELSE
  NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; TNode; 15,15,25,25);
  TSB(TNode, %InFuse; OutPin; 10,10,13,13,25,25,25,25);
 %END;
%MACEND;

NOR7ENABLE(%SF00, %FF00, P22, N1);
NOR7ENABLE(%SF320, %FF320, P21, N2);
NOR7ENABLE(%SF640, %FF640, P20, N3);
NOR7ENABLE(%SF960, %FF960, P19, N4);
NOR7ENABLE(%SF1280, %FF1280, P18, N5);
NOR7ENABLE(%SF1600, %FF1600, P17, N6);
NOR7ENABLE(%SF1920, %FF1920, P16, N7);
NOR7ENABLE(%SF2240, %FF2240, P15, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:20R4
%PartNumber:PAL20R4A
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P23 ~P23  P3 ~P3 P22 ~P22 P4 ~P4 P21 ~P21 P5 ~P5 N3 ~N3 P6 ~P6
   N4 ~N4 P7 ~P7 N5 ~N5 P8 ~P8 N6 ~N6 P9 ~P9 P16 ~P16 P10 ~P10 P15 ~P15
   P11 ~P11 P14 ~P14 *

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
  LNOR(%InFuse,%InFuse+40,%InFuse+80,%InFuse+120,%InFuse+160,%InFuse+200,%InFuse+240,%InFuse+280;TLNode);
  DQFF(TLNode,P1;NodeInp;10,10,15,0,7,7,15,15,25,0,15,15);
  TSB(NodeInp,L1;OutPin;10,10,11,11,20,20,20,20);
%MACEND;

%MACRO NOR7ENABLE(InFuse:%FF, EnableFuse:%SF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; OutPin; 15,15,25,25);
 %ELSE
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; TNode; 15,15,25,25);
   TSB(TNode, %InFuse; OutPin;10,10,13,13,25,25,25,25);
 %END;
%MACEND;

LINV(P13; L1);
NOR7ENABLE(%FF00, %SF00, P22, N1);
NOR7ENABLE(%FF320, %SF320, P21, N2);
NOR8DFF(%FF640, N3, L2, P20);
NOR8DFF(%FF960, N4, L3, P19);
NOR8DFF(%FF1280, N5, L4, P18);
NOR8DFF(%FF1600, N6, L5, P17);
NOR7ENABLE(%FF1920, %SF1920, P16, N7);
NOR7ENABLE(%FF2240, %SF2240, P15, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:20R4
%PartNumber:PAL20R4A-2
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P23 ~P23  P3 ~P3 P22 ~P22 P4 ~P4 P21 ~P21 P5 ~P5 N3 ~N3 P6 ~P6
   N4 ~N4 P7 ~P7 N5 ~N5 P8 ~P8 N6 ~N6 P9 ~P9 P16 ~P16 P10 ~P10 P15 ~P15
   P11 ~P11 P14 ~P14 *

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
  LNOR(%InFuse,%InFuse+40,%InFuse+80,%InFuse+120,%InFuse+160,%InFuse+200,%InFuse+240,%InFuse+280;TLNode);
  DQFF(TLNode,P1;NodeInp;15,15,25,0,10,10,25,25,35,0,25,25);
  TSB(NodeInp,L1;OutPin;15,15,15,15,25,25,25,25);
%MACEND;

%MACRO NOR7ENABLE(InFuse:%FF, EnableFuse:%SF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; OutPin; 25,25,35,35);
 %ELSE
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; TNode; 25,25,35,35);
   TSB(TNode, %InFuse; OutPin; 25,25,25,25,35,35,35,35);
 %END;
%MACEND;

LINV(P13; L1);
NOR7ENABLE(%FF00, %SF00, P22, N1);
NOR7ENABLE(%FF320, %SF320, P21, N2);
NOR8DFF(%FF640, N3, L2, P20);
NOR8DFF(%FF960, N4, L3, P19);
NOR8DFF(%FF1280, N5, L4, P18);
NOR8DFF(%FF1600, N6, L5, P17);
NOR7ENABLE(%FF1920, %SF1920, P16, N7);
NOR7ENABLE(%FF2240, %SF2240, P15, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:20R4
%PartNumber:PAL20R4B
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P23 ~P23  P3 ~P3 P22 ~P22 P4 ~P4 P21 ~P21 P5 ~P5 N3 ~N3 P6 ~P6
   N4 ~N4 P7 ~P7 N5 ~N5 P8 ~P8 N6 ~N6 P9 ~P9 P16 ~P16 P10 ~P10 P15 ~P15
   P11 ~P11 P14 ~P14 *

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
  LNOR(%InFuse,%InFuse+40,%InFuse+80,%InFuse+120,%InFuse+160,%InFuse+200,%InFuse+240,%InFuse+280;TLNode);
  DQFF(TLNode,P1;NodeInp;8,8,10,0,8,6,12,12,15,0,12,10);
  TSB(NodeInp,L1;OutPin;10,10,8,8,15,15,12,12);
%MACEND;

%MACRO NOR7ENABLE(InFuse:%FF, EnableFuse:%SF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; OutPin; 12,12,15,15);
 %ELSE
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; TNode; 12,12,15,15);
   TSB(TNode, %InFuse; OutPin; 12,12,12,12,18,18,15,15);
 %END;
%MACEND;

LINV(P13; L1);
NOR7ENABLE(%FF00, %SF00, P22, N1);
NOR7ENABLE(%FF320, %SF320, P21, N2);
NOR8DFF(%FF640, N3, L2, P20);
NOR8DFF(%FF960, N4, L3, P19);
NOR8DFF(%FF1280, N5, L4, P18);
NOR8DFF(%FF1600, N6, L5, P17);
NOR7ENABLE(%FF1920, %SF1920, P16, N7);
NOR7ENABLE(%FF2240, %SF2240, P15, N8);
%EndModel

;The registers on the following device reset upon power-up, whereby the
;active-low outputs are set to a logic High.
%StartModel
%Manufacturer:AMD
%Type:20R4
%PartNumber:PAL20R4B-2
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P23 ~P23  P3 ~P3 P22 ~P22 P4 ~P4 P21 ~P21 P5 ~P5 N3 ~N3 P6 ~P6
   N4 ~N4 P7 ~P7 N5 ~N5 P8 ~P8 N6 ~N6 P9 ~P9 P16 ~P16 P10 ~P10 P15 ~P15
   P11 ~P11 P14 ~P14 *

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
  LNOR(%InFuse,%InFuse+40,%InFuse+80,%InFuse+120,%InFuse+160,%InFuse+200,%InFuse+240,%InFuse+280;TLNode);
  DQFFC(TLNode,P1,IPL;NodeInp;10,10,15,0,10,10,1,1,1,1,15,15,25,0,15,15,1,1,1,1);
  TSB(NodeInp,L1;OutPin;10,10,11,11,20,20,20,20);
%MACEND;

%MACRO NOR7ENABLE(InFuse:%FF, EnableFuse:%SF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; OutPin; 15,15,25,25);
 %ELSE
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; TNode; 15,15,25,25);
   TSB(TNode, %InFuse; OutPin; 10,10,13,13,25,25,25,25);
 %END;
%MACEND;

LINV(P13; L1);
NOR7ENABLE(%FF00, %SF00, P22, N1);
NOR7ENABLE(%FF320, %SF320, P21, N2);
NOR8DFF(%FF640, N3, L2, P20);
NOR8DFF(%FF960, N4, L3, P19);
NOR8DFF(%FF1280, N5, L4, P18);
NOR8DFF(%FF1600, N6, L5, P17);
NOR7ENABLE(%FF1920, %SF1920, P16, N7);
NOR7ENABLE(%FF2240, %SF2240, P15, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:20R6
%PartNumber:PAL20R6A
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P23 ~P23  P3 ~P3 P22 ~P22 P4 ~P4 N2 ~N2 P5 ~P5 N3 ~N3 P6 ~P6
   N4 ~N4 P7 ~P7 N5 ~N5 P8 ~P8 N6 ~N6 P9 ~P9 N7 ~N7 P10 ~P10 P15 ~P15
   P11 ~P11 P14 ~P14 *

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
  LNOR(%InFuse,%InFuse+40,%InFuse+80,%InFuse+120,%InFuse+160,%InFuse+200,%InFuse+240,%InFuse+280;TLNode);
  DQFF(TLNode,P1;NodeInp;10,10,15,0,7,7,15,15,25,0,15,15);
  TSB(NodeInp,L1;OutPin;10,10,11,11,20,20,20,20);
%MACEND;

%MACRO NOR7ENABLE(InFuse:%FF, EnableFuse:%SF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; OutPin; 15,15,25,25);
 %ELSE
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; TNode; 15,15,25,25);
  TSB(TNode, %InFuse; OutPin; 10,10,13,13,25,25,25,25);
 %END;
%MACEND;

LINV(P13; L1);
NOR7ENABLE(%FF00, %SF00, P22, N1);
NOR8DFF(%FF320, N2, L2, P21);
NOR8DFF(%FF640, N3, L3, P20);
NOR8DFF(%FF960, N4, L4, P19);
NOR8DFF(%FF1280, N5, L5, P18);
NOR8DFF(%FF1600, N6, L6, P17);
NOR8DFF(%FF1920, N7, L7, P16);
NOR7ENABLE(%FF2240, %SF2240, P15, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:20R6
%PartNumber:PAL20R6A-2
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P23 ~P23  P3 ~P3 P22 ~P22 P4 ~P4 N2 ~N2 P5 ~P5 N3 ~N3 P6 ~P6
   N4 ~N4 P7 ~P7 N5 ~N5 P8 ~P8 N6 ~N6 P9 ~P9 N7 ~N7 P10 ~P10 P15 ~P15
   P11 ~P11 P14 ~P14 *

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
  LNOR(%InFuse,%InFuse+40,%InFuse+80,%InFuse+120,%InFuse+160,%InFuse+200,%InFuse+240,%InFuse+280;TLNode);
  DQFF(TLNode,P1;NodeInp;15,15,25,0,10,10,25,25,35,0,25,25);
  TSB(NodeInp,L1;OutPin;15,15,15,15,25,25,25,25);
%MACEND;

%MACRO NOR7ENABLE(InFuse:%FF, EnableFuse:%SF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; OutPin; 25,25,35,35);
 %ELSE
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; TNode; 25,25,35,35);
  TSB(TNode, %InFuse; OutPin; 25,25,25,25,35,35,35,35);
 %END;
%MACEND;

LINV(P13; L1);
NOR7ENABLE(%FF00, %SF00, P22, N1);
NOR8DFF(%FF320, N2, L2, P21);
NOR8DFF(%FF640, N3, L3, P20);
NOR8DFF(%FF960, N4, L4, P19);
NOR8DFF(%FF1280, N5, L5, P18);
NOR8DFF(%FF1600, N6, L6, P17);
NOR8DFF(%FF1920, N7, L7, P16);
NOR7ENABLE(%FF2240, %SF2240, P15, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:20R6
%PartNumber:PAL20R6B
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P23 ~P23  P3 ~P3 P22 ~P22 P4 ~P4 N2 ~N2 P5 ~P5 N3 ~N3 P6 ~P6
   N4 ~N4 P7 ~P7 N5 ~N5 P8 ~P8 N6 ~N6 P9 ~P9 N7 ~N7 P10 ~P10 P15 ~P15
   P11 ~P11 P14 ~P14 *

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
  LNOR(%InFuse,%InFuse+40,%InFuse+80,%InFuse+120,%InFuse+160,%InFuse+200,%InFuse+240,%InFuse+280;TLNode);
  DQFF(TLNode,P1;NodeInp;8,8,10,0,8,6,12,12,15,0,12,10);
  TSB(NodeInp,L1;OutPin;10,10,8,8,15,15,12,12);
%MACEND;

%MACRO NOR7ENABLE(InFuse:%FF, EnableFuse:%SF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; OutPin; 12,12,15,15);
 %ELSE
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; TNode; 12,12,15,15);
  TSB(TNode, %InFuse; OutPin; 12,12,12,12,18,18,15,15);
 %END;
%MACEND;

LINV(P13; L1);
NOR7ENABLE(%FF00, %SF00, P22, N1);
NOR8DFF(%FF320, N2, L2, P21);
NOR8DFF(%FF640, N3, L3, P20);
NOR8DFF(%FF960, N4, L4, P19);
NOR8DFF(%FF1280, N5, L5, P18);
NOR8DFF(%FF1600, N6, L6, P17);
NOR8DFF(%FF1920, N7, L7, P16);
NOR7ENABLE(%FF2240, %SF2240, P15, N8);
%EndModel

;The registers on the following device reset upon power-up, whereby the
;ctive-low outputs are set to a logic High.
%StartModel
%Manufacturer:AMD
%Type:20R6
%PartNumber:PAL20R6B-2
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P23 ~P23  P3 ~P3 P22 ~P22 P4 ~P4 N2 ~N2 P5 ~P5 N3 ~N3 P6 ~P6
   N4 ~N4 P7 ~P7 N5 ~N5 P8 ~P8 N6 ~N6 P9 ~P9 N7 ~N7 P10 ~P10 P15 ~P15
   P11 ~P11 P14 ~P14 *

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
  LNOR(%InFuse,%InFuse+40,%InFuse+80,%InFuse+120,%InFuse+160,%InFuse+200,%InFuse+240,%InFuse+280;TLNode);
  DQFFC(TLNode,P1,IPL;NodeInp;10,10,15,0,10,10,1,1,1,1,15,15,25,0,15,15,1,1,1,1);
  TSB(NodeInp,L1;OutPin;10,10,11,11,20,20,20,20);
%MACEND;

%MACRO NOR7ENABLE(InFuse:%FF, EnableFuse:%SF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; OutPin; 15,15,25,25);
 %ELSE
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; TNode; 15,15,25,25);
  TSB(TNode, %InFuse; OutPin; 10,10,13,13,25,25,25,25);
 %END;
%MACEND;

LINV(P13; L1);
NOR7ENABLE(%FF00, %SF00, P22, N1);
NOR8DFF(%FF320, N2, L2, P21);
NOR8DFF(%FF640, N3, L3, P20);
NOR8DFF(%FF960, N4, L4, P19);
NOR8DFF(%FF1280, N5, L5, P18);
NOR8DFF(%FF1600, N6, L6, P17);
NOR8DFF(%FF1920, N7, L7, P16);
NOR7ENABLE(%FF2240, %SF2240, P15, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:20R8
%PartNumber:PAL20R8A
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P23 ~P23  P3 ~P3 N1 ~N1 P4 ~P4 N2 ~N2 P5 ~P5 N3 ~N3 P6 ~P6
   N4 ~N4 P7 ~P7 N5 ~N5 P8 ~P8 N6 ~N6 P9 ~P9 N7 ~N7 P10 ~P10 N8 ~N8
   P11 ~P11 P14 ~P14 *

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
  LNOR(%InFuse,%InFuse+40,%InFuse+80,%InFuse+120,%InFuse+160,%InFuse+200,%InFuse+240,%InFuse+280;TLNode);
  DQFF(TLNode,P1;NodeInp;10,10,15,0,7,7,15,15,25,0,15,15);
  TSB(NodeInp,L1;OutPin;10,10,11,11,20,20,20,20);
%MACEND;

LINV(P13; L1);
NOR8DFF(%FF00, N1, L2, P22);
NOR8DFF(%FF320, N2, L3, P21);
NOR8DFF(%FF640, N3, L4, P20);
NOR8DFF(%FF960, N4, L5, P19);
NOR8DFF(%FF1280, N5, L6, P18);
NOR8DFF(%FF1600, N6, L7, P17);
NOR8DFF(%FF1920, N7, L8, P16);
NOR8DFF(%FF2240, N8, L9, P15);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:20R8
%PartNumber:PAL20R8A-2
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P23 ~P23  P3 ~P3 N1 ~N1 P4 ~P4 N2 ~N2 P5 ~P5 N3 ~N3 P6 ~P6
   N4 ~N4 P7 ~P7 N5 ~N5 P8 ~P8 N6 ~N6 P9 ~P9 N7 ~N7 P10 ~P10 N8 ~N8
   P11 ~P11 P14 ~P14 *

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
  LNOR(%InFuse,%InFuse+40,%InFuse+80,%InFuse+120,%InFuse+160,%InFuse+200,%InFuse+240,%InFuse+280;TLNode);
  DQFF(TLNode,P1;NodeInp;15,15,25,0,10,10,25,25,35,0,25,25);
  TSB(NodeInp,L1;OutPin;15,15,15,15,25,25,25,25);
%MACEND;

LINV(P13; L1);
NOR8DFF(%FF00, N1, L2, P22);
NOR8DFF(%FF320, N2, L3, P21);
NOR8DFF(%FF640, N3, L4, P20);
NOR8DFF(%FF960, N4, L5, P19);
NOR8DFF(%FF1280, N5, L6, P18);
NOR8DFF(%FF1600, N6, L7, P17);
NOR8DFF(%FF1920, N7, L8, P16);
NOR8DFF(%FF2240, N8, L9, P15);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:20R8
%PartNumber:PAL20R8B
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P23 ~P23  P3 ~P3 N1 ~N1 P4 ~P4 N2 ~N2 P5 ~P5 N3 ~N3 P6 ~P6
   N4 ~N4 P7 ~P7 N5 ~N5 P8 ~P8 N6 ~N6 P9 ~P9 N7 ~N7 P10 ~P10 N8 ~N8
   P11 ~P11 P14 ~P14 *

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
  LNOR(%InFuse,%InFuse+40,%InFuse+80,%InFuse+120,%InFuse+160,%InFuse+200,%InFuse+240,%InFuse+280;TLNode);
  DQFF(TLNode,P1;NodeInp;8,8,10,0,8,6,15,15,15,0,12,10);
  TSB(NodeInp,L1;OutPin;10,10,8,8,15,15,12,12);
%MACEND;

LINV(P13; L1);
NOR8DFF(%FF00, N1, L2, P22);
NOR8DFF(%FF320, N2, L3, P21);
NOR8DFF(%FF640, N3, L4, P20);
NOR8DFF(%FF960, N4, L5, P19);
NOR8DFF(%FF1280, N5, L6, P18);
NOR8DFF(%FF1600, N6, L7, P17);
NOR8DFF(%FF1920, N7, L8, P16);
NOR8DFF(%FF2240, N8, L9, P15);
%EndModel

;The registers on the following device reset upon power-up, whereby the
;active-low outputs are set to a logic High.
%StartModel
%Manufacturer:AMD
%Type:20R8
%PartNumber:PAL20R8B-2
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P23 ~P23  P3 ~P3 N1 ~N1 P4 ~P4 N2 ~N2 P5 ~P5 N3 ~N3 P6 ~P6
   N4 ~N4 P7 ~P7 N5 ~N5 P8 ~P8 N6 ~N6 P9 ~P9 N7 ~N7 P10 ~P10 N8 ~N8
   P11 ~P11 P14 ~P14 *

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
  LNOR(%InFuse,%InFuse+40,%InFuse+80,%InFuse+120,%InFuse+160,%InFuse+200,%InFuse+240,%InFuse+280;TLNode);
  DQFFC(TLNode,P1,IPL;NodeInp;10,10,15,0,10,10,1,1,1,1,15,15,25,0,15,15,1,1,1,1);
  TSB(NodeInp,L1;OutPin;10,10,11,11,20,20,20,20);
%MACEND;

LINV(P13; L1);
NOR8DFF(%FF00, N1, L2, P22);
NOR8DFF(%FF320, N2, L3, P21);
NOR8DFF(%FF640, N3, L4, P20);
NOR8DFF(%FF960, N4, L5, P19);
NOR8DFF(%FF1280, N5, L6, P18);
NOR8DFF(%FF1600, N6, L7, P17);
NOR8DFF(%FF1920, N7, L8, P16);
NOR8DFF(%FF2240, N8, L9, P15);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:20RA10
%PartNumber:PAL20RA10
%LastNode ? ?
%NumPins: 24
%FDF AND 0 P2 ~P2 P23 ~P23 P3 ~P3 P22 ~P22 P4 ~P4 P21 ~P21 P5 ~P5 P20 ~P20 P6 ~P6
           P19 ~P19 P7 ~P7 P18 ~P18 P8 ~P8 P17 ~P17  P9 ~P9 P16 ~P16 P10 ~P10  P15 ~P15
           P11 ~P11 P14 ~P14 *


%MACRO LOADMac(IO:%TEXT, IOBar:%TEXT, InFuse:%FF, TLNode1:%TEXT,
                   TLNode2:%TEXT, ResetLoadInput:%TEXT, TLNode3:%TEXT,
        	   SetLoadInput:%TEXT, XorFuse:%SF, TLNode:%TEXT, PClock:%TEXT,
                   RegOut:%TEXT, TLSet:%TEXT);

  LINV(IO; IOBar);
  LAND(P1, %InFuse+80; TLNode1);
  LAND(L1, IOBar; TLNode2);
  LNOR(TLNode1, TLNode2, IPH; ResetLoadInput);
  LINV(%InFuse+120; TLSet);
  LAND(P1, TLSet; TLNode3);
  LOR(TLNode2, TLNode3; SetLoadInput);

 %IF %XorFuse=1 %THEN
  LOR(%InFuse+160, %InFuse+200, %InFuse+240, %InFuse+280; TLNode);
 %ELSE
  LNOR(%InFuse+160, %InFuse+200, %InFuse+240, %InFuse+280; TLNode);
 %END;
  AND(%InFuse+40; PClock; 0,0,0,0);
  DQFFPC(TLNode, PClock, SetLoadInput, ResetLoadInput; RegOut; 17,17,10,0,13,13,22,27,15,0,30,30,20,0,20,20,35,40,35,0);
%MACEND;

%MACRO OUTPUTMac(InFuse:%FF, TLNode:%TEXT, RegOutput:%TEXT, Output:%TEXT,
                 TsbEnable:%TEXT, IO:%TEXT, EnableFuse:%SF, SETFuse:%SF,
		 RESETFuse:%SF);

%IF %SETFuse..%SETFuse+39 = 1 %THEN
 %IF %RESETFuse..%RESETFuse+39 = 1 %THEN

   %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
     ITSB(TLNode, L2; IO; 10,10,10,10,20,20,20,20);
   %ELSE
     AND(%InFuse, L2; TSBEnable; 18,18,30,30);
     ITSB(TLNode, TsbEnable; IO; 10,10,10,10,20,20,20,20);
   %END;

 %ELSE

   %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
     ITSB(RegOutput, L2; IO; 10,10,10,10,20,20,20,20);
   %ELSE
     AND(%InFuse, L2; TsbEnable; 18,18,30,30);
     ITSB(RegOutput, TsbEnable; IO; 10,10,10,10,20,20,20,20);
   %END;
 %END;
%ELSE
 %IF %RESETFuse..%RESETFuse+39 = 1 %THEN

   %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
     ITSB(RegOutput, L2; IO; 10,10,10,10,20,20,20,20);
   %ELSE
     AND(%InFuse, L2; TsbEnable; 18,18,30,30);
     ITSB(RegOutput, TsbEnable; IO; 10,10,10,10,20,20,20,20);
   %END;

 %ELSE

   %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
     ITSB(RegOutput, L2; IO; 10,10,10,10,20,20,20,20);
   %ELSE
     AND(%InFuse, L2; TsbEnable; 18,18,30,30);
     ITSB(RegOutput, TsbEnable; IO; 10,10,10,10,20,20,20,20);
   %END;
 %END;
%END;
%MACEND;

LINV(P1;L1);
LINV(P13;L2);

LOADMac(P23, L3, %FF00, L4, L5, L6, L7, L8, %SF3200, L9, N1, N2, L73);
LOADMac(P22, L10, %FF320, L11, L12, L13, L14, L15, %SF3201, L16, N3, N4, L74);
LOADMac(P21, L17, %FF640, L18, L19, L20, L21, L22, %SF3202, L23, N5, N6, L75);
LOADMac(P20, L24, %FF960, L25, L26, L27, L28, L29, %SF3203, L30, N7, N8, L76);
LOADMac(P19, L31, %FF1280, L32, L33, L34, L35, L36, %SF3204, L37, N9, N10, L77);
LOADMac(P18, L38, %FF1600, L39, L40, L41, L42, L43, %SF3205, L44, N11, N12, L78);
LOADMac(P17, L45, %FF1920, L46, L47, L48, L49, L50, %SF3206, L51, N13, N14, L79);
LOADMac(P16, L52, %FF2240, L53, L54, L55, L56, L57, %SF3207, L58, N15, N16, L80);
LOADMac(P15, L59, %FF2560, L60, L61, L62, L63, L64, %SF3208, L65, N17, N18, L81);
LOADMac(P14, L66, %FF2880, L67, L68, L69, L70, L71, %SF3209, L72, N19, N20, L82);

OUTPUTMac(%FF00, L9, N2, L83, N21, P23, %SF00, %SF120, %SF80);
OUTPUTMac(%FF320,L16, N4, L85, N22, P22, %SF320, %SF440, %SF400);
OUTPUTMac(%FF640, L23, N6, L87, N23, P21, %SF640, %SF760, %SF720);
OUTPUTMac(%FF960, L30, N8, L89, N24, P20, %SF960, %SF1080, %SF1040);
OUTPUTMac(%FF1280, L37, N10, L91, N25, P19, %SF1280, %SF1400, %SF1360);
OUTPUTMac(%FF1600, L44, N12, L93, N26, P18, %SF1600, %SF1720, %SF1680);
OUTPUTMac(%FF1920, L51, N14, L95, N27, P17, %SF1920, %SF2040, %SF2000);
OUTPUTMac(%FF2240, L58, N16, L97, N28, P16, %SF2240, %SF2360, %SF2320);
OUTPUTMac(%FF2560, L65, N18, L99, N29, P15, %SF2560, %SF2680, %SF2640);
OUTPUTMac(%FF2880, L72, N20, L100, N30, P14, %SF2880, %SF3000, %SF2960);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:24L10
%PartNumber:PAL24L10-10
%LastNode ? ?
%NumPins:28
%FDF AND 0 P2 ~P2 P28 ~P28 P3 ~P3 P27 ~P27 P4 ~P4 P1 ~P1 P5 ~P5 P25 ~P25
     P6 ~P6 P24 ~P24 P8 ~P8 P23 ~P23 P9 ~P9 P22 ~P22 P10 ~P10 P20 ~P20
     P11 ~P11 P19 ~P19 P12 ~P12 P18 ~P18 P13 ~P13 P17 ~P17 P14 ~P14
     P15 ~P15*

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+47 = 1 %THEN
  NOR(%InFuse+48, %InFuse+96, %InFuse+144, %InFuse+192, %InFuse+240,
      %InFuse+288, %InFuse+336; OutPin; 2,2,8,8);
 %ELSE
  NOR(%InFuse+48, %InFuse+96, %InFuse+144, %InFuse+192, %InFuse+240,
      %InFuse+288, %InFuse+336; OutPin; 2,2,8,8);
  TSB(TNode, %InFuse; OutPin; 3,3,3,3,10,10,10,10);
 %END;
%MACEND;

NOR7ENABLE(%SF00, %FF00, P26, N1);
NOR7ENABLE(%SF384, %FF384, P25, N2);
NOR7ENABLE(%SF768, %FF768, P24, N3);
NOR7ENABLE(%SF1152, %FF1152, P23, N4);
NOR7ENABLE(%SF1536, %FF1536, P22, N5);
NOR7ENABLE(%SF1920, %FF1920, P20, N6);
NOR7ENABLE(%SF2304, %FF2304, P19, N7);
NOR7ENABLE(%SF2688, %FF2688, P18, N8);
NOR7ENABLE(%SF3072, %FF3072, P17, N9);
NOR7ENABLE(%SF3456, %FF3456, P16, N10);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:24R10
%PartNumber:PAL24R10-10
%LastNode ? ?
%NumPins:28
%FDF AND 0 P2 ~P2 P28 ~P28 P3 ~P3 P27 ~P27 P4 ~P4 N1 ~N1 P5 ~P5 N2 ~N2
   P6 ~P6 N3 ~N3 P8 ~P8 N4 ~N4 P9 ~P9 N5 ~N5 P10 ~P10 N6 ~N6 P11 ~P11
   N7 ~N7 P12 ~P12 N8 ~N8 P13 ~P13 N9 ~N9 P14 ~P14 N10 ~N10*

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT,
               TSBInput:%TEXT);
  LNOR(%InFuse, %InFuse+48, %InFuse+96, %InFuse+144, %InFuse+192, %InFuse+240,
      %InFuse+288, %InFuse+336; TLNode);
  DQFFC(TLNode,P1,IPL;NodeInp;1,1,10,0,7,7,1,1,1,1,7,7,10,0,7,7,1,1,1,1);
  BUF(NodeInp; TSBInput; 1,1,1,1);
  TSB(TSBInput,L1;OutPin; 1,1,1,1,10,10,10,10);
%MACEND;

LINV(P15; L1);
NOR8DFF(%FF00, N1, L2, P26, N11);
NOR8DFF(%FF384, N2, L3, P25, N12);
NOR8DFF(%FF768, N3, L4, P24, N13);
NOR8DFF(%FF1152, N4, L5, P23, N14);
NOR8DFF(%FF1536, N5, L6, P22, N15);
NOR8DFF(%FF1920, N6, L7, P20, N16);
NOR8DFF(%FF2304, N7, L8, P19, N17);
NOR8DFF(%FF2688, N8, L10, P18, N18);
NOR8DFF(%FF3072, N9, L11, P17, N19);
NOR8DFF(%FF3456, N10, L12, P16, N20);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:24R4
%PartNumber:PAL24R4-10
%LastNode ? ?
%NumPins:28
%FDF AND 0 P2 ~P2 P28 ~P28 P3 ~P3 P27 ~P27 P4 ~P4 P26 ~P26 P5 ~P5 P25 P6 ~P6
   P24 ~P24 P8 ~P8 N1 ~N1 P9 ~P9 N2 ~N2 P10 ~P10 N3 ~N3 P11 ~P11 N4 ~N4
   P12 ~P12 P18 ~P18 P13 ~P13 P17 ~P17 P14 ~P14 P16 ~P16*

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT,
               TSBInput:%TEXT);
  LNOR(%InFuse, %InFuse+48, %InFuse+96, %InFuse+144, %InFuse+192, %InFuse+240,
      %InFuse+288, %InFuse+336; TLNode);
  DQFFC(TLNode,P1,IPL;NodeInp;1,1,10,0,7,7,1,1,1,1,7,7,10,0,7,7,1,1,1,1);
  BUF(NodeInp; TSBInput; 1,1,1,1);
  TSB(TSBInput,L1;OutPin; 1,1,1,1,10,10,10,10);
%MACEND;

%MACRO NOR7ENABLE(InFuse:%FF, EnableFuse:%SF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+47 = 1 %THEN
   NOR(%InFuse+48, %InFuse+96, %InFuse+144, %InFuse+192, %InFuse+240,
      %InFuse+288, %InFuse+336; OutPin; 2,2,8,8);
 %ELSE
   NOR(%InFuse+48, %InFuse+96, %InFuse+144, %InFuse+192, %InFuse+240,
      %InFuse+288, %InFuse+336; OutPin; 2,2,8,8);
   TSB(TNode, %InFuse; OutPin; 3,3,3,3,10,10,10,10);
 %END;
%MACEND;

LINV(P15; L1);
NOR7ENABLE(%FF00, %SF00, P26, N5);
NOR7ENABLE(%FF384, %SF384, P25, N6);
NOR7ENABLE(%FF768, %SF768, P24, N7);
NOR8DFF(%FF1152, N1, L2, P23, N8);
NOR8DFF(%FF1536, N2, L3, P22, N9);
NOR8DFF(%FF1920, N3, L4, P20, N10);
NOR8DFF(%FF2304, N4, L5, P19, N11);
NOR7ENABLE(%FF2688, %SF2688, P18, N12);
NOR7ENABLE(%FF3072, %SF3072, P17, N13);
NOR7ENABLE(%FF3456, %SF3456, P16, N14);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:24R8
%PartNumber:PAL24R8-10
%LastNode ? ?
%NumPins:28
%FDF AND 0 P2 ~P2 P28 ~P28 P3 ~P3 P27 ~P27 P4 ~P4 P26 ~P26 P5 ~P5 N1 ~N1
   P6 ~P6 N2 ~N2 P8 ~P8 N3 ~N3 P9 ~P9 N4 ~N4 P10 ~P10 N5 ~N5 P11 ~P11
   N6 ~N6 P12 ~P12 N7 ~N7 P13 ~P13 N8 ~N8 P14 ~P14 P16 ~P16 *

%MACRO NOR7ENABLE(InFuse:%FF, EnableFuse:%SF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+47 = 1 %THEN
   NOR(%InFuse+48, %InFuse+96, %InFuse+144, %InFuse+192, %InFuse+240,
      %InFuse+288, %InFuse+336; OutPin; 2,2,8,8);
 %ELSE
   NOR(%InFuse+48, %InFuse+96, %InFuse+144, %InFuse+192, %InFuse+240,
      %InFuse+288, %InFuse+336; TNode; 2,2,8,8);
   TSB(TNode, %InFuse; OutPin; 3,3,3,3,10,10,10,10);
 %END;
%MACEND;

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT,
               TSBInput:%TEXT);
  LNOR(%InFuse, %InFuse+48, %InFuse+96, %InFuse+144, %InFuse+192, %InFuse+240,
      %InFuse+288, %InFuse+336; TLNode);
  DQFFC(TLNode,P1,IPL;NodeInp;1,1,10,0,7,7,1,1,1,1,7,7,10,0,7,7,1,1,1,1);
  BUF(NodeInp; TSBInput; 1,1,1,1);
  TSB(TSBInput,L1;OutPin; 1,1,1,1,10,10,10,10);
%MACEND;

LINV(P15; L1);

NOR7ENABLE(%FF00, %SF00, P26, N9);
NOR8DFF(%FF384, N1, L2, P25, N10);
NOR8DFF(%FF768, N2, L3, P24, N11);
NOR8DFF(%FF1152, N3, L4, P23, N12);
NOR8DFF(%FF1536, N4, L5, P22, N13);
NOR8DFF(%FF1920, N5, L6, P20, N14);
NOR8DFF(%FF2304, N6, L7, P19, N15);
NOR8DFF(%FF2688, N7, L8, P18, N16);
NOR8DFF(%FF3072, N8, L9, P17, N17);
NOR7ENABLE(%FF3456, %SF3456, P16, N18);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:6L16
%PartNumber:PAL6L16A
%LastNode ? ?
%NumPins:24
%FDF AND 0 P4 ~P4 P5 ~P5 P6 ~P6 P7 ~P7 P8 ~P8 P9 ~P9 *

INV(%FF00; P1; 15,15,25,25);
INV(%FF12; P23; 15,15,25,25);
INV(%FF24; P2; 15,15,25,25);
INV(%FF36; P3; 15,15,25,25);
INV(%FF48; P22; 15,15,25,25);
INV(%FF60; P21; 15,15,25,25);
INV(%FF72; P20; 15,15,25,25);
INV(%FF84; P19; 15,15,25,25);
INV(%FF96; P18; 15,15,25,25);
INV(%FF108; P17; 15,15,25,25);
INV(%FF120; P16; 15,15,25,25);
INV(%FF132; P10; 15,15,25,25);
INV(%FF144; P15; 15,15,25,25);
INV(%FF156; P14; 15,15,25,25);
INV(%FF168; P11; 15,15,25,25);
INV(%FF180; P13; 15,15,25,25);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:8L14
%PartNumber:PAL8L14
%LastNode ? ?
%NumPins:24
%FDF AND 0 P3 ~P3 P4 ~P4 P5 ~P5 P6 ~P6 P7 ~P7 P8 ~P8 P9 ~P9 P10 ~P10 *

INV(%FF00; P1; 15,15,25,25);
INV(%FF16; P23; 15,15,25,25);
INV(%FF32; P2; 15,15,25,25);
INV(%FF48; P22; 15,15,25,25);
INV(%FF64; P21; 15,15,25,25);
INV(%FF80; P20; 15,15,25,25);
INV(%FF96; P19; 15,15,25,25);
INV(%FF112; P18; 15,15,25,25);
INV(%FF128; P17; 15,15,25,25);
INV(%FF144; P16; 15,15,25,25);
INV(%FF160; P15; 15,15,25,25);
INV(%FF176; P14; 15,15,25,25);
INV(%FF192; P11; 15,15,25,25);
INV(%FF208; P13; 15,15,25,25);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:20L8
%PartNumber:PALC20L8Z-35
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P23 ~P23 P4 ~P4 P21 ~P21 P5 ~P5 P20 ~P20
     P6 ~P6 P19 ~P19 P7 ~P7 P18 ~P18 P8 ~P8 P17 ~P17 P9 ~P9 P16 ~P16
     P10 ~P10 P14 ~P14 P11 ~P11 P13 ~P13 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
  NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
     %InFuse+240, %InFuse+280; OutPin; 30,30,35,35);
 %ELSE
  NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; TNode; 30,30,35,35);
  TSB(TNode, %InFuse; OutPin; 30,30,30,30,35,35,35,35);
 %END;
%MACEND;

NOR7ENABLE(%SF00, %FF00, P22, N1);
NOR7ENABLE(%SF320, %FF320, P21, N2);
NOR7ENABLE(%SF640, %FF640, P20, N3);
NOR7ENABLE(%SF960, %FF960, P19, N4);
NOR7ENABLE(%SF1280, %FF1280, P18, N5);
NOR7ENABLE(%SF1600, %FF1600, P17, N6);
NOR7ENABLE(%SF1920, %FF1920, P16, N7);
NOR7ENABLE(%SF2240, %FF2240, P15, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:20L8
%PartNumber:PALC20L8Z-45
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P23 ~P23 P4 ~P4 P21 ~P21 P5 ~P5 P20 ~P20
     P6 ~P6 P19 ~P19 P7 ~P7 P18 ~P18 P8 ~P8 P17 ~P17 P9 ~P9 P16 ~P16
     P10 ~P10 P14 ~P14 P11 ~P11 P13 ~P13 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
  NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
     %InFuse+240, %InFuse+280; OutPin; 40,40,45,45);
 %ELSE
  NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; TNode; 40,40,45,45);
  TSB(TNode, %InFuse; OutPin; 40,40,40,40,45,45,45,45);
 %END;
%MACEND;

NOR7ENABLE(%SF00, %FF00, P22, N1);
NOR7ENABLE(%SF320, %FF320, P21, N2);
NOR7ENABLE(%SF640, %FF640, P20, N3);
NOR7ENABLE(%SF960, %FF960, P19, N4);
NOR7ENABLE(%SF1280, %FF1280, P18, N5);
NOR7ENABLE(%SF1600, %FF1600, P17, N6);
NOR7ENABLE(%SF1920, %FF1920, P16, N7);
NOR7ENABLE(%SF2240, %FF2240, P15, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:20R4
%PartNumber:PALC20R4Z-35
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P23 ~P23  P3 ~P3 P22 ~P22 P4 ~P4 P21 ~P21 P5 ~P5 N3 ~N3 P6 ~P6
   N4 ~N4 P7 ~P7 N5 ~N5 P8 ~P8 N6 ~N6 P9 ~P9 P16 ~P16 P10 ~P10 P15 ~P15
   P11 ~P11 P14 ~P14 *

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
  LNOR(%InFuse,%InFuse+40,%InFuse+80,%InFuse+120,%InFuse+160,%InFuse+200,%InFuse+240,%InFuse+280;TLNode);
  DQFF(TLNode,P1;NodeInp;15,15,25,0,10,10,20,20,30,0,15,15);
  TSB(NodeInp,L1;OutPin;15,15,15,15,20,20,20,20);
%MACEND;

%MACRO NOR7ENABLE(InFuse:%FF, EnableFuse:%SF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; OutPin; 30,30,35,35);
 %ELSE
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; TNode; 30,30,35,35);
   TSB(TNode, %InFuse; OutPin; 30,30,30,30,35,35,35,35);
 %END;
%MACEND;

LINV(P13; L1);
NOR7ENABLE(%FF00, %SF00, P22, N1);
NOR7ENABLE(%FF320, %SF320, P21, N2);
NOR8DFF(%FF640, N3, L2, P20);
NOR8DFF(%FF960, N4, L3, P19);
NOR8DFF(%FF1280, N5, L4, P18);
NOR8DFF(%FF1600, N6, L5, P17);
NOR7ENABLE(%FF1920, %SF1920, P16, N7);
NOR7ENABLE(%FF2240, %SF2240, P15, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:20R4
%PartNumber:PALC20R4Z-45
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P23 ~P23  P3 ~P3 P22 ~P22 P4 ~P4 P21 ~P21 P5 ~P5 N3 ~N3 P6 ~P6
   N4 ~N4 P7 ~P7 N5 ~N5 P8 ~P8 N6 ~N6 P9 ~P9 P16 ~P16 P10 ~P10 P15 ~P15
   P11 ~P11 P14 ~P14 *

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
  LNOR(%InFuse,%InFuse+40,%InFuse+80,%InFuse+120,%InFuse+160,%InFuse+200,%InFuse+240,%InFuse+280;TLNode);
  DQFF(TLNode,P1;NodeInp;20,20,30,0,10,10,25,25,40,0,15,15);
  TSB(NodeInp,L1;OutPin;20,20,20,20,25,25,25,25);
%MACEND;

%MACRO NOR7ENABLE(InFuse:%FF, EnableFuse:%SF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; OutPin; 40,40,45,45);
 %ELSE
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; TNode; 40,40,45,45);
   TSB(TNode, %InFuse; OutPin; 40,40,40,40,45,45,45,45);
 %END;
%MACEND;

LINV(P13; L1);
NOR7ENABLE(%FF00, %SF00, P22, N1);
NOR7ENABLE(%FF320, %SF320, P21, N2);
NOR8DFF(%FF640, N3, L2, P20);
NOR8DFF(%FF960, N4, L3, P19);
NOR8DFF(%FF1280, N5, L4, P18);
NOR8DFF(%FF1600, N6, L5, P17);
NOR7ENABLE(%FF1920, %SF1920, P16, N7);
NOR7ENABLE(%FF2240, %SF2240, P15, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:20R6
%PartNumber:PALC20R6Z-35
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P23 ~P23  P3 ~P3 P22 ~P22 P4 ~P4 N2 ~N2 P5 ~P5 N3 ~N3 P6 ~P6
   N4 ~N4 P7 ~P7 N5 ~N5 P8 ~P8 N6 ~N6 P9 ~P9 N7 ~N7 P10 ~P10 P15 ~P15
   P11 ~P11 P14 ~P14 *

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
  LNOR(%InFuse,%InFuse+40,%InFuse+80,%InFuse+120,%InFuse+160,%InFuse+200,%InFuse+240,%InFuse+280;TLNode);
  DQFF(TLNode,P1;NodeInp;15,15,25,0,10,10,20,20,30,0,15,15);
  TSB(NodeInp,L1;OutPin;15,15,15,15,20,20,20,20);
%MACEND;

%MACRO NOR7ENABLE(InFuse:%FF, EnableFuse:%SF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; OutPin; 30,30,35,35);
 %ELSE
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; TNode; 30,30,35,35);
  TSB(TNode, %InFuse; OutPin; 30,30,30,30,35,35,35,35);
 %END;
%MACEND;

LINV(P13; L1);
NOR7ENABLE(%FF00, %SF00, P22, N1);
NOR8DFF(%FF320, N2, L2, P21);
NOR8DFF(%FF640, N3, L3, P20);
NOR8DFF(%FF960, N4, L4, P19);
NOR8DFF(%FF1280, N5, L5, P18);
NOR8DFF(%FF1600, N6, L6, P17);
NOR8DFF(%FF1920, N7, L7, P16);
NOR7ENABLE(%FF2240, %SF2240, P15, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:20R6
%PartNumber:PALC20R6Z-45
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P23 ~P23  P3 ~P3 P22 ~P22 P4 ~P4 N2 ~N2 P5 ~P5 N3 ~N3 P6 ~P6
   N4 ~N4 P7 ~P7 N5 ~N5 P8 ~P8 N6 ~N6 P9 ~P9 N7 ~N7 P10 ~P10 P15 ~P15
   P11 ~P11 P14 ~P14 *

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
  LNOR(%InFuse,%InFuse+40,%InFuse+80,%InFuse+120,%InFuse+160,%InFuse+200,%InFuse+240,%InFuse+280;TLNode);
  DQFF(TLNode,P1;NodeInp;20,20,30,0,10,10,25,25,40,0,15,15);
  TSB(NodeInp,L1;OutPin;20,20,20,20,25,25,25,25);
%MACEND;

%MACRO NOR7ENABLE(InFuse:%FF, EnableFuse:%SF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; OutPin; 40,40,45,45);
 %ELSE
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280; TNode; 40,40,45,45);
  TSB(TNode, %InFuse; OutPin; 40,40,40,40,45,45,45,45);
 %END;
%MACEND;

LINV(P13; L1);
NOR7ENABLE(%FF00, %SF00, P22, N1);
NOR8DFF(%FF320, N2, L2, P21);
NOR8DFF(%FF640, N3, L3, P20);
NOR8DFF(%FF960, N4, L4, P19);
NOR8DFF(%FF1280, N5, L5, P18);
NOR8DFF(%FF1600, N6, L6, P17);
NOR8DFF(%FF1920, N7, L7, P16);
NOR7ENABLE(%FF2240, %SF2240, P15, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:20R8
%PartNumber:PALC20R8Z-35
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P23 ~P23  P3 ~P3 N1 ~N1 P4 ~P4 N2 ~N2 P5 ~P5 N3 ~N3 P6 ~P6
   N4 ~N4 P7 ~P7 N5 ~N5 P8 ~P8 N6 ~N6 P9 ~P9 N7 ~N7 P10 ~P10 N8 ~N8
   P11 ~P11 P14 ~P14 *

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
  LNOR(%InFuse,%InFuse+40,%InFuse+80,%InFuse+120,%InFuse+160,%InFuse+200,%InFuse+240,%InFuse+280;TLNode);
  DQFF(TLNode,P1;NodeInp;15,15,25,0,10,10,20,20,30,0,15,15);
  TSB(NodeInp,L1;OutPin;15,15,15,15,20,20,20,20);
%MACEND;

LINV(P13; L1);
NOR8DFF(%FF00, N1, L2, P22);
NOR8DFF(%FF320, N2, L3, P21);
NOR8DFF(%FF640, N3, L4, P20);
NOR8DFF(%FF960, N4, L5, P19);
NOR8DFF(%FF1280, N5, L6, P18);
NOR8DFF(%FF1600, N6, L7, P17);
NOR8DFF(%FF1920, N7, L8, P16);
NOR8DFF(%FF2240, N8, L9, P15);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:20R8
%PartNumber:PALC20R8Z-45
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P23 ~P23  P3 ~P3 N1 ~N1 P4 ~P4 N2 ~N2 P5 ~P5 N3 ~N3 P6 ~P6
   N4 ~N4 P7 ~P7 N5 ~N5 P8 ~P8 N6 ~N6 P9 ~P9 N7 ~N7 P10 ~P10 N8 ~N8
   P11 ~P11 P14 ~P14 *

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
  LNOR(%InFuse,%InFuse+40,%InFuse+80,%InFuse+120,%InFuse+160,%InFuse+200,%InFuse+240,%InFuse+280;TLNode);
  DQFF(TLNode,P1;NodeInp;20,20,30,0,10,10,25,25,40,0,15,15);
  TSB(NodeInp,L1;OutPin;20,20,20,20,25,25,25,25);
%MACEND;

LINV(P13; L1);
NOR8DFF(%FF00, N1, L2, P22);
NOR8DFF(%FF320, N2, L3, P21);
NOR8DFF(%FF640, N3, L4, P20);
NOR8DFF(%FF960, N4, L5, P19);
NOR8DFF(%FF1280, N5, L6, P18);
NOR8DFF(%FF1600, N6, L7, P17);
NOR8DFF(%FF1920, N7, L8, P16);
NOR8DFF(%FF2240, N8, L9, P15);
%EndModel

;Delays for the following device are typical and maximum.
%StartModel
%Manufacturer:AMD
%Type:22V10
%PartNumber:PALC22V10H-25
%LastNode ? ?
%NumPins: 24
%FDF AND 0 P1 ~P1 N1 ~N1 P2 ~P2 N2 ~N2 P3 ~P3 N3 ~N3 P4 ~P4 N4 ~N4 P5 ~P5
     N5 ~N5 P6 ~P6 N6 ~N6 P7 ~P7 N7 ~N7 P8 ~P8 N8 ~N8 P9 ~P9 N9 ~N9
     P10 ~P10 N10 ~N10 P11 ~P11 P13 ~P13 *

%MACRO LOR16(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308,%InFuse+352,%InFuse+396,%InFuse+440,%InFuse+484,
     %InFuse+528,%InFuse+572,%InFuse+616,%InFuse+660; OutLNode);
%MACEND;

%MACRO LOR14(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308,%InFuse+352,%InFuse+396,%InFuse+440,%InFuse+484,
     %InFuse+528,%InFuse+572; OutLNode);
%MACEND;

%MACRO LOR12(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308,%InFuse+352,%InFuse+396,%InFuse+440,
     %InFuse+484; OutLNode);
%MACEND;

%MACRO LOR10(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308,%InFuse+352,%InFuse+396; OutLNode);
%MACEND;

%MACRO LOR8(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308; OutLNode);
%MACEND;

%MACRO V10Mac(S1:%SF, S0:%SF, FeedBack:%TEXT, OrOutput:%TEXT, TNode:%TEXT,
              OutPin:%TEXT, InFuse:%FF, EnableFuse:%SF, TLNode:%TEXT);
 %CASE %S1,%S0
   0:
     LOR(OrOutput, L21; TLNode);
     DQFFC(TLNode, P1, L22; TNode; 13,13,11,0,9,9,20,20,20,20,15,15,15,0,13,13,25,25,25,25);
    %IF %EnableFuse..%EnableFuse+43 = 1 %THEN
     INV(TNode; OutPin; 0,0,0,0);
    %ELSE
     ITSB(TNode, %InFuse; OutPin; 20,20,20,20,25,25,25,25);
    %END;
    INV(TNode; FeedBack; 0,0,0,0);
  |1:
     LOR(OrOutput, L21; TLNode);
     DQFFC(TLNode, P1, L22; TNode; 13,13,11,0,9,9,20,20,20,20,15,15,15,0,13,13,25,25,25,25);
    %IF %EnableFuse..%EnableFuse+43 = 1 %THEN
     BUF(TNode; OutPin; 0,0,0,0);
    %ELSE
     TSB(TNode, %InFuse; OutPin; 20,20,20,20,25,25,25,25);
    %END;
    INV(TNode; FeedBack; 0,0,0,0);
  |2:
    %IF %EnableFuse..%EnableFuse+43 = 1 %THEN
     INV(OrOutput; OutPin; 20,20,25,25);
    %ELSE
     INV(OrOutput; TNode; 20,20,25,25);
     TSB(TNode, %InFuse; OutPin; 20,20,20,20,25,25,25,25);
    %END;
    BUF(OutPin; FeedBack; 0,0,0,0);
  |3:
    %IF %EnableFuse..%EnableFuse+43 = 1 %THEN
     BUF(OrOutput; OutPin; 20,20,25,25);
    %ELSE
     BUF(OrOutput; TNode; 20,20,25,25);
     TSB(TNode, %InFuse; OutPin; 20,20,20,20,25,25,25,25);
    %END;
    BUF(OutPin; FeedBack; 0,0,0,0);
  %END;
%MACEND;

LAND(%FF5764; L21);
LNOR(%FF00, IPH; L22);

LOR8(%FF88, L1);
LOR10(%FF484, L2);
LOR12(%FF968, L3);
LOR14(%FF1540, L4);
LOR16(%FF2200, L5);
LOR16(%FF2948, L6);
LOR14(%FF3696, L7);
LOR12(%FF4356, L8);
LOR10(%FF4928, L9);
LOR8(%FF5412, L10);

V10Mac(%SF5809, %SF5808, N1, L1, N11, P23, %FF44, %SF44, L11);
V10Mac(%SF5811, %SF5810, N2, L2, N12, P22, %FF440, %SF440, L12);
V10Mac(%SF5813, %SF5812, N3, L3, N13, P21, %FF924, %SF924, L13);
V10Mac(%SF5815, %SF5814, N4, L4, N14, P20, %FF1496, %SF1496, L14);
V10Mac(%SF5817, %SF5816, N5, L5, N15, P19, %FF2156, %SF2156, L15);
V10Mac(%SF5819, %SF5818, N6, L6, N16, P18, %FF2904, %SF2904, L16);
V10Mac(%SF5821, %SF5820, N7, L7, N17, P17, %FF3652, %SF3652, L17);
V10Mac(%SF5823, %SF5822, N8, L8, N18, P16, %FF4312, %SF4312, L18);
V10Mac(%SF5825, %SF5824, N9, L9, N19, P15, %FF4884, %SF4884, L19);
V10Mac(%SF5827, %SF5826, N10, L10, N20, P14, %FF5368, %SF5368, L20);
%EndModel

;Delays for the following device are typical and maximum.
%StartModel
%Manufacturer:AMD
%Type:22V10
%PartNumber:PALC22V10H-35
%LastNode ? ?
%NumPins: 24
%FDF AND 0 P1 ~P1 N1 ~N1 P2 ~P2 N2 ~N2 P3 ~P3 N3 ~N3 P4 ~P4 N4 ~N4 P5 ~P5
     N5 ~N5 P6 ~P6 N6 ~N6 P7 ~P7 N7 ~N7 P8 ~P8 N8 ~N8 P9 ~P9 N9 ~N9
     P10 ~P10 N10 ~N10 P11 ~P11 P13 ~P13 *

%MACRO LOR16(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308,%InFuse+352,%InFuse+396,%InFuse+440,%InFuse+484,
     %InFuse+528,%InFuse+572,%InFuse+616,%InFuse+660; OutLNode);
%MACEND;

%MACRO LOR14(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308,%InFuse+352,%InFuse+396,%InFuse+440,%InFuse+484,
     %InFuse+528,%InFuse+572; OutLNode);
%MACEND;

%MACRO LOR12(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308,%InFuse+352,%InFuse+396,%InFuse+440,
     %InFuse+484; OutLNode);
%MACEND;

%MACRO LOR10(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308,%InFuse+352,%InFuse+396; OutLNode);
%MACEND;

%MACRO LOR8(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308; OutLNode);
%MACEND;

%MACRO V10Mac(S1:%SF, S0:%SF, FeedBack:%TEXT, OrOutput:%TEXT, TNode:%TEXT,
              OutPin:%TEXT, InFuse:%FF, EnableFuse:%SF, TLNode:%TEXT);
 %CASE %S1,%S0
   0:
     LOR(OrOutput, L21; TLNode);
     DQFFC(TLNode, P1, L22; TNode; 20,20,20,0,14,14,25,25,30,30,25,25,25,0,17,17,35,35,35,35);
    %IF %EnableFuse..%EnableFuse+43 = 1 %THEN
     INV(TNode; OutPin; 0,0,0,0);
    %ELSE
     ITSB(TNode, %InFuse; OutPin; 30,30,30,30,35,35,35,35);
    %END;
    INV(TNode; FeedBack; 0,0,0,0);
  |1:
     LOR(OrOutput, L21; TLNode);
     DQFFC(TLNode, P1, L22; TNode; 20,20,20,0,14,14,25,25,30,30,25,25,25,0,17,17,35,35,35,35);
    %IF %EnableFuse..%EnableFuse+43 = 1 %THEN
     BUF(TNode; OutPin; 0,0,0,0);
    %ELSE
     TSB(TNode, %InFuse; OutPin; 30,30,30,30,35,35,35,35);
    %END;
    INV(TNode; FeedBack; 0,0,0,0);
  |2:
    %IF %EnableFuse..%EnableFuse+43 = 1 %THEN
     INV(OrOutput; OutPin; 25,25,35,35);
    %ELSE
     INV(OrOutput; TNode; 25,25,35,35);
     TSB(TNode, %InFuse; OutPin; 30,30,30,30,35,35,35,35);
    %END;
    BUF(OutPin; FeedBack; 0,0,0,0);
  |3:
    %IF %EnableFuse..%EnableFuse+43 = 1 %THEN
     BUF(OrOutput; OutPin; 25,25,35,35);
    %ELSE
     BUF(OrOutput; TNode; 25,25,35,35);
     TSB(TNode, %InFuse; OutPin; 30,30,30,30,35,35,35,35);
    %END;
    BUF(OutPin; FeedBack; 0,0,0,0);
  %END;
%MACEND;

LAND(%FF5764; L21);
LNOR(%FF00, IPH; L22);

LOR8(%FF88, L1);
LOR10(%FF484, L2);
LOR12(%FF968, L3);
LOR14(%FF1540, L4);
LOR16(%FF2200, L5);
LOR16(%FF2948, L6);
LOR14(%FF3696, L7);
LOR12(%FF4356, L8);
LOR10(%FF4928, L9);
LOR8(%FF5412, L10);

V10Mac(%SF5809, %SF5808, N1, L1, N11, P23, %FF44, %SF44, L11);
V10Mac(%SF5811, %SF5810, N2, L2, N12, P22, %FF440, %SF440, L12);
V10Mac(%SF5813, %SF5812, N3, L3, N13, P21, %FF924, %SF924, L13);
V10Mac(%SF5815, %SF5814, N4, L4, N14, P20, %FF1496, %SF1496, L14);
V10Mac(%SF5817, %SF5816, N5, L5, N15, P19, %FF2156, %SF2156, L15);
V10Mac(%SF5819, %SF5818, N6, L6, N16, P18, %FF2904, %SF2904, L16);
V10Mac(%SF5821, %SF5820, N7, L7, N17, P17, %FF3652, %SF3652, L17);
V10Mac(%SF5823, %SF5822, N8, L8, N18, P16, %FF4312, %SF4312, L18);
V10Mac(%SF5825, %SF5824, N9, L9, N19, P15, %FF4884, %SF4884, L19);
V10Mac(%SF5827, %SF5826, N10, L10, N20, P14, %FF5368, %SF5368, L20);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16L8
%PartNumber:AMPAL16L8
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P18 ~P18 P4 ~P4 P17 ~P17 P5 ~P5 P16 ~P16
     P6 ~P6 P15 ~P15 P7 ~P7 P14 ~P14 P8 ~P8 P13 ~P13 P9 ~P9 P11 ~P11 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 23,23,35,35);
 %ELSE
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 23,23,35,35);
  TSB(TNode, %InFuse; OutPin; 23,23,23,23,35,35,35,35);
 %END;
%MACEND;

NOR7ENABLE(%SF00, %FF00, P19, N1);
NOR7ENABLE(%SF256, %FF256, P18, N2);
NOR7ENABLE(%SF512, %FF512, P17, N3);
NOR7ENABLE(%SF768, %FF768, P16, N4);
NOR7ENABLE(%SF1024, %FF1024, P15, N5);
NOR7ENABLE(%SF1280, %FF1280, P14, N6);
NOR7ENABLE(%SF1536, %FF1536, P13, N7);
NOR7ENABLE(%SF1792, %FF1792, P12, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16L8A
%PartNumber:AMPAL16L8A
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P18 ~P18 P4 ~P4 P17 ~P17 P5 ~P5 P16 ~P16
     P6 ~P6 P15 ~P15 P7 ~P7 P14 ~P14 P8 ~P8 P13 ~P13 P9 ~P9 P11 ~P11 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 17,17,25,25);
 %ELSE
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 17,17,25,25);
  TSB(TNode, %InFuse; OutPin; 17,17,17,17,25,25,25,25);
 %END;
%MACEND;

NOR7ENABLE(%SF00, %FF00, P19, N1);
NOR7ENABLE(%SF256, %FF256, P18, N2);
NOR7ENABLE(%SF512, %FF512, P17, N3);
NOR7ENABLE(%SF768, %FF768, P16, N4);
NOR7ENABLE(%SF1024, %FF1024, P15, N5);
NOR7ENABLE(%SF1280, %FF1280, P14, N6);
NOR7ENABLE(%SF1536, %FF1536, P13, N7);
NOR7ENABLE(%SF1792, %FF1792, P12, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16L8B
%PartNumber:AMPAL16L8B
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P18 ~P18 P4 ~P4 P17 ~P17 P5 ~P5 P16 ~P16
     P6 ~P6 P15 ~P15 P7 ~P7 P14 ~P14 P8 ~P8 P13 ~P13 P9 ~P9 P11 ~P11 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 12,12,15,15);
 %ELSE
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 12,12,15,15);
  TSB(TNode, %InFuse; OutPin; 12,12,12,12,15,15,15,15);
 %END;
%MACEND;

NOR7ENABLE(%SF00, %FF00, P19, N1);
NOR7ENABLE(%SF256, %FF256, P18, N2);
NOR7ENABLE(%SF512, %FF512, P17, N3);
NOR7ENABLE(%SF768, %FF768, P16, N4);
NOR7ENABLE(%SF1024, %FF1024, P15, N5);
NOR7ENABLE(%SF1280, %FF1280, P14, N6);
NOR7ENABLE(%SF1536, %FF1536, P13, N7);
NOR7ENABLE(%SF1792, %FF1792, P12, N8);
%EndModel

;The registers on the following device reset upon power-up, whereby the
;active-low outputs are set to a logic High.
%StartModel
%Manufacturer:AMD
%Type:16R4
%PartNumber:AMPAL16R4
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P19 ~P19 P3 ~P3 P18 ~P18 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 P13 ~P13 P9 ~P9 P12 ~P12 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 23,23,35,35);
 %ELSE
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 23,23,35,35);
  TSB(TNode, %InFuse; OutPin; 23,23,23,23,35,35,35,35);
 %END;
%MACEND;

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 DQFFC(TLNode,P1,IPL;NodeInp;17,17,20,0,25,25,1,1,1,1,25,25,30,0,25,25,1,1,1,1);
 TSB(NodeInp,L1;OutPin;17,17,17,17,25,25,25,25);
%MACEND;

LINV(P11;L1);
NOR7ENABLE(%SF00, %FF00, P19, N1);
NOR7ENABLE(%SF256, %FF256, P18, N2);
NOR8DFF(%FF512, N3, L2, P17);
NOR8DFF(%FF768, N4, L3, P16);
NOR8DFF(%FF1024, N5, L4, P15);
NOR8DFF(%FF1280, N6, L5, P14);
NOR7ENABLE(%SF1536, %FF1536, P13, N7);
NOR7ENABLE(%SF1792, %FF1792, P12, N8);
%EndModel

;The registers on the following device reset upon power-up, whereby the
;active-low outputs are set to a logic High.
%StartModel
%Manufacturer:AMD
%Type:16R4
%PartNumber:AMPAL16R4A
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P19 ~P19 P3 ~P3 P18 ~P18 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 P13 ~P13 P9 ~P9 P12 ~P12 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 17,17,25,25);
 %ELSE
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 17,17,25,25);
  TSB(TNode, %InFuse; OutPin; 17,17,17,17,25,25,25,25);
 %END;
%MACEND;

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 DQFFC(TLNode,P1,IPL;NodeInp;12,12,15,0,15,15,1,1,1,1,15,15,20,0,15,15,1,1,1,1);
 TSB(NodeInp,L1;OutPin;12,12,12,12,20,20,20,20);
%MACEND;

LINV(P11;L1);
NOR7ENABLE(%SF00, %FF00, P19, N1);
NOR7ENABLE(%SF256, %FF256, P18, N2);
NOR8DFF(%FF512, N3, L2, P17);
NOR8DFF(%FF768, N4, L3, P16);
NOR8DFF(%FF1024, N5, L4, P15);
NOR8DFF(%FF1280, N6, L5, P14);
NOR7ENABLE(%SF1536, %FF1536, P13, N7);
NOR7ENABLE(%SF1792, %FF1792, P12, N8);
%EndModel

;The registers on the following device reset upon power-up, whereby the
;active-low outputs are set to a logic High.
%StartModel
%Manufacturer:AMD
%Type:16R4
%PartNumber:AMPAL16R4B
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P19 ~P19 P3 ~P3 P18 ~P18 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 P13 ~P13 P9 ~P9 P12 ~P12 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 12,12,15,15);
 %ELSE
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 12,12,15,15);
  TSB(TNode, %InFuse; OutPin; 12,12,12,12,15,15,15,15);
 %END;
%MACEND;

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 DQFFC(TLNode,P1,IPL;NodeInp;8,8,10,0,10,10,1,1,1,1,12,12,13,0,10,10,1,1,1,1);
 TSB(NodeInp,L1;OutPin;8,8,8,8,15,15,15,15);
%MACEND;

LINV(P11;L1);
NOR7ENABLE(%SF00, %FF00, P19, N1);
NOR7ENABLE(%SF256, %FF256, P18, N2);
NOR8DFF(%FF512, N3, L2, P17);
NOR8DFF(%FF768, N4, L3, P16);
NOR8DFF(%FF1024, N5, L4, P15);
NOR8DFF(%FF1280, N6, L5, P14);
NOR7ENABLE(%SF1536, %FF1536, P13, N7);
NOR7ENABLE(%SF1792, %FF1792, P12, N8);
%EndModel

;The registers on the following device reset upon power-up, whereby the
;active-low outputs are set to a logic High.
%StartModel
%Manufacturer:AMD
%Type:16R6
%PartNumber:AMPAL16R6
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P19 ~P19 P3 ~P3 N2 ~N2 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 N7 ~N7 P9 ~P9 P12 ~P12 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 23,23,35,35);
 %ELSE
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 23,23,35,35);
  TSB(TNode, %InFuse; OutPin; 23,23,23,23,35,35,35,35);
 %END;
%MACEND;

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 DQFFC(TLNode,P1,IPL;NodeInp;17,17,20,0,25,25,1,1,1,1,25,25,30,0,25,25,1,1,1,1);
 TSB(NodeInp,L1;OutPin;17,17,17,17,25,25,25,25);
%MACEND;

LINV(P11;L1);
NOR7ENABLE(%SF00, %FF00, P19, N1);
NOR8DFF(%FF256, N2, L2, P18);
NOR8DFF(%FF512, N3, L3, P17);
NOR8DFF(%FF768, N4, L4, P16);
NOR8DFF(%FF1024, N5, L5, P15);
NOR8DFF(%FF1280, N6, L6, P14);
NOR8DFF(%FF1536, N7, L7, P13);
NOR7ENABLE(%SF1792, %FF1792, P12, N8);
%EndModel

;The registers on the following device reset upon power-up, whereby the
;active-low outputs are set to a logic High.
%StartModel
%Manufacturer:AMD
%Type:16R6
%PartNumber:AMPAL16R6A
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P19 ~P19 P3 ~P3 N2 ~N2 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 N7 ~N7 P9 ~P9 P12 ~P12 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 17,17,25,25);
 %ELSE
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 17,17,25,25);
  TSB(TNode, %InFuse; OutPin; 17,17,17,17,25,25,25,25);
 %END;
%MACEND;

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 DQFFC(TLNode,P1,IPL;NodeInp;12,12,15,10,15,15,1,1,1,1,15,15,20,0,15,15,1,1,1,1);
 TSB(NodeInp,L1;OutPin;12,12,12,12,20,20,20,20);
%MACEND;

LINV(P11;L1);
NOR7ENABLE(%SF00, %FF00, P19, N1);
NOR8DFF(%FF256, N2, L2, P18);
NOR8DFF(%FF512, N3, L3, P17);
NOR8DFF(%FF768, N4, L4, P16);
NOR8DFF(%FF1024, N5, L5, P15);
NOR8DFF(%FF1280, N6, L6, P14);
NOR8DFF(%FF1536, N7, L7, P13);
NOR7ENABLE(%SF1792, %FF1792, P12, N8);
%EndModel

;The registers on the following device reset upon power-up, whereby the
;active-low outputs are set to a logic High.
%StartModel
%Manufacturer:AMD
%Type:16R6
%PartNumber:AMPAL16R6B
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P19 ~P19 P3 ~P3 N2 ~N2 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 N7 ~N7 P9 ~P9 P12 ~P12 *

%MACRO NOR7ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; OutPin; 12,12,15,15);
 %ELSE
  NOR(%InFuse+32, %InFuse+64, %InFuse+96, %InFuse+128, %InFuse+160,
     %InFuse+192, %InFuse+224; TNode; 12,12,15,15);
  TSB(TNode, %InFuse; OutPin; 12,12,12,12,15,15,15,15);
 %END;
%MACEND;

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 DQFFC(TLNode,P1,IPL;NodeInp;8,8,10,0,10,10,1,1,1,1,12,12,13,0,10,10,1,1,1,1);
 TSB(NodeInp,L1;OutPin;8,8,8,8,15,15,15,15);
%MACEND;

LINV(P11;L1);
NOR7ENABLE(%SF00, %FF00, P19, N1);
NOR8DFF(%FF256, N2, L2, P18);
NOR8DFF(%FF512, N3, L3, P17);
NOR8DFF(%FF768, N4, L4, P16);
NOR8DFF(%FF1024, N5, L5, P15);
NOR8DFF(%FF1280, N6, L6, P14);
NOR8DFF(%FF1536, N7, L7, P13);
NOR7ENABLE(%SF1792, %FF1792, P12, N8);
%EndModel

;The registers on the following device reset upon power-up, whereby the
;active-low outputs are set to a logic High.
%StartModel
%Manufacturer:AMD
%Type:16R8
%PartNumber:AMPAL16R8
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 N1 ~N1 P3 ~P3 N2 ~N2 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 N7 ~N7 P9 ~P9 N8 ~N8 *

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 DQFFC(TLNode,P1,IPL;NodeInp;17,17,20,0,25,25,1,1,1,1,25,25,30,0,25,25,1,1,1,1);
 TSB(NodeInp,L1;OutPin;17,17,17,17,25,25,25,25);
%MACEND;

LINV(P11;L1);
NOR8DFF(%FF00, N1, L2, P19);
NOR8DFF(%FF256, N2, L3, P18);
NOR8DFF(%FF512, N3, L4, P17);
NOR8DFF(%FF768, N4, L5, P16);
NOR8DFF(%FF1024, N5, L6, P15);
NOR8DFF(%FF1280, N6, L7, P14);
NOR8DFF(%FF1536, N7, L8, P13);
NOR8DFF(%FF1792, N8, L9, P12);
%EndModel

;The registers on the following device reset upon power-up, whereby the
;active-low outputs are set to a logic High.
%StartModel
%Manufacturer:AMD
%Type:16R8
%PartNumber:AMPAL16R8A
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 N1 ~N1 P3 ~P3 N2 ~N2 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 N7 ~N7 P9 ~P9 N8 ~N8 *

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 DQFFC(TLNode,P1,IPL;NodeInp;12,12,15,0,15,15,1,1,1,1,15,15,20,0,15,15,1,1,1,1);
 TSB(NodeInp,L1;OutPin;12,12,12,12,20,20,20,20);
%MACEND;

LINV(P11;L1);
NOR8DFF(%FF00, N1, L2, P19);
NOR8DFF(%FF256, N2, L3, P18);
NOR8DFF(%FF512, N3, L4, P17);
NOR8DFF(%FF768, N4, L5, P16);
NOR8DFF(%FF1024, N5, L6, P15);
NOR8DFF(%FF1280, N6, L7, P14);
NOR8DFF(%FF1536, N7, L8, P13);
NOR8DFF(%FF1792, N8, L9, P12);
%EndModel

;The registers on the following device reset upon power-up, whereby the
;active-low outputs are set to a logic High.
%StartModel
%Manufacturer:AMD
%Type:16R8
%PartNumber:AMPAL16R8B
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 N1 ~N1 P3 ~P3 N2 ~N2 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4
     P6 ~P6 N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 N7 ~N7 P9 ~P9 N8 ~N8 *

%MACRO NOR8DFF(InFuse:%FF, NodeInp:%TEXT, TLNode:%TEXT, OutPin:%TEXT);
 LNOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,%InFuse+192,%InFuse+224;TLNode);
 DQFFC(TLNode,P1,IPL;NodeInp;8,8,10,0,10,10,1,1,1,1,12,12,13,0,10,10,1,1,1,1);
 TSB(NodeInp,L1;OutPin;8,8,8,8,15,15,15,15);
%MACEND;

LINV(P11;L1);
NOR8DFF(%FF00, N1, L2, P19);
NOR8DFF(%FF256, N2, L3, P18);
NOR8DFF(%FF512, N3, L4, P17);
NOR8DFF(%FF768, N4, L5, P16);
NOR8DFF(%FF1024, N5, L6, P15);
NOR8DFF(%FF1280, N6, L7, P14);
NOR8DFF(%FF1536, N7, L8, P13);
NOR8DFF(%FF1792, N8, L9, P12);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:18P8
%PartNumber:AMPAL18P8A
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P18 ~P18 P4 ~P4 P17 ~P17 P5 ~P5 P16 ~P16 P6 ~P6
   P15 ~P15 P7 ~P7 P14 ~P14 P8 ~P8 P13 ~P13 P9 ~P9 P11 ~P11 P19 ~P19 P12 ~P12 *

%MACRO POR8ENABLE(EnableFuse:%SF, InFuse:%FF, XorFuse:%SF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+35 = 1 %THEN
  %IF %XorFuse = 0 %THEN
   NOR(%InFuse+36, %InFuse+72, %InFuse+108, %InFuse+144, %InFuse+180,
      %InFuse+216, %InFuse+252, %InFuse+288; OutPin; 15,15,25,25);
  %ELSE
   OR(%InFuse+36, %InFuse+72, %InFuse+108, %InFuse+144, %InFuse+180,
       %InFuse+216, %InFuse+252, %InFuse+288; OutPin; 15,15,25,25);
  %END;
 %ELSE
  %IF %XorFuse = 0 %THEN
   NOR(%InFuse+36, %InFuse+72, %InFuse+108, %InFuse+144, %InFuse+180,
      %InFuse+216, %InFuse+252, %InFuse+288; TNode; 15,15,25,25);
  %ELSE
   OR(%InFuse+36, %InFuse+72, %InFuse+108, %InFuse+144, %InFuse+180,
     %InFuse+216, %InFuse+252, %InFuse+288; TNode; 15,15,25,25);
  %END;
  TSB(TNode, %InFuse; OutPin; 15,15,15,15,25,25,25,25);
 %END;
%MACEND;

POR8ENABLE(%SF00, %FF00, %SF2592, P19, N1);
POR8ENABLE(%SF324, %FF324, %SF2593, P18, N2);
POR8ENABLE(%SF648, %FF648, %SF2594, P17, N3);
POR8ENABLE(%SF972, %FF972, %SF2595, P16, N4);
POR8ENABLE(%SF1296, %FF1296, %SF2596, P15, N5);
POR8ENABLE(%SF1620, %FF1620, %SF2597, P14, N6);
POR8ENABLE(%SF1944, %FF1944, %SF2598, P13, N7);
POR8ENABLE(%SF2268, %FF2268, %SF2599, P12, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:18P8
%PartNumber:AMPAL18P8B
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P18 ~P18 P4 ~P4 P17 ~P17 P5 ~P5 P16 ~P16 P6 ~P6
   P15 ~P15 P7 ~P7 P14 ~P14 P8 ~P8 P13 ~P13 P9 ~P9 P11 ~P11 P19 ~P19 P12 ~P12 *

%MACRO POR8ENABLE(EnableFuse:%SF, InFuse:%FF, XorFuse:%SF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+35 = 1 %THEN
  %IF %XorFuse = 0 %THEN
   NOR(%InFuse+36, %InFuse+72, %InFuse+108, %InFuse+144, %InFuse+180,
      %InFuse+216, %InFuse+252, %InFuse+288; OutPin; 12,12,15,15);
  %ELSE
   OR(%InFuse+36, %InFuse+72, %InFuse+108, %InFuse+144, %InFuse+180,
       %InFuse+216, %InFuse+252, %InFuse+288; OutPin; 12,12,15,15);
  %END;
 %ELSE
  %IF %XorFuse = 0 %THEN
   NOR(%InFuse+36, %InFuse+72, %InFuse+108, %InFuse+144, %InFuse+180,
      %InFuse+216, %InFuse+252, %InFuse+288; TNode; 12,12,15,15);
  %ELSE
   OR(%InFuse+36, %InFuse+72, %InFuse+108, %InFuse+144, %InFuse+180,
     %InFuse+216, %InFuse+252, %InFuse+288; TNode; 12,12,15,15);
  %END;
  TSB(TNode, %InFuse; OutPin; 12,12,12,12,15,15,15,15);
 %END;
%MACEND;

POR8ENABLE(%SF00, %FF00, %SF2592, P19, N1);
POR8ENABLE(%SF324, %FF324, %SF2593, P18, N2);
POR8ENABLE(%SF648, %FF648, %SF2594, P17, N3);
POR8ENABLE(%SF972, %FF972, %SF2595, P16, N4);
POR8ENABLE(%SF1296, %FF1296, %SF2596, P15, N5);
POR8ENABLE(%SF1620, %FF1620, %SF2597, P14, N6);
POR8ENABLE(%SF1944, %FF1944, %SF2598, P13, N7);
POR8ENABLE(%SF2268, %FF2268, %SF2599, P12, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:18P8
%PartNumber:AMPAL18P8L
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P18 ~P18 P4 ~P4 P17 ~P17 P5 ~P5 P16 ~P16 P6 ~P6
   P15 ~P15 P7 ~P7 P14 ~P14 P8 ~P8 P13 ~P13 P9 ~P9 P11 ~P11 P19 ~P19 P12 ~P12 *

%MACRO POR8ENABLE(EnableFuse:%SF, InFuse:%FF, XorFuse:%SF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+35 = 1 %THEN
  %IF %XorFuse = 0 %THEN
   NOR(%InFuse+36, %InFuse+72, %InFuse+108, %InFuse+144, %InFuse+180,
      %InFuse+216, %InFuse+252, %InFuse+288; OutPin; 25,25,35,35);
  %ELSE
   OR(%InFuse+36, %InFuse+72, %InFuse+108, %InFuse+144, %InFuse+180,
       %InFuse+216, %InFuse+252, %InFuse+288; OutPin; 25,25,35,35);
  %END;
 %ELSE
  %IF %XorFuse = 0 %THEN
   NOR(%InFuse+36, %InFuse+72, %InFuse+108, %InFuse+144, %InFuse+180,
      %InFuse+216, %InFuse+252, %InFuse+288; TNode; 25,25,35,35);
  %ELSE
   OR(%InFuse+36, %InFuse+72, %InFuse+108, %InFuse+144, %InFuse+180,
     %InFuse+216, %InFuse+252, %InFuse+288; TNode; 25,25,35,35);
  %END;
  TSB(TNode, %InFuse; OutPin; 25,25,25,25,35,35,35,35);
 %END;
%MACEND;

POR8ENABLE(%SF00, %FF00, %SF2592, P19, N1);
POR8ENABLE(%SF324, %FF324, %SF2593, P18, N2);
POR8ENABLE(%SF648, %FF648, %SF2594, P17, N3);
POR8ENABLE(%SF972, %FF972, %SF2595, P16, N4);
POR8ENABLE(%SF1296, %FF1296, %SF2596, P15, N5);
POR8ENABLE(%SF1620, %FF1620, %SF2597, P14, N6);
POR8ENABLE(%SF1944, %FF1944, %SF2598, P13, N7);
POR8ENABLE(%SF2268, %FF2268, %SF2599, P12, N8);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:18P8
%PartNumber:AMPAL18P8Q
%LastNode ? ?
%NumPins:20
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P18 ~P18 P4 ~P4 P17 ~P17 P5 ~P5 P16 ~P16 P6 ~P6
   P15 ~P15 P7 ~P7 P14 ~P14 P8 ~P8 P13 ~P13 P9 ~P9 P11 ~P11 P19 ~P19 P12 ~P12 *

%MACRO POR8ENABLE(EnableFuse:%SF, InFuse:%FF, XorFuse:%SF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+35 = 1 %THEN
  %IF %XorFuse = 0 %THEN
   NOR(%InFuse+36, %InFuse+72, %InFuse+108, %InFuse+144, %InFuse+180,
      %InFuse+216, %InFuse+252, %InFuse+288; OutPin; 25,25,35,35);
  %ELSE
   OR(%InFuse+36, %InFuse+72, %InFuse+108, %InFuse+144, %InFuse+180,
       %InFuse+216, %InFuse+252, %InFuse+288; OutPin; 25,25,35,35);
  %END;
 %ELSE
  %IF %XorFuse = 0 %THEN
   NOR(%InFuse+36, %InFuse+72, %InFuse+108, %InFuse+144, %InFuse+180,
      %InFuse+216, %InFuse+252, %InFuse+288; TNode; 25,25,35,35);
  %ELSE
   OR(%InFuse+36, %InFuse+72, %InFuse+108, %InFuse+144, %InFuse+180,
     %InFuse+216, %InFuse+252, %InFuse+288; TNode; 25,25,35,35);
  %END;
  TSB(TNode, %InFuse; OutPin; 25,25,25,25,35,35,35,35);
 %END;
%MACEND;

POR8ENABLE(%SF00, %FF00, %SF2592, P19, N1);
POR8ENABLE(%SF324, %FF324, %SF2593, P18, N2);
POR8ENABLE(%SF648, %FF648, %SF2594, P17, N3);
POR8ENABLE(%SF972, %FF972, %SF2595, P16, N4);
POR8ENABLE(%SF1296, %FF1296, %SF2596, P15, N5);
POR8ENABLE(%SF1620, %FF1620, %SF2597, P14, N6);
POR8ENABLE(%SF1944, %FF1944, %SF2598, P13, N7);
POR8ENABLE(%SF2268, %FF2268, %SF2599, P12, N8);
%EndModel

;Values for the 20L10-20 are not given for the "other"delays.
;Values for "Max" delays are used for both cases.
%StartModel
%Manufacturer:AMD
%Type:20L10
%PartNumber:AMPAL20L10-20
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P22 ~P22 P4 ~P4 P21 ~P21 P5 ~P5 P20 ~P20
     P6 ~P6 P19 ~P19 P7 ~P7 P18 ~P18 P8 ~P8 P17 ~P17 P9 ~P9 P16 ~P16
     P10 ~P10 P15 ~P15 P11 ~P11 P13 ~P13 *

%MACRO NOR3ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
  NOR(%InFuse+40, %InFuse+80, %InFuse+120; OutPin; 20,20,20,20);
 %ELSE
  NOR(%InFuse+40, %InFuse+80, %InFuse+120; TNode; 20,20,20,20);
  TSB(TNode, %InFuse; OutPin; 20,20,20,20,20,20,20,20);
 %END;
%MACEND;

NOR3ENABLE(%SF00, %FF00, P23, N1);
NOR3ENABLE(%SF160, %FF160, P22, N2);
NOR3ENABLE(%SF320, %FF320, P21, N3);
NOR3ENABLE(%SF480, %FF480, P20, N4);
NOR3ENABLE(%SF640, %FF640, P19, N5);
NOR3ENABLE(%SF800, %FF800, P18, N6);
NOR3ENABLE(%SF960, %FF960, P17, N7);
NOR3ENABLE(%SF1120, %FF1120, P16, N8);
NOR3ENABLE(%SF1280, %FF1280, P15, N9);
NOR3ENABLE(%SF1440, %FF1440, P14, N10);
%EndModel

;Values for the 20L10AL are not given for the "other"delays.
;Values for "Max" delays are used for both cases.
%StartModel
%Manufacturer:AMD
%Type:20L10
%PartNumber:AMPAL20L10AL
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P22 ~P22 P4 ~P4 P21 ~P21 P5 ~P5 P20 ~P20
     P6 ~P6 P19 ~P19 P7 ~P7 P18 ~P18 P8 ~P8 P17 ~P17 P9 ~P9 P16 ~P16
     P10 ~P10 P15 ~P15 P11 ~P11 P13 ~P13 *

%MACRO NOR3ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
  NOR(%InFuse+40, %InFuse+80, %InFuse+120; OutPin; 25,25,25,25);
 %ELSE
  NOR(%InFuse+40, %InFuse+80, %InFuse+120; TNode; 25,25,25,25);
  TSB(TNode, %InFuse; OutPin; 25,25,25,25,25,25,25,25);
 %END;
%MACEND;

NOR3ENABLE(%SF00, %FF00, P23, N1);
NOR3ENABLE(%SF160, %FF160, P22, N2);
NOR3ENABLE(%SF320, %FF320, P21, N3);
NOR3ENABLE(%SF480, %FF480, P20, N4);
NOR3ENABLE(%SF640, %FF640, P19, N5);
NOR3ENABLE(%SF800, %FF800, P18, N6);
NOR3ENABLE(%SF960, %FF960, P17, N7);
NOR3ENABLE(%SF1120, %FF1120, P16, N8);
NOR3ENABLE(%SF1280, %FF1280, P15, N9);
NOR3ENABLE(%SF1440, %FF1440, P14, N10);
%EndModel

;Values for the 20L10B are not given for the "other"delays.
;Values for "Max" delays are used for both cases.
%StartModel
%Manufacturer:AMD
%Type:20L10
%PartNumber:AMPAL20L10B
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P1 ~P1 P3 ~P3 P22 ~P22 P4 ~P4 P21 ~P21 P5 ~P5 P20 ~P20
     P6 ~P6 P19 ~P19 P7 ~P7 P18 ~P18 P8 ~P8 P17 ~P17 P9 ~P9 P16 ~P16
     P10 ~P10 P15 ~P15 P11 ~P11 P13 ~P13 *

%MACRO NOR3ENABLE(EnableFuse:%SF, InFuse:%FF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
  NOR(%InFuse+40, %InFuse+80, %InFuse+120; OutPin; 15,15,15,15);
 %ELSE
  NOR(%InFuse+40, %InFuse+80, %InFuse+120; TNode; 15,15,15,15);
  TSB(TNode, %InFuse; OutPin; 18,18,15,15,18,18,15,15);
 %END;
%MACEND;

NOR3ENABLE(%SF00, %FF00, P23, N1);
NOR3ENABLE(%SF160, %FF160, P22, N2);
NOR3ENABLE(%SF320, %FF320, P21, N3);
NOR3ENABLE(%SF480, %FF480, P20, N4);
NOR3ENABLE(%SF640, %FF640, P19, N5);
NOR3ENABLE(%SF800, %FF800, P18, N6);
NOR3ENABLE(%SF960, %FF960, P17, N7);
NOR3ENABLE(%SF1120, %FF1120, P16, N8);
NOR3ENABLE(%SF1280, %FF1280, P15, N9);
NOR3ENABLE(%SF1440, %FF1440, P14, N10);
%EndModel


;Values for the 20XRP10 FAMILY (20XRP10,20XRP4,20XRP6,20XRP8)
;are not given for the "other"delays.
;Values for "Max" delays are used for both cases.

;The registers on the following device reset upon power-up, whereby the
;active-low outputs are set to a logic High.
%StartModel
%Manufacturer:AMD
%Type:20XRP10
%PartNumber:AMPAL20XRP10-20
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 ~N1 N1 P3 ~P3 ~N2 N2 P4 ~P4 ~N3 N3 P5 ~P5 ~N4 N4
           P6 ~P6 ~N5 N5 P7 ~P7 ~N6 N6 P8 ~P8 ~N7 N7 P9 ~P9 ~N8 N8
           P10 ~P10 ~N9 N9 P11 ~P11 ~N10 N10 *


%MACRO PXDFF(XorFuse:%SF, InFuse:%FF, TL1:%TEXT, TL2:%TEXT, TL3:%TEXT, TN1:%TEXT, OutPin:%TEXT);
  LOR(%InFuse, %InFuse+40; TL1);
  LOR(%InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200, %InFuse+240, %InFuse+280; TL2);
  %IF %XorFuse=0 %THEN
   LXOR(TL1, TL2; TL3);
  %ELSE
   LXNOR(TL1, TL2; TL3);
  %END;
  DQFFC(TL3, P1, IPL; TN1; 13,13,20,0,10,10,1,1,1,1,13,13,20,0,10,10,1,1,1,1);
  ITSB(TN1, L1; OutPin; 15,15,15,15,15,15,15,15);
%MACEND;

LINV(P13; L1);

PXDFF(%SF3200, %FF00, L2, L3, L4, N1, P23);
PXDFF(%SF3201, %FF320, L5, L6, L7, N2, P22);
PXDFF(%SF3202, %FF640, L8, L9, L10, N3, P21);
PXDFF(%SF3203, %FF960, L11, L12, L13, N4, P20);
PXDFF(%SF3204, %FF1280, L14, L15, L16, N5, P19);
PXDFF(%SF3205, %FF1600, L17, L18, L19, N6, P18);
PXDFF(%SF3206, %FF1920, L20, L21, L22, N7, P17);
PXDFF(%SF3207, %FF2240, L23, L24, L25, N8, P16);
PXDFF(%SF3208, %FF2560, L26, L27, L28, N9, P15);
PXDFF(%SF3209, %FF2880, L29, L30, L31, N10, P14);
%EndModel

;The registers on the following device reset upon power-up, whereby the
;active-low outputs are set to a logic High.
%StartModel
%Manufacturer:AMD
%Type:20XRP10
%PartNumber:AMPAL20XRP10-30
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 ~N1 N1 P3 ~P3 ~N2 N2 P4 ~P4 ~N3 N3 P5 ~P5 ~N4 N4
           P6 ~P6 ~N5 N5 P7 ~P7 ~N6 N6 P8 ~P8 ~N7 N7 P9 ~P9 ~N8 N8
           P10 ~P10 ~N9 N9 P11 ~P11 ~N10 N10 *


%MACRO PXDFF(XorFuse:%SF, InFuse:%FF, TL1:%TEXT, TL2:%TEXT, TL3:%TEXT, TN1:%TEXT, OutPin:%TEXT);
  LOR(%InFuse, %InFuse+40; TL1);
  LOR(%InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200, %InFuse+240, %InFuse+280; TL2);
  %IF %XorFuse=0 %THEN
   LXOR(TL1, TL2; TL3);
  %ELSE
   LXNOR(TL1, TL2; TL3);
  %END;
  DQFFC(TL3, P1,IPL; TN1; 15,15,30,0,15,15,1,1,1,1,15,15,30,0,15,15,1,1,1,1);
  ITSB(TN1, L1; OutPin; 20,20,20,20,20,20,20,20);
%MACEND;

LINV(P13; L1);

PXDFF(%SF3200, %FF00, L2, L3, L4, N1, P23);
PXDFF(%SF3201, %FF320, L5, L6, L7, N2, P22);
PXDFF(%SF3202, %FF640, L8, L9, L10, N3, P21);
PXDFF(%SF3203, %FF960, L11, L12, L13, N4, P20);
PXDFF(%SF3204, %FF1280, L14, L15, L16, N5, P19);
PXDFF(%SF3205, %FF1600, L17, L18, L19, N6, P18);
PXDFF(%SF3206, %FF1920, L20, L21, L22, N7, P17);
PXDFF(%SF3207, %FF2240, L23, L24, L25, N8, P16);
PXDFF(%SF3208, %FF2560, L26, L27, L28, N9, P15);
PXDFF(%SF3209, %FF2880, L29, L30, L31, N10, P14);
%EndModel

;The registers on the following device reset upon power-up, whereby the
;active-low outputs are set to a logic High.
%StartModel
%Manufacturer:AMD
%Type:20XRP10
%PartNumber:AMPAL20XRP10-40L
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 ~N1 N1 P3 ~P3 ~N2 N2 P4 ~P4 ~N3 N3 P5 ~P5 ~N4 N4
           P6 ~P6 ~N5 N5 P7 ~P7 ~N6 N6 P8 ~P8 ~N7 N7 P9 ~P9 ~N8 N8
           P10 ~P10 ~N9 N9 P11 ~P11 ~N10 N10 *


%MACRO PXDFF(XorFuse:%SF, InFuse:%FF, TL1:%TEXT, TL2:%TEXT, TL3:%TEXT, TN1:%TEXT, OutPin:%TEXT);
  LOR(%InFuse, %InFuse+40; TL1);
  LOR(%InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200, %InFuse+240, %InFuse+280; TL2);
  %IF %XorFuse=0 %THEN
   LXOR(TL1, TL2; TL3);
  %ELSE
   LXNOR(TL1, TL2; TL3);
  %END;
  DQFFC(TL3, P1, IPL; TN1; 30,30,40,0,25,25,1,1,1,1,30,30,40,0,25,25,1,1,1,1);
  ITSB(TN1, L1; OutPin; 35,35,35,35,35,35,35,35);
%MACEND;

LINV(P13; L1);

PXDFF(%SF3200, %FF00, L2, L3, L4, N1, P23);
PXDFF(%SF3201, %FF320, L5, L6, L7, N2, P22);
PXDFF(%SF3202, %FF640, L8, L9, L10, N3, P21);
PXDFF(%SF3203, %FF960, L11, L12, L13, N4, P20);
PXDFF(%SF3204, %FF1280, L14, L15, L16, N5, P19);
PXDFF(%SF3205, %FF1600, L17, L18, L19, N6, P18);
PXDFF(%SF3206, %FF1920, L20, L21, L22, N7, P17);
PXDFF(%SF3207, %FF2240, L23, L24, L25, N8, P16);
PXDFF(%SF3208, %FF2560, L26, L27, L28, N9, P15);
PXDFF(%SF3209, %FF2880, L29, L30, L31, N10, P14);
%EndModel

;The registers on the following device reset upon power-up, whereby the
;active-low outputs are set to a logic High.
%StartModel
%Manufacturer:AMD
%Type:20XRP4
%PartNumber:AMPAL20XRP4-20
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P23 ~P23 P3 ~P3 P22 ~P22 P4 ~P4 P21 ~P21 P5 ~P5 ~N4 N4
           P6 ~P6 ~N5 N5 P7 ~P7 ~N6 N6 P8 ~P8 ~N7 N7 P9 ~P9 P16 ~P16
           P10 ~P10 P15 ~P15 P11 ~P11 P14 ~P14 *


%MACRO POR8ENABLE(EnableFuse:%SF, InFuse:%FF, XorFuse:%SF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
  %IF %XorFuse = 0 %THEN
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280, %InFuse+320; OutPin; 20,20,20,20);
  %ELSE
   OR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
     %InFuse+240, %InFuse+280, %InFuse+320; OutPin; 20,20,20,20);
  %END;
 %ELSE
  %IF %XorFuse = 0 %THEN
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280, %InFuse+320; TNode; 20,20,20,20);
  %ELSE
   OR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
     %InFuse+240, %InFuse+280, %InFuse+320; TNode; 20,20,20,20);
  %END;
  TSB(TNode, %InFuse; OutPin; 20,20,20,20,20,20,20,20);
 %END;
%MACEND;

%MACRO PXDFF(XorFuse:%SF, InFuse:%FF, TL1:%TEXT, TL2:%TEXT, TL3:%TEXT, TN1:%TEXT, OutPin:%TEXT);
  LOR(%InFuse, %InFuse+40; TL1);
  LOR(%InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200, %InFuse+240, %InFuse+280; TL2);
  %IF %XorFuse=0 %THEN
   LXOR(TL1, TL2; TL3);
  %ELSE
   LXNOR(TL1, TL2; TL3);
  %END;
  DQFFC(TL3, P1, IPL; TN1; 13,13,20,0,10,10,1,1,1,1,13,13,20,0,10,10,1,1,1,1);
  ITSB(TN1, L1; OutPin; 15,15,15,15,15,15,15,15);
%MACEND;

LINV(P13; L1);

POR8ENABLE(%SF00, %FF00, %SF3440, P23, N1);
POR8ENABLE(%SF360, %FF360, %SF3441, P22, N2);
POR8ENABLE(%SF720, %FF720, %SF3442, P21, N3);
PXDFF(%SF3443, %FF1080, L2, L3, L4, N4, P20);
PXDFF(%SF3444, %FF1400, L5, L6, L7, N5, P19);
PXDFF(%SF3445, %FF1720, L8, L9, L10, N6, P18);
PXDFF(%SF3446, %FF2040, L11, L12, L13, N7, P17);
POR8ENABLE(%SF2360, %FF2360, %SF3447, P16, N8);
POR8ENABLE(%SF2720, %FF2720, %SF3448, P15, N9);
POR8ENABLE(%SF3080, %FF3080, %SF3449, P14, N10);
%EndModel

;The registers on the following device reset upon power-up, whereby the
;active-low outputs are set to a logic High.
%StartModel
%Manufacturer:AMD
%Type:20XRP4
%PartNumber:AMPAL20XRP4-30
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P23 ~P23 P3 ~P3 P22 ~P22 P4 ~P4 P21 ~P21 P5 ~P5 ~N4 N4
           P6 ~P6 ~N5 N5 P7 ~P7 ~N6 N6 P8 ~P8 ~N7 N7 P9 ~P9 P16 ~P16
           P10 ~P10 P15 ~P15 P11 ~P11 P14 ~P14 *


%MACRO POR8ENABLE(EnableFuse:%SF, InFuse:%FF, XorFuse:%SF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
  %IF %XorFuse = 0 %THEN
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280, %InFuse+320; OutPin; 30,30,30,30);
  %ELSE
   OR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
     %InFuse+240, %InFuse+280, %InFuse+320; OutPin; 30,30,30,30);
  %END;
 %ELSE
  %IF %XorFuse = 0 %THEN
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280, %InFuse+320; TNode; 30,30,30,30);
  %ELSE
   OR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
     %InFuse+240, %InFuse+280, %InFuse+320; TNode; 30,30,30,30);
  %END;
  TSB(TNode, %InFuse; OutPin; 30,30,30,30,30,30,30,30);
 %END;
%MACEND;

%MACRO PXDFF(XorFuse:%SF, InFuse:%FF, TL1:%TEXT, TL2:%TEXT, TL3:%TEXT, TN1:%TEXT, OutPin:%TEXT);
  LOR(%InFuse, %InFuse+40; TL1);
  LOR(%InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200, %InFuse+240, %InFuse+280; TL2);
  %IF %XorFuse=0 %THEN
   LXOR(TL1, TL2; TL3);
  %ELSE
   LXNOR(TL1, TL2; TL3);
  %END;
  DQFFC(TL3, P1, IPL; TN1; 15,15,30,0,15,15,1,1,1,1,15,15,30,0,15,15,1,1,1,1);
  ITSB(TN1, L1; OutPin; 20,20,20,20,20,20,20,20);
%MACEND;

LINV(P13; L1);

POR8ENABLE(%SF00, %FF00, %SF3440, P23, N1);
POR8ENABLE(%SF360, %FF360, %SF3441, P22, N2);
POR8ENABLE(%SF720, %FF720, %SF3442, P21, N3);
PXDFF(%SF3443, %FF1080, L2, L3, L4, N4, P20);
PXDFF(%SF3444, %FF1400, L5, L6, L7, N5, P19);
PXDFF(%SF3445, %FF1720, L8, L9, L10, N6, P18);
PXDFF(%SF3446, %FF2040, L11, L12, L13, N7, P17);
POR8ENABLE(%SF2360, %FF2360, %SF3447, P16, N8);
POR8ENABLE(%SF2720, %FF2720, %SF3448, P15, N9);
POR8ENABLE(%SF3080, %FF3080, %SF3449, P14, N10);
%EndModel

;The registers on the following device reset upon power-up, whereby the
;active-low outputs are set to a logic High.
%StartModel
%Manufacturer:AMD
%Type:20XRP4
%PartNumber:AMPAL20XRP4-40L
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P23 ~P23 P3 ~P3 P22 ~P22 P4 ~P4 P21 ~P21 P5 ~P5 ~N4 N4
           P6 ~P6 ~N5 N5 P7 ~P7 ~N6 N6 P8 ~P8 ~N7 N7 P9 ~P9 P16 ~P16
           P10 ~P10 P15 ~P15 P11 ~P11 P14 ~P14 *


%MACRO POR8ENABLE(EnableFuse:%SF, InFuse:%FF, XorFuse:%SF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
  %IF %XorFuse = 0 %THEN
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280, %InFuse+320; OutPin; 40,40,40,40);
  %ELSE
   OR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
     %InFuse+240, %InFuse+280, %InFuse+320; OutPin; 40,40,40,40);
  %END;
 %ELSE
  %IF %XorFuse = 0 %THEN
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280, %InFuse+320; TNode; 40,40,40,40);
  %ELSE
   OR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
     %InFuse+240, %InFuse+280, %InFuse+320; TNode; 40,40,40,40);
  %END;
  TSB(TNode, %InFuse; OutPin; 40,40,40,40,40,40,40,40);
 %END;
%MACEND;

%MACRO PXDFF(XorFuse:%SF, InFuse:%FF, TL1:%TEXT, TL2:%TEXT, TL3:%TEXT, TN1:%TEXT, OutPin:%TEXT);
  LOR(%InFuse, %InFuse+40; TL1);
  LOR(%InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200, %InFuse+240, %InFuse+280; TL2);
  %IF %XorFuse=0 %THEN
   LXOR(TL1, TL2; TL3);
  %ELSE
   LXNOR(TL1, TL2; TL3);
  %END;
  DQFFC(TL3, P1, IPL; TN1; 30,30,40,0,25,25,1,1,1,1,30,30,40,0,25,25,1,1,1,1);
  ITSB(TN1, L1; OutPin; 35,35,35,35,35,35,35,35);
%MACEND;

LINV(P13; L1);

POR8ENABLE(%SF00, %FF00, %SF3440, P23, N1);
POR8ENABLE(%SF360, %FF360, %SF3441, P22, N2);
POR8ENABLE(%SF720, %FF720, %SF3442, P21, N3);
PXDFF(%SF3443, %FF1080, L2, L3, L4, N4, P20);
PXDFF(%SF3444, %FF1400, L5, L6, L7, N5, P19);
PXDFF(%SF3445, %FF1720, L8, L9, L10, N6, P18);
PXDFF(%SF3446, %FF2040, L11, L12, L13, N7, P17);
POR8ENABLE(%SF2360, %FF2360, %SF3447, P16, N8);
POR8ENABLE(%SF2720, %FF2720, %SF3448, P15, N9);
POR8ENABLE(%SF3080, %FF3080, %SF3449, P14, N10);
%EndModel

;The registers on the following device reset upon power-up, whereby the
;active-low outputs are set to a logic High.
%StartModel
%Manufacturer:AMD
%Type:20XRP6
%PartNumber:AMPAL20XRP6-20
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P23 ~P23 P3 ~P3 P22 ~P22 P4 ~P4 ~N3 N3 P5 ~P5 ~N4 N4
           P6 ~P6 ~N5 N5 P7 ~P7 ~N6 N6 P8 ~P8 ~N7 N7 P9 ~P9 ~N8 N8
           P10 ~P10 P15 ~P15 P11 ~P11 P14 ~P14 *


%MACRO POR8ENABLE(EnableFuse:%SF, InFuse:%FF, XorFuse:%SF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
  %IF %XorFuse = 0 %THEN
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280, %InFuse+320; OutPin; 20,20,20,20);
  %ELSE
   OR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
     %InFuse+240, %InFuse+280, %InFuse+320; OutPin; 20,20,20,20);
  %END;
 %ELSE
  %IF %XorFuse = 0 %THEN
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280, %InFuse+320; TNode; 20,20,20,20);
  %ELSE
   OR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
     %InFuse+240, %InFuse+280, %InFuse+320; TNode; 20,20,20,20);
  %END;
  TSB(TNode, %InFuse; OutPin; 20,20,20,20,20,20,20,20);
 %END;
%MACEND;

%MACRO PXDFF(XorFuse:%SF, InFuse:%FF, TL1:%TEXT, TL2:%TEXT, TL3:%TEXT, TN1:%TEXT, OutPin:%TEXT);
  LOR(%InFuse, %InFuse+40; TL1);
  LOR(%InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200, %InFuse+240, %InFuse+280; TL2);
  %IF %XorFuse=0 %THEN
   LXOR(TL1, TL2; TL3);
  %ELSE
   LXNOR(TL1, TL2; TL3);
  %END;
  DQFFC(TL3, P1, IPL; TN1; 13,13,20,0,10,10,1,1,1,1,13,13,20,0,10,10,1,1,1,1);
  ITSB(TN1, L1; OutPin; 15,15,15,15,15,15,15,15);
%MACEND;

LINV(P13; L1);

POR8ENABLE(%SF00, %FF00, %SF3360, P23, N1);
POR8ENABLE(%SF360, %FF360, %SF3361, P22, N2);
PXDFF(%SF3362, %FF720,  L2, L3, L4, N3, P21);
PXDFF(%SF3363, %FF1040, L5, L6, L7, N4, P20);
PXDFF(%SF3364, %FF1360, L8, L9, L10, N5, P19);
PXDFF(%SF3365, %FF1680, L11, L12, L13, N6, P18);
PXDFF(%SF3366, %FF2000, L14, L15, L16, N7, P17);
PXDFF(%SF3367, %FF2320, L17, L18, L19, N8, P16);
POR8ENABLE(%SF2640, %FF2640, %SF3368, P15, N9);
POR8ENABLE(%SF3000, %FF3000, %SF3369, P14, N10);
%EndModel

;The registers on the following device reset upon power-up, whereby the
;active-low outputs are set to a logic High.
%StartModel
%Manufacturer:AMD
%Type:20XRP6
%PartNumber:AMPAL20XRP6-30
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P23 ~P23 P3 ~P3 P22 ~P22 P4 ~P4 ~N3 N3 P5 ~P5 ~N4 N4
           P6 ~P6 ~N5 N5 P7 ~P7 ~N6 N6 P8 ~P8 ~N7 N7 P9 ~P9 ~N8 N8
           P10 ~P10 P15 ~P15 P11 ~P11 P14 ~P14 *


%MACRO POR8ENABLE(EnableFuse:%SF, InFuse:%FF, XorFuse:%SF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
  %IF %XorFuse = 0 %THEN
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280, %InFuse+320; OutPin; 30,30,30,30);
  %ELSE
   OR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
     %InFuse+240, %InFuse+280, %InFuse+320; OutPin; 30,30,30,30);
  %END;
 %ELSE
  %IF %XorFuse = 0 %THEN
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280, %InFuse+320; TNode; 30,30,30,30);
  %ELSE
   OR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
     %InFuse+240, %InFuse+280, %InFuse+320; TNode; 30,30,30,30);
  %END;
  TSB(TNode, %InFuse; OutPin; 30,30,30,30,30,30,30,30);
 %END;
%MACEND;

%MACRO PXDFF(XorFuse:%SF, InFuse:%FF, TL1:%TEXT, TL2:%TEXT, TL3:%TEXT, TN1:%TEXT, OutPin:%TEXT);
  LOR(%InFuse, %InFuse+40; TL1);
  LOR(%InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200, %InFuse+240, %InFuse+280; TL2);
  %IF %XorFuse=0 %THEN
   LXOR(TL1, TL2; TL3);
  %ELSE
   LXNOR(TL1, TL2; TL3);
  %END;
  DQFFC(TL3, P1, IPL; TN1; 15,15,30,0,15,15,1,1,1,1,15,15,30,0,15,15,1,1,1,1);
  ITSB(TN1, L1; OutPin; 20,20,20,20,20,20,20,20);
%MACEND;

LINV(P13; L1);

POR8ENABLE(%SF00, %FF00, %SF3360, P23, N1);
POR8ENABLE(%SF360, %FF360, %SF3361, P22, N2);
PXDFF(%SF3362, %FF720,  L2, L3, L4, N3, P21);
PXDFF(%SF3363, %FF1040, L5, L6, L7, N4, P20);
PXDFF(%SF3364, %FF1360, L8, L9, L10, N5, P19);
PXDFF(%SF3365, %FF1680, L11, L12, L13, N6, P18);
PXDFF(%SF3366, %FF2000, L14, L15, L16, N7, P17);
PXDFF(%SF3367, %FF2320, L17, L18, L19, N8, P16);
POR8ENABLE(%SF2640, %FF2640, %SF3368, P15, N9);
POR8ENABLE(%SF3000, %FF3000, %SF3369, P14, N10);
%EndModel

;The registers on the following device reset upon power-up, whereby the
;active-low outputs are set to a logic High.
%StartModel
%Manufacturer:AMD
%Type:20XRP6
%PartNumber:AMPAL20XRP6-40L
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P23 ~P23 P3 ~P3 P22 ~P22 P4 ~P4 ~N3 N3 P5 ~P5 ~N4 N4
           P6 ~P6 ~N5 N5 P7 ~P7 ~N6 N6 P8 ~P8 ~N7 N7 P9 ~P9 ~N8 N8
           P10 ~P10 P15 ~P15 P11 ~P11 P14 ~P14 *


%MACRO POR8ENABLE(EnableFuse:%SF, InFuse:%FF, XorFuse:%SF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
  %IF %XorFuse = 0 %THEN
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280, %InFuse+320; OutPin; 40,40,40,40);
  %ELSE
   OR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
     %InFuse+240, %InFuse+280, %InFuse+320; OutPin; 40,40,40,40);
  %END;
 %ELSE
  %IF %XorFuse = 0 %THEN
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280, %InFuse+320; TNode; 40,40,40,40);
  %ELSE
   OR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
     %InFuse+240, %InFuse+280, %InFuse+320; TNode; 40,40,40,40);
  %END;
  TSB(TNode, %InFuse; OutPin; 40,40,40,40,40,40,40,40);
 %END;
%MACEND;

%MACRO PXDFF(XorFuse:%SF, InFuse:%FF, TL1:%TEXT, TL2:%TEXT, TL3:%TEXT, TN1:%TEXT, OutPin:%TEXT);
  LOR(%InFuse, %InFuse+40; TL1);
  LOR(%InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200, %InFuse+240, %InFuse+280; TL2);
  %IF %XorFuse=0 %THEN
   LXOR(TL1, TL2; TL3);
  %ELSE
   LXNOR(TL1, TL2; TL3);
  %END;
  DQFFC(TL3, P1, IPL; TN1; 30,30,40,0,25,25,1,1,1,1,30,30,40,0,25,25,1,1,1,1);
  ITSB(TN1, L1; OutPin; 35,35,35,35,35,35,35,35);
%MACEND;

LINV(P13; L1);

POR8ENABLE(%SF00, %FF00, %SF3360, P23, N1);
POR8ENABLE(%SF360, %FF360, %SF3361, P22, N2);
PXDFF(%SF3362, %FF720,  L2, L3, L4, N3, P21);
PXDFF(%SF3363, %FF1040, L5, L6, L7, N4, P20);
PXDFF(%SF3364, %FF1360, L8, L9, L10, N5, P19);
PXDFF(%SF3365, %FF1680, L11, L12, L13, N6, P18);
PXDFF(%SF3366, %FF2000, L14, L15, L16, N7, P17);
PXDFF(%SF3367, %FF2320, L17, L18, L19, N8, P16);
POR8ENABLE(%SF2640, %FF2640, %SF3368, P15, N9);
POR8ENABLE(%SF3000, %FF3000, %SF3369, P14, N10);
%EndModel

;The registers on the following device reset upon power-up, whereby the
;active-low outputs are set to a logic High.
%StartModel
%Manufacturer:AMD
%Type:20XRP8
%PartNumber:AMPAL20XRP8-20
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P23 ~P23 P3 ~P3 ~N2 N2 P4 ~P4 ~N3 N3 P5 ~P5 ~N4 N4
           P6 ~P6 ~N5 N5 P7 ~P7 ~N6 N6 P8 ~P8 ~N7 N7 P9 ~P9 ~N8 N8
           P10 ~P10 ~N9 N9 P11 ~P11 P14 ~P14 *


%MACRO POR8ENABLE(EnableFuse:%SF, InFuse:%FF, XorFuse:%SF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
  %IF %XorFuse = 0 %THEN
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280, %InFuse+320; OutPin; 20,20,20,20);
  %ELSE
   OR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
     %InFuse+240, %InFuse+280, %InFuse+320; OutPin; 20,20,20,20);
  %END;
 %ELSE
  %IF %XorFuse = 0 %THEN
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280, %InFuse+320; TNode; 20,20,20,20);
  %ELSE
   OR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
     %InFuse+240, %InFuse+280, %InFuse+320; TNode; 20,20,20,20);
  %END;
  TSB(TNode, %InFuse; OutPin; 20,20,20,20,20,20,20,20);
 %END;
%MACEND;

%MACRO PXDFF(XorFuse:%SF, InFuse:%FF, TL1:%TEXT, TL2:%TEXT, TL3:%TEXT, TN1:%TEXT, OutPin:%TEXT);
  LOR(%InFuse, %InFuse+40; TL1);
  LOR(%InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200, %InFuse+240, %InFuse+280; TL2);
  %IF %XorFuse=0 %THEN
   LXOR(TL1, TL2; TL3);
  %ELSE
   LXNOR(TL1, TL2; TL3);
  %END;
  DQFFC(TL3, P1, IPL; TN1; 13,13,20,0,10,10,1,1,1,1,13,13,20,0,10,10,1,1,1,1);
  ITSB(TN1, L1; OutPin; 15,15,15,15,15,15,15,15);
%MACEND;

LINV(P13; L1);

POR8ENABLE(%SF00, %FF00, %SF3280, P23, N1);
PXDFF(%SF3281, %FF360, L2, L3, L4, N2, P22);
PXDFF(%SF3282, %FF680,  L5, L6, L7, N3, P21);
PXDFF(%SF3283, %FF1000, L8, L9, L10, N4, P20);
PXDFF(%SF3284, %FF1320, L11, L12, L13, N5, P19);
PXDFF(%SF3285, %FF1640, L14, L15, L16, N6, P18);
PXDFF(%SF3286, %FF1960, L17, L18, L19, N7, P17);
PXDFF(%SF3287, %FF2280, L20, L21, L22, N8, P16);
PXDFF(%SF3288, %FF2600, L23, L24, L25, N9, P15);
POR8ENABLE(%SF2920, %FF2920, %SF3289, P14, N10);
%EndModel

;The registers on the following device reset upon power-up, whereby the
;active-low outputs are set to a logic High.
%StartModel
%Manufacturer:AMD
%Type:20XRP8
%PartNumber:AMPAL20XRP8-30
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P23 ~P23 P3 ~P3 ~N2 N2 P4 ~P4 ~N3 N3 P5 ~P5 ~N4 N4
           P6 ~P6 ~N5 N5 P7 ~P7 ~N6 N6 P8 ~P8 ~N7 N7 P9 ~P9 ~N8 N8
           P10 ~P10 ~N9 N9 P11 ~P11 P14 ~P14 *


%MACRO POR8ENABLE(EnableFuse:%SF, InFuse:%FF, XorFuse:%SF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
  %IF %XorFuse = 0 %THEN
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280, %InFuse+320; OutPin; 30,30,30,30);
  %ELSE
   OR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
     %InFuse+240, %InFuse+280, %InFuse+320; OutPin; 30,30,30,30);
  %END;
 %ELSE
  %IF %XorFuse = 0 %THEN
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280, %InFuse+320; TNode; 30,30,30,30);
  %ELSE
   OR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
     %InFuse+240, %InFuse+280, %InFuse+320; TNode; 30,30,30,30);
  %END;
  TSB(TNode, %InFuse; OutPin; 30,30,30,30,30,30,30,30);
 %END;
%MACEND;

%MACRO PXDFF(XorFuse:%SF, InFuse:%FF, TL1:%TEXT, TL2:%TEXT, TL3:%TEXT, TN1:%TEXT, OutPin:%TEXT);
  LOR(%InFuse, %InFuse+40; TL1);
  LOR(%InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200, %InFuse+240, %InFuse+280; TL2);
  %IF %XorFuse=0 %THEN
   LXOR(TL1, TL2; TL3);
  %ELSE
   LXNOR(TL1, TL2; TL3);
  %END;
  DQFFC(TL3, P1, IPL; TN1; 15,15,30,0,15,15,1,1,1,1,15,15,30,0,15,15,1,1,1,1);
  ITSB(TN1, L1; OutPin; 20,20,20,20,20,20,20,20);
%MACEND;

LINV(P13; L1);

POR8ENABLE(%SF00, %FF00, %SF3280, P23, N1);
PXDFF(%SF3281, %FF360, L2, L3, L4, N2, P22);
PXDFF(%SF3282, %FF680,  L5, L6, L7, N3, P21);
PXDFF(%SF3283, %FF1000, L8, L9, L10, N4, P20);
PXDFF(%SF3284, %FF1320, L11, L12, L13, N5, P19);
PXDFF(%SF3285, %FF1640, L14, L15, L16, N6, P18);
PXDFF(%SF3286, %FF1960, L17, L18, L19, N7, P17);
PXDFF(%SF3287, %FF2280, L20, L21, L22, N8, P16);
PXDFF(%SF3288, %FF2600, L23, L24, L25, N9, P15);
POR8ENABLE(%SF2920, %FF2920, %SF3289, P14, N10);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:20XRP8
%PartNumber:AMPAL20XRP8-40L
%LastNode ? ?
%NumPins:24
%FDF AND 0 P2 ~P2 P23 ~P23 P3 ~P3 ~N2 N2 P4 ~P4 ~N3 N3 P5 ~P5 ~N4 N4
           P6 ~P6 ~N5 N5 P7 ~P7 ~N6 N6 P8 ~P8 ~N7 N7 P9 ~P9 ~N8 N8
           P10 ~P10 ~N9 N9 P11 ~P11 P14 ~P14 *


%MACRO POR8ENABLE(EnableFuse:%SF, InFuse:%FF, XorFuse:%SF, OutPin:%TEXT, TNode:%TEXT);
 %IF %EnableFuse..%EnableFuse+39 = 1 %THEN
  %IF %XorFuse = 0 %THEN
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280, %InFuse+320; OutPin; 40,40,40,40);
  %ELSE
   OR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
     %InFuse+240, %InFuse+280, %InFuse+320; OutPin; 40,40,40,40);
  %END;
 %ELSE
  %IF %XorFuse = 0 %THEN
   NOR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
      %InFuse+240, %InFuse+280, %InFuse+320; TNode; 40,40,40,40);
  %ELSE
   OR(%InFuse+40, %InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200,
     %InFuse+240, %InFuse+280, %InFuse+320; TNode; 40,40,40,40);
  %END;
  TSB(TNode, %InFuse; OutPin; 40,40,40,40,40,40,40,40);
 %END;
%MACEND;

%MACRO PXDFF(XorFuse:%SF, InFuse:%FF, TL1:%TEXT, TL2:%TEXT, TL3:%TEXT, TN1:%TEXT, OutPin:%TEXT);
  LOR(%InFuse, %InFuse+40; TL1);
  LOR(%InFuse+80, %InFuse+120, %InFuse+160, %InFuse+200, %InFuse+240, %InFuse+280; TL2);
  %IF %XorFuse=0 %THEN
   LXOR(TL1, TL2; TL3);
  %ELSE
   LXNOR(TL1, TL2; TL3);
  %END;
  DQFFC(TL3, P1, IPL; TN1; 30,30,40,0,25,25,0,0,0,0,30,30,40,0,25,25,0,0,0,0);
  ITSB(TN1, L1; OutPin; 35,35,35,35,35,35,35,35);
%MACEND;

LINV(P13; L1);

POR8ENABLE(%SF00, %FF00, %SF3280, P23, N1);
PXDFF(%SF3281, %FF360, L2, L3, L4, N2, P22);
PXDFF(%SF3282, %FF680,  L5, L6, L7, N3, P21);
PXDFF(%SF3283, %FF1000, L8, L9, L10, N4, P20);
PXDFF(%SF3284, %FF1320, L11, L12, L13, N5, P19);
PXDFF(%SF3285, %FF1640, L14, L15, L16, N6, P18);
PXDFF(%SF3286, %FF1960, L17, L18, L19, N7, P17);
PXDFF(%SF3287, %FF2280, L20, L21, L22, N8, P16);
PXDFF(%SF3288, %FF2600, L23, L24, L25, N9, P15);
POR8ENABLE(%SF2920, %FF2920, %SF3289, P14, N10);
%EndModel

;Delays for the following device are given for maximum only.
%StartModel
%Manufacturer:AMD
%Type:22V10
%PartNumber:AMPAL22V10
%LastNode ? ?
%NumPins: 24
%FDF AND 0 P1 ~P1 N1 ~N1 P2 ~P2 N2 ~N2 P3 ~P3 N3 ~N3 P4 ~P4 N4 ~N4 P5 ~P5
     N5 ~N5 P6 ~P6 N6 ~N6 P7 ~P7 N7 ~N7 P8 ~P8 N8 ~N8 P9 ~P9 N9 ~N9
     P10 ~P10 N10 ~N10 P11 ~P11 P13 ~P13 *

%MACRO LOR16(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308,%InFuse+352,%InFuse+396,%InFuse+440,%InFuse+484,
     %InFuse+528,%InFuse+572,%InFuse+616,%InFuse+660; OutLNode);
%MACEND;

%MACRO LOR14(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308,%InFuse+352,%InFuse+396,%InFuse+440,%InFuse+484,
     %InFuse+528,%InFuse+572; OutLNode);
%MACEND;

%MACRO LOR12(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308,%InFuse+352,%InFuse+396,%InFuse+440,
     %InFuse+484; OutLNode);
%MACEND;

%MACRO LOR10(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308,%InFuse+352,%InFuse+396; OutLNode);
%MACEND;

%MACRO LOR8(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308; OutLNode);
%MACEND;

%MACRO V10Mac(S1:%SF, S0:%SF, FeedBack:%TEXT, OrOutput:%TEXT, TNode:%TEXT,
              OutPin:%TEXT, InFuse:%FF, EnableFuse:%SF, TLNode:%TEXT);
 %CASE %S1,%S0
   0:
     LOR(OrOutput, L21; TLNode);
     DQFFC(TLNode, P1, L22; TNode; 15,15,30,0,25,25,40,40,35,35,15,15,30,0,25,25,40,40,35,35);
    %IF %EnableFuse..%EnableFuse+43 = 1 %THEN
     INV(TNode; OutPin; 0,0,0,0);
    %ELSE
     ITSB(TNode, %InFuse; OutPin; 35,35,35,35,35,35,35,35);
    %END;
    INV(TNode; FeedBack; 10,10,10,10);
  |1:
     LOR(OrOutput, L21; TLNode);
     DQFFC(TLNode, P1, L22; TNode; 15,15,30,0,25,25,40,40,35,35,15,15,30,0,25,25,40,40,35,35);
    %IF %EnableFuse..%EnableFuse+43 = 1 %THEN
     BUF(TNode; OutPin; 0,0,0,0);
    %ELSE
     TSB(TNode, %InFuse; OutPin; 35,35,35,35,35,35,35,35);
    %END;
    INV(TNode; FeedBack; 10,10,10,10);
  |2:
    %IF %EnableFuse..%EnableFuse+43 = 1 %THEN
     INV(OrOutput; OutPin; 25,25,25,25);
    %ELSE
     INV(OrOutput; TNode; 25,25,25,25);
     TSB(TNode, %InFuse; OutPin; 35,35,35,35,35,35,35,35);
    %END;
    BUF(OutPin; FeedBack; 0,0,0,0);
  |3:
    %IF %EnableFuse..%EnableFuse+43 = 1 %THEN
     BUF(OrOutput; OutPin; 25,25,25,25);
    %ELSE
     BUF(OrOutput; TNode; 25,25,25,25);
     TSB(TNode, %InFuse; OutPin; 35,35,35,35,35,35,35,35);
    %END;
    BUF(OutPin; FeedBack; 0,0,0,0);
  %END;
%MACEND;

LAND(%FF5764; L21);
LNOR(%FF00, IPH; L22);

LOR8(%FF88, L1);
LOR10(%FF484, L2);
LOR12(%FF968, L3);
LOR14(%FF1540, L4);
LOR16(%FF2200, L5);
LOR16(%FF2948, L6);
LOR14(%FF3696, L7);
LOR12(%FF4356, L8);
LOR10(%FF4928, L9);
LOR8(%FF5412, L10);

V10Mac(%SF5809, %SF5808, N1, L1, N11, P23, %FF44, %SF44, L11);
V10Mac(%SF5811, %SF5810, N2, L2, N12, P22, %FF440, %SF440, L12);
V10Mac(%SF5813, %SF5812, N3, L3, N13, P21, %FF924, %SF924, L13);
V10Mac(%SF5815, %SF5814, N4, L4, N14, P20, %FF1496, %SF1496, L14);
V10Mac(%SF5817, %SF5816, N5, L5, N15, P19, %FF2156, %SF2156, L15);
V10Mac(%SF5819, %SF5818, N6, L6, N16, P18, %FF2904, %SF2904, L16);
V10Mac(%SF5821, %SF5820, N7, L7, N17, P17, %FF3652, %SF3652, L17);
V10Mac(%SF5823, %SF5822, N8, L8, N18, P16, %FF4312, %SF4312, L18);
V10Mac(%SF5825, %SF5824, N9, L9, N19, P15, %FF4884, %SF4884, L19);
V10Mac(%SF5827, %SF5826, N10, L10, N20, P14, %FF5368, %SF5368, L20);
%EndModel

;Delays for the following device are given for maximum only.
%StartModel
%Manufacturer:AMD
%Type:22V10
%PartNumber:AMPAL22V10-15
%LastNode ? ?
%NumPins: 24
%FDF AND 0 P1 ~P1 N1 ~N1 P2 ~P2 N2 ~N2 P3 ~P3 N3 ~N3 P4 ~P4 N4 ~N4 P5 ~P5
     N5 ~N5 P6 ~P6 N6 ~N6 P7 ~P7 N7 ~N7 P8 ~P8 N8 ~N8 P9 ~P9 N9 ~N9
     P10 ~P10 N10 ~N10 P11 ~P11 P13 ~P13 *

%MACRO LOR16(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308,%InFuse+352,%InFuse+396,%InFuse+440,%InFuse+484,
     %InFuse+528,%InFuse+572,%InFuse+616,%InFuse+660; OutLNode);
%MACEND;

%MACRO LOR14(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308,%InFuse+352,%InFuse+396,%InFuse+440,%InFuse+484,
     %InFuse+528,%InFuse+572; OutLNode);
%MACEND;

%MACRO LOR12(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308,%InFuse+352,%InFuse+396,%InFuse+440,
     %InFuse+484; OutLNode);
%MACEND;

%MACRO LOR10(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308,%InFuse+352,%InFuse+396; OutLNode);
%MACEND;

%MACRO LOR8(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308; OutLNode);
%MACEND;

%MACRO V10Mac(S1:%SF, S0:%SF, FeedBack:%TEXT, OrOutput:%TEXT, TNode:%TEXT,
              OutPin:%TEXT, InFuse:%FF, EnableFuse:%SF, TLNode:%TEXT);
 %CASE %S1,%S0
   0:
     LOR(OrOutput, L21; TLNode);
     DQFFC(TLNode, P1, L22; TNode; 15,15,13,0,10,10,20,20,15,15,15,15,13,0,10,10,20,20,15,15);
    %IF %EnableFuse..%EnableFuse+43 = 1 %THEN
     INV(TNode; OutPin; 0,0,0,0);
    %ELSE
     ITSB(TNode, %InFuse; OutPin; 15,15,15,15,15,15,15,15);
    %END;
    INV(TNode; FeedBack; 0,0,0,0);
  |1:
     LOR(OrOutput, L21; TLNode);
     DQFFC(TLNode, P1, L22; TNode; 15,15,13,0,10,10,20,20,15,15,15,15,13,0,10,10,20,20,15,15);
    %IF %EnableFuse..%EnableFuse+43 = 1 %THEN
     BUF(TNode; OutPin; 0,0,0,0);
    %ELSE
     TSB(TNode, %InFuse; OutPin; 15,15,15,15,15,15,15,15);
    %END;
    INV(TNode; FeedBack; 0,0,0,0);
  |2:
    %IF %EnableFuse..%EnableFuse+43 = 1 %THEN
     INV(OrOutput; OutPin; 15,15,15,15);
    %ELSE
     INV(OrOutput; TNode; 15,15,15,15);
     TSB(TNode, %InFuse; OutPin; 15,15,15,15,15,15,15,15);
    %END;
    BUF(OutPin; FeedBack; 0,0,0,0);
  |3:
    %IF %EnableFuse..%EnableFuse+43 = 1 %THEN
     BUF(OrOutput; OutPin; 15,15,15,15);
    %ELSE
     BUF(OrOutput; TNode; 15,15,15,15);
     TSB(TNode, %InFuse; OutPin; 15,15,15,15,15,15,15,15);
    %END;
    BUF(OutPin; FeedBack; 0,0,0,0);
  %END;
%MACEND;

LAND(%FF5764; L21);
LNOR(%FF00, IPH; L22);

LOR8(%FF88, L1);
LOR10(%FF484, L2);
LOR12(%FF968, L3);
LOR14(%FF1540, L4);
LOR16(%FF2200, L5);
LOR16(%FF2948, L6);
LOR14(%FF3696, L7);
LOR12(%FF4356, L8);
LOR10(%FF4928, L9);
LOR8(%FF5412, L10);

V10Mac(%SF5809, %SF5808, N1, L1, N11, P23, %FF44, %SF44, L11);
V10Mac(%SF5811, %SF5810, N2, L2, N12, P22, %FF440, %SF440, L12);
V10Mac(%SF5813, %SF5812, N3, L3, N13, P21, %FF924, %SF924, L13);
V10Mac(%SF5815, %SF5814, N4, L4, N14, P20, %FF1496, %SF1496, L14);
V10Mac(%SF5817, %SF5816, N5, L5, N15, P19, %FF2156, %SF2156, L15);
V10Mac(%SF5819, %SF5818, N6, L6, N16, P18, %FF2904, %SF2904, L16);
V10Mac(%SF5821, %SF5820, N7, L7, N17, P17, %FF3652, %SF3652, L17);
V10Mac(%SF5823, %SF5822, N8, L8, N18, P16, %FF4312, %SF4312, L18);
V10Mac(%SF5825, %SF5824, N9, L9, N19, P15, %FF4884, %SF4884, L19);
V10Mac(%SF5827, %SF5826, N10, L10, N20, P14, %FF5368, %SF5368, L20);
%EndModel

;Delays for the following device are given for maximum only.
%StartModel
%Manufacturer:AMD
%Type:22V10
%PartNumber:AMPAL22V10A
%LastNode ? ?
%NumPins: 24
%FDF AND 0 P1 ~P1 N1 ~N1 P2 ~P2 N2 ~N2 P3 ~P3 N3 ~N3 P4 ~P4 N4 ~N4 P5 ~P5
     N5 ~N5 P6 ~P6 N6 ~N6 P7 ~P7 N7 ~N7 P8 ~P8 N8 ~N8 P9 ~P9 N9 ~N9
     P10 ~P10 N10 ~N10 P11 ~P11 P13 ~P13 *

%MACRO LOR16(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308,%InFuse+352,%InFuse+396,%InFuse+440,%InFuse+484,
     %InFuse+528,%InFuse+572,%InFuse+616,%InFuse+660; OutLNode);
%MACEND;

%MACRO LOR14(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308,%InFuse+352,%InFuse+396,%InFuse+440,%InFuse+484,
     %InFuse+528,%InFuse+572; OutLNode);
%MACEND;

%MACRO LOR12(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308,%InFuse+352,%InFuse+396,%InFuse+440,
     %InFuse+484; OutLNode);
%MACEND;

%MACRO LOR10(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308,%InFuse+352,%InFuse+396; OutLNode);
%MACEND;

%MACRO LOR8(InFuse:%FF, OutLNode:%TEXT);
 LOR(%InFuse,%InFuse+44,%InFuse+88,%InFuse+132,%InFuse+176,%InFuse+220,
     %InFuse+264,%InFuse+308; OutLNode);
%MACEND;

%MACRO V10Mac(S1:%SF, S0:%SF, FeedBack:%TEXT, OrOutput:%TEXT, TNode:%TEXT,
              OutPin:%TEXT, InFuse:%FF, EnableFuse:%SF, TLNode:%TEXT);
 %CASE %S1,%S0
   0:
     LOR(OrOutput, L21; TLNode);
     DQFFC(TLNode, P1, L22; TNode; 15,15,20,0,15,15,30,30,25,25,15,15,20,0,15,15,30,30,25,25);
    %IF %EnableFuse..%EnableFuse+43 = 1 %THEN
     INV(TNode; OutPin; 0,0,0,0);
    %ELSE
     ITSB(TNode, %InFuse; OutPin; 25,25,25,25,25,25,25,25);
    %END;
    INV(TNode; FeedBack; 0,0,0,0);
  |1:
     LOR(OrOutput, L21; TLNode);
     DQFFC(TLNode, P1, L22; TNode; 15,15,20,0,15,15,30,30,25,25,15,15,20,0,15,15,30,30,25,25);
    %IF %EnableFuse..%EnableFuse+43 = 1 %THEN
     BUF(TNode; OutPin; 0,0,0,0);
    %ELSE
     TSB(TNode, %InFuse; OutPin; 25,25,25,25,25,25,25,25);
    %END;
    INV(TNode; FeedBack; 0,0,0,0);
  |2:
    %IF %EnableFuse..%EnableFuse+43 = 1 %THEN
     INV(OrOutput; OutPin; 25,25,25,25);
    %ELSE
     INV(OrOutput; TNode; 25,25,25,25);
     TSB(TNode, %InFuse; OutPin; 25,25,25,25,25,25,25,25);
    %END;
    BUF(OutPin; FeedBack; 0,0,0,0);
  |3:
    %IF %EnableFuse..%EnableFuse+43 = 1 %THEN
     BUF(OrOutput; OutPin; 25,25,25,25);
    %ELSE
     BUF(OrOutput; TNode; 25,25,25,25);
     TSB(TNode, %InFuse; OutPin; 25,25,25,25,25,25,25,25);
    %END;
    BUF(OutPin; FeedBack; 0,0,0,0);
  %END;
%MACEND;

LAND(%FF5764; L21);
LNOR(%FF00, IPH; L22);

LOR8(%FF88, L1);
LOR10(%FF484, L2);
LOR12(%FF968, L3);
LOR14(%FF1540, L4);
LOR16(%FF2200, L5);
LOR16(%FF2948, L6);
LOR14(%FF3696, L7);
LOR12(%FF4356, L8);
LOR10(%FF4928, L9);
LOR8(%FF5412, L10);

V10Mac(%SF5809, %SF5808, N1, L1, N11, P23, %FF44, %SF44, L11);
V10Mac(%SF5811, %SF5810, N2, L2, N12, P22, %FF440, %SF440, L12);
V10Mac(%SF5813, %SF5812, N3, L3, N13, P21, %FF924, %SF924, L13);
V10Mac(%SF5815, %SF5814, N4, L4, N14, P20, %FF1496, %SF1496, L14);
V10Mac(%SF5817, %SF5816, N5, L5, N15, P19, %FF2156, %SF2156, L15);
V10Mac(%SF5819, %SF5818, N6, L6, N16, P18, %FF2904, %SF2904, L16);
V10Mac(%SF5821, %SF5820, N7, L7, N17, P17, %FF3652, %SF3652, L17);
V10Mac(%SF5823, %SF5822, N8, L8, N18, P16, %FF4312, %SF4312, L18);
V10Mac(%SF5825, %SF5824, N9, L9, N19, P15, %FF4884, %SF4884, L19);
V10Mac(%SF5827, %SF5826, N10, L10, N20, P14, %FF5368, %SF5368, L20);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16V8
%PartNumber:PALCE16V8H-15
%LastNode ? ?
%NumPins: 20
%FDF AND 0 P2 ~P2 N1 ~N1 P3 ~P3 N2 ~N2 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4 P6 ~P6
     N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 N7 ~N7 P9 ~P9 N8 ~N8 *
     
%MACRO V8MAC(S0:%SF, XorFuse:%SF, FeedBack:%TEXT, LorOutput:%TEXT, InFuse:%FF, 
             OutPin:%TEXT, TNode:%TEXT, EnableFuse:%SF, TLNode:%TEXT, 
	     TSNode:%TEXT, NextPin:%TEXT, PrevPin:%TEXT);

 %CASE %SF2192,%SF2193,%S0
   2:
     LOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,
         %InFuse+192,%InFuse+224;LorOutput);
     %IF %XorFuse=0 %THEN
      LINV(LorOutput;TLNode);
      DQFFC(TLNode, P1, IPL; TNode; 10,10,12,0,8,8,1,1,1,1,10,10,12,0,8,8,1,1,1,1);
     %ELSE	     
      DQFFC(LorOutput, P1, IPL; TNode; 10,10,12,0,8,8,1,1,1,1,10,10,12,0,8,8,1,1,1,1);
     %END;
     TSB(TNode, L17; OutPin; 15,15,15,15,15,15,15,15);
     BUF(TNode; FeedBack; 0,0,0,0);
  |3:
     LOR(%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,
         %InFuse+192,%InFuse+224;LorOutput);
     %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
      %IF %XorFuse = 0 %THEN
       INV(LorOutput; OutPin; 15,15,15,15);
      %ELSE
       BUF(LorOutput; OutPin; 15,15,15,15);
      %END;
     %ELSE
      %IF %XorFuse = 0 %THEN
       INV(LorOutput; TNode; 15,15,15,15);
      %ELSE
       BUF(LorOutput; TNode; 15,15,15,15);
      %END;
      TSB(TNode, %InFuse; OutPin; 15,15,15,15,15,15,15,15);
     %END;
     BUF(OutPin; FeedBack; 0,0,0,0);
  |4:
     LOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,
         %InFuse+192,%InFuse+224;LorOutput);
     %IF %XorFuse = 0 %THEN
      INV(LorOutput; OutPin; 15,15,15,15);
     %ELSE
      BUF(LorOutput; OutPin; 15,15,15,15);
     %END;
     BUF(ZERO; FeedBack; 0,0,0,0);
  |5:
     TSB(TSNode, ZERO; OutPin; 15,15,15,15,15,15,15,15); 
     BUF(NextPin; FeedBack; 0,0,0,0);    
  |7:
     LOR(%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,
         %InFuse+192,%InFuse+224;LorOutput);
     %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
      %IF %XorFuse = 0 %THEN
       INV(LorOutput; OutPin; 15,15,15,15);
      %ELSE
       BUF(LorOutput; OutPin; 15,15,15,15);
      %END;
     %ELSE
      %IF %XorFuse = 0 %THEN
       INV(LorOutput; TNode; 15,15,15,15);
      %ELSE
       BUF(LorOutput; TNode; 15,15,15,15);
      %END;
      TSB(TNode, %InFuse; OutPin; 15,15,15,15,15,15,15,15);
     %END;
     BUF(PrevPin; FeedBack; 0,0,0,0);
 %END;
%MACEND;

LINV(P11;L17);
     
V8MAC(%SF2120, %SF2048, N1, L1, %FF00, P19, N9, %SF00, L9, N17, P1, P1);
V8MAC(%SF2121, %SF2049, N2, L2, %FF256, P18, N10, %SF256, L10, N18, P19, P18);
V8MAC(%SF2122, %SF2050, N3, L3, %FF512, P17, N11, %SF512, L11, N19, P18, P17);
V8MAC(%SF2123, %SF2051, N4, L4, %FF768, P16, N12, %SF768, L12, N20, P17, P16);
V8MAC(%SF2124, %SF2052, N5, L5, %FF1024, P15, N13, %SF1024, L13, N21, P14, P15);
V8MAC(%SF2125, %SF2053, N6, L6, %FF1280, P14, N14, %SF1280, L14, N22, P13, P14);
V8MAC(%SF2126, %SF2054, N7, L7, %FF1536, P13, N15, %SF1536, L15, N23, P12, P13);
V8MAC(%SF2127, %SF2055, N8, L8, %FF1792, P12, N16, %SF1792, L16, N24, P11, P11);
%EndModel

%StartModel
%Manufacturer:AMD
%Type:16V8
%PartNumber:PALCE16V8H-25
%LastNode ? ?
%NumPins: 20
%FDF AND 0 P2 ~P2 N1 ~N1 P3 ~P3 N2 ~N2 P4 ~P4 N3 ~N3 P5 ~P5 N4 ~N4 P6 ~P6
     N5 ~N5 P7 ~P7 N6 ~N6 P8 ~P8 N7 ~N7 P9 ~P9 N8 ~N8 *
     
%MACRO V8MAC(S0:%SF, XorFuse:%SF, FeedBack:%TEXT, LorOutput:%TEXT, InFuse:%FF, 
             OutPin:%TEXT, TNode:%TEXT, EnableFuse:%SF, TLNode:%TEXT, 
	     TSNode:%TEXT, NextPin:%TEXT, PrevPin:%TEXT);

 %CASE %SF2192,%SF2193,%S0
   2:
     LOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,
         %InFuse+192,%InFuse+224;LorOutput);
     %IF %XorFuse=0 %THEN
      LINV(LorOutput;TLNode);
      DQFFC(TLNode, P1, IPL; TNode; 12,12,15,0,10,10,1,1,1,1,12,12,15,0,10,10,1,1,1,1);
     %ELSE	     
      DQFFC(LorOutput, P1, IPL; TNode; 12,12,15,0,10,10,1,1,1,1,12,12,15,0,10,10,1,1,1,1);
     %END;
     TSB(TNode, L17; OutPin; 20,20,20,20,20,20,20,20);
     BUF(TNode; FeedBack; 0,0,0,0);
  |3:
     LOR(%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,
         %InFuse+192,%InFuse+224;LorOutput);
     %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
      %IF %XorFuse = 0 %THEN
       INV(LorOutput; OutPin; 25,25,25,25);
      %ELSE
       BUF(LorOutput; OutPin; 25,25,25,25);
      %END;
     %ELSE
      %IF %XorFuse = 0 %THEN
       INV(LorOutput; TNode; 25,25,25,25);
      %ELSE
       BUF(LorOutput; TNode; 25,25,25,25);
      %END;
      TSB(TNode, %InFuse; OutPin; 20,20,20,20,20,20,20,20);
     %END;
     BUF(OutPin; FeedBack; 0,0,0,0);
  |4:
     LOR(%InFuse,%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,
         %InFuse+192,%InFuse+224;LorOutput);
     %IF %XorFuse = 0 %THEN
      INV(LorOutput; OutPin; 25,25,25,25);
     %ELSE
      BUF(LorOutput; OutPin; 25,25,25,25);
     %END;
     BUF(ZERO; FeedBack; 0,0,0,0);
  |5:
     TSB(TSNode, ZERO; OutPin; 20,20,20,20,20,20,20,20); 
     BUF(NextPin; FeedBack; 0,0,0,0);    
  |7:
     LOR(%InFuse+32,%InFuse+64,%InFuse+96,%InFuse+128,%InFuse+160,
         %InFuse+192,%InFuse+224;LorOutput);
     %IF %EnableFuse..%EnableFuse+31 = 1 %THEN
      %IF %XorFuse = 0 %THEN
       INV(LorOutput; OutPin; 25,25,25,25);
      %ELSE
       BUF(LorOutput; OutPin; 25,25,25,25);
      %END;
     %ELSE
      %IF %XorFuse = 0 %THEN
       INV(LorOutput; TNode; 25,25,25,25);
      %ELSE
       BUF(LorOutput; TNode; 25,25,25,25);
      %END;
      TSB(TNode, %InFuse; OutPin; 20,20,20,20,20,20,20,20);
     %END;
     BUF(PrevPin; FeedBack; 0,0,0,0);
 %END;
%MACEND;

LINV(P11;L17);
     
V8MAC(%SF2120, %SF2048, N1, L1, %FF00, P19, N9, %SF00, L9, N17, P1, P1);
V8MAC(%SF2121, %SF2049, N2, L2, %FF256, P18, N10, %SF256, L10, N18, P19, P18);
V8MAC(%SF2122, %SF2050, N3, L3, %FF512, P17, N11, %SF512, L11, N19, P18, P17);
V8MAC(%SF2123, %SF2051, N4, L4, %FF768, P16, N12, %SF768, L12, N20, P17, P16);
V8MAC(%SF2124, %SF2052, N5, L5, %FF1024, P15, N13, %SF1024, L13, N21, P14, P15);
V8MAC(%SF2125, %SF2053, N6, L6, %FF1280, P14, N14, %SF1280, L14, N22, P13, P14);
V8MAC(%SF2126, %SF2054, N7, L7, %FF1536, P13, N15, %SF1536, L15, N23, P12, P13);
V8MAC(%SF2127, %SF2055, N8, L8, %FF1792, P12, N16, %SF1792, L16, N24, P11, P11);
%EndModel

