(***************************************************************************)
(*                                                                         *)
(*                         Copyright (C) 1987-1990                         *)
(*                      by Gogesch Micro Systems, INC.                     *)
(*                                                                         *)
(*                           All rights reserved.                          *)
(*                                                                         *)
(***************************************************************************)


%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP900DC
%LastNode ? ?
%NumPins: 40
%FDF AND 0 ~P2 P2 ~P3 P3 ~P4 P4 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P17 P17 ~P18 P18
	 ~P19 P19 ~P22 P22 ~P23 P23 ~P24 P24 ~N13 N13 ~N14 N14 ~N15 N15
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22
	 ~N23 N23 ~N24 N24 ~P37 P37 ~P38 P38 ~P39 P39 *

%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;
%MACEND;

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 55,55,55,55);
   %ELSE
      BUF(LorOutput; TSBInput; 55,55,55,55);
      TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
   %END;
   BUF(OutPin; FeedBack; 5,5,5,5);
 |1,3:
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(OutPin; FeedBack; 5,5,5,5);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 55,55,55,55);
    %ELSE
       BUF(LorOutput; TSBInput; 55,55,55,55);
       TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(TNode; FeedBack; 0,0,0,0);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 55,55,55,55);
    %ELSE
       BUF(LorOutput; TSBInput; 55,55,55,55);
       TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(TNode; FeedBack; 0,0,0,0);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 %END;
%MACEND;

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P5, L25, %FF9288, N1, N25, N49, %FF9216, L49,
      N73, P1);
EP900(%SF17346, %SF10008, L2, P6, L26, %FF10008, N2, N26, N50, %FF9936, L50,
      N74, P1);
EP900(%SF17351, %SF10728, L3, P7, L27, %FF10728, N3, N27, N51, %FF10656, L51,
      N75, P1);
EP900(%SF17356, %SF11448, L4, P8, L28, %FF11448, N4, N28, N52, %FF11376, L52,
      N76, P1);
EP900(%SF17361, %SF12168, L5, P9, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P1);
EP900(%SF17366, %SF12888, L6, P10, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P1);
EP900(%SF17371, %SF13608, L7, P11, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P1);
EP900(%SF17376, %SF14328, L8, P12, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P1);
EP900(%SF17381, %SF15048, L9, P13, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P1);
EP900(%SF17386, %SF15768, L10, P14, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P1);
EP900(%SF17391, %SF16488, L11, P15, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P1);
EP900(%SF17396, %SF17208, L12, P16, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P1);
EP900(%SF17336, %SF8568, L13, P25, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P21);
EP900(%SF17331, %SF7848, L14, P26, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P21);
EP900(%SF17326, %SF7128, L15, P27, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P21);
EP900(%SF17321, %SF6408, L16, P28, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P21);
EP900(%SF17316, %SF5688, L17, P29, L41, %FF5688, N17, N41, N65, %FF5616, L65,
      N89, P21);
EP900(%SF17311, %SF4968, L18, P30, L42, %FF4968, N18, N42, N66, %FF4896, L66,
      N90, P21);
EP900(%SF17306, %SF4248, L19, P31, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P21);
EP900(%SF17301, %SF3528, L20, P32, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P21);
EP900(%SF17296, %SF2808, L21, P33, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P21);
EP900(%SF17291, %SF2088, L22, P34, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P21);
EP900(%SF17286, %SF1368, L23, P35, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P21);
EP900(%SF17281, %SF648, L24, P36, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P21);
%EndModel

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP900DC-2
%LastNode ? ?
%NumPins: 40
%FDF AND 0 ~P2 P2 ~P3 P3 ~P4 P4 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P17 P17 ~P18 P18
	 ~P19 P19 ~P22 P22 ~P23 P23 ~P24 P24 ~N13 N13 ~N14 N14 ~N15 N15
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22
	 ~N23 N23 ~N24 N24 ~P37 P37 ~P38 P38 ~P39 P39 *

%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;
%MACEND;

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 45,45,45,45);
   %ELSE
      BUF(LorOutput; TSBInput; 45,45,45,45);
      TSB(TSBInput, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
   %END;
   BUF(OutPin; FeedBack; 5,5,5,5);
 |1,3:
   BUF(LorOutput; Outpin; 45,45,45,45);
   BUF(OutPin; FeedBack; 5,5,5,5);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 45,45,45,45);
    %ELSE
       BUF(LorOutput; TSBInput; 45,45,45,45);
       TSB(TSBInput, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(LorOutput; Outpin; 45,45,45,45);
   BUF(TNode; FeedBack; 0,0,0,0);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 45,45,45,45);
    %ELSE
       BUF(LorOutput; TSBInput; 45,45,45,45);
       TSB(TSBInput, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(LorOutput; Outpin; 45,45,45,45);
   BUF(TNode; FeedBack; 0,0,0,0);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 %END;
%MACEND;

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P5, L25, %FF9288, N1, N25, N49, %FF9216, L49,
      N73, P1);
EP900(%SF17346, %SF10008, L2, P6, L26, %FF10008, N2, N26, N50, %FF9936, L50,
      N74, P1);
EP900(%SF17351, %SF10728, L3, P7, L27, %FF10728, N3, N27, N51, %FF10656, L51,
      N75, P1);
EP900(%SF17356, %SF11448, L4, P8, L28, %FF11448, N4, N28, N52, %FF11376, L52,
      N76, P1);
EP900(%SF17361, %SF12168, L5, P9, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P1);
EP900(%SF17366, %SF12888, L6, P10, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P1);
EP900(%SF17371, %SF13608, L7, P11, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P1);
EP900(%SF17376, %SF14328, L8, P12, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P1);
EP900(%SF17381, %SF15048, L9, P13, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P1);
EP900(%SF17386, %SF15768, L10, P14, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P1);
EP900(%SF17391, %SF16488, L11, P15, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P1);
EP900(%SF17396, %SF17208, L12, P16, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P1);
EP900(%SF17336, %SF8568, L13, P25, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P21);
EP900(%SF17331, %SF7848, L14, P26, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P21);
EP900(%SF17326, %SF7128, L15, P27, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P21);
EP900(%SF17321, %SF6408, L16, P28, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P21);
EP900(%SF17316, %SF5688, L17, P29, L41, %FF5688, N17, N41, N65, %FF5616, L65,
      N89, P21);
EP900(%SF17311, %SF4968, L18, P30, L42, %FF4968, N18, N42, N66, %FF4896, L66,
      N90, P21);
EP900(%SF17306, %SF4248, L19, P31, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P21);
EP900(%SF17301, %SF3528, L20, P32, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P21);
EP900(%SF17296, %SF2808, L21, P33, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P21);
EP900(%SF17291, %SF2088, L22, P34, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P21);
EP900(%SF17286, %SF1368, L23, P35, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P21);
EP900(%SF17281, %SF648, L24, P36, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P21);
%EndModel

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP900DC-3
%LastNode ? ?
%NumPins: 40
%FDF AND 0 ~P2 P2 ~P3 P3 ~P4 P4 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P17 P17 ~P18 P18
	 ~P19 P19 ~P22 P22 ~P23 P23 ~P24 P24 ~N13 N13 ~N14 N14 ~N15 N15
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22
	 ~N23 N23 ~N24 N24 ~P37 P37 ~P38 P38 ~P39 P39 *

%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;
%MACEND;

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 50,50,50,50);
   %ELSE
      BUF(LorOutput; TSBInput; 50,50,50,50);
      TSB(TSBInput, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
   %END;
   BUF(OutPin; FeedBack; 5,5,5,5);
 |1,3:
   BUF(LorOutput; Outpin; 50,50,50,50);
   BUF(OutPin; FeedBack; 5,5,5,5);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 50,50,50,50);
    %ELSE
       BUF(LorOutput; TSBInput; 50,50,50,50);
       TSB(TSBInput, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);
   BUF(LorOutput; Outpin; 50,50,50,50);
   BUF(TNode; FeedBack; 0,0,0,0);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 50,50,50,50);
    %ELSE
       BUF(LorOutput; TSBInput; 50,50,50,50);
       TSB(TSBInput, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);
   BUF(LorOutput; Outpin; 50,50,50,50);
   BUF(TNode; FeedBack; 0,0,0,0);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 %END;
%MACEND;

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P5, L25, %FF9288, N1, N25, N49, %FF9216, L49,
      N73, P1);
EP900(%SF17346, %SF10008, L2, P6, L26, %FF10008, N2, N26, N50, %FF9936, L50,
      N74, P1);
EP900(%SF17351, %SF10728, L3, P7, L27, %FF10728, N3, N27, N51, %FF10656, L51,
      N75, P1);
EP900(%SF17356, %SF11448, L4, P8, L28, %FF11448, N4, N28, N52, %FF11376, L52,
      N76, P1);
EP900(%SF17361, %SF12168, L5, P9, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P1);
EP900(%SF17366, %SF12888, L6, P10, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P1);
EP900(%SF17371, %SF13608, L7, P11, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P1);
EP900(%SF17376, %SF14328, L8, P12, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P1);
EP900(%SF17381, %SF15048, L9, P13, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P1);
EP900(%SF17386, %SF15768, L10, P14, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P1);
EP900(%SF17391, %SF16488, L11, P15, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P1);
EP900(%SF17396, %SF17208, L12, P16, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P1);
EP900(%SF17336, %SF8568, L13, P25, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P21);
EP900(%SF17331, %SF7848, L14, P26, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P21);
EP900(%SF17326, %SF7128, L15, P27, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P21);
EP900(%SF17321, %SF6408, L16, P28, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P21);
EP900(%SF17316, %SF5688, L17, P29, L41, %FF5688, N17, N41, N65, %FF5616, L65,
      N89, P21);
EP900(%SF17311, %SF4968, L18, P30, L42, %FF4968, N18, N42, N66, %FF4896, L66,
      N90, P21);
EP900(%SF17306, %SF4248, L19, P31, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P21);
EP900(%SF17301, %SF3528, L20, P32, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P21);
EP900(%SF17296, %SF2808, L21, P33, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P21);
EP900(%SF17291, %SF2088, L22, P34, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P21);
EP900(%SF17286, %SF1368, L23, P35, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P21);
EP900(%SF17281, %SF648, L24, P36, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P21);
%EndModel

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP900DI
%LastNode ? ?
%NumPins: 40
%FDF AND 0 ~P2 P2 ~P3 P3 ~P4 P4 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P17 P17 ~P18 P18
	 ~P19 P19 ~P22 P22 ~P23 P23 ~P24 P24 ~N13 N13 ~N14 N14 ~N15 N15
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22
	 ~N23 N23 ~N24 N24 ~P37 P37 ~P38 P38 ~P39 P39 *

%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;
%MACEND;

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 55,55,55,55);
   %ELSE
      BUF(LorOutput; TSBInput; 55,55,55,55);
      TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
   %END;
   BUF(OutPin; FeedBack; 5,5,5,5);
 |1,3:
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(OutPin; FeedBack; 5,5,5,5);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 55,55,55,55);
    %ELSE
       BUF(LorOutput; TSBInput; 55,55,55,55);
       TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(TNode; FeedBack; 0,0,0,0);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 55,55,55,55);
    %ELSE
       BUF(LorOutput; TSBInput; 55,55,55,55);
       TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(TNode; FeedBack; 0,0,0,0);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 %END;
%MACEND;

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P5, L25, %FF9288, N1, N25, N49, %FF9216, L49,
      N73, P1);
EP900(%SF17346, %SF10008, L2, P6, L26, %FF10008, N2, N26, N50, %FF9936, L50,
      N74, P1);
EP900(%SF17351, %SF10728, L3, P7, L27, %FF10728, N3, N27, N51, %FF10656, L51,
      N75, P1);
EP900(%SF17356, %SF11448, L4, P8, L28, %FF11448, N4, N28, N52, %FF11376, L52,
      N76, P1);
EP900(%SF17361, %SF12168, L5, P9, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P1);
EP900(%SF17366, %SF12888, L6, P10, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P1);
EP900(%SF17371, %SF13608, L7, P11, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P1);
EP900(%SF17376, %SF14328, L8, P12, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P1);
EP900(%SF17381, %SF15048, L9, P13, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P1);
EP900(%SF17386, %SF15768, L10, P14, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P1);
EP900(%SF17391, %SF16488, L11, P15, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P1);
EP900(%SF17396, %SF17208, L12, P16, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P1);
EP900(%SF17336, %SF8568, L13, P25, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P21);
EP900(%SF17331, %SF7848, L14, P26, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P21);
EP900(%SF17326, %SF7128, L15, P27, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P21);
EP900(%SF17321, %SF6408, L16, P28, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P21);
EP900(%SF17316, %SF5688, L17, P29, L41, %FF5688, N17, N41, N65, %FF5616, L65,
      N89, P21);
EP900(%SF17311, %SF4968, L18, P30, L42, %FF4968, N18, N42, N66, %FF4896, L66,
      N90, P21);
EP900(%SF17306, %SF4248, L19, P31, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P21);
EP900(%SF17301, %SF3528, L20, P32, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P21);
EP900(%SF17296, %SF2808, L21, P33, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P21);
EP900(%SF17291, %SF2088, L22, P34, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P21);
EP900(%SF17286, %SF1368, L23, P35, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P21);
EP900(%SF17281, %SF648, L24, P36, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P21);
%EndModel

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP900DI-3
%LastNode ? ?
%NumPins: 40
%FDF AND 0 ~P2 P2 ~P3 P3 ~P4 P4 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P17 P17 ~P18 P18
	 ~P19 P19 ~P22 P22 ~P23 P23 ~P24 P24 ~N13 N13 ~N14 N14 ~N15 N15
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22
	 ~N23 N23 ~N24 N24 ~P37 P37 ~P38 P38 ~P39 P39 *

%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;
%MACEND;

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 50,50,50,50);
   %ELSE
      BUF(LorOutput; TSBInput; 50,50,50,50);
      TSB(TSBInput, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
   %END;
   BUF(OutPin; FeedBack; 5,5,5,5);
 |1,3:
   BUF(LorOutput; Outpin; 50,50,50,50);
   BUF(OutPin; FeedBack; 5,5,5,5);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 50,50,50,50);
    %ELSE
       BUF(LorOutput; TSBInput; 50,50,50,50);
       TSB(TSBInput, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);
   BUF(LorOutput; Outpin; 50,50,50,50);
   BUF(TNode; FeedBack; 0,0,0,0);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 50,50,50,50);
    %ELSE
       BUF(LorOutput; TSBInput; 50,50,50,50);
       TSB(TSBInput, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);
   BUF(LorOutput; Outpin; 50,50,50,50);
   BUF(TNode; FeedBack; 0,0,0,0);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 %END;
%MACEND;

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P5, L25, %FF9288, N1, N25, N49, %FF9216, L49,
      N73, P1);
EP900(%SF17346, %SF10008, L2, P6, L26, %FF10008, N2, N26, N50, %FF9936, L50,
      N74, P1);
EP900(%SF17351, %SF10728, L3, P7, L27, %FF10728, N3, N27, N51, %FF10656, L51,
      N75, P1);
EP900(%SF17356, %SF11448, L4, P8, L28, %FF11448, N4, N28, N52, %FF11376, L52,
      N76, P1);
EP900(%SF17361, %SF12168, L5, P9, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P1);
EP900(%SF17366, %SF12888, L6, P10, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P1);
EP900(%SF17371, %SF13608, L7, P11, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P1);
EP900(%SF17376, %SF14328, L8, P12, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P1);
EP900(%SF17381, %SF15048, L9, P13, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P1);
EP900(%SF17386, %SF15768, L10, P14, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P1);
EP900(%SF17391, %SF16488, L11, P15, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P1);
EP900(%SF17396, %SF17208, L12, P16, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P1);
EP900(%SF17336, %SF8568, L13, P25, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P21);
EP900(%SF17331, %SF7848, L14, P26, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P21);
EP900(%SF17326, %SF7128, L15, P27, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P21);
EP900(%SF17321, %SF6408, L16, P28, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P21);
EP900(%SF17316, %SF5688, L17, P29, L41, %FF5688, N17, N41, N65, %FF5616, L65,
      N89, P21);
EP900(%SF17311, %SF4968, L18, P30, L42, %FF4968, N18, N42, N66, %FF4896, L66,
      N90, P21);
EP900(%SF17306, %SF4248, L19, P31, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P21);
EP900(%SF17301, %SF3528, L20, P32, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P21);
EP900(%SF17296, %SF2808, L21, P33, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P21);
EP900(%SF17291, %SF2088, L22, P34, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P21);
EP900(%SF17286, %SF1368, L23, P35, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P21);
EP900(%SF17281, %SF648, L24, P36, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P21);
%EndModel

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP900DM
%LastNode ? ?
%NumPins: 40
%FDF AND 0 ~P2 P2 ~P3 P3 ~P4 P4 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P17 P17 ~P18 P18
	 ~P19 P19 ~P22 P22 ~P23 P23 ~P24 P24 ~N13 N13 ~N14 N14 ~N15 N15
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22
	 ~N23 N23 ~N24 N24 ~P37 P37 ~P38 P38 ~P39 P39 *

%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;
%MACEND;

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 55,55,55,55);
   %ELSE
      BUF(LorOutput; TSBInput; 55,55,55,55);
      TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
   %END;
   BUF(OutPin; FeedBack; 5,5,5,5);
 |1,3:
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(OutPin; FeedBack; 5,5,5,5);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 55,55,55,55);
    %ELSE
       BUF(LorOutput; TSBInput; 55,55,55,55);
       TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(TNode; FeedBack; 0,0,0,0);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 55,55,55,55);
    %ELSE
       BUF(LorOutput; TSBInput; 55,55,55,55);
       TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(TNode; FeedBack; 0,0,0,0);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 %END;
%MACEND;

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P5, L25, %FF9288, N1, N25, N49, %FF9216, L49,
      N73, P1);
EP900(%SF17346, %SF10008, L2, P6, L26, %FF10008, N2, N26, N50, %FF9936, L50,
      N74, P1);
EP900(%SF17351, %SF10728, L3, P7, L27, %FF10728, N3, N27, N51, %FF10656, L51,
      N75, P1);
EP900(%SF17356, %SF11448, L4, P8, L28, %FF11448, N4, N28, N52, %FF11376, L52,
      N76, P1);
EP900(%SF17361, %SF12168, L5, P9, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P1);
EP900(%SF17366, %SF12888, L6, P10, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P1);
EP900(%SF17371, %SF13608, L7, P11, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P1);
EP900(%SF17376, %SF14328, L8, P12, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P1);
EP900(%SF17381, %SF15048, L9, P13, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P1);
EP900(%SF17386, %SF15768, L10, P14, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P1);
EP900(%SF17391, %SF16488, L11, P15, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P1);
EP900(%SF17396, %SF17208, L12, P16, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P1);
EP900(%SF17336, %SF8568, L13, P25, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P21);
EP900(%SF17331, %SF7848, L14, P26, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P21);
EP900(%SF17326, %SF7128, L15, P27, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P21);
EP900(%SF17321, %SF6408, L16, P28, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P21);
EP900(%SF17316, %SF5688, L17, P29, L41, %FF5688, N17, N41, N65, %FF5616, L65,
      N89, P21);
EP900(%SF17311, %SF4968, L18, P30, L42, %FF4968, N18, N42, N66, %FF4896, L66,
      N90, P21);
EP900(%SF17306, %SF4248, L19, P31, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P21);
EP900(%SF17301, %SF3528, L20, P32, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P21);
EP900(%SF17296, %SF2808, L21, P33, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P21);
EP900(%SF17291, %SF2088, L22, P34, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P21);
EP900(%SF17286, %SF1368, L23, P35, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P21);
EP900(%SF17281, %SF648, L24, P36, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P21);
%EndModel

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP900JC
%LastNode ? ?
%NumPins: 44
%FDF AND 0 ~P3 P3 ~P4 P4 ~P5 P5 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P19 P19 ~P20 P20
	 ~P21 P21 ~P25 P25 ~P26 P26 ~P27 P27 ~N13 N13 ~N14 N14 ~N15 N15
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22
	 ~N23 N23 ~N24 N24 ~P41 P41 ~P42 P42 ~P43 P43 *

%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;
%MACEND;

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 55,55,55,55);
   %ELSE
      BUF(LorOutput; TSBInput; 55,55,55,55);
      TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
   %END;
   BUF(OutPin; FeedBack; 5,5,5,5);
 |1,3:
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(OutPin; FeedBack; 5,5,5,5);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 55,55,55,55);
    %ELSE
       BUF(LorOutput; TSBInput; 55,55,55,55);
       TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(TNode; FeedBack; 0,0,0,0);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 55,55,55,55);
    %ELSE
       BUF(LorOutput; TSBInput; 55,55,55,55);
       TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(TNode; FeedBack; 0,0,0,0);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 %END;
%MACEND;

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P6, L25, %FF9288, N1, N25, N49, %FF9216, L49,
      N73, P2);
EP900(%SF17346, %SF10008, L2, P7, L26, %FF10008, N2, N26, N50, %FF9936, L50,
      N74, P2);
EP900(%SF17351, %SF10728, L3, P8, L27, %FF10728, N3, N27, N51, %FF10656, L51,
      N75, P2);
EP900(%SF17356, %SF11448, L4, P9, L28, %FF11448, N4, N28, N52, %FF11376, L52,
      N76, P2);
EP900(%SF17361, %SF12168, L5, P10, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P2);
EP900(%SF17366, %SF12888, L6, P11, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P2);
EP900(%SF17371, %SF13608, L7, P12, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P2);
EP900(%SF17376, %SF14328, L8, P13, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P2);
EP900(%SF17381, %SF15048, L9, P14, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P2);
EP900(%SF17386, %SF15768, L10, P15, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P2);
EP900(%SF17391, %SF16488, L11, P16, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P2);
EP900(%SF17396, %SF17208, L12, P18, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P2);
EP900(%SF17336, %SF8568, L13, P28, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P24);
EP900(%SF17331, %SF7848, L14, P29, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P24);
EP900(%SF17326, %SF7128, L15, P30, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P24);
EP900(%SF17321, %SF6408, L16, P31, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P24);
EP900(%SF17316, %SF5688, L17, P32, L41, %FF5688, N17, N41, N65, %FF5616, L65,
      N89, P24);
EP900(%SF17311, %SF4968, L18, P33, L42, %FF4968, N18, N42, N66, %FF4896, L66,
      N90, P24);
EP900(%SF17306, %SF4248, L19, P34, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P24);
EP900(%SF17301, %SF3528, L20, P35, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P24);
EP900(%SF17296, %SF2808, L21, P36, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P24);
EP900(%SF17291, %SF2088, L22, P37, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P24);
EP900(%SF17286, %SF1368, L23, P38, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P24);
EP900(%SF17281, %SF648, L24, P40, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P24);
%EndModel

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP900JC-2
%LastNode ? ?
%NumPins: 44
%FDF AND 0 ~P3 P3 ~P4 P4 ~P5 P5 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P19 P19 ~P20 P20
	 ~P21 P21 ~P25 P25 ~P26 P26 ~P27 P27 ~N13 N13 ~N14 N14 ~N15 N15
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22
	 ~N23 N23 ~N24 N24 ~P41 P41 ~P42 P42 ~P43 P43 *

%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;
%MACEND;

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 45,45,45,45);
   %ELSE
      BUF(LorOutput; TSBInput; 45,45,45,45);
      TSB(TSBInput, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
   %END;
   BUF(OutPin; FeedBack; 5,5,5,5);
 |1,3:
   BUF(LorOutput; Outpin; 45,45,45,45);
   BUF(OutPin; FeedBack; 5,5,5,5);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 45,45,45,45);
    %ELSE
       BUF(LorOutput; TSBInput; 45,45,45,45);
       TSB(TSBInput, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(LorOutput; Outpin; 45,45,45,45);
   BUF(TNode; FeedBack; 0,0,0,0);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 45,45,45,45);
    %ELSE
       BUF(LorOutput; TSBInput; 45,45,45,45);
       TSB(TSBInput, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(LorOutput; Outpin; 45,45,45,45);
   BUF(TNode; FeedBack; 0,0,0,0);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 %END;
%MACEND;

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P6, L25, %FF9288, N1, N25, N49, %FF9216, L49,
      N73, P2);
EP900(%SF17346, %SF10008, L2, P7, L26, %FF10008, N2, N26, N50, %FF9936, L50,
      N74, P2);
EP900(%SF17351, %SF10728, L3, P8, L27, %FF10728, N3, N27, N51, %FF10656, L51,
      N75, P2);
EP900(%SF17356, %SF11448, L4, P9, L28, %FF11448, N4, N28, N52, %FF11376, L52,
      N76, P2);
EP900(%SF17361, %SF12168, L5, P10, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P2);
EP900(%SF17366, %SF12888, L6, P11, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P2);
EP900(%SF17371, %SF13608, L7, P12, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P2);
EP900(%SF17376, %SF14328, L8, P13, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P2);
EP900(%SF17381, %SF15048, L9, P14, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P2);
EP900(%SF17386, %SF15768, L10, P15, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P2);
EP900(%SF17391, %SF16488, L11, P16, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P2);
EP900(%SF17396, %SF17208, L12, P18, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P2);
EP900(%SF17336, %SF8568, L13, P28, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P24);
EP900(%SF17331, %SF7848, L14, P29, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P24);
EP900(%SF17326, %SF7128, L15, P30, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P24);
EP900(%SF17321, %SF6408, L16, P31, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P24);
EP900(%SF17316, %SF5688, L17, P32, L41, %FF5688, N17, N41, N65, %FF5616, L65,
      N89, P24);
EP900(%SF17311, %SF4968, L18, P33, L42, %FF4968, N18, N42, N66, %FF4896, L66,
      N90, P24);
EP900(%SF17306, %SF4248, L19, P34, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P24);
EP900(%SF17301, %SF3528, L20, P35, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P24);
EP900(%SF17296, %SF2808, L21, P36, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P24);
EP900(%SF17291, %SF2088, L22, P37, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P24);
EP900(%SF17286, %SF1368, L23, P38, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P24);
EP900(%SF17281, %SF648, L24, P40, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P24);
%EndModel

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP900JC-3
%LastNode ? ?
%NumPins: 44
%FDF AND 0 ~P3 P3 ~P4 P4 ~P5 P5 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P19 P19 ~P20 P20
	 ~P21 P21 ~P25 P25 ~P26 P26 ~P27 P27 ~N13 N13 ~N14 N14 ~N15 N15
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22
	 ~N23 N23 ~N24 N24 ~P41 P41 ~P42 P42 ~P43 P43 *

%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;
%MACEND;

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 50,50,50,50);
   %ELSE
      BUF(LorOutput; TSBInput; 50,50,50,50);
      TSB(TSBInput, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
   %END;
   BUF(OutPin; FeedBack; 5,5,5,5);
 |1,3:
   BUF(LorOutput; Outpin; 50,50,50,50);
   BUF(OutPin; FeedBack; 5,5,5,5);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 50,50,50,50);
    %ELSE
       BUF(LorOutput; TSBInput; 50,50,50,50);
       TSB(TSBInput, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);
   BUF(LorOutput; Outpin; 50,50,50,50);
   BUF(TNode; FeedBack; 0,0,0,0);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 50,50,50,50);
    %ELSE
       BUF(LorOutput; TSBInput; 50,50,50,50);
       TSB(TSBInput, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);
   BUF(LorOutput; Outpin; 50,50,50,50);
   BUF(TNode; FeedBack; 0,0,0,0);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 %END;
%MACEND;

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P6, L25, %FF9288, N1, N25, N49, %FF9216, L49,
      N73, P2);
EP900(%SF17346, %SF10008, L2, P7, L26, %FF10008, N2, N26, N50, %FF9936, L50,
      N74, P2);
EP900(%SF17351, %SF10728, L3, P8, L27, %FF10728, N3, N27, N51, %FF10656, L51,
      N75, P2);
EP900(%SF17356, %SF11448, L4, P9, L28, %FF11448, N4, N28, N52, %FF11376, L52,
      N76, P2);
EP900(%SF17361, %SF12168, L5, P10, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P2);
EP900(%SF17366, %SF12888, L6, P11, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P2);
EP900(%SF17371, %SF13608, L7, P12, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P2);
EP900(%SF17376, %SF14328, L8, P13, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P2);
EP900(%SF17381, %SF15048, L9, P14, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P2);
EP900(%SF17386, %SF15768, L10, P15, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P2);
EP900(%SF17391, %SF16488, L11, P16, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P2);
EP900(%SF17396, %SF17208, L12, P18, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P2);
EP900(%SF17336, %SF8568, L13, P28, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P24);
EP900(%SF17331, %SF7848, L14, P29, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P24);
EP900(%SF17326, %SF7128, L15, P30, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P24);
EP900(%SF17321, %SF6408, L16, P31, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P24);
EP900(%SF17316, %SF5688, L17, P32, L41, %FF5688, N17, N41, N65, %FF5616, L65,
      N89, P24);
EP900(%SF17311, %SF4968, L18, P33, L42, %FF4968, N18, N42, N66, %FF4896, L66,
      N90, P24);
EP900(%SF17306, %SF4248, L19, P34, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P24);
EP900(%SF17301, %SF3528, L20, P35, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P24);
EP900(%SF17296, %SF2808, L21, P36, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P24);
EP900(%SF17291, %SF2088, L22, P37, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P24);
EP900(%SF17286, %SF1368, L23, P38, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P24);
EP900(%SF17281, %SF648, L24, P40, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P24);
%EndModel

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP900JI
%LastNode ? ?
%NumPins: 44
%FDF AND 0 ~P3 P3 ~P4 P4 ~P5 P5 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P19 P19 ~P20 P20
	 ~P21 P21 ~P25 P25 ~P26 P26 ~P27 P27 ~N13 N13 ~N14 N14 ~N15 N15
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22
	 ~N23 N23 ~N24 N24 ~P41 P41 ~P42 P42 ~P43 P43 *

%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;
%MACEND;

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 55,55,55,55);
   %ELSE
      BUF(LorOutput; TSBInput; 55,55,55,55);
      TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
   %END;
   BUF(OutPin; FeedBack; 5,5,5,5);
 |1,3:
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(OutPin; FeedBack; 5,5,5,5);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 55,55,55,55);
    %ELSE
       BUF(LorOutput; TSBInput; 55,55,55,55);
       TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(TNode; FeedBack; 0,0,0,0);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 55,55,55,55);
    %ELSE
       BUF(LorOutput; TSBInput; 55,55,55,55);
       TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(TNode; FeedBack; 0,0,0,0);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 %END;
%MACEND;

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P6, L25, %FF9288, N1, N25, N49, %FF9216, L49,
      N73, P2);
EP900(%SF17346, %SF10008, L2, P7, L26, %FF10008, N2, N26, N50, %FF9936, L50,
      N74, P2);
EP900(%SF17351, %SF10728, L3, P8, L27, %FF10728, N3, N27, N51, %FF10656, L51,
      N75, P2);
EP900(%SF17356, %SF11448, L4, P9, L28, %FF11448, N4, N28, N52, %FF11376, L52,
      N76, P2);
EP900(%SF17361, %SF12168, L5, P10, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P2);
EP900(%SF17366, %SF12888, L6, P11, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P2);
EP900(%SF17371, %SF13608, L7, P12, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P2);
EP900(%SF17376, %SF14328, L8, P13, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P2);
EP900(%SF17381, %SF15048, L9, P14, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P2);
EP900(%SF17386, %SF15768, L10, P15, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P2);
EP900(%SF17391, %SF16488, L11, P16, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P2);
EP900(%SF17396, %SF17208, L12, P18, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P2);
EP900(%SF17336, %SF8568, L13, P28, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P24);
EP900(%SF17331, %SF7848, L14, P29, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P24);
EP900(%SF17326, %SF7128, L15, P30, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P24);
EP900(%SF17321, %SF6408, L16, P31, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P24);
EP900(%SF17316, %SF5688, L17, P32, L41, %FF5688, N17, N41, N65, %FF5616, L65,
      N89, P24);
EP900(%SF17311, %SF4968, L18, P33, L42, %FF4968, N18, N42, N66, %FF4896, L66,
      N90, P24);
EP900(%SF17306, %SF4248, L19, P34, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P24);
EP900(%SF17301, %SF3528, L20, P35, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P24);
EP900(%SF17296, %SF2808, L21, P36, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P24);
EP900(%SF17291, %SF2088, L22, P37, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P24);
EP900(%SF17286, %SF1368, L23, P38, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P24);
EP900(%SF17281, %SF648, L24, P40, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P24);
%EndModel

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP900JI-3
%LastNode ? ?
%NumPins: 44
%FDF AND 0 ~P3 P3 ~P4 P4 ~P5 P5 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P19 P19 ~P20 P20
	 ~P21 P21 ~P25 P25 ~P26 P26 ~P27 P27 ~N13 N13 ~N14 N14 ~N15 N15
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22
	 ~N23 N23 ~N24 N24 ~P41 P41 ~P42 P42 ~P43 P43 *

%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;
%MACEND;

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 50,50,50,50);
   %ELSE
      BUF(LorOutput; TSBInput; 50,50,50,50);
      TSB(TSBInput, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
   %END;
   BUF(OutPin; FeedBack; 5,5,5,5);
 |1,3:
   BUF(LorOutput; Outpin; 50,50,50,50);
   BUF(OutPin; FeedBack; 5,5,5,5);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 50,50,50,50);
    %ELSE
       BUF(LorOutput; TSBInput; 50,50,50,50);
       TSB(TSBInput, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);
   BUF(LorOutput; Outpin; 50,50,50,50);
   BUF(TNode; FeedBack; 0,0,0,0);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 50,50,50,50);
    %ELSE
       BUF(LorOutput; TSBInput; 50,50,50,50);
       TSB(TSBInput, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);
   BUF(LorOutput; Outpin; 50,50,50,50);
   BUF(TNode; FeedBack; 0,0,0,0);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 %END;
%MACEND;

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P6, L25, %FF9288, N1, N25, N49, %FF9216, L49,
      N73, P2);
EP900(%SF17346, %SF10008, L2, P7, L26, %FF10008, N2, N26, N50, %FF9936, L50,
      N74, P2);
EP900(%SF17351, %SF10728, L3, P8, L27, %FF10728, N3, N27, N51, %FF10656, L51,
      N75, P2);
EP900(%SF17356, %SF11448, L4, P9, L28, %FF11448, N4, N28, N52, %FF11376, L52,
      N76, P2);
EP900(%SF17361, %SF12168, L5, P10, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P2);
EP900(%SF17366, %SF12888, L6, P11, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P2);
EP900(%SF17371, %SF13608, L7, P12, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P2);
EP900(%SF17376, %SF14328, L8, P13, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P2);
EP900(%SF17381, %SF15048, L9, P14, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P2);
EP900(%SF17386, %SF15768, L10, P15, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P2);
EP900(%SF17391, %SF16488, L11, P16, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P2);
EP900(%SF17396, %SF17208, L12, P18, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P2);
EP900(%SF17336, %SF8568, L13, P28, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P24);
EP900(%SF17331, %SF7848, L14, P29, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P24);
EP900(%SF17326, %SF7128, L15, P30, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P24);
EP900(%SF17321, %SF6408, L16, P31, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P24);
EP900(%SF17316, %SF5688, L17, P32, L41, %FF5688, N17, N41, N65, %FF5616, L65,
      N89, P24);
EP900(%SF17311, %SF4968, L18, P33, L42, %FF4968, N18, N42, N66, %FF4896, L66,
      N90, P24);
EP900(%SF17306, %SF4248, L19, P34, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P24);
EP900(%SF17301, %SF3528, L20, P35, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P24);
EP900(%SF17296, %SF2808, L21, P36, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P24);
EP900(%SF17291, %SF2088, L22, P37, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P24);
EP900(%SF17286, %SF1368, L23, P38, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P24);
EP900(%SF17281, %SF648, L24, P40, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P24);
%EndModel

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP900JM
%LastNode ? ?
%NumPins: 44
%FDF AND 0 ~P3 P3 ~P4 P4 ~P5 P5 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P19 P19 ~P20 P20
	 ~P21 P21 ~P25 P25 ~P26 P26 ~P27 P27 ~N13 N13 ~N14 N14 ~N15 N15
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22
	 ~N23 N23 ~N24 N24 ~P41 P41 ~P42 P42 ~P43 P43 *

%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;
%MACEND;

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 55,55,55,55);
   %ELSE
      BUF(LorOutput; TSBInput; 55,55,55,55);
      TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
   %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |1,3:
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 55,55,55,55);
    %ELSE
       BUF(LorOutput; TSBInput; 55,55,55,55);
       TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(TNode; FeedBack; 0,0,0,0);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 55,55,55,55);
    %ELSE
       BUF(LorOutput; TSBInput; 55,55,55,55);
       TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(TNode; FeedBack; 0,0,0,0);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 %END;
%MACEND;

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P6, L25, %FF9288, N1, N25, N49, %FF9216, L49,
      N73, P2);
EP900(%SF17346, %SF10008, L2, P7, L26, %FF10008, N2, N26, N50, %FF9936, L50,
      N74, P2);
EP900(%SF17351, %SF10728, L3, P8, L27, %FF10728, N3, N27, N51, %FF10656, L51,
      N75, P2);
EP900(%SF17356, %SF11448, L4, P9, L28, %FF11448, N4, N28, N52, %FF11376, L52,
      N76, P2);
EP900(%SF17361, %SF12168, L5, P10, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P2);
EP900(%SF17366, %SF12888, L6, P11, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P2);
EP900(%SF17371, %SF13608, L7, P12, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P2);
EP900(%SF17376, %SF14328, L8, P13, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P2);
EP900(%SF17381, %SF15048, L9, P14, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P2);
EP900(%SF17386, %SF15768, L10, P15, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P2);
EP900(%SF17391, %SF16488, L11, P16, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P2);
EP900(%SF17396, %SF17208, L12, P18, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P2);
EP900(%SF17336, %SF8568, L13, P28, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P24);
EP900(%SF17331, %SF7848, L14, P29, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P24);
EP900(%SF17326, %SF7128, L15, P30, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P24);
EP900(%SF17321, %SF6408, L16, P31, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P24);
EP900(%SF17316, %SF5688, L17, P32, L41, %FF5688, N17, N41, N65, %FF5616, L65,
      N89, P24);
EP900(%SF17311, %SF4968, L18, P33, L42, %FF4968, N18, N42, N66, %FF4896, L66,
      N90, P24);
EP900(%SF17306, %SF4248, L19, P34, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P24);
EP900(%SF17301, %SF3528, L20, P35, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P24);
EP900(%SF17296, %SF2808, L21, P36, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P24);
EP900(%SF17291, %SF2088, L22, P37, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P24);
EP900(%SF17286, %SF1368, L23, P38, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P24);
EP900(%SF17281, %SF648, L24, P40, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P24);
%EndModel

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP900LC
%LastNode ? ?
%NumPins: 44
%FDF AND 0 ~P3 P3 ~P4 P4 ~P5 P5 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P19 P19 ~P20 P20
	 ~P21 P21 ~P25 P25 ~P26 P26 ~P27 P27 ~N13 N13 ~N14 N14 ~N15 N15
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22
	 ~N23 N23 ~N24 N24 ~P41 P41 ~P42 P42 ~P43 P43 *

%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;
%MACEND;

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 55,55,55,55);
   %ELSE
      BUF(LorOutput; TSBInput; 55,55,55,55);
      TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
   %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |1,3:
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 55,55,55,55);
    %ELSE
       BUF(LorOutput; TSBInput; 55,55,55,55);
       TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(TNode; FeedBack; 0,0,0,0);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 55,55,55,55);
    %ELSE
       BUF(LorOutput; TSBInput; 55,55,55,55);
       TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(TNode; FeedBack; 0,0,0,0);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 %END;
%MACEND;

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P6, L25, %FF9288, N1, N25, N49, %FF9216, L49,
      N73, P2);
EP900(%SF17346, %SF10008, L2, P7, L26, %FF10008, N2, N26, N50, %FF9936, L50,
      N74, P2);
EP900(%SF17351, %SF10728, L3, P8, L27, %FF10728, N3, N27, N51, %FF10656, L51,
      N75, P2);
EP900(%SF17356, %SF11448, L4, P9, L28, %FF11448, N4, N28, N52, %FF11376, L52,
      N76, P2);
EP900(%SF17361, %SF12168, L5, P10, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P2);
EP900(%SF17366, %SF12888, L6, P11, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P2);
EP900(%SF17371, %SF13608, L7, P12, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P2);
EP900(%SF17376, %SF14328, L8, P13, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P2);
EP900(%SF17381, %SF15048, L9, P14, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P2);
EP900(%SF17386, %SF15768, L10, P15, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P2);
EP900(%SF17391, %SF16488, L11, P16, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P2);
EP900(%SF17396, %SF17208, L12, P18, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P2);
EP900(%SF17336, %SF8568, L13, P28, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P24);
EP900(%SF17331, %SF7848, L14, P29, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P24);
EP900(%SF17326, %SF7128, L15, P30, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P24);
EP900(%SF17321, %SF6408, L16, P31, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P24);
EP900(%SF17316, %SF5688, L17, P32, L41, %FF5688, N17, N41, N65, %FF5616, L65,
      N89, P24);
EP900(%SF17311, %SF4968, L18, P33, L42, %FF4968, N18, N42, N66, %FF4896, L66,
      N90, P24);
EP900(%SF17306, %SF4248, L19, P34, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P24);
EP900(%SF17301, %SF3528, L20, P35, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P24);
EP900(%SF17296, %SF2808, L21, P36, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P24);
EP900(%SF17291, %SF2088, L22, P37, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P24);
EP900(%SF17286, %SF1368, L23, P38, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P24);
EP900(%SF17281, %SF648, L24, P40, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P24);
%EndModel

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP900LC-2
%LastNode ? ?
%NumPins: 44
%FDF AND 0 ~P3 P3 ~P4 P4 ~P5 P5 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P19 P19 ~P20 P20
	 ~P21 P21 ~P25 P25 ~P26 P26 ~P27 P27 ~N13 N13 ~N14 N14 ~N15 N15
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22
	 ~N23 N23 ~N24 N24 ~P41 P41 ~P42 P42 ~P43 P43 *

%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;
%MACEND;

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 45,45,45,45);
   %ELSE
      BUF(LorOutput; TSBInput; 45,45,45,45);
      TSB(TSBInput, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
   %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |1,3:
   BUF(LorOutput; Outpin; 45,45,45,45);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 45,45,45,45);
    %ELSE
       BUF(LorOutput; TSBInput; 45,45,45,45);
       TSB(TSBInput, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(LorOutput; Outpin; 45,45,45,45);
   BUF(TNode; FeedBack; 0,0,0,0);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 45,45,45,45);
    %ELSE
       BUF(LorOutput; TSBInput; 45,45,45,45);
       TSB(TSBInput, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(LorOutput; Outpin; 45,45,45,45);
   BUF(TNode; FeedBack; 0,0,0,0);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 50,50,50,50,50,50,50,50);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 %END;
%MACEND;

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P6, L25, %FF9288, N1, N25, N49, %FF9216, L49,
      N73, P2);
EP900(%SF17346, %SF10008, L2, P7, L26, %FF10008, N2, N26, N50, %FF9936, L50,
      N74, P2);
EP900(%SF17351, %SF10728, L3, P8, L27, %FF10728, N3, N27, N51, %FF10656, L51,
      N75, P2);
EP900(%SF17356, %SF11448, L4, P9, L28, %FF11448, N4, N28, N52, %FF11376, L52,
      N76, P2);
EP900(%SF17361, %SF12168, L5, P10, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P2);
EP900(%SF17366, %SF12888, L6, P11, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P2);
EP900(%SF17371, %SF13608, L7, P12, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P2);
EP900(%SF17376, %SF14328, L8, P13, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P2);
EP900(%SF17381, %SF15048, L9, P14, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P2);
EP900(%SF17386, %SF15768, L10, P15, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P2);
EP900(%SF17391, %SF16488, L11, P16, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P2);
EP900(%SF17396, %SF17208, L12, P18, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P2);
EP900(%SF17336, %SF8568, L13, P28, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P24);
EP900(%SF17331, %SF7848, L14, P29, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P24);
EP900(%SF17326, %SF7128, L15, P30, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P24);
EP900(%SF17321, %SF6408, L16, P31, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P24);
EP900(%SF17316, %SF5688, L17, P32, L41, %FF5688, N17, N41, N65, %FF5616, L65,
      N89, P24);
EP900(%SF17311, %SF4968, L18, P33, L42, %FF4968, N18, N42, N66, %FF4896, L66,
      N90, P24);
EP900(%SF17306, %SF4248, L19, P34, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P24);
EP900(%SF17301, %SF3528, L20, P35, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P24);
EP900(%SF17296, %SF2808, L21, P36, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P24);
EP900(%SF17291, %SF2088, L22, P37, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P24);
EP900(%SF17286, %SF1368, L23, P38, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P24);
EP900(%SF17281, %SF648, L24, P40, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P24);
%EndModel

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP900LC-3
%LastNode ? ?
%NumPins: 44
%FDF AND 0 ~P3 P3 ~P4 P4 ~P5 P5 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P19 P19 ~P20 P20
	 ~P21 P21 ~P25 P25 ~P26 P26 ~P27 P27 ~N13 N13 ~N14 N14 ~N15 N15
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22
	 ~N23 N23 ~N24 N24 ~P41 P41 ~P42 P42 ~P43 P43 *

%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;
%MACEND;

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 50,50,50,50);
   %ELSE
      BUF(LorOutput; TSBInput; 50,50,50,50);
      TSB(TSBInput, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
   %END;
   BUF(OutPin; FeedBack; 5,5,5,5);
 |1,3:
   BUF(LorOutput; Outpin; 50,50,50,50);
   BUF(OutPin; FeedBack; 5,5,5,5);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 50,50,50,50);
    %ELSE
       BUF(LorOutput; TSBInput; 50,50,50,50);
       TSB(TSBInput, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);
   BUF(LorOutput; Outpin; 50,50,50,50);
   BUF(TNode; FeedBack; 0,0,0,0);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 50,50,50,50);
    %ELSE
       BUF(LorOutput; TSBInput; 50,50,50,50);
       TSB(TSBInput, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);
   BUF(LorOutput; Outpin; 50,50,50,50);
   BUF(TNode; FeedBack; 0,0,0,0);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 %END;
%MACEND;

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P6, L25, %FF9288, N1, N25, N49, %FF9216, L49,
      N73, P2);
EP900(%SF17346, %SF10008, L2, P7, L26, %FF10008, N2, N26, N50, %FF9936, L50,
      N74, P2);
EP900(%SF17351, %SF10728, L3, P8, L27, %FF10728, N3, N27, N51, %FF10656, L51,
      N75, P2);
EP900(%SF17356, %SF11448, L4, P9, L28, %FF11448, N4, N28, N52, %FF11376, L52,
      N76, P2);
EP900(%SF17361, %SF12168, L5, P10, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P2);
EP900(%SF17366, %SF12888, L6, P11, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P2);
EP900(%SF17371, %SF13608, L7, P12, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P2);
EP900(%SF17376, %SF14328, L8, P13, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P2);
EP900(%SF17381, %SF15048, L9, P14, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P2);
EP900(%SF17386, %SF15768, L10, P15, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P2);
EP900(%SF17391, %SF16488, L11, P16, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P2);
EP900(%SF17396, %SF17208, L12, P18, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P2);
EP900(%SF17336, %SF8568, L13, P28, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P24);
EP900(%SF17331, %SF7848, L14, P29, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P24);
EP900(%SF17326, %SF7128, L15, P30, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P24);
EP900(%SF17321, %SF6408, L16, P31, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P24);
EP900(%SF17316, %SF5688, L17, P32, L41, %FF5688, N17, N41, N65, %FF5616, L65,
      N89, P24);
EP900(%SF17311, %SF4968, L18, P33, L42, %FF4968, N18, N42, N66, %FF4896, L66,
      N90, P24);
EP900(%SF17306, %SF4248, L19, P34, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P24);
EP900(%SF17301, %SF3528, L20, P35, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P24);
EP900(%SF17296, %SF2808, L21, P36, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P24);
EP900(%SF17291, %SF2088, L22, P37, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P24);
EP900(%SF17286, %SF1368, L23, P38, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P24);
EP900(%SF17281, %SF648, L24, P40, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P24);
%EndModel

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP900LI
%LastNode ? ?
%NumPins: 44
%FDF AND 0 ~P3 P3 ~P4 P4 ~P5 P5 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P19 P19 ~P20 P20
	 ~P21 P21 ~P25 P25 ~P26 P26 ~P27 P27 ~N13 N13 ~N14 N14 ~N15 N15
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22
	 ~N23 N23 ~N24 N24 ~P41 P41 ~P42 P42 ~P43 P43 *

%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;
%MACEND;

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT,
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2:
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 55,55,55,55);
   %ELSE
      BUF(LorOutput; TSBInput; 55,55,55,55);
      TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
   %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |1,3:
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |4:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 55,55,55,55);
    %ELSE
       BUF(LorOutput; TSBInput; 55,55,55,55);
       TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(TNode; FeedBack; 0,0,0,0);
 |6:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 55,55,55,55);
    %ELSE
       BUF(LorOutput; TSBInput; 55,55,55,55);
       TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(TNode; FeedBack; 0,0,0,0);
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |9:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |10:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |12:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |13:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 |14:
   LXOR(LorOutput, TNode; XorInput);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);
 %END;
%MACEND;

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P6, L25, %FF9288, N1, N25, N49, %FF9216, L49,
      N73, P2);
EP900(%SF17346, %SF10008, L2, P7, L26, %FF10008, N2, N26, N50, %FF9936, L50,
      N74, P2);
EP900(%SF17351, %SF10728, L3, P8, L27, %FF10728, N3, N27, N51, %FF10656, L51,
      N75, P2);
EP900(%SF17356, %SF11448, L4, P9, L28, %FF11448, N4, N28, N52, %FF11376, L52,
      N76, P2);
EP900(%SF17361, %SF12168, L5, P10, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P2);
EP900(%SF17366, %SF12888, L6, P11, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P2);
EP900(%SF17371, %SF13608, L7, P12, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P2);
EP900(%SF17376, %SF14328, L8, P13, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P2);
EP900(%SF17381, %SF15048, L9, P14, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P2);
EP900(%SF17386, %SF15768, L10, P15, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P2);
EP900(%SF17391, %SF16488, L11, P16, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P2);
EP900(%SF17396, %SF17208, L12, P18, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P2);
EP900(%SF17336, %SF8568, L13, P28, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P24);
EP900(%SF17331, %SF7848, L14, P29, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P24);
EP900(%SF17326, %SF7128, L15, P30, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P24);
EP900(%SF17321, %SF6408, L16, P31, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P24);   
EP900(%SF17316, %SF5688, L17, P32, L41, %FF5688, N17, N41, N65, %FF5616, L65, 
      N89, P24);
EP900(%SF17311, %SF4968, L18, P33, L42, %FF4968, N18, N42, N66, %FF4896, L66, 
      N90, P24);
EP900(%SF17306, %SF4248, L19, P34, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P24);
EP900(%SF17301, %SF3528, L20, P35, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P24);
EP900(%SF17296, %SF2808, L21, P36, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P24);
EP900(%SF17291, %SF2088, L22, P37, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P24);
EP900(%SF17286, %SF1368, L23, P38, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P24);
EP900(%SF17281, %SF648, L24, P40, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P24);
%EndModel      

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP900LI-3
%LastNode ? ?
%NumPins: 44
%FDF AND 0 ~P3 P3 ~P4 P4 ~P5 P5 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P19 P19 ~P20 P20
	 ~P21 P21 ~P25 P25 ~P26 P26 ~P27 P27 ~N13 N13 ~N14 N14 ~N15 N15 
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22 
	 ~N23 N23 ~N24 N24 ~P41 P41 ~P42 P42 ~P43 P43 *
	 
%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE            
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;     
%MACEND;      

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT, 
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2: 
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 50,50,50,50);
   %ELSE
      BUF(LorOutput; TSBInput; 50,50,50,50);       
      TSB(TSBInput, %InFuse; Outpin; 55,55,55,55,55,55,55,55);       
   %END;
   BUF(OutPin; FeedBack; 5,5,5,5);    
 |1,3:
   BUF(LorOutput; Outpin; 50,50,50,50);
   BUF(OutPin; FeedBack; 5,5,5,5);    
 |4:                    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 50,50,50,50);
    %ELSE
       BUF(LorOutput; TSBInput; 50,50,50,50);
       TSB(TSBInput, %InFuse; Outpin; 55,55,55,55,55,55,55,55);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);    
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);         
   BUF(LorOutput; Outpin; 50,50,50,50);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |6:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 50,50,50,50);
    %ELSE
       BUF(LorOutput; TSBInput; 50,50,50,50); 
       TSB(TSBInput, %InFuse; Outpin; 55,55,55,55,55,55,55,55);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);         
   BUF(LorOutput; Outpin; 50,50,50,50);
   BUF(TNode; FeedBack; 0,0,0,0);   
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);       
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);
 |9:   
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);
 |10:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);       
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);   
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);   
 |12:    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);       
 |13:
   AND(%InFuse; CLK; 0,0,0,0);   
   LNOR(%ClrFuse, IPH; Clear);  
   DQFFC(LorOutput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |14:   
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);   
 %END;
%MACEND;   

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P6, L25, %FF9288, N1, N25, N49, %FF9216, L49, 
      N73, P2);   
EP900(%SF17346, %SF10008, L2, P7, L26, %FF10008, N2, N26, N50, %FF9936, L50, 
      N74, P2);   
EP900(%SF17351, %SF10728, L3, P8, L27, %FF10728, N3, N27, N51, %FF10656, L51, 
      N75, P2);   
EP900(%SF17356, %SF11448, L4, P9, L28, %FF11448, N4, N28, N52, %FF11376, L52, 
      N76, P2);   
EP900(%SF17361, %SF12168, L5, P10, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P2);   
EP900(%SF17366, %SF12888, L6, P11, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P2);   
EP900(%SF17371, %SF13608, L7, P12, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P2);   
EP900(%SF17376, %SF14328, L8, P13, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P2);   
EP900(%SF17381, %SF15048, L9, P14, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P2);   
EP900(%SF17386, %SF15768, L10, P15, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P2);   
EP900(%SF17391, %SF16488, L11, P16, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P2);   
EP900(%SF17396, %SF17208, L12, P18, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P2);   
EP900(%SF17336, %SF8568, L13, P28, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P24);   
EP900(%SF17331, %SF7848, L14, P29, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P24);   
EP900(%SF17326, %SF7128, L15, P30, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P24);   
EP900(%SF17321, %SF6408, L16, P31, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P24);   
EP900(%SF17316, %SF5688, L17, P32, L41, %FF5688, N17, N41, N65, %FF5616, L65, 
      N89, P24);
EP900(%SF17311, %SF4968, L18, P33, L42, %FF4968, N18, N42, N66, %FF4896, L66, 
      N90, P24);
EP900(%SF17306, %SF4248, L19, P34, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P24);
EP900(%SF17301, %SF3528, L20, P35, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P24);
EP900(%SF17296, %SF2808, L21, P36, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P24);
EP900(%SF17291, %SF2088, L22, P37, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P24);
EP900(%SF17286, %SF1368, L23, P38, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P24);
EP900(%SF17281, %SF648, L24, P40, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P24);
%EndModel      

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP900PC
%LastNode ? ?
%NumPins: 40
%FDF AND 0 ~P2 P2 ~P3 P3 ~P4 P4 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P17 P17 ~P18 P18
	 ~P19 P19 ~P22 P22 ~P23 P23 ~P24 P24 ~N13 N13 ~N14 N14 ~N15 N15 
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22 
	 ~N23 N23 ~N24 N24 ~P37 P37 ~P38 P38 ~P39 P39 *
	 
%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE            
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;     
%MACEND;      

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT, 
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2: 
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 55,55,55,55);
   %ELSE
      BUF(LorOutput; TSBInput; 55,55,55,55);       
      TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);       
   %END;
   BUF(OutPin; FeedBack; 5,5,5,5);    
 |1,3:
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(OutPin; FeedBack; 5,5,5,5);    
 |4:                    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 55,55,55,55);
    %ELSE
       BUF(LorOutput; TSBInput; 55,55,55,55);
       TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);    
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);         
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |6:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);       
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 55,55,55,55);
    %ELSE
       BUF(LorOutput; TSBInput; 55,55,55,55); 
       TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);         
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(TNode; FeedBack; 0,0,0,0);   
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);         
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);       
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);    
 |9:   
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);    
 |10:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);       
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);   
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);   
 |12:    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);         
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);       
 |13:
   AND(%InFuse; CLK; 0,0,0,0);   
   LNOR(%ClrFuse, IPH; Clear);  
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |14:   
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);   
 %END;
%MACEND;   

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P5, L25, %FF9288, N1, N25, N49, %FF9216, L49, 
      N73, P1);   
EP900(%SF17346, %SF10008, L2, P6, L26, %FF10008, N2, N26, N50, %FF9936, L50, 
      N74, P1);   
EP900(%SF17351, %SF10728, L3, P7, L27, %FF10728, N3, N27, N51, %FF10656, L51, 
      N75, P1);   
EP900(%SF17356, %SF11448, L4, P8, L28, %FF11448, N4, N28, N52, %FF11376, L52, 
      N76, P1);   
EP900(%SF17361, %SF12168, L5, P9, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P1);   
EP900(%SF17366, %SF12888, L6, P10, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P1);   
EP900(%SF17371, %SF13608, L7, P11, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P1);   
EP900(%SF17376, %SF14328, L8, P12, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P1);   
EP900(%SF17381, %SF15048, L9, P13, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P1);   
EP900(%SF17386, %SF15768, L10, P14, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P1);   
EP900(%SF17391, %SF16488, L11, P15, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P1);   
EP900(%SF17396, %SF17208, L12, P16, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P1);   
EP900(%SF17336, %SF8568, L13, P25, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P21);   
EP900(%SF17331, %SF7848, L14, P26, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P21);   
EP900(%SF17326, %SF7128, L15, P27, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P21);   
EP900(%SF17321, %SF6408, L16, P28, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P21);   
EP900(%SF17316, %SF5688, L17, P29, L41, %FF5688, N17, N41, N65, %FF5616, L65, 
      N89, P21);
EP900(%SF17311, %SF4968, L18, P30, L42, %FF4968, N18, N42, N66, %FF4896, L66, 
      N90, P21);
EP900(%SF17306, %SF4248, L19, P31, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P21);
EP900(%SF17301, %SF3528, L20, P32, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P21);
EP900(%SF17296, %SF2808, L21, P33, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P21);
EP900(%SF17291, %SF2088, L22, P34, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P21);
EP900(%SF17286, %SF1368, L23, P35, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P21);
EP900(%SF17281, %SF648, L24, P36, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P21);
%EndModel      

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP900PC-2
%LastNode ? ?
%NumPins: 40
%FDF AND 0 ~P2 P2 ~P3 P3 ~P4 P4 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P17 P17 ~P18 P18
	 ~P19 P19 ~P22 P22 ~P23 P23 ~P24 P24 ~N13 N13 ~N14 N14 ~N15 N15 
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22 
	 ~N23 N23 ~N24 N24 ~P37 P37 ~P38 P38 ~P39 P39 *
	 
%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE            
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;     
%MACEND;      

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT, 
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2: 
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 45,45,45,45);
   %ELSE
      BUF(LorOutput; TSBInput; 45,45,45,45);       
      TSB(TSBInput, %InFuse; Outpin; 50,50,50,50,50,50,50,50);       
   %END;
   BUF(OutPin; FeedBack; 5,5,5,5);    
 |1,3:
   BUF(LorOutput; Outpin; 45,45,45,45);
   BUF(OutPin; FeedBack; 5,5,5,5);    
 |4:                    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 45,45,45,45);
    %ELSE
       BUF(LorOutput; TSBInput; 45,45,45,45);
       TSB(TSBInput, %InFuse; Outpin; 50,50,50,50,50,50,50,50);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);    
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);         
   BUF(LorOutput; Outpin; 45,45,45,45);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |6:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);       
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 45,45,45,45);
    %ELSE
       BUF(LorOutput; TSBInput; 45,45,45,45); 
       TSB(TSBInput, %InFuse; Outpin; 50,50,50,50,50,50,50,50);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);         
   BUF(LorOutput; Outpin; 45,45,45,45);
   BUF(TNode; FeedBack; 0,0,0,0);   
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);         
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 50,50,50,50,50,50,50,50);       
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);    
 |9:   
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);    
 |10:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 50,50,50,50,50,50,50,50);       
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);   
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);   
 |12:    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);         
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 50,50,50,50,50,50,50,50);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);       
 |13:
   AND(%InFuse; CLK; 0,0,0,0);   
   LNOR(%ClrFuse, IPH; Clear);  
   DQFFC(LorOutput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |14:   
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 23,23,38,0,18,18,50,50,0,0,23,23,38,0,18,18,50,50,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 50,50,50,50,50,50,50,50);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 48,48,13,15,18,18,50,50,0,0,48,48,13,15,18,18,50,50,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);   
 %END;
%MACEND;   

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P5, L25, %FF9288, N1, N25, N49, %FF9216, L49, 
      N73, P1);   
EP900(%SF17346, %SF10008, L2, P6, L26, %FF10008, N2, N26, N50, %FF9936, L50, 
      N74, P1);   
EP900(%SF17351, %SF10728, L3, P7, L27, %FF10728, N3, N27, N51, %FF10656, L51, 
      N75, P1);   
EP900(%SF17356, %SF11448, L4, P8, L28, %FF11448, N4, N28, N52, %FF11376, L52, 
      N76, P1);   
EP900(%SF17361, %SF12168, L5, P9, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P1);   
EP900(%SF17366, %SF12888, L6, P10, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P1);   
EP900(%SF17371, %SF13608, L7, P11, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P1);   
EP900(%SF17376, %SF14328, L8, P12, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P1);   
EP900(%SF17381, %SF15048, L9, P13, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P1);   
EP900(%SF17386, %SF15768, L10, P14, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P1);   
EP900(%SF17391, %SF16488, L11, P15, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P1);   
EP900(%SF17396, %SF17208, L12, P16, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P1);   
EP900(%SF17336, %SF8568, L13, P25, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P21);   
EP900(%SF17331, %SF7848, L14, P26, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P21);   
EP900(%SF17326, %SF7128, L15, P27, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P21);   
EP900(%SF17321, %SF6408, L16, P28, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P21);   
EP900(%SF17316, %SF5688, L17, P29, L41, %FF5688, N17, N41, N65, %FF5616, L65, 
      N89, P21);
EP900(%SF17311, %SF4968, L18, P30, L42, %FF4968, N18, N42, N66, %FF4896, L66, 
      N90, P21);
EP900(%SF17306, %SF4248, L19, P31, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P21);
EP900(%SF17301, %SF3528, L20, P32, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P21);
EP900(%SF17296, %SF2808, L21, P33, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P21);
EP900(%SF17291, %SF2088, L22, P34, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P21);
EP900(%SF17286, %SF1368, L23, P35, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P21);
EP900(%SF17281, %SF648, L24, P36, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P21);
%EndModel      

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP900PC-3
%LastNode ? ?
%NumPins: 40
%FDF AND 0 ~P2 P2 ~P3 P3 ~P4 P4 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P17 P17 ~P18 P18
	 ~P19 P19 ~P22 P22 ~P23 P23 ~P24 P24 ~N13 N13 ~N14 N14 ~N15 N15 
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22 
	 ~N23 N23 ~N24 N24 ~P37 P37 ~P38 P38 ~P39 P39 *
	 
%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE            
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;     
%MACEND;      

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT, 
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2: 
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 50,50,50,50);
   %ELSE
      BUF(LorOutput; TSBInput; 50,50,50,50);       
      TSB(TSBInput, %InFuse; Outpin; 55,55,55,55,55,55,55,55);       
   %END;
   BUF(OutPin; FeedBack; 5,5,5,5);    
 |1,3:
   BUF(LorOutput; Outpin; 50,50,50,50);
   BUF(OutPin; FeedBack; 5,5,5,5);    
 |4:                    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 50,50,50,50);
    %ELSE
       BUF(LorOutput; TSBInput; 50,50,50,50);
       TSB(TSBInput, %InFuse; Outpin; 55,55,55,55,55,55,55,55);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);    
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);         
   BUF(LorOutput; Outpin; 50,50,50,50);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |6:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);       
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 50,50,50,50);
    %ELSE
       BUF(LorOutput; TSBInput; 50,50,50,50); 
       TSB(TSBInput, %InFuse; Outpin; 55,55,55,55,55,55,55,55);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);         
   BUF(LorOutput; Outpin; 50,50,50,50);
   BUF(TNode; FeedBack; 0,0,0,0);   
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);         
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);       
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);    
 |9:   
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);    
 |10:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);       
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);   
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);   
 |12:    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);         
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);       
 |13:
   AND(%InFuse; CLK; 0,0,0,0);   
   LNOR(%ClrFuse, IPH; Clear);  
   DQFFC(LorOutput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |14:   
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);   
 %END;
%MACEND;   

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P5, L25, %FF9288, N1, N25, N49, %FF9216, L49, 
      N73, P1);   
EP900(%SF17346, %SF10008, L2, P6, L26, %FF10008, N2, N26, N50, %FF9936, L50, 
      N74, P1);   
EP900(%SF17351, %SF10728, L3, P7, L27, %FF10728, N3, N27, N51, %FF10656, L51, 
      N75, P1);   
EP900(%SF17356, %SF11448, L4, P8, L28, %FF11448, N4, N28, N52, %FF11376, L52, 
      N76, P1);   
EP900(%SF17361, %SF12168, L5, P9, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P1);   
EP900(%SF17366, %SF12888, L6, P10, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P1);   
EP900(%SF17371, %SF13608, L7, P11, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P1);   
EP900(%SF17376, %SF14328, L8, P12, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P1);   
EP900(%SF17381, %SF15048, L9, P13, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P1);   
EP900(%SF17386, %SF15768, L10, P14, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P1);   
EP900(%SF17391, %SF16488, L11, P15, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P1);   
EP900(%SF17396, %SF17208, L12, P16, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P1);   
EP900(%SF17336, %SF8568, L13, P25, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P21);   
EP900(%SF17331, %SF7848, L14, P26, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P21);   
EP900(%SF17326, %SF7128, L15, P27, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P21);   
EP900(%SF17321, %SF6408, L16, P28, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P21);   
EP900(%SF17316, %SF5688, L17, P29, L41, %FF5688, N17, N41, N65, %FF5616, L65, 
      N89, P21);
EP900(%SF17311, %SF4968, L18, P30, L42, %FF4968, N18, N42, N66, %FF4896, L66, 
      N90, P21);
EP900(%SF17306, %SF4248, L19, P31, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P21);
EP900(%SF17301, %SF3528, L20, P32, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P21);
EP900(%SF17296, %SF2808, L21, P33, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P21);
EP900(%SF17291, %SF2088, L22, P34, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P21);
EP900(%SF17286, %SF1368, L23, P35, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P21);
EP900(%SF17281, %SF648, L24, P36, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P21);
%EndModel      

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP900PI
%LastNode ? ?
%NumPins: 40
%FDF AND 0 ~P2 P2 ~P3 P3 ~P4 P4 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P17 P17 ~P18 P18
	 ~P19 P19 ~P22 P22 ~P23 P23 ~P24 P24 ~N13 N13 ~N14 N14 ~N15 N15 
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22 
	 ~N23 N23 ~N24 N24 ~P37 P37 ~P38 P38 ~P39 P39 *
	 
%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE            
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;     
%MACEND;      

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT, 
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2: 
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 55,55,55,55);
   %ELSE
      BUF(LorOutput; TSBInput; 55,55,55,55);       
      TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);       
   %END;
   BUF(OutPin; FeedBack; 5,5,5,5);    
 |1,3:
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(OutPin; FeedBack; 5,5,5,5);    
 |4:                    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 55,55,55,55);
    %ELSE
       BUF(LorOutput; TSBInput; 55,55,55,55);
       TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);    
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);         
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |6:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);       
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 55,55,55,55);
    %ELSE
       BUF(LorOutput; TSBInput; 55,55,55,55); 
       TSB(TSBInput, %InFuse; Outpin; 60,60,60,60,60,60,60,60);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);         
   BUF(LorOutput; Outpin; 55,55,55,55);
   BUF(TNode; FeedBack; 0,0,0,0);   
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);         
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);       
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);    
 |9:   
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);    
 |10:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);       
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);   
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);   
 |12:    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);         
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);       
 |13:
   AND(%InFuse; CLK; 0,0,0,0);   
   LNOR(%ClrFuse, IPH; Clear);  
   DQFFC(LorOutput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |14:   
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 28,28,46,0,23,23,60,60,0,0,28,28,46,0,23,23,60,60,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 60,60,60,60,60,60,60,60);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 59,59,15,15,23,23,60,60,0,0,59,59,15,15,23,23,60,60,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);   
 %END;
%MACEND;   

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P5, L25, %FF9288, N1, N25, N49, %FF9216, L49, 
      N73, P1);   
EP900(%SF17346, %SF10008, L2, P6, L26, %FF10008, N2, N26, N50, %FF9936, L50, 
      N74, P1);   
EP900(%SF17351, %SF10728, L3, P7, L27, %FF10728, N3, N27, N51, %FF10656, L51, 
      N75, P1);   
EP900(%SF17356, %SF11448, L4, P8, L28, %FF11448, N4, N28, N52, %FF11376, L52, 
      N76, P1);   
EP900(%SF17361, %SF12168, L5, P9, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P1);   
EP900(%SF17366, %SF12888, L6, P10, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P1);   
EP900(%SF17371, %SF13608, L7, P11, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P1);   
EP900(%SF17376, %SF14328, L8, P12, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P1);   
EP900(%SF17381, %SF15048, L9, P13, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P1);   
EP900(%SF17386, %SF15768, L10, P14, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P1);   
EP900(%SF17391, %SF16488, L11, P15, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P1);   
EP900(%SF17396, %SF17208, L12, P16, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P1);   
EP900(%SF17336, %SF8568, L13, P25, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P21);   
EP900(%SF17331, %SF7848, L14, P26, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P21);   
EP900(%SF17326, %SF7128, L15, P27, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P21);   
EP900(%SF17321, %SF6408, L16, P28, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P21);   
EP900(%SF17316, %SF5688, L17, P29, L41, %FF5688, N17, N41, N65, %FF5616, L65, 
      N89, P21);
EP900(%SF17311, %SF4968, L18, P30, L42, %FF4968, N18, N42, N66, %FF4896, L66, 
      N90, P21);
EP900(%SF17306, %SF4248, L19, P31, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P21);
EP900(%SF17301, %SF3528, L20, P32, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P21);
EP900(%SF17296, %SF2808, L21, P33, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P21);
EP900(%SF17291, %SF2088, L22, P34, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P21);
EP900(%SF17286, %SF1368, L23, P35, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P21);
EP900(%SF17281, %SF648, L24, P36, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P21);
%EndModel      

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP900PI-3
%LastNode ? ?
%NumPins: 40
%FDF AND 0 ~P2 P2 ~P3 P3 ~P4 P4 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P17 P17 ~P18 P18
	 ~P19 P19 ~P22 P22 ~P23 P23 ~P24 P24 ~N13 N13 ~N14 N14 ~N15 N15 
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22 
	 ~N23 N23 ~N24 N24 ~P37 P37 ~P38 P38 ~P39 P39 *
	 
%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE            
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;     
%MACEND;      

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT, 
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2: 
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 50,50,50,50);
   %ELSE
      BUF(LorOutput; TSBInput; 50,50,50,50);       
      TSB(TSBInput, %InFuse; Outpin; 55,55,55,55,55,55,55,55);       
   %END;
   BUF(OutPin; FeedBack; 5,5,5,5);    
 |1,3:
   BUF(LorOutput; Outpin; 50,50,50,50);
   BUF(OutPin; FeedBack; 5,5,5,5);    
 |4:                    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 50,50,50,50);
    %ELSE
       BUF(LorOutput; TSBInput; 50,50,50,50);
       TSB(TSBInput, %InFuse; Outpin; 55,55,55,55,55,55,55,55);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);    
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);         
   BUF(LorOutput; Outpin; 50,50,50,50);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |6:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);       
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 50,50,50,50);
    %ELSE
       BUF(LorOutput; TSBInput; 50,50,50,50); 
       TSB(TSBInput, %InFuse; Outpin; 55,55,55,55,55,55,55,55);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);         
   BUF(LorOutput; Outpin; 50,50,50,50);
   BUF(TNode; FeedBack; 0,0,0,0);   
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);         
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);       
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);    
 |9:   
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);    
 |10:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);       
    %END;
   BUF(Outpin; FeedBack; 5,5,5,5);   
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 5,5,5,5);   
 |12:    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);         
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);       
 |13:
   AND(%InFuse; CLK; 0,0,0,0);   
   LNOR(%ClrFuse, IPH; Clear);  
   DQFFC(LorOutput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |14:   
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 25,25,42,0,20,20,55,55,0,0,25,25,42,0,20,20,55,55,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 55,55,55,55,55,55,55,55);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 53,53,14,15,20,20,55,55,0,0,53,53,14,15,20,20,55,55,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);   
 %END;
%MACEND;   

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P5, L25, %FF9288, N1, N25, N49, %FF9216, L49, 
      N73, P1);   
EP900(%SF17346, %SF10008, L2, P6, L26, %FF10008, N2, N26, N50, %FF9936, L50, 
      N74, P1);   
EP900(%SF17351, %SF10728, L3, P7, L27, %FF10728, N3, N27, N51, %FF10656, L51, 
      N75, P1);   
EP900(%SF17356, %SF11448, L4, P8, L28, %FF11448, N4, N28, N52, %FF11376, L52, 
      N76, P1);   
EP900(%SF17361, %SF12168, L5, P9, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P1);   
EP900(%SF17366, %SF12888, L6, P10, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P1);   
EP900(%SF17371, %SF13608, L7, P11, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P1);   
EP900(%SF17376, %SF14328, L8, P12, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P1);   
EP900(%SF17381, %SF15048, L9, P13, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P1);   
EP900(%SF17386, %SF15768, L10, P14, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P1);   
EP900(%SF17391, %SF16488, L11, P15, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P1);   
EP900(%SF17396, %SF17208, L12, P16, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P1);   
EP900(%SF17336, %SF8568, L13, P25, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P21);   
EP900(%SF17331, %SF7848, L14, P26, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P21);   
EP900(%SF17326, %SF7128, L15, P27, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P21);   
EP900(%SF17321, %SF6408, L16, P28, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P21);   
EP900(%SF17316, %SF5688, L17, P29, L41, %FF5688, N17, N41, N65, %FF5616, L65, 
      N89, P21);
EP900(%SF17311, %SF4968, L18, P30, L42, %FF4968, N18, N42, N66, %FF4896, L66, 
      N90, P21);
EP900(%SF17306, %SF4248, L19, P31, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P21);
EP900(%SF17301, %SF3528, L20, P32, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P21);
EP900(%SF17296, %SF2808, L21, P33, L45, %FF2808, N21, N45, N69, %FF2736, L69,      N93, P21);
EP900(%SF17291, %SF2088, L22, P34, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P21);
EP900(%SF17286, %SF1368, L23, P35, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P21);
EP900(%SF17281, %SF648, L24, P36, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P21);
%EndModel      

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP910DC-30
%LastNode ? ?
%NumPins: 40
%FDF AND 0 ~P2 P2 ~P3 P3 ~P4 P4 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P17 P17 ~P18 P18
	 ~P19 P19 ~P22 P22 ~P23 P23 ~P24 P24 ~N13 N13 ~N14 N14 ~N15 N15 
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22 
	 ~N23 N23 ~N24 N24 ~P37 P37 ~P38 P38 ~P39 P39 *
	 
%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE            
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;     
%MACEND;      

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT, 
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2: 
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 30,30,30,30);
   %ELSE
      BUF(LorOutput; TSBInput; 30,30,30,30);       
      TSB(TSBInput, %InFuse; Outpin; 25,25,25,25,25,25,25,25);       
   %END;
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |1,3:
   BUF(LorOutput; Outpin; 30,30,30,30);
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |4:                    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 15,15,20,0,10,10,25,25,0,0,15,15,20,0,10,10,25,25,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 30,30,30,30);
    %ELSE
       BUF(LorOutput; TSBInput; 30,30,30,30);
       TSB(TSBInput, %InFuse; Outpin; 25,25,25,25,25,25,25,25);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);    
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 25,25,5,5,10,10,25,25,0,0,25,25,5,5,10,10,25,25,0,0);         
   BUF(LorOutput; Outpin; 30,30,30,30);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |6:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 15,15,20,0,10,10,25,25,0,0,15,15,20,0,10,10,25,25,0,0);       
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 30,30,30,30);
    %ELSE
       BUF(LorOutput; TSBInput; 30,30,30,30); 
       TSB(TSBInput, %InFuse; Outpin; 25,25,25,25,25,25,25,25);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 25,25,5,5,10,10,25,25,0,0,25,25,5,5,10,10,25,25,0,0);         
   BUF(LorOutput; Outpin; 30,30,30,30);
   BUF(TNode; FeedBack; 0,0,0,0);   
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 15,15,20,0,10,10,25,25,0,0,15,15,20,0,10,10,25,25,0,0);         
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 25,25,25,25,25,25,25,25);       
    %END;
   BUF(Outpin; FeedBack; 2,2,2,2);    
 |9:   
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 25,25,5,5,10,10,25,25,0,0,25,25,5,5,10,10,25,25,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 2,2,2,2);    
 |10:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 15,15,20,0,10,10,25,25,0,0,15,15,20,0,10,10,25,25,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 25,25,25,25,25,25,25,25);       
    %END;
   BUF(Outpin; FeedBack; 2,2,2,2);   
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 25,25,5,5,10,10,25,25,0,0,25,25,5,5,10,10,25,25,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 2,2,2,2);   
 |12:    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 15,15,20,0,10,10,25,25,0,0,15,15,20,0,10,10,25,25,0,0);         
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 25,25,25,25,25,25,25,25);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);       
 |13:
   AND(%InFuse; CLK; 0,0,0,0);   
   LNOR(%ClrFuse, IPH; Clear);  
   DQFFC(LorOutput, CLK, Clear; TNode; 25,25,5,5,10,10,25,25,0,0,25,25,5,5,10,10,25,25,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |14:   
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 15,15,20,0,10,10,25,25,0,0,15,15,20,0,10,10,25,25,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 25,25,25,25,25,25,25,25);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 25,25,5,5,10,10,25,25,0,0,25,25,5,5,10,10,25,25,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);   
 %END;
%MACEND;   

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P5, L25, %FF9288, N1, N25, N49, %FF9216, L49, 
      N73, P1);   
EP900(%SF17346, %SF10008, L2, P6, L26, %FF10008, N2, N26, N50, %FF9936, L50, 
      N74, P1);   
EP900(%SF17351, %SF10728, L3, P7, L27, %FF10728, N3, N27, N51, %FF10656, L51, 
      N75, P1);   
EP900(%SF17356, %SF11448, L4, P8, L28, %FF11448, N4, N28, N52, %FF11376, L52, 
      N76, P1);   
EP900(%SF17361, %SF12168, L5, P9, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P1);   
EP900(%SF17366, %SF12888, L6, P10, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P1);   
EP900(%SF17371, %SF13608, L7, P11, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P1);   
EP900(%SF17376, %SF14328, L8, P12, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P1);   
EP900(%SF17381, %SF15048, L9, P13, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P1);   
EP900(%SF17386, %SF15768, L10, P14, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P1);   
EP900(%SF17391, %SF16488, L11, P15, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P1);   
EP900(%SF17396, %SF17208, L12, P16, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P1);   
EP900(%SF17336, %SF8568, L13, P25, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P21);   
EP900(%SF17331, %SF7848, L14, P26, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P21);   
EP900(%SF17326, %SF7128, L15, P27, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P21);   
EP900(%SF17321, %SF6408, L16, P28, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P21);   
EP900(%SF17316, %SF5688, L17, P29, L41, %FF5688, N17, N41, N65, %FF5616, L65, 
      N89, P21);
EP900(%SF17311, %SF4968, L18, P30, L42, %FF4968, N18, N42, N66, %FF4896, L66, 
      N90, P21);
EP900(%SF17306, %SF4248, L19, P31, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P21);
EP900(%SF17301, %SF3528, L20, P32, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P21);
EP900(%SF17296, %SF2808, L21, P33, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P21);
EP900(%SF17291, %SF2088, L22, P34, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P21);
EP900(%SF17286, %SF1368, L23, P35, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P21);
EP900(%SF17281, %SF648, L24, P36, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P21);
%EndModel      
 
%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP910DC-35
%LastNode ? ?
%NumPins: 40
%FDF AND 0 ~P2 P2 ~P3 P3 ~P4 P4 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P17 P17 ~P18 P18
	 ~P19 P19 ~P22 P22 ~P23 P23 ~P24 P24 ~N13 N13 ~N14 N14 ~N15 N15 
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22 
	 ~N23 N23 ~N24 N24 ~P37 P37 ~P38 P38 ~P39 P39 *
	 
%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE            
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;     
%MACEND;      

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT, 
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2: 
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 35,35,35,35);
   %ELSE
      BUF(LorOutput; TSBInput; 35,35,35,35);       
      TSB(TSBInput, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
   %END;
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |1,3:
   BUF(LorOutput; Outpin; 35,35,35,35);
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |4:                    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 35,35,35,35);
    %ELSE
       BUF(LorOutput; TSBInput; 35,35,35,35);
       TSB(TSBInput, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);    
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(LorOutput; Outpin; 35,35,35,35);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |6:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);       
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 35,35,35,35);
    %ELSE
       BUF(LorOutput; TSBInput; 35,35,35,35); 
       TSB(TSBInput, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(LorOutput; Outpin; 35,35,35,35);
   BUF(TNode; FeedBack; 0,0,0,0);   
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);         
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(Outpin; FeedBack; 2,2,2,2);    
 |9:   
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 2,2,2,2);    
 |10:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(Outpin; FeedBack; 2,2,2,2);   
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 2,2,2,2);   
 |12:    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);         
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);       
 |13:
   AND(%InFuse; CLK; 0,0,0,0);   
   LNOR(%ClrFuse, IPH; Clear);  
   DQFFC(LorOutput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |14:   
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);   
 %END;
%MACEND;   

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P5, L25, %FF9288, N1, N25, N49, %FF9216, L49, 
      N73, P1);   
EP900(%SF17346, %SF10008, L2, P6, L26, %FF10008, N2, N26, N50, %FF9936, L50, 
      N74, P1);   
EP900(%SF17351, %SF10728, L3, P7, L27, %FF10728, N3, N27, N51, %FF10656, L51, 
      N75, P1);   
EP900(%SF17356, %SF11448, L4, P8, L28, %FF11448, N4, N28, N52, %FF11376, L52, 
      N76, P1);   
EP900(%SF17361, %SF12168, L5, P9, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P1);   
EP900(%SF17366, %SF12888, L6, P10, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P1);   
EP900(%SF17371, %SF13608, L7, P11, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P1);   
EP900(%SF17376, %SF14328, L8, P12, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P1);   
EP900(%SF17381, %SF15048, L9, P13, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P1);   
EP900(%SF17386, %SF15768, L10, P14, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P1);   
EP900(%SF17391, %SF16488, L11, P15, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P1);   
EP900(%SF17396, %SF17208, L12, P16, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P1);   
EP900(%SF17336, %SF8568, L13, P25, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P21);   
EP900(%SF17331, %SF7848, L14, P26, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P21);   
EP900(%SF17326, %SF7128, L15, P27, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P21);   
EP900(%SF17321, %SF6408, L16, P28, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P21);   
EP900(%SF17316, %SF5688, L17, P29, L41, %FF5688, N17, N41, N65, %FF5616, L65, 
      N89, P21);
EP900(%SF17311, %SF4968, L18, P30, L42, %FF4968, N18, N42, N66, %FF4896, L66, 
      N90, P21);
EP900(%SF17306, %SF4248, L19, P31, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P21);
EP900(%SF17301, %SF3528, L20, P32, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P21);
EP900(%SF17296, %SF2808, L21, P33, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P21);
EP900(%SF17291, %SF2088, L22, P34, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P21);
EP900(%SF17286, %SF1368, L23, P35, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P21);
EP900(%SF17281, %SF648, L24, P36, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P21);
%EndModel      

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP910DC-40
%LastNode ? ?
%NumPins: 40
%FDF AND 0 ~P2 P2 ~P3 P3 ~P4 P4 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P17 P17 ~P18 P18
	 ~P19 P19 ~P22 P22 ~P23 P23 ~P24 P24 ~N13 N13 ~N14 N14 ~N15 N15 
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22 
	 ~N23 N23 ~N24 N24 ~P37 P37 ~P38 P38 ~P39 P39 *
	 
%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE            
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;     
%MACEND;      

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT, 
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2: 
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 40,40,40,40);
   %ELSE
      BUF(LorOutput; TSBInput; 40,40,40,40);       
      TSB(TSBInput, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
   %END;
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |1,3:
   BUF(LorOutput; Outpin; 40,40,40,40);
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |4:                    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 40,40,40,40);
    %ELSE
       BUF(LorOutput; TSBInput; 40,40,40,40);
       TSB(TSBInput, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);    
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(LorOutput; Outpin; 40,40,40,40);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |6:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);       
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 40,40,40,40);
    %ELSE
       BUF(LorOutput; TSBInput; 40,40,40,40); 
       TSB(TSBInput, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(LorOutput; Outpin; 40,40,40,40);
   BUF(TNode; FeedBack; 0,0,0,0);   
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);         
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(Outpin; FeedBack; 2,2,2,2);    
 |9:   
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 2,2,2,2);    
 |10:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(Outpin; FeedBack; 2,2,2,2);   
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 2,2,2,2);   
 |12:    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);         
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);       
 |13:
   AND(%InFuse; CLK; 0,0,0,0);   
   LNOR(%ClrFuse, IPH; Clear);  
   DQFFC(LorOutput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |14:   
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);   
 %END;
%MACEND;   

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P5, L25, %FF9288, N1, N25, N49, %FF9216, L49, 
      N73, P1);   
EP900(%SF17346, %SF10008, L2, P6, L26, %FF10008, N2, N26, N50, %FF9936, L50, 
      N74, P1);   
EP900(%SF17351, %SF10728, L3, P7, L27, %FF10728, N3, N27, N51, %FF10656, L51, 
      N75, P1);   
EP900(%SF17356, %SF11448, L4, P8, L28, %FF11448, N4, N28, N52, %FF11376, L52, 
      N76, P1);   
EP900(%SF17361, %SF12168, L5, P9, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P1);   
EP900(%SF17366, %SF12888, L6, P10, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P1);   
EP900(%SF17371, %SF13608, L7, P11, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P1);   
EP900(%SF17376, %SF14328, L8, P12, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P1);   
EP900(%SF17381, %SF15048, L9, P13, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P1);   
EP900(%SF17386, %SF15768, L10, P14, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P1);   
EP900(%SF17391, %SF16488, L11, P15, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P1);   
EP900(%SF17396, %SF17208, L12, P16, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P1);   
EP900(%SF17336, %SF8568, L13, P25, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P21);   
EP900(%SF17331, %SF7848, L14, P26, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P21);   
EP900(%SF17326, %SF7128, L15, P27, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P21);   
EP900(%SF17321, %SF6408, L16, P28, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P21);   
EP900(%SF17316, %SF5688, L17, P29, L41, %FF5688, N17, N41, N65, %FF5616, L65, 
      N89, P21);
EP900(%SF17311, %SF4968, L18, P30, L42, %FF4968, N18, N42, N66, %FF4896, L66, 
      N90, P21);
EP900(%SF17306, %SF4248, L19, P31, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P21);
EP900(%SF17301, %SF3528, L20, P32, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P21);
EP900(%SF17296, %SF2808, L21, P33, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P21);
EP900(%SF17291, %SF2088, L22, P34, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P21);
EP900(%SF17286, %SF1368, L23, P35, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P21);
EP900(%SF17281, %SF648, L24, P36, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P21);
%EndModel      

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP910DI-35
%LastNode ? ?
%NumPins: 40
%FDF AND 0 ~P2 P2 ~P3 P3 ~P4 P4 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P17 P17 ~P18 P18
	 ~P19 P19 ~P22 P22 ~P23 P23 ~P24 P24 ~N13 N13 ~N14 N14 ~N15 N15 
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22 
	 ~N23 N23 ~N24 N24 ~P37 P37 ~P38 P38 ~P39 P39 *
	 
%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE            
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;     
%MACEND;      

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT, 
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2: 
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 35,35,35,35);
   %ELSE
      BUF(LorOutput; TSBInput; 35,35,35,35);       
      TSB(TSBInput, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
   %END;
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |1,3:
   BUF(LorOutput; Outpin; 35,35,35,35);
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |4:                    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 35,35,35,35);
    %ELSE
       BUF(LorOutput; TSBInput; 35,35,35,35);
       TSB(TSBInput, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);    
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(LorOutput; Outpin; 35,35,35,35);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |6:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);       
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 35,35,35,35);
    %ELSE
       BUF(LorOutput; TSBInput; 35,35,35,35); 
       TSB(TSBInput, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(LorOutput; Outpin; 35,35,35,35);
   BUF(TNode; FeedBack; 0,0,0,0);   
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);         
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(Outpin; FeedBack; 2,2,2,2);    
 |9:   
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 2,2,2,2);    
 |10:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(Outpin; FeedBack; 2,2,2,2);   
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 2,2,2,2);   
 |12:    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);         
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);       
 |13:
   AND(%InFuse; CLK; 0,0,0,0);   
   LNOR(%ClrFuse, IPH; Clear);  
   DQFFC(LorOutput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |14:   
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);   
 %END;
%MACEND;   

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P5, L25, %FF9288, N1, N25, N49, %FF9216, L49, 
      N73, P1);   
EP900(%SF17346, %SF10008, L2, P6, L26, %FF10008, N2, N26, N50, %FF9936, L50, 
      N74, P1);   
EP900(%SF17351, %SF10728, L3, P7, L27, %FF10728, N3, N27, N51, %FF10656, L51, 
      N75, P1);   
EP900(%SF17356, %SF11448, L4, P8, L28, %FF11448, N4, N28, N52, %FF11376, L52, 
      N76, P1);   
EP900(%SF17361, %SF12168, L5, P9, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P1);   
EP900(%SF17366, %SF12888, L6, P10, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P1);   
EP900(%SF17371, %SF13608, L7, P11, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P1);   
EP900(%SF17376, %SF14328, L8, P12, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P1);   
EP900(%SF17381, %SF15048, L9, P13, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P1);   
EP900(%SF17386, %SF15768, L10, P14, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P1);   
EP900(%SF17391, %SF16488, L11, P15, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P1);   
EP900(%SF17396, %SF17208, L12, P16, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P1);   
EP900(%SF17336, %SF8568, L13, P25, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P21);   
EP900(%SF17331, %SF7848, L14, P26, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P21);   
EP900(%SF17326, %SF7128, L15, P27, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P21);   
EP900(%SF17321, %SF6408, L16, P28, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P21);   
EP900(%SF17316, %SF5688, L17, P29, L41, %FF5688, N17, N41, N65, %FF5616, L65, 
      N89, P21);
EP900(%SF17311, %SF4968, L18, P30, L42, %FF4968, N18, N42, N66, %FF4896, L66, 
      N90, P21);
EP900(%SF17306, %SF4248, L19, P31, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P21);
EP900(%SF17301, %SF3528, L20, P32, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P21);
EP900(%SF17296, %SF2808, L21, P33, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P21);
EP900(%SF17291, %SF2088, L22, P34, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P21);
EP900(%SF17286, %SF1368, L23, P35, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P21);
EP900(%SF17281, %SF648, L24, P36, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P21);
%EndModel      

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP910DI-40
%LastNode ? ?
%NumPins: 40
%FDF AND 0 ~P2 P2 ~P3 P3 ~P4 P4 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P17 P17 ~P18 P18
	 ~P19 P19 ~P22 P22 ~P23 P23 ~P24 P24 ~N13 N13 ~N14 N14 ~N15 N15 
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22 
	 ~N23 N23 ~N24 N24 ~P37 P37 ~P38 P38 ~P39 P39 *
	 
%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE            
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;     
%MACEND;      

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT, 
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2: 
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 40,40,40,40);
   %ELSE
      BUF(LorOutput; TSBInput; 40,40,40,40);       
      TSB(TSBInput, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
   %END;
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |1,3:
   BUF(LorOutput; Outpin; 40,40,40,40);
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |4:                    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 40,40,40,40);
    %ELSE
       BUF(LorOutput; TSBInput; 40,40,40,40);
       TSB(TSBInput, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);    
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(LorOutput; Outpin; 40,40,40,40);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |6:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);       
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 40,40,40,40);
    %ELSE
       BUF(LorOutput; TSBInput; 40,40,40,40); 
       TSB(TSBInput, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(LorOutput; Outpin; 40,40,40,40);
   BUF(TNode; FeedBack; 0,0,0,0);   
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);         
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(Outpin; FeedBack; 2,2,2,2);    
 |9:   
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 2,2,2,2);    
 |10:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(Outpin; FeedBack; 2,2,2,2);   
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 2,2,2,2);   
 |12:    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);         
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);       
 |13:
   AND(%InFuse; CLK; 0,0,0,0);   
   LNOR(%ClrFuse, IPH; Clear);  
   DQFFC(LorOutput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |14:   
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);   
 %END;
%MACEND;   

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P5, L25, %FF9288, N1, N25, N49, %FF9216, L49, 
      N73, P1);   
EP900(%SF17346, %SF10008, L2, P6, L26, %FF10008, N2, N26, N50, %FF9936, L50, 
      N74, P1);   
EP900(%SF17351, %SF10728, L3, P7, L27, %FF10728, N3, N27, N51, %FF10656, L51, 
      N75, P1);   
EP900(%SF17356, %SF11448, L4, P8, L28, %FF11448, N4, N28, N52, %FF11376, L52, 
      N76, P1);   
EP900(%SF17361, %SF12168, L5, P9, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P1);   
EP900(%SF17366, %SF12888, L6, P10, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P1);   
EP900(%SF17371, %SF13608, L7, P11, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P1);   
EP900(%SF17376, %SF14328, L8, P12, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P1);   
EP900(%SF17381, %SF15048, L9, P13, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P1);   
EP900(%SF17386, %SF15768, L10, P14, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P1);   
EP900(%SF17391, %SF16488, L11, P15, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P1);   
EP900(%SF17396, %SF17208, L12, P16, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P1);   
EP900(%SF17336, %SF8568, L13, P25, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P21);   
EP900(%SF17331, %SF7848, L14, P26, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P21);   
EP900(%SF17326, %SF7128, L15, P27, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P21);   
EP900(%SF17321, %SF6408, L16, P28, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P21);   
EP900(%SF17316, %SF5688, L17, P29, L41, %FF5688, N17, N41, N65, %FF5616, L65, 
      N89, P21);
EP900(%SF17311, %SF4968, L18, P30, L42, %FF4968, N18, N42, N66, %FF4896, L66, 
      N90, P21);
EP900(%SF17306, %SF4248, L19, P31, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P21);
EP900(%SF17301, %SF3528, L20, P32, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P21);
EP900(%SF17296, %SF2808, L21, P33, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P21);
EP900(%SF17291, %SF2088, L22, P34, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P21);
EP900(%SF17286, %SF1368, L23, P35, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P21);
EP900(%SF17281, %SF648, L24, P36, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P21);
%EndModel      

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP910JC-30
%LastNode ? ?
%NumPins: 44
%FDF AND 0 ~P3 P3 ~P4 P4 ~P5 P5 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P19 P19 ~P20 P20
	 ~P21 P21 ~P25 P25 ~P26 P26 ~P27 P27 ~N13 N13 ~N14 N14 ~N15 N15 
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22 
	 ~N23 N23 ~N24 N24 ~P41 P41 ~P42 P42 ~P43 P43 *
	 
%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE            
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;     
%MACEND;      

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT, 
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2: 
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 30,30,30,30);
   %ELSE
      BUF(LorOutput; TSBInput; 30,30,30,30);       
      TSB(TSBInput, %InFuse; Outpin; 25,25,25,25,25,25,25,25);       
   %END;
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |1,3:
   BUF(LorOutput; Outpin; 30,30,30,30);
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |4:                    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 15,15,20,0,10,10,25,25,0,0,15,15,20,0,10,10,25,25,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 30,30,30,30);
    %ELSE
       BUF(LorOutput; TSBInput; 30,30,30,30);
       TSB(TSBInput, %InFuse; Outpin; 25,25,25,25,25,25,25,25);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);    
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 25,25,5,5,10,10,25,25,0,0,25,25,5,5,10,10,25,25,0,0);         
   BUF(LorOutput; Outpin; 30,30,30,30);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |6:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 15,15,20,0,10,10,25,25,0,0,15,15,20,0,10,10,25,25,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 30,30,30,30);
    %ELSE
       BUF(LorOutput; TSBInput; 30,30,30,30); 
       TSB(TSBInput, %InFuse; Outpin; 25,25,25,25,25,25,25,25);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 25,25,5,5,10,10,25,25,0,0,25,25,5,5,10,10,25,25,0,0);         
   BUF(LorOutput; Outpin; 30,30,30,30);
   BUF(TNode; FeedBack; 0,0,0,0);   
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 15,15,20,0,10,10,25,25,0,0,15,15,20,0,10,10,25,25,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 25,25,25,25,25,25,25,25);       
    %END;
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |9:   
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 25,25,5,5,10,10,25,25,0,0,25,25,5,5,10,10,25,25,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |10:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 15,15,20,0,10,10,25,25,0,0,15,15,20,0,10,10,25,25,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 25,25,25,25,25,25,25,25);       
    %END;
   BUF(OutPin; FeedBack; 2,2,2,2);   
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 25,25,5,5,10,10,25,25,0,0,25,25,5,5,10,10,25,25,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(OutPin; FeedBack; 2,2,2,2);   
 |12:    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 15,15,20,0,10,10,25,25,0,0,15,15,20,0,10,10,25,25,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 25,25,25,25,25,25,25,25);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);       
 |13:
   AND(%InFuse; CLK; 0,0,0,0);   
   LNOR(%ClrFuse, IPH; Clear);  
   DQFFC(LorOutput, CLK, Clear; TNode; 25,25,5,5,10,10,25,25,0,0,25,25,5,5,10,10,25,25,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |14:   
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 15,15,20,0,10,10,25,25,0,0,15,15,20,0,10,10,25,25,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 25,25,25,25,25,25,25,25);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 25,25,5,5,10,10,25,25,0,0,25,25,5,5,10,10,25,25,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);   
 %END;
%MACEND;   

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P6, L25, %FF9288, N1, N25, N49, %FF9216, L49, 
      N73, P2);   
EP900(%SF17346, %SF10008, L2, P7, L26, %FF10008, N2, N26, N50, %FF9936, L50, 
      N74, P2);   
EP900(%SF17351, %SF10728, L3, P8, L27, %FF10728, N3, N27, N51, %FF10656, L51, 
      N75, P2);   
EP900(%SF17356, %SF11448, L4, P9, L28, %FF11448, N4, N28, N52, %FF11376, L52, 
      N76, P2);   
EP900(%SF17361, %SF12168, L5, P10, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P2);   
EP900(%SF17366, %SF12888, L6, P11, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P2);   
EP900(%SF17371, %SF13608, L7, P12, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P2);   
EP900(%SF17376, %SF14328, L8, P13, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P2);   
EP900(%SF17381, %SF15048, L9, P14, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P2);   
EP900(%SF17386, %SF15768, L10, P15, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P2);   
EP900(%SF17391, %SF16488, L11, P16, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P2);   
EP900(%SF17396, %SF17208, L12, P18, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P2);   
EP900(%SF17336, %SF8568, L13, P28, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P24);   
EP900(%SF17331, %SF7848, L14, P29, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P24);   
EP900(%SF17326, %SF7128, L15, P30, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P24);   
EP900(%SF17321, %SF6408, L16, P31, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P24);   
EP900(%SF17316, %SF5688, L17, P32, L41, %FF5688, N17, N41, N65, %FF5616, L65, 
      N89, P24);
EP900(%SF17311, %SF4968, L18, P33, L42, %FF4968, N18, N42, N66, %FF4896, L66, 
      N90, P24);
EP900(%SF17306, %SF4248, L19, P34, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P24);
EP900(%SF17301, %SF3528, L20, P35, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P24);
EP900(%SF17296, %SF2808, L21, P36, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P24);
EP900(%SF17291, %SF2088, L22, P37, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P24);
EP900(%SF17286, %SF1368, L23, P38, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P24);
EP900(%SF17281, %SF648, L24, P40, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P24);
%EndModel      

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP910JC-35
%LastNode ? ?
%NumPins: 44
%FDF AND 0 ~P3 P3 ~P4 P4 ~P5 P5 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P19 P19 ~P20 P20
	 ~P21 P21 ~P25 P25 ~P26 P26 ~P27 P27 ~N13 N13 ~N14 N14 ~N15 N15 
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22 
	 ~N23 N23 ~N24 N24 ~P41 P41 ~P42 P42 ~P43 P43 *
	 
%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE            
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;     
%MACEND;      

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT, 
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2: 
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 35,35,35,35);
   %ELSE
      BUF(LorOutput; TSBInput; 35,35,35,35);       
      TSB(TSBInput, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
   %END;
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |1,3:
   BUF(LorOutput; Outpin; 35,35,35,35);
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |4:                    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 35,35,35,35);
    %ELSE
       BUF(LorOutput; TSBInput; 35,35,35,35);
       TSB(TSBInput, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);    
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(LorOutput; Outpin; 35,35,35,35);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |6:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 35,35,35,35);
    %ELSE
       BUF(LorOutput; TSBInput; 35,35,35,35); 
       TSB(TSBInput, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(LorOutput; Outpin; 35,35,35,35);
   BUF(TNode; FeedBack; 0,0,0,0);   
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |9:   
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |10:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(Outpin; FeedBack; 2,2,2,2);   
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(OutPin; FeedBack; 2,2,2,2);   
 |12:    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);       
 |13:
   AND(%InFuse; CLK; 0,0,0,0);   
   LNOR(%ClrFuse, IPH; Clear);  
   DQFFC(LorOutput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |14:   
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);   
 %END;
%MACEND;   

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P6, L25, %FF9288, N1, N25, N49, %FF9216, L49, 
      N73, P2);   
EP900(%SF17346, %SF10008, L2, P7, L26, %FF10008, N2, N26, N50, %FF9936, L50, 
      N74, P2);   
EP900(%SF17351, %SF10728, L3, P8, L27, %FF10728, N3, N27, N51, %FF10656, L51, 
      N75, P2);   
EP900(%SF17356, %SF11448, L4, P9, L28, %FF11448, N4, N28, N52, %FF11376, L52, 
      N76, P2);   
EP900(%SF17361, %SF12168, L5, P10, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P2);   
EP900(%SF17366, %SF12888, L6, P11, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P2);   
EP900(%SF17371, %SF13608, L7, P12, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P2);   
EP900(%SF17376, %SF14328, L8, P13, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P2);   
EP900(%SF17381, %SF15048, L9, P14, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P2);   
EP900(%SF17386, %SF15768, L10, P15, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P2);   
EP900(%SF17391, %SF16488, L11, P16, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P2);   
EP900(%SF17396, %SF17208, L12, P18, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P2);   
EP900(%SF17336, %SF8568, L13, P28, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P24);   
EP900(%SF17331, %SF7848, L14, P29, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P24);   
EP900(%SF17326, %SF7128, L15, P30, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P24);   
EP900(%SF17321, %SF6408, L16, P31, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P24);   
EP900(%SF17316, %SF5688, L17, P32, L41, %FF5688, N17, N41, N65, %FF5616, L65, 
      N89, P24);
EP900(%SF17311, %SF4968, L18, P33, L42, %FF4968, N18, N42, N66, %FF4896, L66, 
      N90, P24);
EP900(%SF17306, %SF4248, L19, P34, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P24);
EP900(%SF17301, %SF3528, L20, P35, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P24);
EP900(%SF17296, %SF2808, L21, P36, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P24);
EP900(%SF17291, %SF2088, L22, P37, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P24);
EP900(%SF17286, %SF1368, L23, P38, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P24);
EP900(%SF17281, %SF648, L24, P40, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P24);
%EndModel      

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP910JC-40
%LastNode ? ?
%NumPins: 44
%FDF AND 0 ~P3 P3 ~P4 P4 ~P5 P5 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P19 P19 ~P20 P20
	 ~P21 P21 ~P25 P25 ~P26 P26 ~P27 P27 ~N13 N13 ~N14 N14 ~N15 N15 
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22 
	 ~N23 N23 ~N24 N24 ~P41 P41 ~P42 P42 ~P43 P43 *
	 
%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE            
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;     
%MACEND;      

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT, 
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2: 
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 40,40,40,40);
   %ELSE
      BUF(LorOutput; TSBInput; 40,40,40,40);       
      TSB(TSBInput, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
   %END;
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |1,3:
   BUF(LorOutput; Outpin; 40,40,40,40);
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |4:                    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 40,40,40,40);
    %ELSE
       BUF(LorOutput; TSBInput; 40,40,40,40);
       TSB(TSBInput, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);    
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(LorOutput; Outpin; 40,40,40,40);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |6:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 40,40,40,40);
    %ELSE
       BUF(LorOutput; TSBInput; 40,40,40,40); 
       TSB(TSBInput, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(LorOutput; Outpin; 40,40,40,40);
   BUF(TNode; FeedBack; 0,0,0,0);   
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |9:   
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |10:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(OutPin; FeedBack; 2,2,2,2);   
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(OutPin; FeedBack; 2,2,2,2);   
 |12:    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);       
 |13:
   AND(%InFuse; CLK; 0,0,0,0);   
   LNOR(%ClrFuse, IPH; Clear);  
   DQFFC(LorOutput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |14:   
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);   
 %END;
%MACEND;   

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P6, L25, %FF9288, N1, N25, N49, %FF9216, L49, 
      N73, P2);   
EP900(%SF17346, %SF10008, L2, P7, L26, %FF10008, N2, N26, N50, %FF9936, L50, 
      N74, P2);   
EP900(%SF17351, %SF10728, L3, P8, L27, %FF10728, N3, N27, N51, %FF10656, L51, 
      N75, P2);   
EP900(%SF17356, %SF11448, L4, P9, L28, %FF11448, N4, N28, N52, %FF11376, L52, 
      N76, P2);   
EP900(%SF17361, %SF12168, L5, P10, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P2);   
EP900(%SF17366, %SF12888, L6, P11, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P2);   
EP900(%SF17371, %SF13608, L7, P12, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P2);   
EP900(%SF17376, %SF14328, L8, P13, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P2);   
EP900(%SF17381, %SF15048, L9, P14, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P2);   
EP900(%SF17386, %SF15768, L10, P15, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P2);   
EP900(%SF17391, %SF16488, L11, P16, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P2);   
EP900(%SF17396, %SF17208, L12, P18, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P2);   
EP900(%SF17336, %SF8568, L13, P28, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P24);   
EP900(%SF17331, %SF7848, L14, P29, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P24);   
EP900(%SF17326, %SF7128, L15, P30, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P24);   
EP900(%SF17321, %SF6408, L16, P31, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P24);   
EP900(%SF17316, %SF5688, L17, P32, L41, %FF5688, N17, N41, N65, %FF5616, L65, 
      N89, P24);
EP900(%SF17311, %SF4968, L18, P33, L42, %FF4968, N18, N42, N66, %FF4896, L66, 
      N90, P24);
EP900(%SF17306, %SF4248, L19, P34, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P24);
EP900(%SF17301, %SF3528, L20, P35, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P24);
EP900(%SF17296, %SF2808, L21, P36, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P24);
EP900(%SF17291, %SF2088, L22, P37, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P24);
EP900(%SF17286, %SF1368, L23, P38, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P24);
EP900(%SF17281, %SF648, L24, P40, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P24);
%EndModel      

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP910JI-35
%LastNode ? ?
%NumPins: 44
%FDF AND 0 ~P3 P3 ~P4 P4 ~P5 P5 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P19 P19 ~P20 P20
	 ~P21 P21 ~P25 P25 ~P26 P26 ~P27 P27 ~N13 N13 ~N14 N14 ~N15 N15 
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22 
	 ~N23 N23 ~N24 N24 ~P41 P41 ~P42 P42 ~P43 P43 *
	 
%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE            
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;     
%MACEND;      

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT, 
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2: 
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 35,35,35,35);
   %ELSE
      BUF(LorOutput; TSBInput; 35,35,35,35);       
      TSB(TSBInput, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
   %END;
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |1,3:
   BUF(LorOutput; Outpin; 35,35,35,35);
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |4:                    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 35,35,35,35);
    %ELSE
       BUF(LorOutput; TSBInput; 35,35,35,35);
       TSB(TSBInput, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);    
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(LorOutput; Outpin; 35,35,35,35);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |6:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 35,35,35,35);
    %ELSE
       BUF(LorOutput; TSBInput; 35,35,35,35); 
       TSB(TSBInput, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(LorOutput; Outpin; 35,35,35,35);
   BUF(TNode; FeedBack; 0,0,0,0);   
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |9:   
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |10:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(Outpin; FeedBack; 2,2,2,2);   
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(OutPin; FeedBack; 2,2,2,2);   
 |12:    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);       
 |13:
   AND(%InFuse; CLK; 0,0,0,0);   
   LNOR(%ClrFuse, IPH; Clear);  
   DQFFC(LorOutput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |14:   
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);   
 %END;
%MACEND;   

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P6, L25, %FF9288, N1, N25, N49, %FF9216, L49, 
      N73, P2);   
EP900(%SF17346, %SF10008, L2, P7, L26, %FF10008, N2, N26, N50, %FF9936, L50, 
      N74, P2);   
EP900(%SF17351, %SF10728, L3, P8, L27, %FF10728, N3, N27, N51, %FF10656, L51, 
      N75, P2);   
EP900(%SF17356, %SF11448, L4, P9, L28, %FF11448, N4, N28, N52, %FF11376, L52, 
      N76, P2);   
EP900(%SF17361, %SF12168, L5, P10, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P2);   
EP900(%SF17366, %SF12888, L6, P11, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P2);   
EP900(%SF17371, %SF13608, L7, P12, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P2);   
EP900(%SF17376, %SF14328, L8, P13, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P2);   
EP900(%SF17381, %SF15048, L9, P14, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P2);   
EP900(%SF17386, %SF15768, L10, P15, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P2);   
EP900(%SF17391, %SF16488, L11, P16, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P2);   
EP900(%SF17396, %SF17208, L12, P18, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P2);   
EP900(%SF17336, %SF8568, L13, P28, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P24);   
EP900(%SF17331, %SF7848, L14, P29, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P24);   
EP900(%SF17326, %SF7128, L15, P30, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P24);   
EP900(%SF17321, %SF6408, L16, P31, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P24);   
EP900(%SF17316, %SF5688, L17, P32, L41, %FF5688, N17, N41, N65, %FF5616, L65, 
      N89, P24);
EP900(%SF17311, %SF4968, L18, P33, L42, %FF4968, N18, N42, N66, %FF4896, L66, 
      N90, P24);
EP900(%SF17306, %SF4248, L19, P34, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P24);
EP900(%SF17301, %SF3528, L20, P35, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P24);
EP900(%SF17296, %SF2808, L21, P36, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P24);
EP900(%SF17291, %SF2088, L22, P37, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P24);
EP900(%SF17286, %SF1368, L23, P38, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P24);
EP900(%SF17281, %SF648, L24, P40, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P24);
%EndModel      

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP910JI-40
%LastNode ? ?
%NumPins: 44
%FDF AND 0 ~P3 P3 ~P4 P4 ~P5 P5 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P19 P19 ~P20 P20
	 ~P21 P21 ~P25 P25 ~P26 P26 ~P27 P27 ~N13 N13 ~N14 N14 ~N15 N15 
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22 
	 ~N23 N23 ~N24 N24 ~P41 P41 ~P42 P42 ~P43 P43 *
	 
%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE            
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;     
%MACEND;      

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT, 
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2: 
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 40,40,40,40);
   %ELSE
      BUF(LorOutput; TSBInput; 40,40,40,40);       
      TSB(TSBInput, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
   %END;
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |1,3:
   BUF(LorOutput; Outpin; 40,40,40,40);
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |4:                    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 40,40,40,40);
    %ELSE
       BUF(LorOutput; TSBInput; 40,40,40,40);
       TSB(TSBInput, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);    
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(LorOutput; Outpin; 40,40,40,40);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |6:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 40,40,40,40);
    %ELSE
       BUF(LorOutput; TSBInput; 40,40,40,40); 
       TSB(TSBInput, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(LorOutput; Outpin; 40,40,40,40);
   BUF(TNode; FeedBack; 0,0,0,0);   
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |9:   
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |10:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(OutPin; FeedBack; 2,2,2,2);   
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(OutPin; FeedBack; 2,2,2,2);   
 |12:    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);       
 |13:
   AND(%InFuse; CLK; 0,0,0,0);   
   LNOR(%ClrFuse, IPH; Clear);  
   DQFFC(LorOutput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |14:   
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);   
 %END;
%MACEND;   

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P6, L25, %FF9288, N1, N25, N49, %FF9216, L49, 
      N73, P2);   
EP900(%SF17346, %SF10008, L2, P7, L26, %FF10008, N2, N26, N50, %FF9936, L50, 
      N74, P2);   
EP900(%SF17351, %SF10728, L3, P8, L27, %FF10728, N3, N27, N51, %FF10656, L51, 
      N75, P2);   
EP900(%SF17356, %SF11448, L4, P9, L28, %FF11448, N4, N28, N52, %FF11376, L52, 
      N76, P2);   
EP900(%SF17361, %SF12168, L5, P10, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P2);   
EP900(%SF17366, %SF12888, L6, P11, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P2);   
EP900(%SF17371, %SF13608, L7, P12, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P2);   
EP900(%SF17376, %SF14328, L8, P13, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P2);   
EP900(%SF17381, %SF15048, L9, P14, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P2);   
EP900(%SF17386, %SF15768, L10, P15, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P2);   
EP900(%SF17391, %SF16488, L11, P16, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P2);   
EP900(%SF17396, %SF17208, L12, P18, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P2);   
EP900(%SF17336, %SF8568, L13, P28, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P24);   
EP900(%SF17331, %SF7848, L14, P29, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P24);   
EP900(%SF17326, %SF7128, L15, P30, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P24);   
EP900(%SF17321, %SF6408, L16, P31, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P24);   
EP900(%SF17316, %SF5688, L17, P32, L41, %FF5688, N17, N41, N65, %FF5616, L65, 
      N89, P24);
EP900(%SF17311, %SF4968, L18, P33, L42, %FF4968, N18, N42, N66, %FF4896, L66, 
      N90, P24);
EP900(%SF17306, %SF4248, L19, P34, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P24);
EP900(%SF17301, %SF3528, L20, P35, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P24);
EP900(%SF17296, %SF2808, L21, P36, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P24);
EP900(%SF17291, %SF2088, L22, P37, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P24);
EP900(%SF17286, %SF1368, L23, P38, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P24);
EP900(%SF17281, %SF648, L24, P40, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P24);
%EndModel      

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP910LC-30
%LastNode ? ?
%NumPins: 44
%FDF AND 0 ~P3 P3 ~P4 P4 ~P5 P5 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P19 P19 ~P20 P20
	 ~P21 P21 ~P25 P25 ~P26 P26 ~P27 P27 ~N13 N13 ~N14 N14 ~N15 N15 
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22 
	 ~N23 N23 ~N24 N24 ~P41 P41 ~P42 P42 ~P43 P43 *
	 
%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE            
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;     
%MACEND;      

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT, 
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2: 
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 30,30,30,30);
   %ELSE
      BUF(LorOutput; TSBInput; 30,30,30,30);       
      TSB(TSBInput, %InFuse; Outpin; 25,25,25,25,25,25,25,25);       
   %END;
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |1,3:
   BUF(LorOutput; Outpin; 30,30,30,30);
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |4:                    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 15,15,20,0,10,10,25,25,0,0,15,15,20,0,10,10,25,25,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 30,30,30,30);
    %ELSE
       BUF(LorOutput; TSBInput; 30,30,30,30);
       TSB(TSBInput, %InFuse; Outpin; 25,25,25,25,25,25,25,25);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);    
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 25,25,5,5,10,10,25,25,0,0,25,25,5,5,10,10,25,25,0,0);         
   BUF(LorOutput; Outpin; 30,30,30,30);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |6:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 15,15,20,0,10,10,25,25,0,0,15,15,20,0,10,10,25,25,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 30,30,30,30);
    %ELSE
       BUF(LorOutput; TSBInput; 30,30,30,30); 
       TSB(TSBInput, %InFuse; Outpin; 25,25,25,25,25,25,25,25);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 25,25,5,5,10,10,25,25,0,0,25,25,5,5,10,10,25,25,0,0);         
   BUF(LorOutput; Outpin; 30,30,30,30);
   BUF(TNode; FeedBack; 0,0,0,0);   
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 15,15,20,0,10,10,25,25,0,0,15,15,20,0,10,10,25,25,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 25,25,25,25,25,25,25,25);       
    %END;
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |9:   
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 25,25,5,5,10,10,25,25,0,0,25,25,5,5,10,10,25,25,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |10:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 15,15,20,0,10,10,25,25,0,0,15,15,20,0,10,10,25,25,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 25,25,25,25,25,25,25,25);       
    %END;
   BUF(OutPin; FeedBack; 2,2,2,2);   
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 25,25,5,5,10,10,25,25,0,0,25,25,5,5,10,10,25,25,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(OutPin; FeedBack; 2,2,2,2);   
 |12:    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 15,15,20,0,10,10,25,25,0,0,15,15,20,0,10,10,25,25,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 25,25,25,25,25,25,25,25);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);       
 |13:
   AND(%InFuse; CLK; 0,0,0,0);   
   LNOR(%ClrFuse, IPH; Clear);  
   DQFFC(LorOutput, CLK, Clear; TNode; 25,25,5,5,10,10,25,25,0,0,25,25,5,5,10,10,25,25,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |14:   
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 15,15,20,0,10,10,25,25,0,0,15,15,20,0,10,10,25,25,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 25,25,25,25,25,25,25,25);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 25,25,5,5,10,10,25,25,0,0,25,25,5,5,10,10,25,25,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);   
 %END;
%MACEND;   

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P6, L25, %FF9288, N1, N25, N49, %FF9216, L49, 
      N73, P2);   
EP900(%SF17346, %SF10008, L2, P7, L26, %FF10008, N2, N26, N50, %FF9936, L50, 
      N74, P2);   
EP900(%SF17351, %SF10728, L3, P8, L27, %FF10728, N3, N27, N51, %FF10656, L51, 
      N75, P2);   
EP900(%SF17356, %SF11448, L4, P9, L28, %FF11448, N4, N28, N52, %FF11376, L52, 
      N76, P2);   
EP900(%SF17361, %SF12168, L5, P10, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P2);   
EP900(%SF17366, %SF12888, L6, P11, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P2);   
EP900(%SF17371, %SF13608, L7, P12, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P2);   
EP900(%SF17376, %SF14328, L8, P13, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P2);   
EP900(%SF17381, %SF15048, L9, P14, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P2);   
EP900(%SF17386, %SF15768, L10, P15, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P2);   
EP900(%SF17391, %SF16488, L11, P16, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P2);   
EP900(%SF17396, %SF17208, L12, P18, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P2);   
EP900(%SF17336, %SF8568, L13, P28, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P24);   
EP900(%SF17331, %SF7848, L14, P29, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P24);   
EP900(%SF17326, %SF7128, L15, P30, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P24);   
EP900(%SF17321, %SF6408, L16, P31, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P24);   
EP900(%SF17316, %SF5688, L17, P32, L41, %FF5688, N17, N41, N65, %FF5616, L65, 
      N89, P24);
EP900(%SF17311, %SF4968, L18, P33, L42, %FF4968, N18, N42, N66, %FF4896, L66, 
      N90, P24);
EP900(%SF17306, %SF4248, L19, P34, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P24);
EP900(%SF17301, %SF3528, L20, P35, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P24);
EP900(%SF17296, %SF2808, L21, P36, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P24);
EP900(%SF17291, %SF2088, L22, P37, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P24);
EP900(%SF17286, %SF1368, L23, P38, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P24);
EP900(%SF17281, %SF648, L24, P40, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P24);
%EndModel      

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP910LC-35
%LastNode ? ?
%NumPins: 44
%FDF AND 0 ~P3 P3 ~P4 P4 ~P5 P5 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P19 P19 ~P20 P20
	 ~P21 P21 ~P25 P25 ~P26 P26 ~P27 P27 ~N13 N13 ~N14 N14 ~N15 N15 
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22 
	 ~N23 N23 ~N24 N24 ~P41 P41 ~P42 P42 ~P43 P43 *
	 
%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE            
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;     
%MACEND;      

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT, 
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2: 
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 35,35,35,35);
   %ELSE
      BUF(LorOutput; TSBInput; 35,35,35,35);       
      TSB(TSBInput, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
   %END;
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |1,3:
   BUF(LorOutput; Outpin; 35,35,35,35);
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |4:                    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 35,35,35,35);
    %ELSE
       BUF(LorOutput; TSBInput; 35,35,35,35);
       TSB(TSBInput, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);    
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(LorOutput; Outpin; 35,35,35,35);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |6:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 35,35,35,35);
    %ELSE
       BUF(LorOutput; TSBInput; 35,35,35,35); 
       TSB(TSBInput, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(LorOutput; Outpin; 35,35,35,35);
   BUF(TNode; FeedBack; 0,0,0,0);   
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |9:   
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |10:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(Outpin; FeedBack; 2,2,2,2);   
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(OutPin; FeedBack; 2,2,2,2);   
 |12:    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);       
 |13:
   AND(%InFuse; CLK; 0,0,0,0);   
   LNOR(%ClrFuse, IPH; Clear);  
   DQFFC(LorOutput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |14:   
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);   
 %END;
%MACEND;   

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P6, L25, %FF9288, N1, N25, N49, %FF9216, L49, 
      N73, P2);   
EP900(%SF17346, %SF10008, L2, P7, L26, %FF10008, N2, N26, N50, %FF9936, L50, 
      N74, P2);   
EP900(%SF17351, %SF10728, L3, P8, L27, %FF10728, N3, N27, N51, %FF10656, L51, 
      N75, P2);   
EP900(%SF17356, %SF11448, L4, P9, L28, %FF11448, N4, N28, N52, %FF11376, L52, 
      N76, P2);   
EP900(%SF17361, %SF12168, L5, P10, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P2);   
EP900(%SF17366, %SF12888, L6, P11, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P2);   
EP900(%SF17371, %SF13608, L7, P12, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P2);   
EP900(%SF17376, %SF14328, L8, P13, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P2);   
EP900(%SF17381, %SF15048, L9, P14, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P2);   
EP900(%SF17386, %SF15768, L10, P15, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P2);   
EP900(%SF17391, %SF16488, L11, P16, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P2);   
EP900(%SF17396, %SF17208, L12, P18, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P2);   
EP900(%SF17336, %SF8568, L13, P28, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P24);   
EP900(%SF17331, %SF7848, L14, P29, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P24);   
EP900(%SF17326, %SF7128, L15, P30, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P24);   
EP900(%SF17321, %SF6408, L16, P31, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P24);   
EP900(%SF17316, %SF5688, L17, P32, L41, %FF5688, N17, N41, N65, %FF5616, L65, 
      N89, P24);
EP900(%SF17311, %SF4968, L18, P33, L42, %FF4968, N18, N42, N66, %FF4896, L66, 
      N90, P24);
EP900(%SF17306, %SF4248, L19, P34, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P24);
EP900(%SF17301, %SF3528, L20, P35, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P24);
EP900(%SF17296, %SF2808, L21, P36, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P24);
EP900(%SF17291, %SF2088, L22, P37, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P24);
EP900(%SF17286, %SF1368, L23, P38, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P24);
EP900(%SF17281, %SF648, L24, P40, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P24);
%EndModel      

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP910LC-40
%LastNode ? ?
%NumPins: 44
%FDF AND 0 ~P3 P3 ~P4 P4 ~P5 P5 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P19 P19 ~P20 P20
	 ~P21 P21 ~P25 P25 ~P26 P26 ~P27 P27 ~N13 N13 ~N14 N14 ~N15 N15 
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22 
	 ~N23 N23 ~N24 N24 ~P41 P41 ~P42 P42 ~P43 P43 *
	 
%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE            
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;     
%MACEND;      

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT, 
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2: 
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 40,40,40,40);
   %ELSE
      BUF(LorOutput; TSBInput; 40,40,40,40);       
      TSB(TSBInput, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
   %END;
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |1,3:
   BUF(LorOutput; Outpin; 40,40,40,40);
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |4:                    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 40,40,40,40);
    %ELSE
       BUF(LorOutput; TSBInput; 40,40,40,40);
       TSB(TSBInput, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);    
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(LorOutput; Outpin; 40,40,40,40);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |6:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 40,40,40,40);
    %ELSE
       BUF(LorOutput; TSBInput; 40,40,40,40); 
       TSB(TSBInput, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(LorOutput; Outpin; 40,40,40,40);
   BUF(TNode; FeedBack; 0,0,0,0);   
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |9:   
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |10:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(OutPin; FeedBack; 2,2,2,2);   
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(OutPin; FeedBack; 2,2,2,2);   
 |12:    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);       
 |13:
   AND(%InFuse; CLK; 0,0,0,0);   
   LNOR(%ClrFuse, IPH; Clear);  
   DQFFC(LorOutput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |14:   
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);   
 %END;
%MACEND;   

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P6, L25, %FF9288, N1, N25, N49, %FF9216, L49, 
      N73, P2);   
EP900(%SF17346, %SF10008, L2, P7, L26, %FF10008, N2, N26, N50, %FF9936, L50, 
      N74, P2);   
EP900(%SF17351, %SF10728, L3, P8, L27, %FF10728, N3, N27, N51, %FF10656, L51, 
      N75, P2);   
EP900(%SF17356, %SF11448, L4, P9, L28, %FF11448, N4, N28, N52, %FF11376, L52, 
      N76, P2);   
EP900(%SF17361, %SF12168, L5, P10, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P2);   
EP900(%SF17366, %SF12888, L6, P11, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P2);   
EP900(%SF17371, %SF13608, L7, P12, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P2);   
EP900(%SF17376, %SF14328, L8, P13, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P2);   
EP900(%SF17381, %SF15048, L9, P14, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P2);   
EP900(%SF17386, %SF15768, L10, P15, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P2);   
EP900(%SF17391, %SF16488, L11, P16, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P2);   
EP900(%SF17396, %SF17208, L12, P18, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P2);   
EP900(%SF17336, %SF8568, L13, P28, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P24);   
EP900(%SF17331, %SF7848, L14, P29, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P24);   
EP900(%SF17326, %SF7128, L15, P30, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P24);   
EP900(%SF17321, %SF6408, L16, P31, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P24);   
EP900(%SF17316, %SF5688, L17, P32, L41, %FF5688, N17, N41, N65, %FF5616, L65, 
      N89, P24);
EP900(%SF17311, %SF4968, L18, P33, L42, %FF4968, N18, N42, N66, %FF4896, L66, 
      N90, P24);
EP900(%SF17306, %SF4248, L19, P34, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P24);
EP900(%SF17301, %SF3528, L20, P35, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P24);
EP900(%SF17296, %SF2808, L21, P36, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P24);
EP900(%SF17291, %SF2088, L22, P37, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P24);
EP900(%SF17286, %SF1368, L23, P38, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P24);
EP900(%SF17281, %SF648, L24, P40, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P24);
%EndModel      

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP910LI-35
%LastNode ? ?
%NumPins: 44
%FDF AND 0 ~P3 P3 ~P4 P4 ~P5 P5 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P19 P19 ~P20 P20
	 ~P21 P21 ~P25 P25 ~P26 P26 ~P27 P27 ~N13 N13 ~N14 N14 ~N15 N15 
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22 
	 ~N23 N23 ~N24 N24 ~P41 P41 ~P42 P42 ~P43 P43 *
	 
%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE            
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;     
%MACEND;      

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT, 
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2: 
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 35,35,35,35);
   %ELSE
      BUF(LorOutput; TSBInput; 35,35,35,35);       
      TSB(TSBInput, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
   %END;
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |1,3:
   BUF(LorOutput; Outpin; 35,35,35,35);
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |4:                    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 35,35,35,35);
    %ELSE
       BUF(LorOutput; TSBInput; 35,35,35,35);
       TSB(TSBInput, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);    
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(LorOutput; Outpin; 35,35,35,35);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |6:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 35,35,35,35);
    %ELSE
       BUF(LorOutput; TSBInput; 35,35,35,35); 
       TSB(TSBInput, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(LorOutput; Outpin; 35,35,35,35);
   BUF(TNode; FeedBack; 0,0,0,0);   
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |9:   
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |10:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(Outpin; FeedBack; 2,2,2,2);   
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(OutPin; FeedBack; 2,2,2,2);   
 |12:    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);       
 |13:
   AND(%InFuse; CLK; 0,0,0,0);   
   LNOR(%ClrFuse, IPH; Clear);  
   DQFFC(LorOutput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |14:   
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);   
 %END;
%MACEND;   

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P6, L25, %FF9288, N1, N25, N49, %FF9216, L49, 
      N73, P2);   
EP900(%SF17346, %SF10008, L2, P7, L26, %FF10008, N2, N26, N50, %FF9936, L50, 
      N74, P2);   
EP900(%SF17351, %SF10728, L3, P8, L27, %FF10728, N3, N27, N51, %FF10656, L51, 
      N75, P2);   
EP900(%SF17356, %SF11448, L4, P9, L28, %FF11448, N4, N28, N52, %FF11376, L52, 
      N76, P2);   
EP900(%SF17361, %SF12168, L5, P10, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P2);   
EP900(%SF17366, %SF12888, L6, P11, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P2);   
EP900(%SF17371, %SF13608, L7, P12, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P2);   
EP900(%SF17376, %SF14328, L8, P13, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P2);   
EP900(%SF17381, %SF15048, L9, P14, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P2);   
EP900(%SF17386, %SF15768, L10, P15, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P2);   
EP900(%SF17391, %SF16488, L11, P16, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P2);   
EP900(%SF17396, %SF17208, L12, P18, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P2);   
EP900(%SF17336, %SF8568, L13, P28, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P24);   
EP900(%SF17331, %SF7848, L14, P29, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P24);   
EP900(%SF17326, %SF7128, L15, P30, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P24);   
EP900(%SF17321, %SF6408, L16, P31, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P24);   
EP900(%SF17316, %SF5688, L17, P32, L41, %FF5688, N17, N41, N65, %FF5616, L65, 
      N89, P24);
EP900(%SF17311, %SF4968, L18, P33, L42, %FF4968, N18, N42, N66, %FF4896, L66, 
      N90, P24);
EP900(%SF17306, %SF4248, L19, P34, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P24);
EP900(%SF17301, %SF3528, L20, P35, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P24);
EP900(%SF17296, %SF2808, L21, P36, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P24);
EP900(%SF17291, %SF2088, L22, P37, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P24);
EP900(%SF17286, %SF1368, L23, P38, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P24);
EP900(%SF17281, %SF648, L24, P40, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P24);
%EndModel      

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP910LI-40
%LastNode ? ?
%NumPins: 44
%FDF AND 0 ~P3 P3 ~P4 P4 ~P5 P5 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P19 P19 ~P20 P20
	 ~P21 P21 ~P25 P25 ~P26 P26 ~P27 P27 ~N13 N13 ~N14 N14 ~N15 N15 
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22 
	 ~N23 N23 ~N24 N24 ~P41 P41 ~P42 P42 ~P43 P43 *
	 
%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE            
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;     
%MACEND;      

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT, 
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2: 
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 40,40,40,40);
   %ELSE
      BUF(LorOutput; TSBInput; 40,40,40,40);       
      TSB(TSBInput, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
   %END;
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |1,3:
   BUF(LorOutput; Outpin; 40,40,40,40);
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |4:                    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 40,40,40,40);
    %ELSE
       BUF(LorOutput; TSBInput; 40,40,40,40);
       TSB(TSBInput, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);    
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(LorOutput; Outpin; 40,40,40,40);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |6:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 40,40,40,40);
    %ELSE
       BUF(LorOutput; TSBInput; 40,40,40,40); 
       TSB(TSBInput, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(LorOutput; Outpin; 40,40,40,40);
   BUF(TNode; FeedBack; 0,0,0,0);   
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |9:   
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |10:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(OutPin; FeedBack; 2,2,2,2);   
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(OutPin; FeedBack; 2,2,2,2);   
 |12:    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);       
 |13:
   AND(%InFuse; CLK; 0,0,0,0);   
   LNOR(%ClrFuse, IPH; Clear);  
   DQFFC(LorOutput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |14:   
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);   
 %END;
%MACEND;   

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P6, L25, %FF9288, N1, N25, N49, %FF9216, L49, 
      N73, P2);   
EP900(%SF17346, %SF10008, L2, P7, L26, %FF10008, N2, N26, N50, %FF9936, L50, 
      N74, P2);   
EP900(%SF17351, %SF10728, L3, P8, L27, %FF10728, N3, N27, N51, %FF10656, L51, 
      N75, P2);   
EP900(%SF17356, %SF11448, L4, P9, L28, %FF11448, N4, N28, N52, %FF11376, L52, 
      N76, P2);   
EP900(%SF17361, %SF12168, L5, P10, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P2);   
EP900(%SF17366, %SF12888, L6, P11, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P2);   
EP900(%SF17371, %SF13608, L7, P12, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P2);   
EP900(%SF17376, %SF14328, L8, P13, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P2);   
EP900(%SF17381, %SF15048, L9, P14, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P2);   
EP900(%SF17386, %SF15768, L10, P15, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P2);   
EP900(%SF17391, %SF16488, L11, P16, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P2);   
EP900(%SF17396, %SF17208, L12, P18, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P2);   
EP900(%SF17336, %SF8568, L13, P28, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P24);   
EP900(%SF17331, %SF7848, L14, P29, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P24);   
EP900(%SF17326, %SF7128, L15, P30, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P24);   
EP900(%SF17321, %SF6408, L16, P31, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P24);   
EP900(%SF17316, %SF5688, L17, P32, L41, %FF5688, N17, N41, N65, %FF5616, L65, 
      N89, P24);
EP900(%SF17311, %SF4968, L18, P33, L42, %FF4968, N18, N42, N66, %FF4896, L66, 
      N90, P24);
EP900(%SF17306, %SF4248, L19, P34, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P24);
EP900(%SF17301, %SF3528, L20, P35, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P24);
EP900(%SF17296, %SF2808, L21, P36, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P24);
EP900(%SF17291, %SF2088, L22, P37, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P24);
EP900(%SF17286, %SF1368, L23, P38, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P24);
EP900(%SF17281, %SF648, L24, P40, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P24);
%EndModel      

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP910PC-30
%LastNode ? ?
%NumPins: 40
%FDF AND 0 ~P2 P2 ~P3 P3 ~P4 P4 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P17 P17 ~P18 P18
	 ~P19 P19 ~P22 P22 ~P23 P23 ~P24 P24 ~N13 N13 ~N14 N14 ~N15 N15 
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22 
	 ~N23 N23 ~N24 N24 ~P37 P37 ~P38 P38 ~P39 P39 *
	 
%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE            
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;     
%MACEND;      

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT, 
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2: 
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 30,30,30,30);
   %ELSE
      BUF(LorOutput; TSBInput; 30,30,30,30);       
      TSB(TSBInput, %InFuse; Outpin; 25,25,25,25,25,25,25,25);       
   %END;
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |1,3:
   BUF(LorOutput; Outpin; 30,30,30,30);
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |4:                    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 15,15,20,0,10,10,25,25,0,0,15,15,20,0,10,10,25,25,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 30,30,30,30);
    %ELSE
       BUF(LorOutput; TSBInput; 30,30,30,30);
       TSB(TSBInput, %InFuse; Outpin; 25,25,25,25,25,25,25,25);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);    
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 25,25,5,5,10,10,25,25,0,0,25,25,5,5,10,10,25,25,0,0);         
   BUF(LorOutput; Outpin; 30,30,30,30);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |6:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 15,15,20,0,10,10,25,25,0,0,15,15,20,0,10,10,25,25,0,0);       
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 30,30,30,30);
    %ELSE
       BUF(LorOutput; TSBInput; 30,30,30,30); 
       TSB(TSBInput, %InFuse; Outpin; 25,25,25,25,25,25,25,25);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 25,25,5,5,10,10,25,25,0,0,25,25,5,5,10,10,25,25,0,0);         
   BUF(LorOutput; Outpin; 30,30,30,30);
   BUF(TNode; FeedBack; 0,0,0,0);   
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 15,15,20,0,10,10,25,25,0,0,15,15,20,0,10,10,25,25,0,0);         
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 25,25,25,25,25,25,25,25);       
    %END;
   BUF(Outpin; FeedBack; 2,2,2,2);    
 |9:   
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 25,25,5,5,10,10,25,25,0,0,25,25,5,5,10,10,25,25,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 2,2,2,2);    
 |10:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 15,15,20,0,10,10,25,25,0,0,15,15,20,0,10,10,25,25,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 25,25,25,25,25,25,25,25);       
    %END;
   BUF(Outpin; FeedBack; 2,2,2,2);   
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 25,25,5,5,10,10,25,25,0,0,25,25,5,5,10,10,25,25,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 2,2,2,2);   
 |12:    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 15,15,20,0,10,10,25,25,0,0,15,15,20,0,10,10,25,25,0,0);         
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 25,25,25,25,25,25,25,25);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);       
 |13:
   AND(%InFuse; CLK; 0,0,0,0);   
   LNOR(%ClrFuse, IPH; Clear);  
   DQFFC(LorOutput, CLK, Clear; TNode; 25,25,5,5,10,10,25,25,0,0,25,25,5,5,10,10,25,25,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |14:   
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 15,15,20,0,10,10,25,25,0,0,15,15,20,0,10,10,25,25,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 25,25,25,25,25,25,25,25);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 25,25,5,5,10,10,25,25,0,0,25,25,5,5,10,10,25,25,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);   
 %END;
%MACEND;   

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P5, L25, %FF9288, N1, N25, N49, %FF9216, L49, 
      N73, P1);   
EP900(%SF17346, %SF10008, L2, P6, L26, %FF10008, N2, N26, N50, %FF9936, L50, 
      N74, P1);   
EP900(%SF17351, %SF10728, L3, P7, L27, %FF10728, N3, N27, N51, %FF10656, L51, 
      N75, P1);   
EP900(%SF17356, %SF11448, L4, P8, L28, %FF11448, N4, N28, N52, %FF11376, L52, 
      N76, P1);   
EP900(%SF17361, %SF12168, L5, P9, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P1);   
EP900(%SF17366, %SF12888, L6, P10, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P1);   
EP900(%SF17371, %SF13608, L7, P11, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P1);   
EP900(%SF17376, %SF14328, L8, P12, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P1);   
EP900(%SF17381, %SF15048, L9, P13, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P1);   
EP900(%SF17386, %SF15768, L10, P14, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P1);   
EP900(%SF17391, %SF16488, L11, P15, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P1);   
EP900(%SF17396, %SF17208, L12, P16, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P1);   
EP900(%SF17336, %SF8568, L13, P25, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P21);   
EP900(%SF17331, %SF7848, L14, P26, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P21);   
EP900(%SF17326, %SF7128, L15, P27, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P21);   
EP900(%SF17321, %SF6408, L16, P28, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P21);   
EP900(%SF17316, %SF5688, L17, P29, L41, %FF5688, N17, N41, N65, %FF5616, L65, 
      N89, P21);
EP900(%SF17311, %SF4968, L18, P30, L42, %FF4968, N18, N42, N66, %FF4896, L66, 
      N90, P21);
EP900(%SF17306, %SF4248, L19, P31, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P21);
EP900(%SF17301, %SF3528, L20, P32, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P21);
EP900(%SF17296, %SF2808, L21, P33, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P21);
EP900(%SF17291, %SF2088, L22, P34, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P21);
EP900(%SF17286, %SF1368, L23, P35, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P21);
EP900(%SF17281, %SF648, L24, P36, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P21);
%EndModel      

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP910PC-35
%LastNode ? ?
%NumPins: 40
%FDF AND 0 ~P2 P2 ~P3 P3 ~P4 P4 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P17 P17 ~P18 P18
	 ~P19 P19 ~P22 P22 ~P23 P23 ~P24 P24 ~N13 N13 ~N14 N14 ~N15 N15 
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22 
	 ~N23 N23 ~N24 N24 ~P37 P37 ~P38 P38 ~P39 P39 *
	 
%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE            
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;     
%MACEND;      

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT, 
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2: 
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 35,35,35,35);
   %ELSE
      BUF(LorOutput; TSBInput; 35,35,35,35);       
      TSB(TSBInput, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
   %END;
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |1,3:
   BUF(LorOutput; Outpin; 35,35,35,35);
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |4:                    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 35,35,35,35);
    %ELSE
       BUF(LorOutput; TSBInput; 35,35,35,35);
       TSB(TSBInput, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);    
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(LorOutput; Outpin; 35,35,35,35);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |6:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);       
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 35,35,35,35);
    %ELSE
       BUF(LorOutput; TSBInput; 35,35,35,35); 
       TSB(TSBInput, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(LorOutput; Outpin; 35,35,35,35);
   BUF(TNode; FeedBack; 0,0,0,0);   
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);         
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(Outpin; FeedBack; 2,2,2,2);    
 |9:   
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 2,2,2,2);    
 |10:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(Outpin; FeedBack; 2,2,2,2);   
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 2,2,2,2);   
 |12:    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);         
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);       
 |13:
   AND(%InFuse; CLK; 0,0,0,0);   
   LNOR(%ClrFuse, IPH; Clear);  
   DQFFC(LorOutput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |14:   
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);   
 %END;
%MACEND;   

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P5, L25, %FF9288, N1, N25, N49, %FF9216, L49, 
      N73, P1);   
EP900(%SF17346, %SF10008, L2, P6, L26, %FF10008, N2, N26, N50, %FF9936, L50, 
      N74, P1);   
EP900(%SF17351, %SF10728, L3, P7, L27, %FF10728, N3, N27, N51, %FF10656, L51, 
      N75, P1);   
EP900(%SF17356, %SF11448, L4, P8, L28, %FF11448, N4, N28, N52, %FF11376, L52, 
      N76, P1);   
EP900(%SF17361, %SF12168, L5, P9, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P1);   
EP900(%SF17366, %SF12888, L6, P10, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P1);   
EP900(%SF17371, %SF13608, L7, P11, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P1);   
EP900(%SF17376, %SF14328, L8, P12, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P1);   
EP900(%SF17381, %SF15048, L9, P13, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P1);   
EP900(%SF17386, %SF15768, L10, P14, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P1);   
EP900(%SF17391, %SF16488, L11, P15, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P1);   
EP900(%SF17396, %SF17208, L12, P16, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P1);   
EP900(%SF17336, %SF8568, L13, P25, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P21);   
EP900(%SF17331, %SF7848, L14, P26, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P21);   
EP900(%SF17326, %SF7128, L15, P27, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P21);   
EP900(%SF17321, %SF6408, L16, P28, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P21);   
EP900(%SF17316, %SF5688, L17, P29, L41, %FF5688, N17, N41, N65, %FF5616, L65, 
      N89, P21);
EP900(%SF17311, %SF4968, L18, P30, L42, %FF4968, N18, N42, N66, %FF4896, L66, 
      N90, P21);
EP900(%SF17306, %SF4248, L19, P31, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P21);
EP900(%SF17301, %SF3528, L20, P32, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P21);
EP900(%SF17296, %SF2808, L21, P33, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P21);
EP900(%SF17291, %SF2088, L22, P34, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P21);
EP900(%SF17286, %SF1368, L23, P35, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P21);
EP900(%SF17281, %SF648, L24, P36, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P21);
%EndModel      

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP910PC-40
%LastNode ? ?
%NumPins: 40
%FDF AND 0 ~P2 P2 ~P3 P3 ~P4 P4 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P17 P17 ~P18 P18
	 ~P19 P19 ~P22 P22 ~P23 P23 ~P24 P24 ~N13 N13 ~N14 N14 ~N15 N15 
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22 
	 ~N23 N23 ~N24 N24 ~P37 P37 ~P38 P38 ~P39 P39 *
	 
%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE            
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;     
%MACEND;      

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT, 
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2: 
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 40,40,40,40);
   %ELSE
      BUF(LorOutput; TSBInput; 40,40,40,40);       
      TSB(TSBInput, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
   %END;
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |1,3:
   BUF(LorOutput; Outpin; 40,40,40,40);
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |4:                    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 40,40,40,40);
    %ELSE
       BUF(LorOutput; TSBInput; 40,40,40,40);
       TSB(TSBInput, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);    
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(LorOutput; Outpin; 40,40,40,40);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |6:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);       
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 40,40,40,40);
    %ELSE
       BUF(LorOutput; TSBInput; 40,40,40,40); 
       TSB(TSBInput, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(LorOutput; Outpin; 40,40,40,40);
   BUF(TNode; FeedBack; 0,0,0,0);   
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);         
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(Outpin; FeedBack; 2,2,2,2);    
 |9:   
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 2,2,2,2);    
 |10:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(Outpin; FeedBack; 2,2,2,2);   
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 2,2,2,2);   
 |12:    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);         
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);       
 |13:
   AND(%InFuse; CLK; 0,0,0,0);   
   LNOR(%ClrFuse, IPH; Clear);  
   DQFFC(LorOutput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |14:   
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);   
 %END;
%MACEND;   

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P5, L25, %FF9288, N1, N25, N49, %FF9216, L49, 
      N73, P1);   
EP900(%SF17346, %SF10008, L2, P6, L26, %FF10008, N2, N26, N50, %FF9936, L50, 
      N74, P1);   
EP900(%SF17351, %SF10728, L3, P7, L27, %FF10728, N3, N27, N51, %FF10656, L51, 
      N75, P1);   
EP900(%SF17356, %SF11448, L4, P8, L28, %FF11448, N4, N28, N52, %FF11376, L52, 
      N76, P1);   
EP900(%SF17361, %SF12168, L5, P9, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P1);   
EP900(%SF17366, %SF12888, L6, P10, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P1);   
EP900(%SF17371, %SF13608, L7, P11, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P1);   
EP900(%SF17376, %SF14328, L8, P12, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P1);   
EP900(%SF17381, %SF15048, L9, P13, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P1);   
EP900(%SF17386, %SF15768, L10, P14, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P1);   
EP900(%SF17391, %SF16488, L11, P15, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P1);   
EP900(%SF17396, %SF17208, L12, P16, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P1);   
EP900(%SF17336, %SF8568, L13, P25, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P21);   
EP900(%SF17331, %SF7848, L14, P26, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P21);   
EP900(%SF17326, %SF7128, L15, P27, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P21);   
EP900(%SF17321, %SF6408, L16, P28, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P21);   
EP900(%SF17316, %SF5688, L17, P29, L41, %FF5688, N17, N41, N65, %FF5616, L65, 
      N89, P21);
EP900(%SF17311, %SF4968, L18, P30, L42, %FF4968, N18, N42, N66, %FF4896, L66, 
      N90, P21);
EP900(%SF17306, %SF4248, L19, P31, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P21);
EP900(%SF17301, %SF3528, L20, P32, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P21);
EP900(%SF17296, %SF2808, L21, P33, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P21);
EP900(%SF17291, %SF2088, L22, P34, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P21);
EP900(%SF17286, %SF1368, L23, P35, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P21);
EP900(%SF17281, %SF648, L24, P36, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P21);
%EndModel      

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP910PI-35
%LastNode ? ?
%NumPins: 40
%FDF AND 0 ~P2 P2 ~P3 P3 ~P4 P4 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P17 P17 ~P18 P18
	 ~P19 P19 ~P22 P22 ~P23 P23 ~P24 P24 ~N13 N13 ~N14 N14 ~N15 N15 
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22 
	 ~N23 N23 ~N24 N24 ~P37 P37 ~P38 P38 ~P39 P39 *
	 
%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE            
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;     
%MACEND;      

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT, 
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2: 
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 35,35,35,35);
   %ELSE
      BUF(LorOutput; TSBInput; 35,35,35,35);       
      TSB(TSBInput, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
   %END;
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |1,3:
   BUF(LorOutput; Outpin; 35,35,35,35);
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |4:                    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 35,35,35,35);
    %ELSE
       BUF(LorOutput; TSBInput; 35,35,35,35);
       TSB(TSBInput, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);    
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(LorOutput; Outpin; 35,35,35,35);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |6:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);       
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 35,35,35,35);
    %ELSE
       BUF(LorOutput; TSBInput; 35,35,35,35); 
       TSB(TSBInput, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(LorOutput; Outpin; 35,35,35,35);
   BUF(TNode; FeedBack; 0,0,0,0);   
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);         
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(Outpin; FeedBack; 2,2,2,2);    
 |9:   
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 2,2,2,2);    
 |10:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(Outpin; FeedBack; 2,2,2,2);   
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 2,2,2,2);   
 |12:    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);         
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);       
 |13:
   AND(%InFuse; CLK; 0,0,0,0);   
   LNOR(%ClrFuse, IPH; Clear);  
   DQFFC(LorOutput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |14:   
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 18,18,23,0,12,12,30,30,0,0,18,18,23,0,12,12,30,30,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 30,30,30,30,30,30,30,30);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 30,30,5,5,12,12,30,30,0,0,30,30,5,5,12,12,30,30,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);   
 %END;
%MACEND;   

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P5, L25, %FF9288, N1, N25, N49, %FF9216, L49, 
      N73, P1);   
EP900(%SF17346, %SF10008, L2, P6, L26, %FF10008, N2, N26, N50, %FF9936, L50, 
      N74, P1);   
EP900(%SF17351, %SF10728, L3, P7, L27, %FF10728, N3, N27, N51, %FF10656, L51, 
      N75, P1);   
EP900(%SF17356, %SF11448, L4, P8, L28, %FF11448, N4, N28, N52, %FF11376, L52, 
      N76, P1);   
EP900(%SF17361, %SF12168, L5, P9, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P1);   
EP900(%SF17366, %SF12888, L6, P10, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P1);   
EP900(%SF17371, %SF13608, L7, P11, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P1);   
EP900(%SF17376, %SF14328, L8, P12, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P1);   
EP900(%SF17381, %SF15048, L9, P13, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P1);   
EP900(%SF17386, %SF15768, L10, P14, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P1);   
EP900(%SF17391, %SF16488, L11, P15, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P1);   
EP900(%SF17396, %SF17208, L12, P16, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P1);   
EP900(%SF17336, %SF8568, L13, P25, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P21);   
EP900(%SF17331, %SF7848, L14, P26, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P21);   
EP900(%SF17326, %SF7128, L15, P27, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P21);   
EP900(%SF17321, %SF6408, L16, P28, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P21);   
EP900(%SF17316, %SF5688, L17, P29, L41, %FF5688, N17, N41, N65, %FF5616, L65, 
      N89, P21);
EP900(%SF17311, %SF4968, L18, P30, L42, %FF4968, N18, N42, N66, %FF4896, L66, 
      N90, P21);
EP900(%SF17306, %SF4248, L19, P31, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P21);
EP900(%SF17301, %SF3528, L20, P32, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P21);
EP900(%SF17296, %SF2808, L21, P33, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P21);
EP900(%SF17291, %SF2088, L22, P34, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P21);
EP900(%SF17286, %SF1368, L23, P35, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P21);
EP900(%SF17281, %SF648, L24, P36, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P21);
%EndModel      

%StartModel
%Manufacturer:Altera
%Type:EP900
%PartNumber:EP910PI-40
%LastNode ? ?
%NumPins: 40
%FDF AND 0 ~P2 P2 ~P3 P3 ~P4 P4 ~N1 N1 ~N2 N2 ~N3 N3 ~N4 N4 ~N5 N5 ~N6 N6 
         ~N7 N7 ~N8 N8 ~N9 N9 ~N10 N10 ~N11 N11 ~N12 N12 ~P17 P17 ~P18 P18
	 ~P19 P19 ~P22 P22 ~P23 P23 ~P24 P24 ~N13 N13 ~N14 N14 ~N15 N15 
	 ~N16 N16 ~N17 N17 ~N18 N18 ~N19 N19 ~N20 N20 ~N21 N21 ~N22 N22 
	 ~N23 N23 ~N24 N24 ~P37 P37 ~P38 P38 ~P39 P39 *
	 
%MACRO LOR8(PolarityFuse:%SF, InFuse:%FF, LorOutput:%TEXT);
 %IF %PolarityFuse = 1 %THEN
  LOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %ELSE            
  LNOR(%InFuse, %InFuse+72, %InFuse+144, %InFuse+216, %InFuse+288, %InFuse+360,
      %InFuse+432, %InFuse+504; LorOutput);
 %END;     
%MACEND;      

%MACRO EP900(ArchBit:%SF, EnableFuse:%SF, LorOutput:%TEXT, Outpin:%TEXT, 
      XorInput:%TEXT, InFuse:%FF, FeedBack:%TEXT, TNode:%TEXT, CLK:%TEXT,
      ClrFuse:%FF, Clear:%TEXT, TSBInput:%TEXT, CLKPin:%TEXT);

%CASE %ArchBit+3, %ArchBit+2, %ArchBit+1, %ArchBit

  0,2: 
   %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
      BUF(LorOutput; Outpin; 40,40,40,40);
   %ELSE
      BUF(LorOutput; TSBInput; 40,40,40,40);       
      TSB(TSBInput, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
   %END;
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |1,3:
   BUF(LorOutput; Outpin; 40,40,40,40);
   BUF(OutPin; FeedBack; 2,2,2,2);    
 |4:                    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 40,40,40,40);
    %ELSE
       BUF(LorOutput; TSBInput; 40,40,40,40);
       TSB(TSBInput, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);    
 |5:
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(LorOutput; Outpin; 40,40,40,40);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |6:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);       
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(LorOutput; Outpin; 40,40,40,40);
    %ELSE
       BUF(LorOutput; TSBInput; 40,40,40,40); 
       TSB(TSBInput, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |7:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(LorOutput; Outpin; 40,40,40,40);
   BUF(TNode; FeedBack; 0,0,0,0);   
 |8:
   LNOR(%ClrFuse, IPH; Clear);
   DQFFC(LorOutput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);         
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(Outpin; FeedBack; 2,2,2,2);    
 |9:   
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 2,2,2,2);    
 |10:
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(Outpin; FeedBack; 2,2,2,2);   
 |11:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(Outpin; FeedBack; 2,2,2,2);   
 |12:    
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(LorOutput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);         
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);       
 |13:
   AND(%InFuse; CLK; 0,0,0,0);   
   LNOR(%ClrFuse, IPH; Clear);  
   DQFFC(LorOutput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);    
 |14:   
   LXOR(LorOutput, TNode; XorInput);      
   LNOR(%ClrFuse, IPH; Clear);      
   DQFFC(XorInput, CLKPin, Clear; TNode; 20,20,27,0,14,14,35,35,0,0,20,20,27,0,14,14,35,35,0,0);        
    %IF %EnableFuse..%EnableFuse+71 = 1 %THEN
       BUF(TNode; Outpin; 0,0,0,0);
    %ELSE
       TSB(TNode, %InFuse; Outpin; 35,35,35,35,35,35,35,35);       
    %END;
   BUF(TNode; FeedBack; 0,0,0,0);   
 |15:
   LXOR(LorOutput, TNode; XorInput);
   AND(%InFuse; CLK; 0,0,0,0);
   LNOR(%ClrFuse, IPH; Clear);   
   DQFFC(XorInput, CLK, Clear; TNode; 35,35,5,5,14,14,35,35,0,0,35,35,5,5,14,14,35,35,0,0);         
   BUF(TNode; Outpin; 0,0,0,0);
   BUF(TNode; FeedBack; 0,0,0,0);   
 %END;
%MACEND;   

LOR8(%SF17340, %FF8640, L1);
LOR8(%SF17345, %FF9360, L2);
LOR8(%SF17350, %FF10080, L3);
LOR8(%SF17355, %FF10800, L4);
LOR8(%SF17360, %FF11520, L5);
LOR8(%SF17365, %FF12240, L6);
LOR8(%SF17370, %FF12960, L7);
LOR8(%SF17375, %FF13680, L8);
LOR8(%SF17380, %FF14400, L9);
LOR8(%SF17385, %FF15120, L10);
LOR8(%SF17390, %FF15840, L11);
LOR8(%SF17395, %FF16560, L12);
LOR8(%SF17335, %FF7920, L13);
LOR8(%SF17330, %FF7200, L14);
LOR8(%SF17325, %FF6480, L15);
LOR8(%SF17320, %FF5760, L16);
LOR8(%SF17315, %FF5040, L17);
LOR8(%SF17310, %FF4320, L18);
LOR8(%SF17305, %FF3600, L19);
LOR8(%SF17300, %FF2880, L20);
LOR8(%SF17295, %FF2160, L21);
LOR8(%SF17290, %FF1440, L22);
LOR8(%SF17285, %FF720, L23);
LOR8(%SF17280, %FF00, L24);

EP900(%SF17341, %SF9288, L1, P5, L25, %FF9288, N1, N25, N49, %FF9216, L49, 
      N73, P1);   
EP900(%SF17346, %SF10008, L2, P6, L26, %FF10008, N2, N26, N50, %FF9936, L50, 
      N74, P1);   
EP900(%SF17351, %SF10728, L3, P7, L27, %FF10728, N3, N27, N51, %FF10656, L51, 
      N75, P1);   
EP900(%SF17356, %SF11448, L4, P8, L28, %FF11448, N4, N28, N52, %FF11376, L52, 
      N76, P1);   
EP900(%SF17361, %SF12168, L5, P9, L29, %FF12168, N5, N29, N53, %FF12096, L53,
      N77, P1);   
EP900(%SF17366, %SF12888, L6, P10, L30, %FF12888, N6, N30, N54, %FF12816, L54,
      N78, P1);   
EP900(%SF17371, %SF13608, L7, P11, L31, %FF13608, N7, N31, N55, %FF13536, L55,
      N79, P1);   
EP900(%SF17376, %SF14328, L8, P12, L32, %FF14328, N8, N32, N56, %FF14256, L56,
      N80, P1);   
EP900(%SF17381, %SF15048, L9, P13, L33, %FF15048, N9, N33, N57, %FF14976, L57,
      N81, P1);   
EP900(%SF17386, %SF15768, L10, P14, L34, %FF15768, N10, N34, N58, %FF15696, L58,
      N82, P1);   
EP900(%SF17391, %SF16488, L11, P15, L35, %FF16488, N11, N35, N59, %FF16416, L59,
      N83, P1);   
EP900(%SF17396, %SF17208, L12, P16, L36, %FF17208, N12, N36, N60, %FF17136, L60,
      N84, P1);   
EP900(%SF17336, %SF8568, L13, P25, L37, %FF8568, N13, N37, N61, %FF8496, L61,
      N85, P21);   
EP900(%SF17331, %SF7848, L14, P26, L38, %FF7848, N14, N38, N62, %FF7776, L62,
      N86, P21);   
EP900(%SF17326, %SF7128, L15, P27, L39, %FF7128, N15, N39, N63, %FF7056, L63,
      N87, P21);   
EP900(%SF17321, %SF6408, L16, P28, L40, %FF6408, N16, N40, N64, %FF6336, L64,
      N88, P21);   
EP900(%SF17316, %SF5688, L17, P29, L41, %FF5688, N17, N41, N65, %FF5616, L65, 
      N89, P21);
EP900(%SF17311, %SF4968, L18, P30, L42, %FF4968, N18, N42, N66, %FF4896, L66, 
      N90, P21);
EP900(%SF17306, %SF4248, L19, P31, L43, %FF4248, N19, N43, N67, %FF4176, L67,
      N91, P21);
EP900(%SF17301, %SF3528, L20, P32, L44, %FF3528, N20, N44, N68, %FF3456, L68,
      N92, P21);
EP900(%SF17296, %SF2808, L21, P33, L45, %FF2808, N21, N45, N69, %FF2736, L69,
      N93, P21);
EP900(%SF17291, %SF2088, L22, P34, L46, %FF2088, N22, N46, N70, %FF2016, L70,
      N94, P21);
EP900(%SF17286, %SF1368, L23, P35, L47, %FF1368, N23, N47, N71, %FF1296, L71,
      N95, P21);
EP900(%SF17281, %SF648, L24, P36, L48, %FF648, N24, N48, N72, %FF576, L72,
      N96, P21);
%EndModel      