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Refresh
Hidden Refresh
Hidden Refresh Control
DRAM Refresh Mode
AT Style Refresh
Decoupled Refresh Option
Burst Refresh
Refresh When CPU Hold
DRAM Burst of 4 Refresh
Fast DRAM Refresh
Divide for Refresh
Hi-speed Refresh
Slow Refresh
Staggered Refresh
Slow Memory Refresh Divider
DRAM Refresh Period
Refresh Value
Refresh RAS active time
Refresh RAS# Assertion
DRAM RAS Only Refresh
DRAM Refresh Queue
DRAM Refresh Method
Data Bus
AT Cycle Wait State
Extra AT Cycle Wait State
16-bit Memory, I/O Wait State
8-bit Memory, I/O Wait State
Command Delay
16-bit I/O Recovery Time
8-bit I/O Recovery Time
ISA I/O Recovery
16 Bit ISA I/O Command
16 Bit ISA Mem Command
AT Bus ISA Mem Command
AT Bus Clock Source
ATCLK Stretch
Bus Clock Selection
ISA Bus Speed
Bus Mode
Fast AT Cycle
ISA IRQ
Master Mode Byte Swap
DMA clock source
DMA Wait States
DMA COmmand Width
MEMR# Signal
MEMW# Signal
DMA Address/Data Hold Time
I/O Recovery Time Delay
I/O Recovery Select
AT Bus Precharge Wait State
I/O Cmd Recovery Control
Single ALE Enable
E0000 ROM belongs to AT BUS
Internal MUX Clock Source
Fast Decode Enable
Fast CPU Reset
Extended I/O Decode
Local Bus Ready Delay 1 Wait
Local Bus Ready
Local Bus Latch Timing
Latch Local Bus
ADS Delay
Fast Programmed I/O Mode
IDE Multi Block Mode
IDE Block Mode Transfer
Multi-Sector Transfers
IDE Multiple Sector Mode
Multiple Sector Settings
IDE (HDD) Block Mode
IDE Primary Master PIO
IDE DMA Transfer Mode
Channel 0 DMA Type F
Channel 1 DMA Type F
ISA IRQ 9,10,11
Onboard CMD IDE Mode3
IDE Translation Mode
IDE LBA Translations LBA Mode Control
Large Disk DOS COmpatibility
IDE 32-bit Transfer
Enhanced ISA Timing
Back to Back I/O Delay
DMA FLOW THRU Mode
Extended DMA Registers
Hard Disk Pre-Delay
Initialization Timeout
Fast Programmed I/O Modes
DMA Channel Select
Data Transfer
DMA Frequency Select
Hold PD Bus
Cacheing
Cache RAM (SRAM) Types
Pipeline Cache Timing
F000 Shadow Cacheable
Fast cache Read/Write
FLush 486 cache every cycle
Async SRAM Leadoff Time
Sync SRAM Leadoff Time
Async SRAM Burst Time
SRAM Write Timing
Cache Read Hit Burst
Cache Burst Read Cycle Time
SRAM Read Timing
Burst SRAM Burst Cycle
Cache Mapping
Data Pipeline
Cache Wait State
Cache Read Burst Mode
Cache Write Burst Mode
Cache Read Cycle
Cache Read Wait State
Cache Write (Hit) Wait State
CPU Cycle Cache Hit WS
Fast Cache Read Hit
Fast Cache Write Hit
Cache Scheme
Internal Cache WB/WT
Cache Write Back
L2 Cache Write Policy
L1 Cache Write Policy
L1 Update Mode
L2 Cache Enable
L2 Cache Zero Wait State
L2 Cache Cacheable Size
Linear Mode SRAM Support
Cache Write Cycle
Posted Write Enable
Posted I/O Write
Tag Ram Includes Dirty
Alt Bit Tag RAM
Tag Option
Non-cacheable Block-1 Size
Non-cacheable Block-1 Base
Non-cacheable Block-2 Size
Non-cacheable Block-2 Base
Memory above 16MB Cacheable
Cacheable RAM Address Range
XXXX Memory Cacheable
C000 Shadow Cacheable
Video BIOS Area cacheable
Shadow RAM cacheable
SRAM Speed Option
SRAM Burst R/W Cycle
Cache Early Rising
VESA L2 Cache Write
VESA L2 Cache Read
1MB Cache Memory
L2 Cache Tag Bits
L2(WB) Tag Bit Length
SRAM Type
SYNC SRAM Support
Tag/Dirty Implement
Dirty pin selection
Shortened 1/2 CLK2 of L2 cache
Cache Memory Data Buffer
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Memory
Add Extra Wait for RAS#
Add Extra Wait for CAS#
DRAM (Read/Write) Wait States
Memory Read Wait State
Mrmoy Write Wait State
DRAM Burst Write Mode
DRAM Read Burst Timing
DRAM Read Burst (B/E/P)
DRAM Write Burst (B/E/P)
DRAM Read /FPM
FP Mode DRAM Read WS
DRAM Write Burst Timing
DRAM Speed
DRAM Timing Option
DRAM Timing
DRAM Post Write
Fast DRAM
DRAM Last Write to CAS#
DRAM Write Page Mode
DRAM Code Read Page Mode
Page Code Read
DRAM RAS# Precharge Time
FP DRAM CAS Prec. Timing
FP DRAM RAS Prec. Timing
DRAM CAS# Hold Time
CAS Address Hold Time
Read CAS# Pulse Width
Write CAS# Pulse Width
EDO CAS Pule Width
EDO CAS Precharge Time
EDO RAS Precharge Time
EDO MDLE Timing
EDO BRDY# Timing
EDO RAMW# Power Setting
Fast EDO Path Select
DRAM CAS Timing Delay
DRAM RAS# Active
DRAM R/W Burst Timing
RAS Precharge Time
RAS Precharge in CLKS
CAS Precharge in CLKS
CAS# width to PCI master write
RAS Active Time
Row Address Hold in CLKS
RAS Pulse Width in CLKS
CAS Read Width in CLKS
CAS Write Width in CLKS
Late RAS Mode
RAS Timeout Feature
RAS to CAS delay time
RAS(#) To CAS(#) Delay
DRAM write push to CAS delay
CAS Before RAS
DRAM Write CAS Pulse Width
DRAM Head Off Timing
Turbo Read Leadoff
CAS Width in Read Cycle
Read-Around-Write
OMC Read Around Write
F000 UMB User Info
Interleave Mode
Fast Page Mode DRAM
Pipelined CAS
*00 Write Protect
Parity Checking Method
F/E Segment Shadow RAM
Disable SHadow Memory Base
Disable Shadow Memory Size
Base Memory Size
Memory Remapping (or Relocation/Rollover)
384 KB Memory Relocation
256 KB Remap Function
DRAM Relocate (2,4 & 8 M0
Memory Reporting
Extended memory Boundary
Global EMS Memory
Shared Memory Size of VGA
Shared Memory Enable
RAM Wait State
Cycle Check Point
Special DRAM WR Mode
MA Timing Setting
MA Additional Wait State
MA Drive Capacity
DRAM R/W Leadoff Timing
DRAM Leadoff Timing
DRAM Fast Leadoff
Fast EDO Leadoff
Speculative Leadoff
SDRAM (CAS Lat/RAS-to-CAS)
Turn-Around Insertion
DRAM ECC/PARITY Select
Single Bit Error Report
ECC Checking/Generation
Memory Parity/ECC Check
Memory Parity SERR# (NMI)
EDO Read Wait State
OMC Mem Address Permuting
OMC DRAM Page Mode
Fast Strings
Fast MA to RAS# Delay
DRAM Quick Read Mode
386 DRAM Quick Write Mode
DRAM Page Idle Timer
DRAM Enhanced Paging
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