06/15/97

Sorry for the tattered documentation of this and past releases of MCLK!
I promise to clean up the source code and docs pretty soon.  Just started
summer vacation so I should have enough free time on my hands.

Ok, here's the long awaited code for the Matrox Mystique.
First, I apologize for not omitting the PLL-driver formula from MCLK's
inline help.  However, the Mystique's clock-arrangement is sufficiently
complicated that I think it warrants a separate text-file with adequate
explanation.

The Mystique's architecture departs from other video chipsets in that the
Mystique's memory-controller and graphics-engine (datapath) use SEPARATE
clock signals.  The Mystique's memory-controller is spec'd for up to 66MHz
operation, while the graphics-engine is spec'd for up to 44MHz.  At first,
you might think that the Mystique carries two independent clock-generators
(PLL) to supply these two clock signals.  Actually, it turns out that the
Mystique has but a single PLL which drives both the datapath (graphics engine)
and SGRAM memory-subsystem.  The 3:2 clock ratio is produced by two divider
units, a /3 divider on the graphics-clock input and a /2 divider on the
memory-clock input.

So to summarize:
        System PLL (default ) = 133MHz
        Memory-clock (dfeault ) = 133 / 2.0 = 66 MHz
        Graphics-clock (default)= 133 / 3.0 = 44 MHz

MCLK currently only reports the System-PLL clock-rate, which is fine since
the MCLK and GXCLK (graphics clock) are both derived from this source.  But,
this means you'll have to use a little thinking to convert your desired
memory-clock frequency (70, 75, 80MHz) to a proper system-PLL rate.

Here is the formula for the Mystique's system PLL driver.
	Formula for Mystique System PLL driver

            (sysplln + 1)
     FVCO = ------------- * 14.31818 MHz
            (syspllm + 1)

  The final PLL frequency is given by

                       FVCO         (sysplln + 1)    14.31818MHz
     PLL freq  =  -------------  =  ------------- * -------------
                  (syspllp + 1)     (syspllm + 1)   (syspllp + 1)

     sysplln, syspllm constitute control parameters in the VCO feedback loop.
	syspllp is a post-divider circuit.

     You can't program just any value(s) into the syspll registers.
     Here's the range of acceptable values:
     	100 <= sysplln <= 127 (feedback divider)
          1 <= syspllm <= 31 (input divider)

               syspllp = { 0, 1, 3, or 7 }


 Why did I break the PLL-formula into two parts (FVCO and PLL-freq) ?  A
 filter inside the PLL circuit stipulates a minimum FVCO rate of 50MHz.
 The VCO is, of course, a stage of its own, independent of the post-divider
 (syspllp.)


The Mystique's register set does allow the programmer to change the clock-div
factor.  For example, you can change both the MCLKDIV and GCLKDIV back to /1.
Keep in mind Matrox designed the GCLK and MCLK to run at a 2:3 ratio.
Assuming my source code works, MCLK should let you change the ratio back to
1:1.  But departing from the factory-preset ratio may have undesirable
consequences...