.C1.GETTING STARTED U3 This chapter assumes that the user has had some experience with programming devices. A basic understanding of logic and logic gates, and how they relate to the design of programmed devices, is required. o.c2. FIRST STEPS Examine the Design Task Take a close look at the design that is needed. Remember that state-machine, Boolean equations, or truth tables are available for the design. Try to determine which type of syntax best suits the design task that is being worked on. Create the CUPL Source File Use the template file provided and remove the sections that do not apply. Remember to edit the header to reflect the new file that is being created. Formulate the Equations Equations must be written in CUPL syntax to specify the logic desired. This can be in Boolean, state-machine, or truth table format. Choosing a Target Device Make sure that there is a sufficient number of input pins. Check that the number of registered and non-registered output pins is sufficient for the design. Ensure that the device has three-state output control, if you need it. Check that the device can adequately handle the number of product terms required. Making Pin Assignments Assign the inputs and outputs of the design to the pins of the device. Make sure that the device is being used properly by consulting the reference material available from the manufacturer. Running CUPL Decide which file formats will be needed for downloading and simulation. A choice of four minimizers is available (M1-M4). CUPL will use M1 minimization if none is specified. See Chapter 1 "CUPL Language" for details. The device library which CUPL will use may be specified when the compiler is invoked. CUPL will use the library defined in the environment variable 'LIBCUPL' if none is specified. See Chapter U2 "Installation" for more information on LIBCUPL. o .c2.SIMPLE LOGIC DESIGN The Subway Turnstile controller is the simplest state machine design. This controller waits for a signal that a coin has been deposited. It then changes its state from locked to open. In the open phase, it waits for someone to walk through the turnstile, then it changes from open to locked. This two-state design cycles between open and locked using a coin detector and a walk-through detector as inputs. The following diagram shows the states and the pulses that change the device from one state to the next. [Picture] Figure U3-1. Subway Turnstile Example The corresponding CUPL state machine code is displayed on the right, so that the relationship between the code and the design concept is easily understood. ------------------------------------------------------------ TURNSTIL.PLD Name Turnstil; Partno FL00001; Date 03/06/89; Designer R. Teixeira; Company LDI; Location D21; Assembly Example /******************************************************/ /* */ /* This is an example to demonstrate how CUPL */ /* compiles a subway turnstile controller */ /* */ /******************************************************/ /* Target Devices: P16R4 */ /******************************************************/ /* Inputs: define inputs to Turnstile controller */ Pin 1 = CLK; Pin 2 = WALK_THRU; Pin 3 = COIN; /* Outputs: define outputs as active HI levels ............................... */ Pin 14 = CNT_PULSE; Pin 15 = LOCK; /* Logic: Subway Turnstile example expressed in CUPL */ $DEFINE LOCKED 'b'0 $DEFINE OPEN 'b'1 Sequence LOCK{ Present LOCKED if COIN Next OPEN; if !COIN Next LOCKED; Present OPEN if WALK_THRU Next LOCKED; Default Next OPEN; Out CNT_PULSE; } ------------------------------------------------------------ Figure U3-2. TURNSTIL.PLD o .c2.SIMPLE GATES EXAMPLE This section will explain in detail the creation of a simple gates program for a PLD. The following diagram shows what design will be implemented. This design is taken from the Chapter U5 "Design Examples". [Picture] Figure U3-3. Simple Gates This design gives a simple set of inputs and generates output simulating some simple gates. The outputs are labeled to reflect the function of their gate; for example, the AND gate has an output labeled AND. Figure U3-4 shows the CUPL source file (GATES.PLD provided in the CUPL package) that describes the design. ------------------------------------------------------------ GATES.PLD Name Gates; Partno CA0001; Date 07/16/87; Designer G Woolheiser; Company ATI; Location San Jose, CA.; Assembly Example /******************************************************/ /* */ /* This is an example to demonstrate how CUPL */ /* compiles simple gates . */ /* */ /******************************************************/ /* Target Devices: P16L8, P16P8, EP300, and 82S153 */ /******************************************************/ /* Inputs: define inputs to build simple gates */ Pin 1 = a; Pin 2 = b; /* Outputs: define outputs as active HI levels For PAL16L8 and PAL16LD8, De Morgan's Theorem is applied to invert all outputs due to fixed inverting buffer in the device. */ Pin 12 = inva; Pin 13 = invb; Pin 14 = and; Pin 15 = nand; Pin 16 = or; Pin 17 = nor; Pin 18 = xor; Pin 19 = xnor; /* Logic: examples of simple gates expressed in CUPL */ inva = !a; /* inverters */ invb = !b; and = a & b; /* and gate */ nand = !(a & b); /* nand gate */ or = a # b; /* or gate */ nor = !(a # b); /*nor gate */ xor = a $ b; /*exclusive or gate */ xnor = !(a $ b); /*exclusive nor gate */ ------------------------------------------------------------ Figure U3-4. Simple Gates Source File (GATES.PLD) The first part of the file provides archival information and a description of the intended function of the design, including compatible PLDs. First, there is the 'Name' line, which CUPL uses to name the output files by adding extensions. 'Partno' specifies the Company's proprietary part number, issued by manufacturing, for a particular PLD design. The part number is not the type of the target PLD. 'Date' is used to specify the date of compilation. The date should be changed to the current date as a good documentation practice. 'Designer' should be the designer's name or the name of the design team. 'Assembly' is used to specify the assembly name or number of the PC board on which the PLD will be used. Use the abbreviation ASSY if desired. 'Location' is supposed to be used to indicate the PC board reference or coordinate where the PLD is located. The abbreviation LOC may also be used. This may be used for other purposes. Pin declarations are made corresponding to the inputs and outputs in the design diagram. The gates in this example require two inputs, which are passed through the gates as necessary. 'a' and 'b' are names for the input pins. Next, names are assigned to the output pins. The names chosen are descriptive of the function being performed. The use of descriptive names is encouraged, as it makes files easier to debug and update at a later time. In the "Logic" section of the file, equations describe each of the gates in the design. Boolean syntax is used to specify each output pin as a function of the input pins 'a' and 'b'. For the PAL16L8 and PAL16LD8 devices, which contain fixed inverting buffers, CUPL applies DeMorgan's Theorem to invert all outputs because they were all declared active-HI in the pin list. For example, during compilation, CUPL converts the following equation for an OR gate, on an output pin that has been declared as active-HI: or = a # b ; to the following single expanded product term (as shown in the documentation file): or => !a & !b The devices chosen for this design were selected because they fit the criteria, as specified earlier, for choosing a device. They have an adequate number of pins, both input and output. They have .i.tri-state control;tri-state control. The number of registered and non-registered pins fits our design, and the device can handle the number of product terms. o .c2.COMPILING THE SOURCE FILE At the system prompt, type: cupl -x P16L8 gates This will execute CUPL. The '-x' means to generate a documentation file (GATES.DOC) so that the expanded listing generated by CUPL may be viewed. The target device is a PAL16L8 and the source file is GATES.PLD. After running CUPL, open the file GATES.DOC, which has the expanded listing generated by CUPL. This shows how CUPL expands the logic equations when it compiles the design for the device chosen. In order to see how CUPL reports errors, edit the source file GATES.PLD and remove the semicolon at the end of one of the assignment statements. Now run CUPL as follows: cupl -l P16L8 gates After it has finished, take a look at the file GATES.LST to see how CUPL reports errors. Notice that an error line appears next to the error, and there are line numbers at the beginning of each line. o .c2.SIMULATING A DESIGN Now the design will be simulated using CSIM. Test vectors must be created for the simulator to function. Test vectors specify the expected functional operation of a PLD by defining the outputs as a function of the inputs. Test vectors are also used to do functional testing of a device once it has been programmed, to see if the device functions as expected. CSIM needs a test specification source file. For this example, it will be called GATES.SI. This file has a description of the function of the device in the circuit. CSIM compares the input pin and output pin test values in the GATES.SI file, as shown in figure U3-5, with the actual values that are calculated from the logic equations in the absolute file GATES.ABS created by CUPL when the '-a' option is used. CSIM will not work unless the GATES.ABS file is created. To create the file GATES.ABS, type: CUPL -a p16l8 gates [Enter] If the results are to be used for simulation, add the J option so that the test vectors will be added to the JEDEC file. CUPL -aj p16l8 gates[Enter] ------------------------------------------------------------ Name Gates; Partno 000000; Revision 03; Date 9/12/83; Designer CUPL Engineering; Company Logical Devices, Inc.; Location None; Assembly None; /****************************************************************/ /* */ /* This is a example to demonstrate how CUPL */ /* compiles simple gates. */ /* */ /****************************************************************/ /* Target Devices: P16L8, P16LD8, P16P8, EP300, and 82S153*/ /****************************************************************/ /* Order: define order, polarity, and output */ /* spacing of stimulus and response values */ Order: a, %2, b, %4, inva, %3, invb, %5, and, %8, nand, %7, or, %8, nor, %7, xor, %8, xnor; /* Vectors: define stimulus and response values, with header */ /* and intermediate messages for the simulator listing */ /* Note: Don't Care state (X) on inputs is reflected in */ /* outputs where appropriate. */ Vectors:$msg ""; $msg " Simple Gates Simulation"; $msg ""; $msg "inverters and nand or nor xor xnor $msg "a b !a !b a & b !(a & b) a # b !(a # b) a $ b !(a$b)"; $msg "- - -- -- ----- -------- ----- ------- ----- ------"; 00 HHLHLHLH 01 HLLHHLHL 10 LHLHHLHL 11 LLHLHLLH 1X LXXXHLXX X1 XLXXHLXX 0X HXLHXXXX X0 XHLHXXXX XX XXXXXXXX ------------------------------------------------------------ Figure U3-5. Gates Simulator Input File (GATES.SI) To run the simulator for the simple gates example, type the following: CSIM -w P16L8 gates [Enter] The waveform output is available for the DOS version of CUPL only. For UNIX, VMS and all other versions, the only output available is the simulator output file. Figure U3-6 shows the simulator output file. The inputs are listed with the corresponding outputs. ------------------------------------------------------------ 1:Name Gates; 2:Partno 000000; 3:Revision 03; 4:Date 9/12/83; 5:Designer CUPL Engineering; 6:Company Logical Devices, Inc.; 7:Location None; 8:Assembly None; 9: 10:/****************************************************************/ 11:/* */ 12:/* This is a example to demonstrate how CUPL */ 13:/* compiles simple gates. */ 14:/* */ 15:/****************************************************************/ 16:/* Target Devices: P16L8, P16LD8, P16P8,EP300, and 82S153 */ 17:/****************************************************************/ 18: 19: 20:/* 21: * Order: define order, polarity, and output 22: * spacing of stimulus and response values 23: */ 24: 25:Order: a, %2, b, %4, inva, %3, invb, %5, and, %8, 26: nand, %7, or, %8, nor, %7, xor, %8, xnor; 27: 28:/* 29: * Vectors: define stimulus and response values, with header 30: * and intermediate messages for the simulator listing. 31: * 32: * Note: Don't Care state (X) on inputs is reflected in outputs 33: * where appropriate. 34: */ 35: ======================================================================= Simulation Results ======================================================================= Simple Gates Simple Simulation inverters and nand or nor xor xnor a a !a !b a & b !(a & b) a # b !(a # b) a $ b !(a $ b) - - -- -- ----- -------- ----- -------- ----- -------- 0001: 0 0 H H L H L H L H 0002: 0 1 H L L H H L H L 0003: 1 0 L H L H H L H L 0004: 1 1 L L H L H L L H 0005: 1 X L X X X H L X X 0006: X 1 X L X X H L X X 0007: 0 X H X L H X X X X 0008: X 0 X H L H X X X X 0009: X X X X X X X X X X ------------------------------------------------------------ Figure U3-6. Gates Simulator Output File (GATES.SO)