.C1. INTRODUCTION TO CUPL U1 Welcome to CUPL Universal Compiler for Programmable Logic. CUPL is a very versatile and powerful logic compiler, and can be used to create very sophisticated logic designs for PLDs. This section will introduce the user to CUPL. o .c2.CUPL OVERVIEW The CUPL package consists of the following programs: CUPL (Universal Compiler for Programmable Logic), CSIM (CUPL Simulator), CBLD (CUPL Build), and PTOC (PALASM to CUPL Translator). Using CUPL, logic descriptions may be written and compiled. The logic descriptions can be assigned to specific programmable logic devices (PLDs). CUPL searches its library and creates a file which can be downloaded to a device programmer and, from there, the PLD can be programmed. CSIM permits a design to be simulated before it is put into production. A file is created, describing the expected functionality of the PLD in terms of input and output values. CSIM compares the expected values to actual values calculated during CUPL operation. The DOS version of CSIM will also allow the simulation to be viewed in waveform. CBLD allows the manipulation of the device libraries containing descriptions of the PLDs supported by CUPL. PTOC converts PALASM designs to CUPL format. The key features of the CUPL package include: _ Universal applicability. CUPL supports products from all manufacturers of PLDs, enabling a user to put the same functional logic into physically different parts, to create a second source at the socket. CUPL produces a standard type of file called JEDEC. This is a download file that is compatible with any logic programmer that uses JEDEC files. The CUPL language translator (PTOC) converts .i.PALASM;PALASM designs to CUPL, enabling the use of any PALASM designs. _ A high-level language. Expression substitution for equations, shorthand notation for lists, address ranges, and bit fields are available to save design time. CUPL simplifies Boolean expressions by the distributive property and DeMorgan' s Theorem. State machine syntax provides a powerful means of implementing any synchronous application using either Mealy or Moore state machine models. Truth table syntax provides a way to clearly express certain logic descriptions. User-defined functions allow the creation of keywords for use by CUPL. _ Flexible documentation. CUPL provides a template file for standard "fill in the blanks" documentation and allows the placement of free-form comments throughout a design. CUPL's comprehensive error-checking capability generates detailed error messages designed to lead to the source of any problems. _ Powerful minimizer and simulation programs. CUPL contains the fastest and most powerful minimizer offered for programmable logic equation reduction, featuring four levels of minimization. The CUPL simulation program enables logic to be simulated prior to using a PLD. This feature prevents blown devices and helps debug system-level problems. Test vectors verified by CSIM can be downloaded to a logic programmer. o .c2.CUPL DATA FLOW This section describes the CUPL data flow. First, a logic description source file is created, using the CUPL language to describe the logic that will be assigned to a programmable logic device. Then, run CUPL to compile the source file to create a fusemap file for downloading to a device programmer. On execution of CUPL, the '-a' flag may be used to cause CUPL to generate an '.ABS' file for later use by CSIM. Optionally, a test specification file may be created to verify the design. CSIM is executed to compare the expected values in the test file to the actual values in the absolute file created by CUPL. When simulation is complete without any errors, the verified test vectors can be appended to the download file generated by CUPL. At this point, the verified fusemap file can be transferred to a device programmer. Figure U1-1 shows the CUPL data flow. [Picture] Figure U1-1. CUPL Data Flow Output file types: .SO Simulator Output with errors .HL HL Download file .HEX Hex Download file .JED JEDEC file without test vectors JEDEC file with test vectors o .c2.SYSTEM OVERVIEW CUPL (Universal Compiler for Programmable Logic) is a set of programs that provides tools for designing with PLDs. The CUPL system consists of the following modules: CUPLX, CUPLA, CUPLB, CUPLM, and CUPLC. A brief description of each of the program modules follows. [Picture] Figure U1-2. CUPL Execution Flow CUPLX: CUPL Language Preprocessor Scans the .PLD (input) file, processing the preprocessor directives, i.e. $DEFINE. Generates an intermediate file with all preprocessor directives expanded. CUPLA: CUPL Language Parser Scans and parses the intermediate file generated by CUPLX. Utilizes a table driven parser to generate a symbol table and expanded equations. Expands state machine, truth table, and user defined function syntax into boolean equations. Also, performs simple logic reduction while processing range statements. CUPLB: CUPL Design to Target Device Linker Resolves links between design and the target device model. Expands the parsed equations according to signal polarity and physical characteristics, via DeMorgan's Theorem. Builds the final symbol table, containing device model links, and bit mapped representation of the logic design. CUPLM: CUPL Logic Minimizer Executes logic minimization algorithms on the bit mapped logic generated in CUPLB. Processes only the equations for which reduction has been requested. If no reduction is requested then the intermediate file generated by CUPLB is renamed for use by CUPLC. Performs multiple output minimization for FPLA architecture. CUPLC: CUPL Design Fitter Determines if the design fits the target device architecture and builds a fuse map. The fuse map and symbol table are used to generate the documentation and JEDEC files. [Picture] Figure U1-3. Device Independent Design Flow [Picture] Figure U1-4. Device Specific Design Flow [Picture] Figure U1-5. CUPL Device Fitting Some Fitter programs currently available include: CUPLC generic device fitter FITR MACH device fitter FITMAPL MAPL device fitter.