.c1. General Introduction This manual is designed to serve as a learning aid and as a reference manual for CUPL, the programmable logic compiler from Logical Devices, Inc. It is divided into three sections: the User Guide section, the Reference section and the Appendices. The User Guide provides information on getting started with the CUPL package. The Reference section provides specific information about the programs that make up the CUPL package. The Appendices contain a variety of information, including error messages, important information about specific devices, node numbering and download formats. Be sure to read the Installation Chapter in the User Guide section to find out what to do before using the CUPL software on a system. Since improvements are made to CUPL quite frequently, additional information is provided in the form of an addendum. Be certain to read the addendum, which provides information on the latest enhancements to the CUPL software. o .c2.USER GUIDE The USER GUIDE provides information on installing and using CUPL. There is also a section that provides several examples. These examples are provided on the distribution disks. Chapter U1: "Introduction" gives a brief overview of CUPL and includes some notes on recent enhancements to CUPL. Also included is a section on getting technical support. Chapter U2: "Installation" provides information necessary to get CUPL to run on a system. Chapter U3: "Getting Started" is a step-by-step guide on how to create a source file, and compile and simulate the design using a simple example. Chapter U4: "CUPL Operation" is a description of the use of CUPL. This includes running CUPL. Chapter U5: "Design Examples" Provides instructions on using CUPL and CSIM and examples of CUPL designs. Part A, "Sample Design Session", goes step-by-step through a sample design session using CUPL and CSIM. Part B, "Sample PLD Files", illustrates some typical designs that can be created using CUPL. o .c2.REFERENCE The REFERENCE section is provided for easy access to random facts related to the CUPL language and related utilities. Chapter 1: CUPL Language Describes CUPL, a programmable logic compiler. This chapter provides an overview of CUPL, and describes the input and output and how to run the program. It also describes the elements of the CUPL design language, and the syntax of the CUPL design language. Chapter 2: Using CSIM Describes CSIM, a logic simulation program. This chapter explains how to use CSIM, including input and output and running the program, and how to create test specification files to verify a CUPL design. Chapter 3: Using CBLD Describes CBLD, a utility program for managing device libraries. Chapter 4: Using PTOC Describes PTOC, a utility program for converting PALASM source files to CUPL format. Chapter 5: FPGA and High Density PLDs describes how to use CUPL to design with FPGAs and High Density PLDs. o.c2. APPENDICES Appendix A: "Error Messages" lists error messages that may appear during operation of any of the CUPL programs. The messages are listed by program name and module name within each program. Appendix B: "Device Usage Notes" provides information about specific devices and how they require special attention with CUPL. Appendix C: "Download Formats" describes the format of the CUPL downloadable files and the documentation file. Appendix D: "Node Numbering" lists the devices which contain internal nodes supported by CUPL. Appendix E: Trouble Shooting Lists some common problems and their respective solutions. Appendix F: FindPLD Describes the FindPLD software utility. Index Is an index of the entire book. o.c2. SOFTWARE DEVELOPMENT TOOLS OTHER CUPL PRODUCT OFFERINGS CUPL is available on workstation platforms such as the SUN 3. SPARC station, VAX/VMS, DEC station 3100 and 5000, HP9000, and Apollo DN3500 and DN4500. It is also available for Macintosh systems. CUPL can integrate into Mentor Graphics, Valid, Viewlogic, Racal-Redac, and other CAD/CAE UNIX-based software environment. An upgrade path is available for those who already own a DOS version of CUPL. Available products which integrate with CUPL include PLPartition and ONCUPL. .c3.CUPL TotalDesigner-386 ... '386 Protected Mode Version CUPL TotalDesigner-386 will take full advantage of the 80386's 32-bit registers, 4-gigabyte physical address space, and enhanced instruction set. It executes in the familiar DOS environment without the need of memory managers or other special operating system enhancements. This means that designs will compile faster and be able to access up to 4 gigabytes of RAM instead of just 640K. The large PLDs and FPGAs are going to be supported with this system (examples: Altera Max, AMD MACH, Xilinx, Plus Logic, Plessey, Actel, etc.). Manufacturer specific place and route software and device fitters are not included. In addition, partitioning software, PLPartition, is provided for creating multiple PLD designs. Also, SchemaQuik and ONCUPL are provided so that schematic entry designs can be created and translated into CUPL source files. All the programmable logic design software an engineer needs is in this package. .c3.PLPartition - Multiple PLD Design One of the major tasks facing PLD designers is the selection of specific devices to implement a design. PLPartition takes the drudgery out of the process. This product will provide you with powerful features that help synthesize your logic design into one of several PLDs. Automatic Device selection and design fitting is accomplished by using a friendly user interface and extremely fast technology. This will decrease the time it takes to implement your final design. .c3.MacCUPL - A Macintosh version of CUPL MacCUPL is a full implementation of the CUPL Programmable Logic Design Tools for the Macintosh. Developed for System 6.0, MacCUPL is also System 7 compatible. A standard Mac interface, an integrated text editor, and interactive as well as batch mode compiling make MacCUPL quick to learn and use. MacCUPL can access all available memory in the computer, allowing for very large and complex designs to be compiled. The software interfaces to McCAD schematic capture package, translating netlists directly into CUPL source files. .c3.DEC 3100 and 5000 CUPL is available for the new DEC5000 computer system. CUPL runs on the DEC5000 encapsulated within Digital's "PowerFrame" framework. PowerFrame is Digital's design management system that provides easy access to commonly used functions and agents encapsulated within its framework. CUPL offers a variety of design expression formats, true language flexibility, powerful logic minimization, simulation and pre-processor capabilities, including interactivities with other agents of PowerFrame. Designers of large and very large state machines and other logic systems can now design their products with CUPL as part of the encapsulated toolkit of PowerFrame and the DEC5000. Other EDA vendors such as Valid and Viewlogic are members of the PowerFrame synergy program. Digital's encapsulation toolkit, PowerFrame, exclusively features CUPL as the logic design tool and provides a link to other PowerFrame agents. .c3.SPARC based Workstations CUPL runs on SPARC based workstations under OpenWindows. OpenWindows. OpenWindows is Sun's windowing environment for OPEN LOOK_ GUI applications. The OpenWindows interface provides the CUPL user with a design development environment in which tools are integrated, easy to learn, and simple to use. This allows the user to focus on the design process rather than the underlying tool and platform manipulation details. This results in reduced design time. .c3.Open-PLA Opening CUPL's proprietary description language is accomplished by providing a development software tool that details Open-PLA standards and facilitates device development of routers and fitters for CUPL-HDL. Logical's Open-PLA, which is fully compatible with Data I/O's Open-ABEL_, is based on the industry standard Berkeley-PLA and several other standard formats. .c3.ONCUPL ONCUPL translates schematic netlists from a wide variety of schematic entry packages into CUPL source files. Schematic entry for logic designs is a very important tool in the CAE industry. A logic design can be created using a schematic entry package and the supplied ONCUPL macros. From this package, a netlist can be created that represents the schematic design. ONCUPL translates this netlist into a PLD file that CUPL compiles into a JEDEC file. Presently, ONCUPL supports the following schematic entry packages: OrCAD's SDTIII, Omation's SCHEMA III, Wintek's HiWire, P-CAD's PC-CAPS, Racal-Redac's CADSTAR, Phase II Logic's CAPFAST, Protel's Protel-Schematic, and Viewlogic's Workview. .c3.ALLPRO-88 - Universal Device Programmer The universal "DAC-PER-PIN" programmer, ALLPRO-88, can integrate with CUPL as a full PLD development workstation. It is fully qualified by the semiconductor manufacturers, and is available in 40, 48, 56, 68, and 88 pin configurations, fully upgradeable with DIP and PLCC socket support. Application Notes Logical Devices, Inc. will accept application notes, design examples and useful design tips for designing with CUPL design software. All forwarded material will be reviewed and become the property of the CUPL User's Group. This information will be available for all CUPL users free of charge. One out of every 10 application notes received will be selected as the best and most useful and the author of the application note will be awarded a one-year CUPL maintenance program. Forward material to: CUPL MARKETING DEPARTMENT LOGICAL DEVICES INC 1201 NW 65 PLACE FORT LAUDERDALE FL 33309 ---------------------------------------------------------------------- Conventions Used In This Manual .i.conventions used;This manual gives step-by-step procedures and examples. To make it easy to follow these procedures, the following conventions are used. Note LDI software is not case sensitive. It doesn't matter whether upper or lower case characters are typed. [key] [A] [Enter] [ESC] The [ and ] characters are used to indicate a key that must be pressed to execute a command or accept an option. This key is called different names on different systems. For example: [Enter], [Return], [ESC], [F1] [key]-[key] Connected keys indicate the keys must be pressed simultaneously. For example: Press [CTRL]-[ALT]-[DEL] An asterisk (*) in a filename indicates any characters can occupy that position and all remaining positions. For more information, refer to the DOS manual. Select Select means use the cursor keys to cycle through options or settings, and press [Enter] to select the desired option or setting. < > Variable names are indicated by angle brackets. For example: .SCH { } Square brackets indicate the enclosed item is optional. For example: pack filename.fil {filename.lib}