UNDER THE LID

David Spencer takes a look at the hardware that makes the Archimedes tick.

Many Archimedes owners (and in fact computer owners in general) have little or no idea what makes their computer tick, and this includes some very experienced programmers that I know. In this short series I will explain the basics of the Archimedes hardware, but without going into the sort of detail which requires a degree in electronic engineering to understand.

GETTING DOWN TO BASICS

Before getting down to the details of the Archimedes we will take a brief look at digital electronics. In electronics, a signal is any piece of information carried within a circuit. For example, the wire connecting a record deck to an amplifier carries a signal (or two for a stereo system) representing the information stamped on the record. On the record the information is stored in the groves, while when the sound emerges from the speaker it is the form of pressure waves that reach our ears. However, between these devices the signal is represented by a varying voltage which will be carried along a wire, or a track on a printed circuit board etc. What is important is that some arbitrary information, in this case music, can be represented by a voltage within a circuit. Furthermore, the voltage can take any value between two extremes. In our example the value of the voltage corresponds to the volume of the music.

The range of values the voltage can take depends entirely on the circuit in question. For the output of a record deck the voltage might range from 0V (V=volt) for absolute quiet to 100mV (1mV=1/1000 V) for maximum volume, while the same signal when amplified to drive a loudspeaker could range in values from 0V to 45V. The critical thing is that any circuits connected together must agree about the range of voltages they use. If you were to connect the loudspeaker output of an amplifier back to the input you would most likely cause a lot of damage because the input signal would be several hundred times the expected voltage.

The situation just described is an analogue system. This is the term used when the voltage of the signal is proportional to some varying information, such as music. In contrast, a computer system at the fundamental machine code level works in binary. Therefore, a signal representing a binary digit (bit) will only ever take two voltage levels, as it represents either the binary value 0 or 1. Such a setup is called a digital system. For historical reasons, computer systems tend to be powered by 5V power supplies. You might therefore expect binary signals to be represented by voltages of 0V and 5V. However, this is the ideal case, and for a number of practical reasons these levels would prove unworkable. A further consideration is noise. In electronic terms noise is an unwanted signal which interferes with genuine signals, typically causing the signal voltage to change slightly. It is highly desirable that even if our digital signal is subjected to noise that it is still possible to determine whether it represents a one or a zero. If this was not the case, then the computer would most likely crash each time a car with a faulty supressor drove past for instance. For this reason, instead of using one single voltage to represent a zero, and a different voltage for a one, two ranges are used. This is shown in figure 1.

Figure 1. Logic voltage levels

Figure 1

It can be seen from figure 1 that a zero may be represented by any voltage between 0V and about 0.8V, while a one has the range 2V to 5V. Any voltage within either of these ranges will be correctly recognised by components in the circuit as representing a zero or one. However, devices that generate signals do so to a much tighter tolerance. Typically, for the devices used in the Archimedes, a zero will be output as 0.2V, and a one as 4.4V, these being marked on the diagram as the thick lines. You should be able to see that even if noise does alter the voltage of the signal significantly, it is unlikely to go out of the allowed range, and can therefore still be interpreted correctly.

CATCHING A BUS

Having looked very briefly at the whys and wherefores of digital electronics we can turn our attention to the signals found in the Archimedes, or in fact any computer. Although a single bit can be represented by one signal, this is not on its own very useful. In general, several bits are treated together to form a binary number. As it takes one electronic signal for each bit, an n-bit number requires n signals, and hence n separate connections within the circuit. Such a set of connections is known as a bus.

Although the term bus refers to any such set of related connections, there are two important buses present in all computer systems - the address bus and the data bus. These buses are used whenever the computer reads or writes memory. Not only does this include all the reads of program instructions and data, but in the case of the Archimedes, all accesses to peripheral devices such as the keyboard and disc drive. This is because on the ARM, all peripherals are treated as special case memory.

When the ARM processor reads or writes a memory location it starts by putting the address of the location as a binary number on the address bus. The hardware of the computer, including the memory controller MEMC which we will come back to later, then uses this address to select a particular location within the RAM or ROM chips, or one of the peripheral devices. Simultaneously with this the ARM also sets up a number of signals to indicate whether it wants to read or write the selected location, and whether it wants to write a whole word, or just one byte (as would be the case using the STRB instruction). Once this has happened, if the operation is a read from memory then the memory device (RAM, ROM etc.) puts the value on the data bus and the ARM reads this in. For a memory write, the ARM places the data on the bus and the memory devices stores it.

In the Archimedes, the data bus is 32 bits wide, because the ARM is a 32 bit processor. The address bus on the other hand is only 26 bits, giving an addressing capability of 64Mbytes, or 16Mwords. We shall look in much more detail later at how the addressable locations (called the address space) are arranged.

PUTTING IT TOGETHER

Having explained briefly some fundamentals of digital electronics, and the idea of a bus, we can now start to look at the Archimedes itself. Figure 2 shows a so-called block diagram of the hardware. In such a diagram, all the major building blocks of the circuit are shown, together with the important interconnections between them. However, the detail of every individual component is not shown. When studying the principles of a complex system, a block diagram is generally much more use than a full component level (schematic) diagram, because the latter tends to become rather cluttered and confusing.

Figure 2. Simplified block diagram of the Archimedes

Figure 2

Looking at figure 2, you can see in the centre the ARM processor and the memory controller MEMC. The other two large blocks are the peripheral controller IOC, and the video controller (VIDC). Together, these four chips form the ARM chip set which was specially designed by Acorn. As these are the key chips, it is these that we will be concentrating on. You will also see the RAM and ROM in figure 2, together with the specific chips for controlling individual peripheral devices such as the disc drive and serial port.

The interconnections between blocks are of two forms. The thin lines represent individual signals, whilst buses are shown as a thicker line. On some block diagrams you may also see buses drawn as two parallel lines - it all depends on what takes the designer's fancy. The same system is also used on schematic diagrams, although in this case because every connection must be clearly depicted individual signals that split off buses are labelled. Another set of vital connections that you will not find on the block diagram, and probably not on a schematic, are the power supply connections. Every single chip in a circuit requires a power supply, and as almost all digital chips use a single +5V supply as stated earlier, it is usually simpler to omit power supply connections. On a block diagram they are missed out altogether, while on a schematic a table is normally used to show the connections for each chip.

The address and data buses are clearly visible on the block diagram. The address bus connects between the ARM processor and MEMC, and also to a set of chips called latches. A latch is a device which can be instructed to store a binary number by means of a control signal. The types of latch used on the address bus are called transparent latches. With these, the number is fed straight through until the control signal is applied. The outputs of the latch are then frozen while the input can continue changing until the control signal is removed at which point the outputs follow the inputs again. The reason for needing the latches is interesting - the ARM is such a fast processor that having started to access a memory location it moves onto the next access before the first one is completed. This would result in the address seen by the memory changing before it has a chance to use it. Therefore the latches are used to hold the address for a short while until the memory has a chance to catch up. This latched address bus is then connected to the ROMs, and the peripheral devices including IOC. We will explain next month how the peripheral devices use the address bus.

You might have noticed that the address bus does not connect to the RAM chips, which appears to be contrary to what we said earlier. The reason for this is the way in which the RAM chips are arranged internally. Rather than having a linear list of locations accessed by a single address (as used by the ROMs), the RAM chips arrange their locations in a grid, with each location being selected by a separate row and column address. This method simplifies the internal design of the RAM chips, and also reduces the number of pins on each chip, because the two addresses are fed in one after the other on the same set of pins. It is the job of MEMC to split the address up as needed, and this will be covered later when we explain the functions of the main chips.

The data can also be seen originating from the ARM, and passing directly into VIDC, the ROM and RAM. The lower half (sixteen bits) of the data bus is then connected into two sets of latches, both in parallel, but in opposite directions. These are used to connect the data bus to IOC and the peripheral devices. Only sixteen bits are used because the majority of peripherals used in computer systems work in eight or sixteen bit chunks, rather than the mammoth thirty-two bits of the ARM data bus. In fact, even IOC which is an integral part of the ARM chip-set uses only eight bits. The latches that face away from the data bus (i.e. those which latch the data from the data bus) serve a similar purpose to those on the address bus - they keep the data stable long enough for the peripheral devices to deal with it. This is necessary because most devices that have to communicate with the outside world (meaning keyboard, disc drive etc.) will work at a much slower speed than the ARM itself.

The purpose of the latches which feed data onto the data bus is different. All the peripheral controlling devices are asynchronous, which means that once the processor has started a read operation from one of them, it is not sure exactly how long the operation will take, and hence when it will finish. Therefore, the latches are used to store the data read from the peripheral controller, so that the ARM does not have to synchronise its reading of data exactly with that of the device being read.

TRISTATE LOGIC

Finally this month we will look at a very important concept in computer circuits. When we introduced the idea of digital signals, we implied that all signals had to be at one of two voltages, representing either a zero or a one. But, look again at the block diagram of figure 2. A number of devices can feed data onto the data bus - namely the RAM, ROM and I/O latches, and the ARM itself. Now, in a binary system all of these devices must be outputting either a zero or a one signal onto the data bus at all times, simply because there are only two possible output states to choose from. However, this will lead to contention because it is most probable that each device will be trying to put a different number onto the data bus, and these will interfere with each other. For example, consider the simplest case of just two devices and a single bit of the data bus. If the first device is trying to put 0V on the data bus line, and the second is putting 5V we have a contention problem. In practice, exactly what happens depends on the particular type of chips connected to the bus, but it is almost certain that the circuit will be thrown into chaos.

To avoid this, most outputs have three states. They can either be a binary '0' or '1', as before, or can be totally disconnected from the circuit. This disconnection is done by means of a control signal. The circuit is arranged so that at any time only one device has its outputs enabled, and hence only one number is being put onto the data bus at any time.

Next month we will look in some detail at the functions of the ARM chip set.